WO2021254039A1 - 移位寄存器的驱动方法及装置 - Google Patents

移位寄存器的驱动方法及装置 Download PDF

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Publication number
WO2021254039A1
WO2021254039A1 PCT/CN2021/093329 CN2021093329W WO2021254039A1 WO 2021254039 A1 WO2021254039 A1 WO 2021254039A1 CN 2021093329 W CN2021093329 W CN 2021093329W WO 2021254039 A1 WO2021254039 A1 WO 2021254039A1
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WIPO (PCT)
Prior art keywords
level
signal
clock
signal terminal
transistor
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PCT/CN2021/093329
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English (en)
French (fr)
Inventor
商广良
董甜
黄硕
郑灿
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京东方科技集团股份有限公司
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Priority to US17/921,082 priority Critical patent/US11854508B2/en
Publication of WO2021254039A1 publication Critical patent/WO2021254039A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving method and device of a shift register.
  • GOA Gate Driver on Array, array substrate row drive
  • TFT Thin Film Transistor, thin film transistor
  • the gate control circuit is usually composed of a plurality of cascaded shift registers.
  • the higher power consumption of the shift register will result in higher power consumption of the display device.
  • the driving method of the shift register provided by the embodiment of the present disclosure includes: at the first refresh frequency, one display frame includes a data refresh phase and a data retention phase;
  • the input signal terminal is loaded with an input signal with a pulse level
  • the control clock signal terminal is loaded with a control clock pulse signal
  • the noise reduction clock signal terminal is loaded with a noise reduction clock pulse signal
  • the first reference signal terminal is loaded.
  • Load a fixed voltage signal with a first level load a fixed voltage signal with a second level to the second reference signal terminal, control the cascade signal terminal of the shift register to output a cascade signal with a pulse level and control
  • the drive signal terminal of the shift register outputs a drive signal with a pulse level;
  • a fixed voltage signal is applied to the input signal terminal, a first setting signal is applied to the control clock signal terminal, a second setting signal is applied to the noise reduction clock signal terminal, and the The first reference signal terminal is loaded with a fixed voltage signal with the first level, the second reference signal terminal is loaded with a fixed voltage signal with the second level, and the cascaded signal terminal is controlled to output the signal with the A fixed voltage signal of the second level and controlling the drive signal terminal to output the fixed voltage signal of the first level;
  • the control clock pulse signal has a first level, a second level, and a first clock period;
  • the first setting signal has a first setting level;
  • the first clock period includes the control One of the durations of the first level and one of the durations of the second level in the clock pulse signal, and one of the first level and the second level in the control clock signal is a control
  • the clock pulse level, the control clock pulse level is the same as the first set level, and the sustaining time of the first set level in the first clock period is greater than the control clock pulse level
  • the noise reduction clock pulse signal has a first level, a second level, and a second clock period; the second setting signal has a second setting level; wherein the second clock period includes the noise reduction
  • One of the durations of the first level and the duration of the second level in the clock pulse signal, and one of the first level and the second level in the noise reduction clock signal is A noise reduction clock pulse level, the noise reduction clock pulse level is the same as the second set level, and the second set level is maintained for a longer period of time in the second clock cycle than the noise reduction The length of time the clock pulse level is maintained in the second clock cycle.
  • the first setting signal is a clock pulse signal
  • the first setting level is one of the first level and the second level.
  • the third clock period of the first setting signal is greater than the first clock period
  • the third clock period includes a duration of the first level and a duration of the second level in the first setting signal.
  • the sustaining duration of the first level in the first setting signal in the first clock period is longer than the first level in the control clock pulse signal in the first clock period. Duration of maintenance;
  • the sustaining duration of the second level in the first setting signal in the first clock cycle is greater than the sustaining duration of the second level in the control clock pulse signal in the first clock cycle.
  • the second setting signal is a clock pulse signal
  • the second setting level is one of the first level and the second level.
  • the fourth clock period of the second setting signal is greater than the second clock period
  • the fourth clock period includes a duration of the first level and a duration of the second level in the second setting signal.
  • the sustaining duration of the first level in the second setting signal in the second clock period is longer than that of the first level in the noise reduction clock signal in the second clock period.
  • the sustaining duration of the second level in the second setting signal in the second clock cycle is greater than the sustaining duration of the second level in the noise reduction clock signal in the second clock cycle.
  • the third clock period of the first setting signal is the same as the fourth clock period of the second setting signal.
  • At least one of the first setting signal and the second setting signal is a fixed voltage signal
  • At least one of the first setting level and the second setting signal is one of the first level and the second level.
  • the first level is a high level
  • the second level is a low level
  • the first level is a low level
  • the second level is a high level
  • the driving method further includes: at the second refresh frequency, one display frame includes a data refresh phase;
  • the input signal terminal is loaded with an input signal with a pulse level
  • the control clock signal terminal is loaded with a control clock pulse signal
  • the noise reduction clock signal terminal is loaded with a noise reduction clock pulse signal
  • the first reference signal terminal is loaded.
  • Load a fixed voltage signal with a first level load a fixed voltage signal with a second level to the second reference signal terminal, control the cascade signal terminal of the shift register to output a cascade signal with a pulse level and control
  • the drive signal terminal of the shift register outputs a drive signal with a pulse level.
  • a display frame includes a data refresh phase and a data retention phase;
  • the driving circuit is configured as:
  • the input signal terminal is loaded with an input signal with a pulse level
  • the control clock signal terminal is loaded with a control clock pulse signal
  • the noise reduction clock signal terminal is loaded with a noise reduction clock pulse signal
  • the first reference signal terminal is loaded.
  • Load a fixed voltage signal with a first level load a fixed voltage signal with a second level to the second reference signal terminal, control the cascade signal terminal of the shift register to output a cascade signal with a pulse level and control
  • the drive signal terminal of the shift register outputs a drive signal with a pulse level;
  • a fixed voltage signal is applied to the input signal terminal, a first setting signal is applied to the control clock signal terminal, a second setting signal is applied to the noise reduction clock signal terminal, and the The first reference signal terminal is loaded with a fixed voltage signal with the first level, the second reference signal terminal is loaded with a fixed voltage signal with the second level, and the cascaded signal terminal is controlled to output the signal with the A fixed voltage signal of the second level and controlling the drive signal terminal to output the fixed voltage signal of the first level;
  • the control clock pulse signal has a first level, a second level, and a first clock period;
  • the first setting signal has a first setting level;
  • the first clock period includes the control One of the durations of the first level and one of the durations of the second level in the clock pulse signal, and one of the first level and the second level in the control clock signal is a control
  • the clock pulse level, the control clock pulse level is the same as the first set level, and the sustaining time of the first set level in the first clock period is greater than the control clock pulse level
  • the noise reduction clock pulse signal has a first level, a second level, and a second clock period; the second setting signal has a second setting level; wherein the second clock period includes the noise reduction
  • One of the durations of the first level and the duration of the second level in the clock pulse signal, and one of the first level and the second level in the noise reduction clock signal is A noise reduction clock pulse level, the noise reduction clock pulse level is the same as the second set level, and the second set level is maintained for a longer period of time in the second clock cycle than the noise reduction The length of time the clock pulse level is maintained in the second clock cycle.
  • one display frame includes a data refresh phase
  • the driving circuit is further configured as:
  • the input signal terminal is loaded with an input signal with a pulse level
  • the control clock signal terminal is loaded with a control clock pulse signal
  • the noise reduction clock signal terminal is loaded with a noise reduction clock pulse signal
  • the first reference signal terminal is loaded.
  • Load a fixed voltage signal with a first level load a fixed voltage signal with a second level to the second reference signal terminal, control the cascade signal terminal of the shift register to output a cascade signal with a pulse level and control
  • the drive signal terminal of the shift register outputs a drive signal with a pulse level.
  • the embodiment of the present disclosure provides a display panel, including a gate driving circuit and the driving circuit; wherein, the gate driving circuit includes a plurality of shift registers connected in cascade;
  • the driving circuit is electrically connected with the plurality of shift registers.
  • the embodiment of the present disclosure provides a display device, which includes a display panel.
  • FIG. 1 is a schematic structural diagram of a shift register provided by an embodiment of the disclosure
  • FIG. 2 is a flowchart of a driving method provided by an embodiment of the disclosure
  • FIG. 3 is a timing diagram of some signals provided by the embodiments of the disclosure.
  • FIG. 4 is some simulation diagrams provided by the embodiments of the disclosure.
  • FIG. 5 is a timing diagram of other signals provided by the embodiments of the disclosure.
  • FIG. 6 is a timing diagram of other signals provided by the embodiments of the disclosure.
  • FIG. 7 is a timing diagram of other signals provided by the embodiments of the disclosure.
  • FIG. 8 is some other simulation diagrams provided by the embodiments of the disclosure.
  • FIG. 9 is a schematic diagram of the structure of some gate control circuits provided by the embodiments of the disclosure.
  • the display device can be driven with a lower refresh frequency (such as 1 Hz). Due to the accumulation of long-term leakage of the transistor, the signal output by the driving signal terminal is abnormal.
  • the embodiments of the present disclosure provide some shift registers, as shown in FIG. 1, which may include:
  • the first transistor M1 the gate of the first transistor M1 is configured to be coupled to the first reference signal terminal VREF1, the first pole of the first transistor M1 is configured to be coupled to the first pull-up node PU_1, and the first transistor M1
  • the second pole of is configured to be coupled to the second pull-up node PU_2;
  • the second transistor M2 the gate of the second transistor M2 is coupled to the cascade signal terminal GP, the first pole of the second transistor M2 is coupled to the second reference signal terminal VREF2, the second pole of the second transistor M2 is coupled to the fifth The gate of the transistor M5 is coupled;
  • the third transistor M3, the gate of the third transistor M3 is coupled to the first noise reduction clock signal terminal CKO, the first pole of the third transistor M3 is coupled to the first reference signal terminal VREF1, and the second pole of the third transistor M3 Coupled to the gate of the fifth transistor M5;
  • the fourth transistor M4 the gate of the fourth transistor M4 is coupled to the cascade signal terminal GP, the first pole of the fourth transistor M4 is coupled to the second reference signal terminal VREF2, and the second pole of the fourth transistor M4 is coupled to the drive signal Terminal OP coupling;
  • the fifth transistor M5, the first electrode of the fifth transistor M5 is coupled to the first reference signal terminal VREF1, and the second electrode of the fifth transistor M5 is coupled to the driving signal terminal OP;
  • the first capacitor C1, the first electrode of the first capacitor C1 is coupled to the second noise reduction clock signal terminal CKBO, and the second electrode of the first capacitor C1 is coupled to the gate of the fifth transistor M5;
  • the second capacitor C2, the first electrode of the second capacitor C2 is coupled to the gate of the fifth transistor M5, and the second electrode of the first capacitor C1 is coupled to the driving signal terminal OP;
  • the sixth transistor M6 the gate of the sixth transistor M6 is coupled to the second pull-up node PU_2, the first pole of the sixth transistor M6 is coupled to the second control clock signal terminal CKB, and the second pole of the sixth transistor M6 is coupled to The cascade signal terminal GP is coupled;
  • the seventh transistor M7 the gate of the seventh transistor M7 is coupled to the pull-down node PD, the first electrode of the seventh transistor M7 is coupled to the second reference signal terminal VREF2, and the second electrode of the seventh transistor M7 is coupled to the cascade signal terminal GP coupling;
  • the third capacitor C3, the first electrode of the third capacitor C3 is coupled to the second pull-up node PU_2, and the second electrode of the third capacitor C3 is coupled to the cascade signal terminal GP;
  • the fourth capacitor C4 the first electrode of the fourth capacitor C4 is coupled to the pull-down node PD, and the second electrode of the fourth capacitor C4 is coupled to the second reference signal terminal VREF2;
  • the eighth transistor M8 the gate of the eighth transistor M8 is coupled to the first control clock signal terminal CK, the first pole of the eighth transistor M8 is coupled to the input signal terminal IP, and the second pole of the eighth transistor M8 is coupled to the first control clock signal terminal CK.
  • the pull-up node PU_1 is coupled;
  • the gate of the ninth transistor M9 is coupled to the first control clock signal terminal CK, the first electrode of the ninth transistor M9 is coupled to the first reference signal terminal VREF1, and the second electrode of the ninth transistor M9 is coupled to The pull-down node PD is coupled;
  • the tenth transistor M10 the gate of the tenth transistor M10 is coupled to the first pull-up node PU_1, the first pole of the tenth transistor M10 is coupled to the first control clock signal terminal CK, and the second pole of the tenth transistor M10 is coupled to The pull-down node PD is coupled;
  • the eleventh transistor M11, the gate of the eleventh transistor M11 is coupled to the pull-down node PD, the first electrode of the eleventh transistor M11 is coupled to the second reference signal terminal VREF2, and the second electrode of the eleventh transistor M11 is coupled to the The first pole of the twelfth transistor M12 is coupled;
  • the twelfth transistor M12, the gate of the twelfth transistor M12 is coupled to the second control clock signal terminal CKB, and the second pole of the twelfth transistor M12 is coupled to the first pull-up node PU_1.
  • the first pull-up node PU_1 is coupled between the second electrode of the eighth transistor M8 and the first electrode of the first transistor M1.
  • the second pull-up node PU_2 is coupled between the gate of the sixth transistor M6 and the second electrode of the first transistor M1.
  • the pull-down node PD is coupled between the second electrode of the ninth transistor M9 and the gate of the seventh transistor M7.
  • the first pull-up node PU_1, the second pull-up node PU_2, and the pull-down node PD are respectively virtual nodes in the shift register. These three nodes are only used to facilitate the structure and signal transmission of the shift register. For description, the specific structure of the shift register and signal transmission can be determined according to the coupling mode between each transistor in the shift register and the capacitor.
  • the shift register provided by the embodiment of the present disclosure, by loading the corresponding signal to each signal terminal, so that each transistor and the capacitor work together, the cascade signal terminal and the driving signal terminal can respectively output corresponding signals.
  • the power consumption of the shift register can be reduced, which can facilitate the application of the shift register in this application to a display device with a lower refresh frequency.
  • the first electrode of the above-mentioned transistor can be used as its source and the second electrode can be used as its drain; or, the first electrode can be used as its drain, and the second electrode can be used as its source. No specific distinction is made here.
  • the transistor mentioned in the above-mentioned embodiments of the present disclosure may be a TFT or a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor, MOS), which is not limited herein.
  • MOS Metal Oxide Semiconductor
  • all transistors may be P-type transistors.
  • the P-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th .
  • the third transistor M3 is a P-type transistor
  • the relationship between the voltage difference V gs3 between the gate and source of the third transistor M3 and its threshold voltage V th3 satisfies the formula: V gs3 ⁇ V th3 Pass.
  • the transistor is a P-type transistor as an example for description.
  • the transistor is an N-type transistor
  • the design principle is the same as that of the present disclosure, and it also falls within the protection scope of the present disclosure.
  • the N-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs >V th .
  • the third transistor M3 is an N-type transistor
  • the relationship between the voltage difference V gs3 between the gate and the source of the third transistor M3 and the threshold voltage V th3 satisfies the formula: V gs3 >V th3 is turned on.
  • the P-type transistor is turned off under the action of a high-level signal, and turned on under the action of a low-level signal.
  • the N-type transistor is turned on under the action of a high-level signal, and cut off under the action of a low-level signal.
  • the aspect ratio of the active layer of the active layer of at least one of the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be made larger than that of the first transistor M1 and the second transistor M7.
  • the aspect ratio of the channel region of the active layer of the fourth transistor M4, the aspect ratio of the channel region of the active layer of the fifth transistor M5, and the channel region of the active layer of the sixth transistor M6 may be set
  • the aspect ratio of the channel region and the aspect ratio of the channel region of the active layer of the seventh transistor M7 are greater than the aspect ratio of the channel region of the active layer of the first transistor M1 and the active layer of the second transistor M2.
  • the aspect ratio of the channel region, the aspect ratio of the channel region of the active layer of the third transistor M3, the aspect ratio of the channel region of the active layer of the eighth transistor M8, the active layer of the ninth transistor M9 The aspect ratio of the channel region of the tenth transistor M10, the aspect ratio of the channel region of the active layer of the tenth transistor M10, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the aspect ratio of the twelfth transistor M12 The width to length ratio of the channel region of the active layer.
  • the width-to-length ratio of the channel region of the active layer of at least one of the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may be in the range of 10 ⁇ m/2 ⁇ m ⁇ 100 ⁇ m/10 ⁇ m.
  • the aspect ratio of the channel region of the active layer of the fourth transistor M4, the aspect ratio of the channel region of the active layer of the fifth transistor M5, and the channel region of the active layer of the sixth transistor M6 may be set
  • the range of the aspect ratio of the track region and the aspect ratio of the channel region of the active layer of the seventh transistor M7 is 10 ⁇ m/2 ⁇ m to 100 ⁇ m/10 ⁇ m, respectively.
  • the aspect ratio of the channel region of the active layer of the fourth transistor M4, the aspect ratio of the channel region of the active layer of the fifth transistor M5, and the channel region of the active layer of the sixth transistor M6 can be set
  • the range of the aspect ratio of and the aspect ratio of the channel region of the active layer of the seventh transistor M7 are respectively 10 ⁇ m/2 ⁇ m. It is also possible to set the aspect ratio of the channel region of the active layer of the fourth transistor M4, the aspect ratio of the channel region of the active layer of the fifth transistor M5, and the channel region of the active layer of the sixth transistor M6.
  • the range of the aspect ratio and the aspect ratio of the channel region of the active layer of the seventh transistor M7 are respectively 100 ⁇ m/10 ⁇ m.
  • the aspect ratio of the channel region of the active layer of the fourth transistor M4 is set by setting the aspect ratio of the channel region of the active layer of the fourth transistor M4, the aspect ratio of the channel region of the active layer of the fifth transistor M5, and the channel region of the active layer of the sixth transistor M6.
  • the range of the aspect ratio and the aspect ratio of the channel region of the active layer of the seventh transistor M7 are respectively 50 ⁇ m/5 ⁇ m.
  • the values of the aspect ratio of the channel region of the active layer of the sixth transistor M6 and the channel region of the active layer of the seventh transistor M7 are not limited here.
  • the first transistor M1, the second transistor M2, the third transistor M3, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 can be
  • the range of the aspect ratio of the channel region of the active layer of at least one transistor is 2 ⁇ m/2 ⁇ m to 20 ⁇ m/10 ⁇ m.
  • the aspect ratio of the channel region of the active layer of the first transistor M1, the aspect ratio of the channel region of the active layer of the second transistor M2, and the channel region of the active layer of the third transistor M3 may be set The aspect ratio of the channel region, the aspect ratio of the channel region of the active layer of the eighth transistor M8, the aspect ratio of the channel region of the active layer of the ninth transistor M9, the aspect ratio of the active layer of the tenth transistor M10
  • the range of the aspect ratio of the channel region, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the aspect ratio of the channel region of the active layer of the twelfth transistor M12 is 2 ⁇ m/2 ⁇ m ⁇ 20 ⁇ m/10 ⁇ m.
  • the aspect ratio of the channel region of the active layer of the first transistor M1, the aspect ratio of the channel region of the active layer of the second transistor M2, and the channel region of the active layer of the third transistor M3 may be set The aspect ratio of the channel region of the active layer of the eighth transistor M8, the aspect ratio of the channel region of the active layer of the ninth transistor M9, the channel of the active layer of the tenth transistor M10
  • the range of the aspect ratio of the region, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the aspect ratio of the channel region of the active layer of the twelfth transistor M12 is 2 ⁇ m/2 ⁇ m.
  • Aspect ratio, aspect ratio of the channel region of the active layer of the eighth transistor M8, aspect ratio of the channel region of the active layer of the ninth transistor M9, channel region of the active layer of the tenth transistor M10 The range of the aspect ratio of, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the aspect ratio of the channel region of the active layer of the twelfth transistor M12 is 20 ⁇ m/10 ⁇ m.
  • Aspect ratio, aspect ratio of the channel region of the active layer of the eighth transistor M8, aspect ratio of the channel region of the active layer of the ninth transistor M9, channel region of the active layer of the tenth transistor M10 The range of the aspect ratio of, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the aspect ratio of the channel region of the active layer of the twelfth transistor M12 is 10 ⁇ m/5 ⁇ m.
  • the width-to-length ratio of the channel region of the active layer of the first transistor M1, the width-to-length ratio of the channel region of the active layer of the second transistor M2, and the first transistor M2 can be specifically designed according to actual application requirements.
  • the aspect ratio of the channel region of the active layer of the tenth transistor M10, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the width of the channel region of the active layer of the twelfth transistor M12 The value of the aspect ratio is not limited here.
  • the capacitance value of at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 may be in the range of 10 fF to 1 pF.
  • the capacitance value of at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 may be in the range of 10 fF. It is also possible to set the capacitance value of at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 to a range of 50 fF.
  • the capacitance value of at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 may also be in the range of 1 pF.
  • the capacitance value of the first capacitor C1, the capacitance value of the second capacitor C2, the capacitance value of the third capacitor C3, and the capacitance value of the fourth capacitor C4 can be specifically designed according to the requirements of the actual application. limited.
  • a display frame includes a data refresh stage T10 and a data retention stage T20;
  • the driving method may include the following steps:
  • a fixed voltage signal is applied to the input signal terminal, the first setting signal is applied to the control clock signal terminal, the second setting signal is applied to the noise reduction clock signal terminal, and the first reference signal terminal is applied to the first reference signal terminal.
  • a fixed voltage signal of one level, a fixed voltage signal of a second level is applied to the second reference signal terminal, the cascade signal terminal is controlled to output a fixed voltage signal of the second level, and the drive signal terminal is controlled to output a fixed voltage signal with the first voltage.
  • Flat fixed voltage signal is applied to the input signal terminal, the first setting signal is applied to the control clock signal terminal, the second setting signal is applied to the noise reduction clock signal terminal, and the first reference signal terminal is applied to the first reference signal terminal.
  • an input signal with a pulse level is loaded to the input signal terminal, a control clock pulse signal is loaded to the control clock signal terminal, and the noise reduction clock signal terminal is loaded Noise reduction clock pulse signal, load a fixed voltage signal with a first level to the first reference signal terminal, load a fixed voltage signal with a second level to the second reference signal terminal, and control the output of the cascaded signal terminal of the shift register
  • the cascade signal with the pulse level and the drive signal terminal of the control shift register output the drive signal with the pulse level. In this way, the cascade output and drive output of the shift register can be realized, so that the display device can refresh the data.
  • a fixed voltage signal is applied to the input signal terminal, the first setting signal is applied to the control clock signal terminal, the second setting signal is applied to the noise reduction clock signal terminal, and the first reference signal terminal is applied to the first reference signal terminal.
  • the control clock signal is a clock signal having a first level and a second level, and is performed by alternately switching between the first level and the second level.
  • the control clock pulse signal has a first clock cycle, and switching between the first level and the second level is performed in the first clock cycle.
  • the first clock period includes a first level duration and a second level duration in the control clock pulse signal.
  • One of the first level and the second level in the control clock pulse signal may be a control clock pulse level, and the first setting signal has a first setting level; wherein, the control clock pulse level and the first setting power level The level is the same, and the sustaining duration of the first set level in the first clock cycle is greater than the sustaining duration of the control clock pulse level in the first clock cycle. In this way, the frequency of level switching of the first setting signal in the data holding phase can be reduced, thereby reducing power consumption.
  • the noise reduction clock signal is a clock signal having a first level and a second level, and is performed by alternately switching between the first level and the second level.
  • the noise reduction clock pulse signal has a second clock cycle, and switching between the first level and the second level is performed in the second clock cycle. Then the second clock period includes a duration of a first level and a duration of a second level in the noise reduction clock pulse signal.
  • One of the first level and the second level in the noise reduction clock pulse signal may be the noise reduction clock pulse level, and the second setting signal has the second setting level; wherein, the noise reduction clock pulse level and the second level The setting levels are the same, and the sustaining duration of the second setting level in the second clock cycle is greater than the sustaining duration of the noise reduction clock pulse level in the second clock cycle. In this way, the frequency of level switching of the second setting signal in the data holding phase can be reduced, thereby reducing power consumption.
  • the display device may be in a static image display state or in a standby state for a long time.
  • the display device can be operated with a lower refresh frequency (for example, 1 Hz, 30 Hz).
  • the shift register in the embodiment of the present disclosure can reduce power consumption by loading the first setting signal and the second setting signal in the data retention phase, thereby facilitating the application of the shift register in this application to a lower refresh frequency In the display device.
  • the first level may be a low level, and the second level may be a high level.
  • the first level may also be a high level, and the second level may also be a low level.
  • it can be designed and determined according to actual application requirements, which is not limited here.
  • the driving method further includes: at the second refresh frequency, one display frame includes a data refresh stage T10; wherein, in the data refresh stage, the input signal terminal is loaded with a pulse level Input signal, load a control clock pulse signal to the control clock signal terminal, load a noise reduction clock pulse signal to the noise reduction clock signal terminal, load a fixed voltage signal with a first level to the first reference signal terminal, and load a fixed voltage signal with a first level to the second reference signal terminal. Load a fixed voltage signal with a second level, control the cascade signal terminal of the shift register to output a cascade signal with a pulse level, and control the drive signal terminal of the shift register to output a drive signal with a pulse level.
  • the display device may be in a static image display state or in a standby state for a long time.
  • the display device can be operated with a lower refresh frequency (for example, 1 Hz, 30 Hz).
  • the display device can also display a video screen.
  • the display device can be made to work with a higher refresh frequency (for example, 60 Hz, 120 Hz).
  • the first refresh frequency may be a lower refresh frequency, for example, 1 Hz or 30 Hz.
  • the second refresh frequency may be a higher refresh frequency, such as 60 Hz or 120 Hz.
  • the control clock signal terminal includes a first control clock signal terminal CK and a second control clock signal terminal CKB; the control clock pulse signal includes a first control clock pulse signal and a second control clock pulse Signal; wherein the periods of the first control clock pulse signal and the second control clock pulse signal are both the first clock period, and the phase difference is 1/2 period.
  • loading the control clock signal terminal with the control clock pulse signal may specifically include: loading the first control clock signal terminal CK with the first control clock signal terminal CK, and loading the second control clock signal terminal CKB with the second control clock signal terminal CKB. 2. Control the clock pulse signal.
  • ck represents the signal loaded by the first control clock signal terminal CK
  • ckb represents the signal loaded by the second control clock signal terminal CKB.
  • the first control clock pulse signal loaded on the first control clock signal terminal CK is a high-low level switching clock pulse signal
  • the second control clock pulse signal loaded on the second control clock signal terminal CKB is also high and low power.
  • Clock pulse signal for level switching is also high and low power.
  • the first control clock signal and the second control clock signal have the same period and have a phase difference of 1/2 period.
  • the duty ratio of the first control clock signal and the second control clock signal are the same, and the duty ratio is greater than 50%.
  • the specific implementations of the first control clock pulse signal and the second control clock pulse signal can be designed and determined according to the requirements of the actual application, and are not limited herein.
  • applying a fixed voltage signal to the input signal terminal IP may specifically include: applying a fixed voltage signal having a second level to the input signal terminal IP.
  • ip represents the signal loaded by the input signal terminal IP.
  • the transistor in the shift register is a P-type transistor, a fixed voltage signal with a high level can be applied to the input signal terminal IP.
  • the transistor in the shift register is an N-type transistor, a fixed voltage signal with a low level can be applied to the input signal terminal IP.
  • controlling the cascade signal terminal GP to output a fixed voltage signal and the driving signal terminal OP to output a fixed voltage signal may specifically include: controlling the cascade signal terminal GP to output The fixed voltage signal with the second level and the control driving signal terminal OP output the fixed voltage signal with the first level.
  • gp represents the signal output by the cascade signal terminal GP
  • op represents the signal output by the driving signal terminal OP.
  • the transistor in the shift register is a P-type transistor
  • the cascade signal terminal GP can be controlled to output a fixed voltage signal with a high level and the drive signal terminal OP can be controlled to output a fixed voltage signal with a low level.
  • the cascade signal terminal GP can be controlled to output a fixed voltage signal with a low level and the drive signal terminal OP can be controlled to output a fixed voltage signal with a high level.
  • the pulse level of the input signal can be set to the first level.
  • the eighth transistor M8 when the eighth transistor M8 is turned on, the pulse level of the input signal can be input to the first pull-up node PU_1, so that the level of the first pull-up node PU_1 is the first level, which can pass through the first pull-up node PU_1.
  • Pulling the level of node PU_1 controls the tenth transistor M10 to turn on.
  • FIGS. 1 and 3 when the transistor in the shift register is a P-type transistor, the pulse level of the input signal is a low level.
  • the transistor in the shift register is an N-type transistor, the pulse level of the input signal is high.
  • the pulse level of the cascaded signal can be set to the first level.
  • the fourth transistor M4 can be turned on under the control of the pulse level of the cascade signal to provide the signal of the second reference signal terminal VREF2 to the driving signal terminal OP.
  • the pulse level of the cascade signal is low.
  • the pulse level of the cascade signal is high.
  • the fixed voltage signal of the first reference signal terminal VREF1 can be at the first level
  • the fixed voltage signal of the second reference signal terminal VREF2 can be at the second level
  • the pulse of the driving signal The level is the second level.
  • the first level is a low level and the second level is a high level.
  • the transistor in the shift register is an N-type transistor
  • the first level is a high level and the second level is a low level.
  • the noise reduction clock signal terminal may include a first noise reduction clock signal terminal CKO and a second noise reduction clock signal terminal CKBO.
  • the noise reduction clock signal includes a first noise reduction clock signal and a second noise reduction clock signal; wherein, the periods of the first noise reduction clock signal and the second noise reduction clock signal are both the second clock period, and the phases The difference is 1/2 cycle.
  • loading the noise reduction clock signal terminal with the noise reduction clock signal may specifically include: loading the first noise reduction clock signal terminal CKO with the first noise reduction clock signal terminal CKO, and loading the second noise reduction clock signal The signal terminal CKBO is loaded with the second noise reduction clock pulse signal.
  • cko represents the signal loaded by the first noise reduction clock signal terminal CKO
  • ckbo represents the signal loaded by the second noise reduction clock signal terminal CKBO.
  • the first noise reduction clock pulse signal loaded by the first noise reduction clock signal terminal CKO is a high-low level switching clock pulse signal
  • the second noise reduction clock signal terminal CKBO loads the second noise reduction clock pulse signal It is also a clock pulse signal for switching between high and low levels.
  • the periods of the first noise reduction clock signal and the second noise reduction clock signal are the same and the phase difference is 1/2 period.
  • the duty cycle of the first noise reduction clock signal and the second noise reduction clock signal are the same, and the duty cycle is greater than 50%.
  • the specific implementation of the first noise reduction clock signal and the second noise reduction clock signal can be designed and determined according to the requirements of the actual application, and is not limited here.
  • the first clock period of the first noise reduction clock signal and the second clock period of the first control clock signal can be made the same, that is, the first clock period and the second clock period are the same .
  • the duty ratio of the first noise reduction clock signal can be made the same as the duty ratio of the first control clock signal.
  • the falling edge of the first noise reduction clock signal is aligned with the rising edge of the second clock signal.
  • the falling edge of the second noise reduction clock signal is aligned with the rising edge of the first control clock signal.
  • the relationship between the first noise reduction clock signal, the second noise reduction clock signal, the first control clock signal, and the second control clock signal can be designed and determined according to actual requirements. This is not limited.
  • the first setting signal in the data retention phase, is loaded to the control clock signal terminal, and the first setting signal has the first setting level; wherein, the control clock pulse level and the first setting signal A set level is the same, and the sustaining duration of the first set level in the first clock cycle is greater than the sustaining duration of the control clock pulse level in the first clock cycle.
  • ck represents the signal loaded by the first control clock signal terminal CK
  • ckb represents the signal loaded by the second control clock signal terminal CKB.
  • a first setting signal of a fixed voltage signal is applied to the first control clock signal terminal CK.
  • the first set level is the first level
  • the first control clock pulse signal loaded on the first control clock signal terminal CK and the second control clock pulse signal loaded on the second control clock signal terminal CKB are the control clocks
  • the pulse level is also the first level.
  • the first level as a low level as an example, as shown in FIG. 3, since the first setting signal is continuously at a low level during the data retention phase, that is, the signal loaded by the first control clock signal terminal CK is in the data retention phase. Medium continues to be low, and the signal loaded by the second control clock signal terminal CKB continues to be low during the data retention phase. Therefore, the sustaining duration of the first set level in the first clock cycle can be longer than the sustaining duration of the control clock pulse level in the first clock cycle, so that the power consumption of the shift register can be reduced.
  • the control clock pulse level is also the second level.
  • the first setting signal continues to be at a high level during the data retention phase. Therefore, the first setting level can be set in the first clock cycle.
  • the sustaining duration of is longer than the sustaining duration of the control clock pulse level in the first clock cycle, so that the power consumption of the shift register can be reduced.
  • a second setting signal is loaded to the noise reduction clock signal terminal, and the second setting signal has a second setting level; wherein, the noise reduction clock pulse circuit The level is the same as the second set level, and the sustaining duration of the second set level in the second clock cycle is greater than the sustaining duration of the noise reduction clock pulse level in the second clock cycle.
  • the second setting signal may be a fixed voltage signal.
  • the noise reduction clock pulse level is also the second level. Taking the first level as a low level as an example, as shown in Fig.
  • the second setting signal is continuously at a low level during the data retention phase, that is, the signal loaded by the first noise reduction clock signal terminal CKO is in the data retention period. During the phase, it continues to be low, and the signal loaded by the second noise reduction clock signal terminal CKBO continues to be low during the data retention phase, so that the power consumption of the shift register can be reduced.
  • the noise reduction clock pulse level is also the second level.
  • the second level as a high level as an example, as shown in Figure 6, the second setting signal continues to be at a high level during the data retention phase. Therefore, the second setting level can be set in the second clock cycle.
  • the sustaining duration of is greater than the sustaining duration of the noise reduction clock pulse level in the second clock cycle, so that the power consumption of the shift register can be reduced.
  • one display frame may include a data refresh phase T10 and a data retention phase T20.
  • the signal timing diagram shown in FIG. 3 is only the working process of a shift register in a current display frame.
  • the working process of the shift register in other display frames is basically the same as the working process in the current display frame, and will not be repeated here.
  • the transistor M10 is turned on, thereby providing the low-level signal of the first control clock signal terminal CK to the pull-down node PD, and further makes the signal of the pull-down node PD a low-level signal.
  • the first transistor M1 Since the first transistor M1 satisfies V gs1 ⁇ V th1 , the first transistor M1 is turned on.
  • the turned-on first transistor M1 conducts the second pull-up node PU_2 and the first pull-up node PU_1, so that the signal of the second pull-up node PU_2 can be a low-level signal in time to control the sixth transistor M6 to turn on Therefore, the high-level signal of the second control clock signal terminal CKB is provided to the cascade signal terminal GP, so that the cascade signal terminal GP outputs a high-level cascade signal. Since the cascade signal terminal GP outputs a high-level signal, the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the third transistor M3 is turned on to provide the low-level signal of the first reference signal terminal VREF1 to the gate of the fifth transistor M5, thereby controlling the fifth transistor M5 to turn on to turn on the first reference signal terminal VREF1.
  • the low-level signal of the signal terminal VREF1 is provided to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the second pull-up node PU_2 maintains a low-level signal under the action of the third capacitor C3 to control the sixth transistor M6 to turn on, so as to provide the low-level signal of the second control clock signal terminal CKB to the cascade signal terminal GP, make the cascade signal terminal GP output a low-level cascade signal.
  • the cascade signal terminal GP outputs a low-level cascade signal.
  • one pole of the first transistor M1 coupled to the first pull-up node PU_1 serves as its source, so that the first transistor M1 cannot satisfy V gs1 ⁇ V th1 , so that the first transistor M1 is turned off.
  • the level of the second pull-up node PU_2 can be kept stable, and the situation that the level of the second pull-up node PU_2 rises due to electric leakage, which causes the output of the cascaded signal terminal GP to be unstable, can be avoided.
  • the tenth transistor M10 provides the high level signal of the first control clock signal terminal CK to the pull-down node PD under the control of the signal of the first pull-up node PU_1, so as to control the seventh transistor M7 to turn off, so as to avoid interference with the cascaded signal.
  • the turned-on second transistor M2 can provide the high-level signal of the second reference signal terminal VREF2 to the gate of the fifth transistor M5 to control the fifth transistor M5 to turn off.
  • the turned-on fourth transistor M4 can provide the high-level signal of the second reference signal terminal VREF2 to the driving signal terminal OP, so that the driving signal terminal OP outputs a high-level driving signal.
  • the second pull-up node PU_2 maintains a low-level signal under the action of the third capacitor C3 to control the sixth transistor M6 to turn on, so as to provide the high-level signal of the second control clock signal terminal CKB to the cascade signal terminal GP, make the cascade signal terminal GP output a high-level cascade signal to control both the second transistor M2 and the fourth transistor M4 to be turned off.
  • the third transistor M3 Since the signal cko of the first noise reduction clock signal terminal CKO changes from a high level to a low level, the third transistor M3 is turned on, so that the low level signal of the first reference signal terminal VREF1 can be provided to the fifth transistor M5 And control the fifth transistor M5 to turn on to provide the low-level signal of the first reference signal terminal VREF1 to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the turned-on eighth transistor M8 provides the high-level signal of the input signal terminal IP to the first pull-up node PU_1, so that the first pull-up node PU_1 is a high-level signal to control the tenth transistor M10 to turn off. Since the first reference signal terminal VREF1 is a low-level signal, the first transistor M1 is turned on to provide the high-level signal of the first pull-up node PU_1 to the second pull-up node PU_2 to control the sixth transistor M6 to turn off .
  • the turned-on ninth transistor M9 provides the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal to control the seventh transistor M7 to turn on.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the cascaded signal terminal GP, so that the cascaded signal terminal GP outputs a high-level signal to control the second transistor M2 and the fourth transistor M4 is all cut off.
  • the third transistor M3 is turned on, so that the low-level signal of the first reference signal terminal VREF1 can be provided to the gate of the fifth transistor M5, and then the fifth transistor M5 is controlled to be turned on to turn on the first
  • the low-level signal of the reference signal terminal VREF1 is provided to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the first capacitor C1 and the second capacitor C2 maintain a stable voltage difference across them.
  • the eighth transistor M8 and the ninth transistor M9 are both turned off, and the signal of the pull-down node PD can be maintained as a low-level signal due to the effect of the fourth capacitor C4, and the seventh transistor M7 is controlled to be turned on to turn on
  • the high-level signal of the second reference signal terminal VREF2 is provided to the cascaded signal terminal GP, so that the cascaded signal terminal GP outputs a high-level signal to control both the second transistor M2 and the fourth transistor M4 to be turned off.
  • the third transistor M3 is turned on, so that the low-level signal of the first reference signal terminal VREF1 can be provided to the gate of the fifth transistor M5, and the fifth transistor M5 is controlled to be turned on to turn on the first reference signal terminal VREF1.
  • the low-level signal of the reference signal terminal VREF1 is provided to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the eleventh transistor M11 and the twelfth transistor M12 are both turned on, so that the first pull-up node PU_1 can be a high-level signal, and the second pull-up node PU_2 can be a high-level signal to control the sixth
  • the transistor M6 is off.
  • the eighth transistor M8 and the ninth transistor M9 are both turned on.
  • the turned-on eighth transistor M8 inputs the high-level signal of the input signal terminal IP to the first pull-up node PU_1 to make the first pull-up node PU_1 a high-level signal to control the sixth transistor M6 to turn off.
  • the turned-on ninth transistor M9 provides the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal to control the seventh transistor M7 to turn on.
  • the signal output by the drive signal terminal OP of the shift register shown in FIG. 1 is simulated, and the simulation simulation diagram is shown in FIG. 4.
  • the abscissa represents time
  • the ordinate represents voltage
  • S1 represents the signal used to simulate the driving signal terminal OP of the shift register shown in FIG. 1 by using the signal timing diagram shown in FIG. 3. 3 and 4, it can be seen that the embodiment of the present disclosure can stabilize the output signal of the driving signal terminal OP by setting the first setting signal and the second setting signal in the data retention stage.
  • the shift register shown in FIG. 1 is driven to work according to the signal timing diagram shown in FIG. 3, and the power consumption of the shift register is detected to be 0.4 mW when the work is performed in the data holding phase T20. Therefore, it can be seen that the power consumption of the shift register can also be within an acceptable range.
  • 1 represents a high-level signal
  • 0 represents a low-level signal.
  • 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. It is not the voltage applied to the gate of each transistor during implementation.
  • one display frame may include a data refresh stage T10.
  • the signal timing diagram shown in FIG. 5 is only the working process of a shift register in a current display frame.
  • the working process of the shift register in other display frames is basically the same as the working process in the current display frame, and will not be repeated here.
  • the data refresh phase T10 includes a T11 phase, a T12 phase, a T13 phase, and a T14 phase.
  • the working process of the above-mentioned shift register provided in the embodiment of the present disclosure in the signal timing diagram shown in FIG. 5 is basically the same as the working process in the data refresh phase T10 in the signal timing diagram shown in FIG. 3, and will not be repeated here.
  • one display frame may include a data refresh phase T10 and a data retention phase T20.
  • the signal timing diagram shown in FIG. 6 is only the working process of a shift register in a current display frame.
  • the working process of the shift register in other display frames is basically the same as the working process in the current display frame, and will not be repeated here.
  • the data refresh stage T10 includes the T11 stage, the T12 stage, the T13 stage, and the T14 stage.
  • the working process of the above-mentioned shift register provided in the embodiment of the present disclosure in the signal timing diagram shown in FIG. 6 is basically the same as the working process in the data refresh phase T10 in the signal timing diagram shown in FIG. 3, and will not be repeated here.
  • both the eighth transistor M8 and the ninth transistor M9 are turned off.
  • the third capacitor C3 maintains the second pull-up node PU_2 as a high-level signal to control the sixth transistor M6 to turn off.
  • the fourth capacitor C4 keeps the pull-down node PD as a low-level signal, and therefore controls the seventh transistor M7 to be turned on.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the cascade signal terminal GP, so that the cascade signal terminal GP outputs a high-level signal.
  • the embodiments of the present disclosure provide other driving methods, which are modified with respect to the implementation in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments are described below, and the similarities are not repeated here.
  • the first setting signal can be a clock pulse signal
  • the first setting level is one of the first level and the second level
  • the first setting signal may also be a clock pulse signal that switches between high and low levels.
  • the first setting signal has a third clock period t03, and the third clock period t03 includes a duration of a first level and a duration of a second level in the first setting signal, and a third clock period t03 may be greater than the first clock period t01.
  • the first set level is the first level.
  • the sustaining duration of the first level in the first setting signal in the first clock cycle is greater than the sustaining duration of the first level in the control clock pulse signal in the first clock cycle.
  • the high level in one period of the first setting signal has a longer duration in the first clock period t01 than in the control clock pulse signal.
  • the sustaining duration of the high level in one period of the first setting signal in the third clock period t03 is longer than the sustaining duration of the high level in one period of the control clock pulse signal in the first clock period t01 duration.
  • the first set level is the second level.
  • the sustaining duration of the second level in the first setting signal in the first clock cycle is greater than the sustaining duration of the second level in the control clock pulse signal in the first clock cycle.
  • the second level as a low level as an example
  • the low level in one cycle of the first setting signal has a longer duration in the first clock cycle t01 than in the control clock pulse signal.
  • the sustaining duration of the low level in one period in the first setting signal in the third clock period t03 is longer than the sustaining time of the low level in one period in the control clock pulse signal in the first clock period t01 duration.
  • the second setting signal can be a clock pulse signal
  • the second setting level is one of the first level and the second level
  • the second setting signal may also be a clock pulse signal that switches between high and low levels.
  • the second setting signal has a fourth clock period t04, and the fourth clock period t04 includes a duration of a first level and a duration of a second level in the second setting signal, and a fourth clock period t04 may be greater than the second clock period t02.
  • the second set level is the first level.
  • the sustaining duration of the first level in the second setting signal in the second clock cycle is greater than the sustaining duration of the first level in the noise reduction clock pulse signal in the second clock cycle.
  • the high level in a period of the second setting signal is maintained for a longer period of time in the second clock period t02 than the noise reduction clock pulse signal
  • the duration of the high level in one period in the second clock period t02 is maintained.
  • the duration of the high level in one period of the second setting signal in the fourth clock period t04 is greater than the duration of the high level in one period in the noise reduction clock signal in the second clock period t02. Maintain time.
  • the second set level is the second level.
  • the sustaining duration of the second level in the second setting signal in the second clock cycle is greater than the sustaining duration of the second level in the noise reduction clock pulse signal in the second clock cycle.
  • the second level in one period in the second setting signal is maintained for a longer time in the second clock period t02 than the noise reduction clock pulse signal
  • the duration of the low level in one period in the second setting signal in the fourth clock period t04 is longer than the low level in one period in the noise reduction clock pulse signal in the second clock period t02 Maintain time.
  • the third clock period t03 of the first setting signal can be made the same as the fourth clock period t04 of the second setting signal, so that the coupling interference of the signal can be reduced.
  • 1 represents a high-level signal
  • 0 represents a low-level signal.
  • 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. It is not the voltage applied to the gate of each transistor during implementation.
  • one display frame may include a data refresh phase T10 and a data retention phase T20.
  • the signal timing diagram shown in FIG. 7 is only the working process of a shift register in a current display frame.
  • the working process of the shift register in other display frames is basically the same as the working process in the current display frame, and will not be repeated here.
  • the working process in the data retention phase T20 is basically the same as the working process after the T14 phase in the data refresh phase T10. The difference is that the high and low level switching of the signal ckb, the signal ck, the signal cko, and the signal ckbo is lower than the frequency in the data refresh phase T10, and the specific working process is not described here.
  • the signal output by the drive signal terminal OP of the shift register shown in FIG. 1 is simulated and the simulation diagram is shown in FIG. 8.
  • the abscissa represents time
  • the ordinate represents voltage
  • S2 represents a signal used to simulate the driving signal terminal OP of the shift register shown in FIG. 1 by using the signal timing diagram shown in FIG. 7. It can be seen from FIG. 7 and FIG. 8 that, by setting the first setting signal and the second setting signal in the data retention stage, the embodiment of the present disclosure can make the output signal of the driving signal terminal OP stable.
  • the shift register shown in FIG. 1 is driven to work according to the signal timing chart shown in FIG. 7.
  • the data holding phase T20 it is detected that the power consumption of the shift register is 0.7 mW. Therefore, it can be seen that even if a clock pulse is inserted in the data holding phase T20, the power consumption of the shift register can be within an acceptable range.
  • the embodiment of the present disclosure also provides a gate control circuit, as shown in FIG. 9, including any of the above-mentioned shift registers SR(1), SR(2)...SR(n-1) provided by multiple cascaded embodiments of the present disclosure. ), SR(n)...SR(N-1), SR(N) (a total of N shift registers, 1 ⁇ n ⁇ N, n is an integer); among them, the first-stage shift register SR(1)
  • the input signal terminal IP is configured to be coupled to the frame trigger signal terminal STV;
  • the input signal terminal IP of the next stage shift register SR(n) is configured to be coupled to the cascade signal output terminal GP of the previous stage shift register SR(n-1) .
  • each shift register in the above-mentioned gate control circuit is the same in function and structure as the above-mentioned shift register of the present disclosure, and the repetition is not repeated here.
  • the gate control circuit can be configured in a liquid crystal display panel or in an electroluminescent display panel, which is not limited here.
  • the first reference signal terminal VREF1 of the shift registers of each stage is coupled to the same first DC signal terminal
  • the second reference signal terminal of the shift register of each stage is coupled to the same first DC signal terminal.
  • the signal terminals VREF2 are all coupled to the same second DC signal terminal.
  • the first control clock signal terminal CK of the shift register of the odd-numbered stage and the second control clock signal terminal CKB of the shift register of the even-numbered stage are both identical to the same clock.
  • the terminal is coupled to the first control clock terminal.
  • the second control clock signal terminal CKB of the odd-numbered shift register and the first control clock signal terminal CK of the even-numbered shift register are both coupled to the same clock terminal, that is, the second control clock terminal.
  • the first noise reduction clock signal terminal CKO of the odd-numbered shift register and the second noise reduction clock signal terminal CKBO of the even-numbered shift register are both connected to The same clock terminal is coupled to the first noise reduction clock terminal.
  • the second noise reduction clock signal terminal CKBO of the odd-number stage shift register and the first noise reduction clock signal terminal CKO of the even-number stage shift register are both coupled to the same clock terminal, that is, the second noise reduction clock terminal.
  • one display frame includes a data refresh phase and a data retention phase;
  • the drive circuit is configured as:
  • a fixed voltage signal is applied to the input signal terminal, the first setting signal is applied to the control clock signal terminal, the second setting signal is applied to the noise reduction clock signal terminal, and the first voltage signal is applied to the first reference signal terminal.
  • Level fixed voltage signal load a fixed voltage signal with a second level to the second reference signal terminal, control the cascade signal terminal to output a fixed voltage signal with the second level and control the drive signal terminal to output a fixed voltage signal with the first level Fixed voltage signal;
  • control clock pulse signal has a first level, a second level, and a first clock period;
  • first setting signal has a first setting level; wherein, the first clock period includes one of the first control clock pulse signals.
  • the duration of the level and the duration of a second level, one of the first level and the second level in the control clock pulse signal is the control clock pulse level, and the control clock pulse level is the same as the first set level, And the sustaining duration of the first set level in the first clock cycle is greater than the sustaining duration of the control clock pulse level in the first clock cycle; and/or,
  • the noise reduction clock signal has a first level, a second level, and a second clock period; the second setting signal has a second setting level; wherein, the second clock period includes one of the first noise reduction clock signals.
  • the duration of the level and the duration of a second level, one of the first level and the second level in the noise reduction clock signal is the noise reduction clock pulse level, the noise reduction clock pulse level and the second set voltage
  • the level is the same, and the sustaining duration of the second set level in the second clock cycle is greater than the sustaining duration of the noise reduction clock pulse level in the second clock cycle.
  • a display frame includes a data refresh phase; the driving circuit is further configured to: load an input signal with a pulse level to the input signal terminal during the data refresh phase Signal, load a control clock pulse signal to the control clock signal terminal, load a noise reduction clock pulse signal to the noise reduction clock signal terminal, load a fixed voltage signal with a first level to the first reference signal terminal, and load a second reference signal terminal
  • the cascade signal terminal of the shift register is controlled to output a cascade signal with a pulse level
  • the drive signal terminal of the shift register is controlled to output a drive signal with a pulse level.
  • the working process of the driving circuit can refer to the process of the above-mentioned driving method, which will not be repeated here.
  • an embodiment of the present disclosure also provides a display panel, including the above-mentioned gate driving circuit and the above-mentioned driving circuit provided by the embodiment of the present disclosure.
  • the driving circuit is electrically connected with a plurality of shift registers.
  • the principle of solving the problems of the display panel is similar to that of the aforementioned driving circuit. Therefore, the implementation of the display panel can refer to the implementation of the aforementioned driving circuit, and the repetitive parts will not be repeated here.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure.
  • the principle of the display device to solve the problem is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned display panel, and the repetitive parts will not be repeated here.
  • the above-mentioned display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, and should not be used as a limitation to the present disclosure.

Abstract

本公开实施例提供的移位寄存器的驱动方法及装置，在数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，控制移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制移位寄存器的驱动信号端输出具有脉冲电平的驱动信号; 在数据保持阶段，对输入信号端加载固定电压信号，对控制时钟信号端加载第一设定信号，对降噪时钟信号端加载第二设定信号，控制级联信号端输出具有第二电平的固定电压信号以及控制驱动信号端输出具有第一电平的固定电压信号。

Description

移位寄存器的驱动方法及装置
相关申请的交叉引用
本申请要求在2020年06月17日提交中国专利局、申请号为202010552721.9、申请名称为“移位寄存器的驱动方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及移位寄存器的驱动方法及装置。
背景技术
随着显示技术的飞速发展，显示装置越来越向着高集成度和低成本的方向发展。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)栅极控制电路集成在显示装置的阵列基板上以形成对显示装置的扫描驱动。其中，栅极控制电路通常由多个级联的移位寄存器构成。然而，移位寄存器的功耗较高，会导致显示装置功耗较高。
发明内容
本公开实施例提供的移位寄存器的驱动方法，包括：在第一刷新频率时，一个显示帧包括数据刷新阶段和数据保持阶段；
在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号；
在所述数据保持阶段，对所述输入信号端加载固定电压信号，对所述控 制时钟信号端加载第一设定信号，对所述降噪时钟信号端加载第二设定信号，对所述第一参考信号端加载具有所述第一电平的固定电压信号，对所述第二参考信号端加载具有所述第二电平的固定电压信号，控制所述级联信号端输出具有所述第二电平的固定电压信号以及控制所述驱动信号端输出具有所述第一电平的固定电压信号；
其中，所述控制时钟脉冲信号具有第一电平和第二电平以及第一时钟周期；所述第一设定信号具有第一设定电平；其中，所述第一时钟周期包括所述控制时钟脉冲信号中的一个所述第一电平的时长和一个所述第二电平的时长，所述控制时钟脉冲信号中的所述第一电平和所述第二电平中的一个为控制时钟脉冲电平，所述控制时钟脉冲电平和所述第一设定电平相同，且所述第一设定电平在所述第一时钟周期中的维持时长大于所述控制时钟脉冲电平在所述第一时钟周期中的维持时长；和/或，
所述降噪时钟脉冲信号具有第一电平和第二电平以及第二时钟周期；所述第二设定信号具有第二设定电平；其中，所述第二时钟周期包括所述降噪时钟脉冲信号中的一个所述第一电平的时长和一个所述第二电平的时长，所述降噪时钟脉冲信号中的所述第一电平和所述第二电平中的一个为降噪时钟脉冲电平，所述降噪时钟脉冲电平和所述第二设定电平相同，且所述第二设定电平在所述第二时钟周期中的维持时长大于所述降噪时钟脉冲电平在所述第二时钟周期中的维持时长。
在一些示例中，所述第一设定信号为时钟脉冲信号，所述第一设定电平为所述第一电平和所述第二电平中的一个。
在一些示例中，所述第一设定信号的第三时钟周期大于所述第一时钟周期；
其中，所述第三时钟周期包括所述第一设定信号中的一个所述第一电平的时长和一个所述第二电平的时长。
在一些示例中，所述第一设定信号中的第一电平在所述第一时钟周期中的维持时长大于所述控制时钟脉冲信号中的第一电平在所述第一时钟周期中 的维持时长；
所述第一设定信号中的第二电平在所述第一时钟周期中的维持时长大于所述控制时钟脉冲信号中的第二电平在所述第一时钟周期中的维持时长。
在一些示例中，所述第二设定信号为时钟脉冲信号，所述第二设定电平为所述第一电平和所述第二电平中的一个。
在一些示例中，所述第二设定信号的第四时钟周期大于所述第二时钟周期；
其中，所述第四时钟周期包括所述第二设定信号中的一个所述第一电平的时长和一个所述第二电平的时长。
在一些示例中，所述第二设定信号中的第一电平在所述第二时钟周期中的维持时长大于所述降噪时钟脉冲信号中的第一电平在所述第二时钟周期中的维持时长；
所述第二设定信号中的第二电平在所述第二时钟周期中的维持时长大于所述降噪时钟脉冲信号中的第二电平在所述第二时钟周期中的维持时长。
在一些示例中，所述第一设定信号的第三时钟周期和所述第二设定信号的第四时钟周期相同。
在一些示例中，所述第一设定信号和所述第二设定信号中的至少一个为固定电压信号；
所述第一设定电平和所述第二设定信号中的至少一个为所述第一电平和所述第二电平中的一个。
在一些示例中，所述第一电平为高电平，所述第二电平为低电平；或者，
所述第一电平为低电平，所述第二电平为高电平。
在一些示例中，所述驱动方法还包括：在第二刷新频率时，一个显示帧包括数据刷新阶段；
在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考 信号端加载具有第二电平的固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号。
本公开实施例提供了移位寄存器的驱动电路，在第一刷新频率时，一个显示帧包括数据刷新阶段和数据保持阶段；
所述驱动电路被配置为：
在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号；
在所述数据保持阶段，对所述输入信号端加载固定电压信号，对所述控制时钟信号端加载第一设定信号，对所述降噪时钟信号端加载第二设定信号，对所述第一参考信号端加载具有所述第一电平的固定电压信号，对所述第二参考信号端加载具有所述第二电平的固定电压信号，控制所述级联信号端输出具有所述第二电平的固定电压信号以及控制所述驱动信号端输出具有所述第一电平的固定电压信号；
其中，所述控制时钟脉冲信号具有第一电平和第二电平以及第一时钟周期；所述第一设定信号具有第一设定电平；其中，所述第一时钟周期包括所述控制时钟脉冲信号中的一个所述第一电平的时长和一个所述第二电平的时长，所述控制时钟脉冲信号中的所述第一电平和所述第二电平中的一个为控制时钟脉冲电平，所述控制时钟脉冲电平和所述第一设定电平相同，且所述第一设定电平在所述第一时钟周期中的维持时长大于所述控制时钟脉冲电平在所述第一时钟周期中的维持时长；和/或，
所述降噪时钟脉冲信号具有第一电平和第二电平以及第二时钟周期；所述第二设定信号具有第二设定电平；其中，所述第二时钟周期包括所述降噪 时钟脉冲信号中的一个所述第一电平的时长和一个所述第二电平的时长，所述降噪时钟脉冲信号中的所述第一电平和所述第二电平中的一个为降噪时钟脉冲电平，所述降噪时钟脉冲电平和所述第二设定电平相同，且所述第二设定电平在所述第二时钟周期中的维持时长大于所述降噪时钟脉冲电平在所述第二时钟周期中的维持时长。
在一些示例中，在第二刷新频率时，一个显示帧包括数据刷新阶段；
所述驱动电路进一步被配置为：
在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号。
本公开实施例提供了显示面板，包括栅极驱动电路和所述的驱动电路；其中，所述栅极驱动电路包括级联的多个移位寄存器；
所述驱动电路与所述多个移位寄存器电连接。
本公开实施例提供了显示装置，其中，包括显示面板。
附图说明
图1为本公开实施例提供的移位寄存器的结构示意图；
图2为本公开实施例提供的驱动方法的流程图；
图3为本公开实施例提供的一些信号时序图；
图4为本公开实施例提供的一些仿真模拟图；
图5为本公开实施例提供的另一些信号时序图；
图6为本公开实施例提供的又一些信号时序图；
图7为本公开实施例提供的又一些信号时序图；
图8为本公开实施例提供的另一些仿真模拟图；
图9为本公开实施例提供的一些栅极控制电路的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
通常情况下为了降低显示装置的功耗，可以使显示装置采用较低刷新频率(如1Hz)进行驱动，由于晶体管长时间漏电积累，从而导致驱动信号端输出的信号出现异常。
本公开实施例提供了一些移位寄存器，如图1所示，可以包括：
第一晶体管M1，第一晶体管M1的栅极被配置为与第一参考信号端VREF1耦接，第一晶体管M1的第一极被配置为与第一上拉节点PU_1耦接，第一晶体管M1的第二极被配置为与第二上拉节点PU_2耦接；
第二晶体管M2，第二晶体管M2的栅极与级联信号端GP耦接，第二晶 体管M2的第一极与第二参考信号端VREF2耦接，第二晶体管M2的第二极与第五晶体管M5的栅极耦接；
第三晶体管M3，第三晶体管M3的栅极与第一降噪时钟信号端CKO耦接，第三晶体管M3的第一极与第一参考信号端VREF1耦接，第三晶体管M3的第二极与第五晶体管M5的栅极耦接；
第四晶体管M4，第四晶体管M4的栅极与级联信号端GP耦接，第四晶体管M4的第一极与第二参考信号端VREF2耦接，第四晶体管M4的第二极与驱动信号端OP耦接；
第五晶体管M5，第五晶体管M5的第一极与第一参考信号端VREF1耦接，第五晶体管M5的第二极与驱动信号端OP耦接；
第一电容C1，第一电容C1的第一电极与第二降噪时钟信号端CKBO耦接，第一电容C1的第二电极与第五晶体管M5的栅极耦接；
第二电容C2，第二电容C2的第一电极与第五晶体管M5的栅极耦接，第一电容C1的第二电极与驱动信号端OP耦接；
第六晶体管M6，第六晶体管M6的栅极与第二上拉节点PU_2耦接，第六晶体管M6的第一极与第二控制时钟信号端CKB耦接，第六晶体管M6的第二极与级联信号端GP耦接；
第七晶体管M7，第七晶体管M7的栅极与下拉节点PD耦接，第七晶体管M7的第一极与第二参考信号端VREF2耦接，第七晶体管M7的第二极与级联信号端GP耦接；
第三电容C3，第三电容C3的第一电极与第二上拉节点PU_2耦接，第三电容C3的第二电极与级联信号端GP耦接；
第四电容C4，第四电容C4的第一电极与下拉节点PD耦接，第四电容C4的第二电极与第二参考信号端VREF2耦接；
第八晶体管M8，第八晶体管M8的栅极与第一控制时钟信号端CK耦接，第八晶体管M8的第一极与输入信号端IP耦接，第八晶体管M8的第二极与第一上拉节点PU_1耦接；
第九晶体管M9，第九晶体管M9的栅极与第一控制时钟信号端CK耦接，第九晶体管M9的第一极与第一参考信号端VREF1耦接，第九晶体管M9的第二极与下拉节点PD耦接；
第十晶体管M10，第十晶体管M10的栅极与第一上拉节点PU_1耦接，第十晶体管M10的第一极与第一控制时钟信号端CK耦接，第十晶体管M10的第二极与下拉节点PD耦接；
第十一晶体管M11，第十一晶体管M11的栅极与下拉节点PD耦接，第十一晶体管M11的第一极与第二参考信号端VREF2耦接，第十一晶体管M11的第二极与第十二晶体管M12的第一极耦接；
第十二晶体管M12，第十二晶体管M12的栅极与第二控制时钟信号端CKB耦接，第十二晶体管M12的第二极与第一上拉节点PU_1耦接。
在具体实施时，如图1所示，第一上拉节点PU_1耦接于第八晶体管M8的第二极与第一晶体管M1的第一极之间。第二上拉节点PU_2耦接于第六晶体管M6的栅极与第一晶体管M1的第二极之间。下拉节点PD耦接于第九晶体管M9的第二极与第七晶体管M7的栅极之间。需要说明的是，第一上拉节点PU_1、第二上拉节点PU_2以及下拉节点PD分别是移位寄存器中的虚拟节点，这三个节点仅是为了方便对移位寄存器的结构和信号的传输进行描述，而针对移位寄存器的具体结构和信号的传输，可以根据移位寄存器中的各晶体管与电容之间的耦接方式来进行确定。
本公开实施例提供的移位寄存器，通过对各信号端加载相应的信号，以使各晶体管和电容相互配合工作，可以使级联信号端和驱动信号端分别输出相应的信号。并且，还可以使移位寄存器的功耗降低，从而可以有利于本申请中的移位寄存器应用于较低刷新频率的显示装置中。
在具体实施时，根据信号的流通方向，上述晶体管的第一极可以作为其源极，第二极可以作为其漏极；或者，第一极作为其漏极，第二极作为其源极，在此不作具体区分。
需要说明的是，本公开上述实施例中提到的晶体管可以是TFT，也可以 是金属氧化物半导体场效应管(Metal Oxide Semiconductor，MOS)，在此不作限定。
为了简化制备工艺，在具体实施时，在本公开实施例中，如图1所示，可以使所有晶体管均为P型晶体管。其中，P型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系V gs<V th时导通。例如，第三晶体管M3为P型晶体管时，则第三晶体管M3在其栅极与其源极之间的电压差V gs3与其阈值电压V th3之间的关系满足公式：V gs3<V th3时导通。当然，在本公开实施例中，仅是以晶体管为P型晶体管为例进行说明的，对于晶体管为N型晶体管的情况，设计原理与本公开相同，也属于本公开保护的范围。并且，N型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系V gs>V th时导通。例如第三晶体管M3为N型晶体管时，第三晶体管M3在其栅极与其源极之间的电压差V gs3与其阈值电压V th3之间的关系满足公式：V gs3>V th3时导通。
进一步的，在具体实施时，P型晶体管在高电平信号作用下截止，在低电平信号作用下导通。N型晶体管在高电平信号作用下导通，在低电平信号作用下截止。
在具体实施时，可以使第四晶体管M4、第五晶体管M5、第六晶体管M6以及第七晶体管M7中的至少一个晶体管的有源层的沟道区的宽长比大于第一晶体管M1、第二晶体管M2、第三晶体管M3、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11以及第十二晶体管M12中的至少一个晶体管的有源层的沟道区的宽长比。示例性地，可以使第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比大于第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管 M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比。
在具体实施时，可以使第四晶体管M4、第五晶体管M5、第六晶体管M6以及第七晶体管M7中的至少一个晶体管的有源层的沟道区的宽长比的范围为10μm/2μm～100μm/10μm。示例性地，可以使第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比的范围分别为10μm/2μm～100μm/10μm。例如，可以使第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比的范围分别为10μm/2μm。也可以使第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比的范围分别为100μm/10μm。也可以使第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比的范围分别为50μm/5μm。
当然，在实际应用中，可以根据实际应用的需求具体设计第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比的数值，在此不作限定。
在具体实施时，可以使第一晶体管M1、第二晶体管M2、第三晶体管M3、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11以及第十二晶体管M12中的至少一个晶体管的有源层的沟道区的宽长比的范围为2μm/2μm～20μm/10μm。示例性地，可以使第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、 第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比的范围为2μm/2μm～20μm/10μm。例如，可以使第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比的范围为2μm/2μm。也可以使第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比的范围为20μm/10μm。也可以使第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比的范围为10μm/5μm。
当然，在实际应用中，可以根据实际应用的需求具体设计第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比的数值，在此不作限定。
在具体实施时，可以使第一电容C1、第二电容C2、第三电容C3以及第四电容C4中的至少一个电容的电容值的范围为10fF～1pF。示例性地，可以使 第一电容C1、第二电容C2、第三电容C3以及第四电容C4中的至少一个电容的电容值的范围为10fF。也可以使第一电容C1、第二电容C2、第三电容C3以及第四电容C4中的至少一个电容的电容值的范围为50fF。也可以使第一电容C1、第二电容C2、第三电容C3以及第四电容C4中的至少一个电容的电容值的范围为1pF。当然，在实际应用中，可以根据实际应用的需求具体设计第一电容C1的电容值、第二电容C2的电容值、第三电容C3的电容值以及第四电容C4的电容值，在此不作限定。
以上仅是举例说明本公开实施例提供的移位寄存器的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
本公开实施例还提供了移位寄存器的驱动方法，结合图2与图3所示，在第一刷新频率时，一个显示帧包括数据刷新阶段T10和数据保持阶段T20；
该驱动方法可以包括如下步骤：
S210、在数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制移位寄存器的驱动信号端输出具有脉冲电平的驱动信号；
S220、在数据保持阶段，对输入信号端加载固定电压信号，对控制时钟信号端加载第一设定信号，对降噪时钟信号端加载第二设定信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制级联信号端输出具有第二电平的固定电压信号以及控制驱动信号端输出具有第一电平的固定电压信号。
本公开实施例提供的移位寄存器的驱动方法，在数据刷新阶段T10，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载 具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制移位寄存器的驱动信号端输出具有脉冲电平的驱动信号。这样可以实现移位寄存器的级联输出和驱动输出，从而可以使显示装置进行数据刷新。
并且，在数据保持阶段，对输入信号端加载固定电压信号，对控制时钟信号端加载第一设定信号，对降噪时钟信号端加载第二设定信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制级联信号端输出具有第二电平的固定电压信号以及控制驱动信号端输出具有第一电平的固定电压信号。
示例性地，控制时钟脉冲信号是具有第一电平和第二电平的时钟脉冲信号，并且由第一电平和第二电平交替切换进行的。并且，控制时钟脉冲信号具有第一时钟周期，在第一时钟周期中进行第一电平和第二电平之间的切换。则第一时钟周期包括控制时钟脉冲信号中的一个第一电平的时长和一个第二电平的时长。控制时钟脉冲信号中的第一电平和第二电平中的一个可以为控制时钟脉冲电平，第一设定信号具有第一设定电平；其中，控制时钟脉冲电平和第一设定电平相同，且第一设定电平在第一时钟周期中的维持时长大于控制时钟脉冲电平在第一时钟周期中的维持时长。这样可以使数据保持阶段中第一设定信号的电平切换的频率降低，从而可以降低功耗。
示例性地，降噪时钟脉冲信号是具有第一电平和第二电平的时钟脉冲信号，并且由第一电平和第二电平交替切换进行的。并且，降噪时钟脉冲信号具有第二时钟周期，在第二时钟周期中进行第一电平和第二电平之间的切换。则第二时钟周期包括降噪时钟脉冲信号中的一个第一电平的时长和一个第二电平的时长。降噪时钟脉冲信号中的第一电平和第二电平中的一个可以为降噪时钟脉冲电平，第二设定信号具有第二设定电平；其中，降噪时钟脉冲电平和第二设定电平相同，且第二设定电平在第二时钟周期中的维持时长大于降噪时钟脉冲电平在第二时钟周期中的维持时长。这样可以使数据保持阶段中第二设定信号的电平切换的频率降低，从而可以降低功耗。
一般显示装置可能会长时间处于静态画面的显示状态，或者待机状态，为了降低功耗，可以使显示装置采用较低的刷新频率(例如1Hz、30Hz)工作。本公开实施例中的移位寄存器，通过加载数据保持阶段中第一设定信号和第二设定信号，可以降低功耗，从而有利于本申请中的移位寄存器应用于较低刷新频率的显示装置中。
在具体实施时，在本公开实施例中，第一电平可以为低电平，第二电平可以为高电平。或者，第一电平也可以为高电平，第二电平也可以为低电平。在实际应用中，可以根据实际应用需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，驱动方法还包括：在第二刷新频率时，一个显示帧包括数据刷新阶段T10；其中，在数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制移位寄存器的驱动信号端输出具有脉冲电平的驱动信号。
一般显示装置可能会长时间处于静态画面的显示状态，或者待机状态，为了降低功耗，可以使显示装置采用较低的刷新频率(例如1Hz、30Hz)工作。当然，显示装置也可以显示视频画面，为了提高视频画面的显示效果，可以使显示装置采用较高的刷新频率(例如60Hz、120Hz)进行工作。在具体实施时，在本公开实施例中，第一刷新频率可以为较低刷新频率，例如1Hz、30Hz。第二刷新频率可以为较高刷新频率，例如60Hz、120Hz。
在具体实施时，在本公开实施例中，控制时钟信号端包括第一控制时钟信号端CK和第二控制时钟信号端CKB；控制时钟脉冲信号包括第一控制时钟脉冲信号和第二控制时钟脉冲信号；其中，第一控制时钟脉冲信号和第二控制时钟脉冲信号的周期均为第一时钟周期，且相位差为1/2周期。并且，在数据刷新阶段T10，对控制时钟信号端加载控制时钟脉冲信号，具体可以包括：对第一控制时钟信号端CK加载第一控制时钟脉冲信号，以及对第二控制时钟 信号端CKB加载第二控制时钟脉冲信号。
示例性地，如图1与图3所示，ck代表第一控制时钟信号端CK加载的信号，ckb代表第二控制时钟信号端CKB加载的信号。在数据刷新阶段T10，第一控制时钟信号端CK加载的第一控制时钟脉冲信号为高低电平切换的时钟脉冲信号，第二控制时钟信号端CKB加载的第二控制时钟脉冲信号也为高低电平切换的时钟脉冲信号。并且，第一控制时钟脉冲信号和第二控制时钟脉冲信号的周期相同且相位差为1/2周期。例如，第一控制时钟脉冲信号和第二控制时钟脉冲信号的占空比相同，且占空比大于50％。当然，在实际应用中，第一控制时钟脉冲信号和第二控制时钟脉冲信号的具体实施方式可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，在数据保持阶段中，对输入信号端IP加载固定电压信号，具体可以包括：对输入信号端IP加载具有第二电平的固定电压信号。示例性地，如图1与图3所示，ip代表输入信号端IP加载的信号。在移位寄存器中的晶体管为P型晶体管时，可以对输入信号端IP加载具有高电平的固定电压信号。在移位寄存器中的晶体管为N型晶体管时，可以对输入信号端IP加载具有低电平的固定电压信号。
在具体实施时，在本公开实施例中，在数据保持阶段中，控制级联信号端GP输出固定电压信号以及控制驱动信号端OP输出固定电压信号，具体可以包括：控制级联信号端GP输出具有第二电平的固定电压信号以及控制驱动信号端OP输出具有第一电平的固定电压信号。示例性地，如图1与图3所示，gp代表级联信号端GP输出的信号，op代表驱动信号端OP输出的信号。在移位寄存器中的晶体管为P型晶体管时，可以控制级联信号端GP输出具有高电平的固定电压信号以及控制驱动信号端OP输出具有低电平的固定电压信号。在移位寄存器中的晶体管为N型晶体管时，可以控制级联信号端GP输出具有低电平的固定电压信号以及控制驱动信号端OP输出具有高电平的固定电压信号。
在具体实施时，在本公开实施例中，可以使输入信号的脉冲电平为第一 电平。这样在第八晶体管M8导通时，可以将输入信号的脉冲电平输入到第一上拉节点PU_1，以使第一上拉节点PU_1的电平为第一电平，从而可以通过第一上拉节点PU_1的电平控制第十晶体管M10导通。示例性地，如图1与图3所示，在移位寄存器中的晶体管为P型晶体管时，输入信号的脉冲电平为低电平。在移位寄存器中的晶体管为N型晶体管时，输入信号的脉冲电平为高电平。
在具体实施时，在本公开实施例中，可以使级联信号的脉冲电平为第一电平。这样可以使第四晶体管M4在级联信号的脉冲电平的控制下导通，以将第二参考信号端VREF2的信号提供给驱动信号端OP。示例性地，如图1与图3所示，在移位寄存器中的晶体管为P型晶体管时，级联信号的脉冲电平为低电平。在移位寄存器中的晶体管为N型晶体管时，级联信号的脉冲电平为高电平。
在具体实施时，在本公开实施例中，可以使第一参考信号端VREF1的固定电压信号为第一电平，第二参考信号端VREF2的固定电压信号为第二电平，驱动信号的脉冲电平为第二电平。示例性地，如图1与图3所示，在移位寄存器中的晶体管为P型晶体管时，第一电平为低电平且第二电平为高电平。在移位寄存器中的晶体管为N型晶体管时，第一电平为高电平且第二电平为低电平。
在具体实施时，在本公开实施例中，降噪时钟信号端可以包括第一降噪时钟信号端CKO和第二降噪时钟信号端CKBO。降噪时钟脉冲信号包括第一降噪时钟脉冲信号和第二降噪时钟脉冲信号；其中，第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的周期均为第二时钟周期，且相位差为1/2周期。并且，在数据刷新阶段T10，对降噪时钟信号端加载降噪时钟脉冲信号，具体可以包括：对第一降噪时钟信号端CKO加载第一降噪时钟脉冲信号，以及对第二降噪时钟信号端CKBO加载第二降噪时钟脉冲信号。
示例性地，如图1与图3所示，cko代表第一降噪时钟信号端CKO加载的信号，ckbo代表第二降噪时钟信号端CKBO加载的信号。在数据刷新阶段 T10，第一降噪时钟信号端CKO加载的第一降噪时钟脉冲信号为高低电平切换的时钟脉冲信号，第二降噪时钟信号端CKBO加载的第二降噪时钟脉冲信号也为高低电平切换的时钟脉冲信号。并且，第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的周期相同且相位差为1/2周期。例如，第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的占空比相同，且占空比大于50％。当然，在实际应用中，第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的具体实施方式可以根据实际应用的需求进行设计确定，在此不作限定。
在一些示例中，如图3所示，可以使第一降噪时钟脉冲信号的第一时钟周期和第一控制时钟脉冲信号的第二时钟周期相同，即第一时钟周期和第二时钟周期相同。进一步地，可以使第一降噪时钟脉冲信号的占空比和第一控制时钟脉冲信号的占空比相同。示例性地，第一降噪时钟脉冲信号的下降沿与第二时钟脉冲信号的上升沿对齐。第二降噪时钟脉冲信号的下降沿与第一控制时钟脉冲信号的上升沿对齐。当然，在实际应用中，第一降噪时钟脉冲信号、第二降噪时钟脉冲信号、第一控制时钟脉冲信号以及第二控制时钟脉冲信号之间的关系，可以根据实际需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，在数据保持阶段，对控制时钟信号端加载第一设定信号，第一设定信号具有第一设定电平；其中，控制时钟脉冲电平和第一设定电平相同，且第一设定电平在第一时钟周期中的维持时长大于控制时钟脉冲电平在第一时钟周期中的维持时长。示例性地，如图1与图3所示，ck代表第一控制时钟信号端CK加载的信号，ckb代表第二控制时钟信号端CKB加载的信号。在数据保持阶段T20，对第一控制时钟信号端CK加载固定电压信号的第一设定信号。例如，第一设定电平为第一电平，则第一控制时钟信号端CK加载的第一控制时钟脉冲信号和第二控制时钟信号端CKB加载的第二控制时钟脉冲信号中的控制时钟脉冲电平也为第一电平。以第一电平为低电平为例，如图3所示，由于第一设定信号在数据保持阶段中持续为低电平，即第一控制时钟信号端CK加载的信号在数据保持阶段中持续为低电平，以及第二控制时钟信号端CKB加载的信号在数据保持阶段中持续 为低电平。因此，可以使第一设定电平在第一时钟周期中的维持时长大于控制时钟脉冲电平在第一时钟周期中的维持时长，从而可以降低移位寄存器的功耗。
例如，第一设定电平为第二电平时，控制时钟脉冲电平也为第二电平。以第二电平为高电平为例，如图6所示，第一设定信号在数据保持阶段中持续为高电平，因此，可以使第一设定电平在第一时钟周期中的维持时长大于控制时钟脉冲电平在第一时钟周期中的维持时长，从而可以降低移位寄存器的功耗。
在具体实施时，在本公开实施例中，在数据保持阶段，对降噪时钟信号端加载第二设定信号，第二设定信号具有第二设定电平；其中，降噪时钟脉冲电平和第二设定电平相同，且第二设定电平在第二时钟周期中的维持时长大于降噪时钟脉冲电平在第二时钟周期中的维持时长。示例性地，如图1与图3所示，第二设定信号可以为固定电压信号。例如，第二设定电平为第一电平时，降噪时钟脉冲电平也为第二电平。以第一电平为低电平为例，如图3所示，由于第二设定信号在数据保持阶段中持续为低电平，即第一降噪时钟信号端CKO加载的信号在数据保持阶段中持续为低电平，以及第二降噪时钟信号端CKBO加载的信号在数据保持阶段中持续为低电平，从而可以降低移位寄存器的功耗。
例如，第二设定电平为第二电平时，降噪时钟脉冲电平也为第二电平。以第二电平为高电平为例，如图6所示，第二设定信号在数据保持阶段中持续为高电平，因此，可以使第二设定电平在第二时钟周期中的维持时长大于降噪时钟脉冲电平在第二时钟周期中的维持时长，从而可以降低移位寄存器的功耗。
下面以图1所示的移位寄存器为例，结合图3所示的信号时序图，对本公开实施例提供的上述移位寄存器，在第一刷新频率时的工作过程作以描述。下述描述中以1表示高电平，0表示低电平，需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是在具体实 施时施加在各晶体管的栅极上的电压。
具体地，如图3所示，在第一刷新频率时，一个显示帧可以包括数据刷新阶段T10和数据保持阶段T20。需要说明的是，图3所示的信号时序图仅是一个移位寄存器在一个当前显示帧中的工作过程。该移位寄存器在其他显示帧中的工作过程分别与该当前显示帧中的工作过程基本相同，在此不作赘述。
其中，数据刷新阶段T10包括T11阶段、T12阶段、T13阶段以及T14阶段。具体地，在T11阶段中，ip＝0，ckb＝1，ck＝0，cko＝0，ckbo＝1。由于ckb＝1，因此第十二晶体管M12截止。由于ck＝0，因此第九晶体管M9导通，以将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第七晶体管M7导通。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号。由于ck＝0，因此第八晶体管M8导通，以将输入信号端IP的低电平信号提供给第一上拉节点PU_1，使第一上拉节点PU_1为低电平信号，以控制第十晶体管M10导通，从而将第一控制时钟信号端CK的低电平信号提供给下拉节点PD，进一步使下拉节点PD的信号为低电平信号。由于第一晶体管M1满足V gs1<V th1，以使第一晶体管M1导通。导通的第一晶体管M1将第二上拉节点PU_2与第一上拉节点PU_1导通，从而可以及时使第二上拉节点PU_2的信号为低电平信号，以控制第六晶体管M6导通，从而将第二控制时钟信号端CKB的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的级联信号。由于级联信号端GP输出高电平的信号，可以控制第二晶体管M2和第四晶体管M4截止。由于cko＝0，因此第三晶体管M3导通，以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，从而控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。
在T12阶段中，ip＝1，ckb＝0，ck＝1，cko＝1，ckbo＝0。由于ck＝1，因此第九晶体管M9和第八晶体管M8均截止。第二上拉节点PU_2在第三电容 C3的作用下保持为低电平信号，以控制第六晶体管M6导通，从而将第二控制时钟信号端CKB的低电平信号提供给级联信号端GP，使级联信号端GP输出低电平的级联信号。由于第三电容C3的作用，使第二上拉节点PU_2的电平进一步拉低，以控制第六晶体管M6可以尽可能充分导通，以将第二控制时钟信号端CKB的低电平信号提供给级联信号端GP，使级联信号端GP输出低电平的级联信号。并且，此阶段中，第一晶体管M1与第一上拉节点PU_1耦接的一极作为其源极，从而可以使第一晶体管M1不能满足V gs1<V th1，以使第一晶体管M1截止，从而可以保持第二上拉节点PU_2的电平稳定，避免由于漏电导致第二上拉节点PU_2的电平升高，而导致的级联信号端GP输出不稳定的情况。
并且，第十晶体管M10在第一上拉节点PU_1的信号的控制下将第一控制时钟信号端CK的高电平信号提供给下拉节点PD，以控制第七晶体管M7截止，避免对级联信号端GP输出的信号造成不利影响。由于cko＝1，因此第三晶体管M3截止。由于级联信号端GP输出低电平的信号，可以控制第二晶体管M2和第四晶体管M4导通。导通的第二晶体管M2可以将第二参考信号端VREF2的高电平信号提供给第五晶体管M5的栅极，以控制第五晶体管M5截止。导通的第四晶体管M4可以将第二参考信号端VREF2的高电平信号提供给驱动信号端OP，使驱动信号端OP输出高电平的驱动信号。
在T12阶段之后，在T13阶段之前，由于ckb＝1，因此第十二晶体管M12截止。由于ck＝1，因此第九晶体管M9和第八晶体管M8均截止。第二上拉节点PU_2在第三电容C3的作用下保持为低电平信号，以控制第六晶体管M6导通，从而将第二控制时钟信号端CKB的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的级联信号，以控制第二晶体管M2和第四晶体管M4均截止。由于第一降噪时钟信号端CKO的信号cko由高电平转变为低电平，因此第三晶体管M3导通，从而可以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，进而控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信 号端OP输出低电平的驱动信号。
在T13阶段中，ip＝1，ckb＝1，ck＝0，cko＝0，ckbo＝1。
由于ckb＝1，因此第十二晶体管M12截止。由于ck＝0，第八晶体管M8和第九晶体管M9均导通。导通的第八晶体管M8将输入信号端IP的高电平信号提供给第一上拉节点PU_1，使第一上拉节点PU_1为高电平信号，以控制第十晶体管M10截止。由于第一参考信号端VREF1为低电平信号，因此第一晶体管M1导通，以将第一上拉节点PU_1的高电平信号提供给第二上拉节点PU_2，以控制第六晶体管M6截止。导通的第九晶体管M9将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第七晶体管M7导通。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号，以控制第二晶体管M2和第四晶体管M4均截止。由于cko＝0，因此第三晶体管M3导通，从而可以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，进而控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。并且，通过第一电容C1和第二电容C2保持其两端的电压差稳定。
在T14阶段中，ip＝1，ckb＝0，ck＝1，cko＝1，ckbo＝0。
由于ck＝1，因此第八晶体管M8和第九晶体管M9均截止，则由于第四电容C4的作用可以将下拉节点PD的信号保持为低电平信号，控制第七晶体管M7导通，以将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号，以控制第二晶体管M2和第四晶体管M4均截止。由于cko＝0，因此第三晶体管M3导通，从而可以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，进而控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。并且，第十一晶体管M11和第十二晶体管M12均导通，从而可以使第一上拉节点PU_1为高电平信号， 进而使第二上拉节点PU_2为高电平信号，以控制第六晶体管M6截止。
在T14阶段之后，一直重复执行T13阶段和T14阶段的工作过程，直至进入去噪保持阶段T21-1。
在数据保持阶段T20，ip＝1，ckb＝0，ck＝0，cko＝0，ckbo＝0。由于ck＝0，因此第八晶体管M8和第九晶体管M9均导通。导通的第八晶体管M8将输入信号端IP的高电平信号输入给第一上拉节点PU_1，使第一上拉节点PU_1为高电平信号，以控制第六晶体管M6截止。导通的第九晶体管M9将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第七晶体管M7导通。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号。由于级联信号端GP输出高电平的信号，可以控制第二晶体管M2和第四晶体管M4截止。由于cko＝0，因此第三晶体管M3导通，以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，从而控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。
需要说明的是，在实际应用中，上述各信号的具体电压值可以根据实际应用环境来设计确定，在此不作限定。
并且，还根据图3所示的信号时序图，对图1所示的移位寄存器的驱动信号端OP输出的信号进行仿真模拟，仿真模拟图如图4所示。其中，横坐标代表时间，纵坐标代表电压。S1代表采用图3所示的信号时序图对图1所示的移位寄存器的驱动信号端OP进行仿真模拟的信号。结合图3与图4可知，本公开实施例通过设置数据保持阶段中第一设定信号和第二设定信号，可以使驱动信号端OP稳定的输出信号。
并且，还根据图3所示的信号时序图驱动图1所示的移位寄存器进行工作，在数据保持阶段T20进行工作时，检测到移位寄存器的功耗为0.4mW。因此可知，移位寄存器的功耗也可以在可接受范围之内。
下面以图1所示的移位寄存器为例，结合图5所示的信号时序图对本公 开实施例提供的上述移位寄存器在第二刷新频率时的工作过程作以描述。下述描述中以1表示高电平信号，0表示低电平信号，需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是在具体实施时施加在各晶体管的栅极上的电压。
具体地，如图5所示，在第二刷新频率时，一个显示帧可以包括数据刷新阶段T10。需要说明的是，图5所示的信号时序图仅是一个移位寄存器在一个当前显示帧中的工作过程。该移位寄存器在其他显示帧中的工作过程分别与该当前显示帧中的工作过程基本相同，在此不作赘述。
数据刷新阶段T10包括T11阶段、T12阶段、T13阶段以及T14阶段。并且，本公开实施例提供的上述移位寄存器在图5所示的信号时序图的工作过程与在图3所示的信号时序图中数据刷新阶段T10的工作过程基本相同，在此不作赘述。
下面以图1所示的移位寄存器为例，结合图6所示的信号时序图对本公开实施例提供的上述移位寄存器在第一刷新频率时的工作过程作以描述。
具体地，如图6所示，在第一刷新频率时，一个显示帧可以包括数据刷新阶段T10和数据保持阶段T20。需要说明的是，图6所示的信号时序图仅是一个移位寄存器在一个当前显示帧中的工作过程。该移位寄存器在其他显示帧中的工作过程分别与该当前显示帧中的工作过程基本相同，在此不作赘述。
其中，数据刷新阶段T10包括T11阶段、T12阶段、T13阶段以及T14阶段。并且，本公开实施例提供的上述移位寄存器在图6所示的信号时序图的工作过程与在图3所示的信号时序图中数据刷新阶段T10的工作过程基本相同，在此不作赘述。
在数据保持阶段T20，ip＝1，ckb＝1，ck＝1，cko＝1，ckbo＝1。由于ck＝1，因此第八晶体管M8和第九晶体管M9均截止。第三电容C3保持第二上拉节点PU_2为高电平信号，以控制第六晶体管M6截止。第四电容C4保持下拉节点PD为低电平信号，因此控制第七晶体管M7导通。导通的第七晶体管 M7将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号。由于级联信号端GP输出高电平的信号，可以控制第二晶体管M2和第四晶体管M4截止。由于cko＝1，因此第三晶体管M3截止。由于第二电容C2的作用，可以保持控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。
本公开实施例又提供了另一些驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图7所示，可以使第一设定信号为时钟脉冲信号，则第一设定电平为第一电平和第二电平中的一个，即第一设定信号也可以为高低电平切换的时钟脉冲信号。其中，第一设定信号具有第三时钟周期t03，并且，第三时钟周期t03包括第一设定信号中的一个第一电平的时长和一个第二电平的时长，以及第三时钟周期t03可以大于第一时钟周期t01。
示例性地，第一设定电平为第一电平。第一设定信号中的第一电平在第一时钟周期中的维持时长大于控制时钟脉冲信号中的第一电平在第一时钟周期中的维持时长。例如，如图7所示，以第一电平为高电平为例，第一设定信号中的一个周期内的高电平在第一时钟周期t01中的维持时长大于控制时钟脉冲信号中的一个周期内的高电平在第一时钟周期t01中的维持时长。进一步地，第一设定信号中的一个周期内的高电平在第三时钟周期t03中的维持时长大于控制时钟脉冲信号中的一个周期内的高电平在第一时钟周期t01中的维持时长。
示例性地，第一设定电平为第二电平。第一设定信号中的第二电平在第一时钟周期中的维持时长大于控制时钟脉冲信号中的第二电平在第一时钟周期中的维持时长。例如，如图7所示，以第二电平为低电平为例，第一设定信号中的一个周期内的低电平在第一时钟周期t01中的维持时长大于控制时 钟脉冲信号中的一个周期内的低电平在第一时钟周期t01中的维持时长。进一步地，第一设定信号中的一个周期内的低电平在第三时钟周期t03中的维持时长大于控制时钟脉冲信号中的一个周期内的低电平在第一时钟周期t01中的维持时长。
在具体实施时，在本公开实施例中，如图7所示，可以使第二设定信号为时钟脉冲信号，则第二设定电平为第一电平和第二电平中的一个，即第二设定信号也可以为高低电平切换的时钟脉冲信号。其中，第二设定信号具有第四时钟周期t04，并且，第四时钟周期t04包括第二设定信号中的一个第一电平的时长和一个第二电平的时长，以及第四时钟周期t04可以大于第二时钟周期t02。
示例性地，第二设定电平为第一电平。第二设定信号中的第一电平在第二时钟周期中的维持时长大于降噪时钟脉冲信号中的第一电平在第二时钟周期中的维持时长。例如，如图7所示，以第一电平为高电平为例，第二设定信号中的一个周期内的高电平在第二时钟周期t02中的维持时长大于降噪时钟脉冲信号中的一个周期内的高电平在第二时钟周期t02中的维持时长。进一步地，第二设定信号中的一个周期内的高电平在第四时钟周期t04中的维持时长大于降噪时钟脉冲信号中的一个周期内的高电平在第二时钟周期t02中的维持时长。
示例性地，第二设定电平为第二电平。第二设定信号中的第二电平在第二时钟周期中的维持时长大于降噪时钟脉冲信号中的第二电平在第二时钟周期中的维持时长。例如，如图7所示，以第二电平为低电平为例，第二设定信号中的一个周期内的低电平在第二时钟周期t02中的维持时长大于降噪时钟脉冲信号中的一个周期内的低电平在第二时钟周期t02中的维持时长。进一步地，第二设定信号中的一个周期内的低电平在第四时钟周期t04中的维持时长大于降噪时钟脉冲信号中的一个周期内的低电平在第二时钟周期t02中的维持时长。
示例性地，可以使第一设定信号的第三时钟周期t03和第二设定信号的第 四时钟周期t04相同，这样可以降低信号的耦合干扰。
下面以图1所示的移位寄存器为例，结合图7所示的信号时序图对本公开实施例提供的上述移位寄存器在第一刷新频率时的工作过程作以描述。下述描述中以1表示高电平信号，0表示低电平信号，需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是在具体实施时施加在各晶体管的栅极上的电压。
具体地，如图7所示，在第一刷新频率时，一个显示帧可以包括数据刷新阶段T10和数据保持阶段T20。需要说明的是，图7所示的信号时序图仅是一个移位寄存器在一个当前显示帧中的工作过程。该移位寄存器在其他显示帧中的工作过程分别与该当前显示帧中的工作过程基本相同，在此不作赘述。
在数据刷新阶段T10的工作过程可以参照上述工作过程，在此不作赘述。
在数据保持阶段T20中的工作过程与数据刷新阶段T10中的T14阶段之后的工作过程基本相同。其不同之处在于，信号ckb、信号ck、信号cko以及信号ckbo的高低电平切换相比数据刷新阶段T10中的频率降低了，具体工作过程在此不作赘述。
并且，还根据图7所示的信号时序图，对图1所示的移位寄存器的驱动信号端OP输出的信号进行仿真模拟，仿真模拟图如图8所示。其中，横坐标代表时间，纵坐标代表电压。S2代表采用图7所示的信号时序图对图1所示的移位寄存器的驱动信号端OP进行仿真模拟的信号。结合图7与图8可知，本公开实施例通过设置数据保持阶段中第一设定信号和第二设定信号，可以使驱动信号端OP稳定的输出信号。
并且，还根据图7所示的信号时序图驱动图1所示的移位寄存器进行工作，在数据保持阶段T20进行工作时，检测到移位寄存器的功耗为0.7mW。因此可知，即使在数据保持阶段T20中插入了时钟脉冲，移位寄存器的功耗也可以在可接受范围之内。
本公开实施例还提供了栅极控制电路，如图9所示，包括级联的多个本 公开实施例提供的上述任意移位寄存器SR(1)、SR(2)…SR(n-1)、SR(n)…SR(N-1)、SR(N)(共N个移位寄存器，1≤n≤N，n为整数)；其中，第一级移位寄存器SR(1)的输入信号端IP被配置为与帧触发信号端STV耦接；
每相邻两个移位寄存器中，下一级移位寄存器SR(n)的输入信号端IP被配置为与上一级移位寄存器SR(n-1)的级联信号输出端GP耦接。
具体地，上述栅极控制电路中的每个移位寄存器的具体结构与本公开上述移位寄存器在功能和结构上均相同，重复之处不再赘述。该栅极控制电路可以应被配置为液晶显示面板中，也可以应被配置为电致发光显示面板中，在此不作限定。
具体地，在本公开实施例提供的上述栅极控制电路中，各级移位寄存器的第一参考信号端VREF1均与同一第一直流信号端耦接，各级移位寄存器的第二参考信号端VREF2均与同一第二直流信号端耦接。
具体地，在本公开实施例提供的上述栅极控制电路中，第奇数级移位寄存器的第一控制时钟信号端CK和第偶数级移位寄存器的第二控制时钟信号端CKB均与同一时钟端即第一控制时钟端耦接。第奇数级移位寄存器的第二控制时钟信号端CKB和第偶数级移位寄存器的第一控制时钟信号端CK均与同一时钟端即第二控制时钟端耦接。
具体地，在本公开实施例提供的上述栅极控制电路中，第奇数级移位寄存器的第一降噪时钟信号端CKO和第偶数级移位寄存器的第二降噪时钟信号端CKBO均与同一时钟端即第一降噪时钟端耦接。第奇数级移位寄存器的第二降噪时钟信号端CKBO和第偶数级移位寄存器的第一降噪时钟信号端CKO均与同一时钟端即第二降噪时钟端耦接。
基于同一公开构思，本公开实施例还提供了移位寄存器的驱动电路，中，在第一刷新频率时，一个显示帧包括数据刷新阶段和数据保持阶段；
驱动电路被配置为：
在数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信 号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制移位寄存器的驱动信号端输出具有脉冲电平的驱动信号；
在数据保持阶段，对输入信号端加载固定电压信号，对控制时钟信号端加载第一设定信号，对降噪时钟信号端加载第二设定信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制级联信号端输出具有第二电平的固定电压信号以及控制驱动信号端输出具有第一电平的固定电压信号；
其中，控制时钟脉冲信号具有第一电平和第二电平以及第一时钟周期；第一设定信号具有第一设定电平；其中，第一时钟周期包括控制时钟脉冲信号中的一个第一电平的时长和一个第二电平的时长，控制时钟脉冲信号中的第一电平和第二电平中的一个为控制时钟脉冲电平，控制时钟脉冲电平和第一设定电平相同，且第一设定电平在第一时钟周期中的维持时长大于控制时钟脉冲电平在第一时钟周期中的维持时长；和/或，
降噪时钟脉冲信号具有第一电平和第二电平以及第二时钟周期；第二设定信号具有第二设定电平；其中，第二时钟周期包括降噪时钟脉冲信号中的一个第一电平的时长和一个第二电平的时长，降噪时钟脉冲信号中的第一电平和第二电平中的一个为降噪时钟脉冲电平，降噪时钟脉冲电平和第二设定电平相同，且第二设定电平在第二时钟周期中的维持时长大于降噪时钟脉冲电平在第二时钟周期中的维持时长。
在具体实施时，在本公开实施例中，在第二刷新频率时，一个显示帧包括数据刷新阶段；驱动电路进一步被配置为：在数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制移位寄 存器的驱动信号端输出具有脉冲电平的驱动信号。
需要说明的是，驱动电路的工作过程可以参考上述的驱动方法的过程，在此不作赘述。
基于同一公开构思，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述栅极驱动电路和上述驱动电路。其中，驱动电路与多个移位寄存器电连接。
该显示面板解决问题的原理与前述驱动电路相似，因此该显示面板的实施可以参见前述驱动电路的实施，重复之处在此不再赘述。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (15)

  1. 一种移位寄存器的驱动方法，其中，包括：在第一刷新频率时，一个显示帧包括数据刷新阶段和数据保持阶段；
    在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号；
    在所述数据保持阶段，对所述输入信号端加载固定电压信号，对所述控制时钟信号端加载第一设定信号，对所述降噪时钟信号端加载第二设定信号，对所述第一参考信号端加载具有所述第一电平的固定电压信号，对所述第二参考信号端加载具有所述第二电平的固定电压信号，控制所述级联信号端输出具有所述第二电平的固定电压信号以及控制所述驱动信号端输出具有所述第一电平的固定电压信号；
    其中，所述控制时钟脉冲信号具有第一电平和第二电平以及第一时钟周期；所述第一设定信号具有第一设定电平；其中，所述第一时钟周期包括所述控制时钟脉冲信号中的一个所述第一电平的时长和一个所述第二电平的时长，所述控制时钟脉冲信号中的所述第一电平和所述第二电平中的一个为控制时钟脉冲电平，所述控制时钟脉冲电平和所述第一设定电平相同，且所述第一设定电平在所述第一时钟周期中的维持时长大于所述控制时钟脉冲电平在所述第一时钟周期中的维持时长；和/或，
    所述降噪时钟脉冲信号具有第一电平和第二电平以及第二时钟周期；所述第二设定信号具有第二设定电平；其中，所述第二时钟周期包括所述降噪时钟脉冲信号中的一个所述第一电平的时长和一个所述第二电平的时长，所述降噪时钟脉冲信号中的所述第一电平和所述第二电平中的一个为降噪时钟 脉冲电平，所述降噪时钟脉冲电平和所述第二设定电平相同，且所述第二设定电平在所述第二时钟周期中的维持时长大于所述降噪时钟脉冲电平在所述第二时钟周期中的维持时长。
  2. 如权利要求1所述的驱动方法，其中，所述第一设定信号为时钟脉冲信号，所述第一设定电平为所述第一电平和所述第二电平中的一个。
  3. 如权利要求2所述的驱动方法，其中，所述第一设定信号的第三时钟周期大于所述第一时钟周期；
    其中，所述第三时钟周期包括所述第一设定信号中的一个所述第一电平的时长和一个所述第二电平的时长。
  4. 如权利要求2或3所述的驱动方法，其中，所述第一设定信号中的第一电平在所述第一时钟周期中的维持时长大于所述控制时钟脉冲信号中的第一电平在所述第一时钟周期中的维持时长；
    所述第一设定信号中的第二电平在所述第一时钟周期中的维持时长大于所述控制时钟脉冲信号中的第二电平在所述第一时钟周期中的维持时长。
  5. 如权利要求1-4任一项所述的驱动方法，其中，所述第二设定信号为时钟脉冲信号，所述第二设定电平为所述第一电平和所述第二电平中的一个。
  6. 如权利要求5所述的驱动方法，其中，所述第二设定信号的第四时钟周期大于所述第二时钟周期；
    其中，所述第四时钟周期包括所述第二设定信号中的一个所述第一电平的时长和一个所述第二电平的时长。
  7. 如权利要求5或6所述的驱动方法，其中，所述第二设定信号中的第一电平在所述第二时钟周期中的维持时长大于所述降噪时钟脉冲信号中的第一电平在所述第二时钟周期中的维持时长；
    所述第二设定信号中的第二电平在所述第二时钟周期中的维持时长大于所述降噪时钟脉冲信号中的第二电平在所述第二时钟周期中的维持时长。
  8. 如权利要求6或7所述的驱动方法，其中，所述第一设定信号的第三时钟周期和所述第二设定信号的第四时钟周期相同。
  9. 如权利要求1所述的驱动方法，其中，所述第一设定信号和所述第二设定信号中的至少一个为固定电压信号；
    所述第一设定电平和所述第二设定信号中的至少一个为所述第一电平和所述第二电平中的一个。
  10. 如权利要求1-9任一项所述的驱动方法，其中，所述第一电平为高电平，所述第二电平为低电平；或者，
    所述第一电平为低电平，所述第二电平为高电平。
  11. 如权利要求1-10任一项所述的驱动方法，其中，所述驱动方法还包括：在第二刷新频率时，一个显示帧包括数据刷新阶段；
    在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号。
  12. 一种移位寄存器的驱动电路，其中，在第一刷新频率时，一个显示帧包括数据刷新阶段和数据保持阶段；
    所述驱动电路被配置为：
    在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号；
    在所述数据保持阶段，对所述输入信号端加载固定电压信号，对所述控制时钟信号端加载第一设定信号，对所述降噪时钟信号端加载第二设定信号，对所述第一参考信号端加载具有所述第一电平的固定电压信号，对所述第二 参考信号端加载具有所述第二电平的固定电压信号，控制所述级联信号端输出具有所述第二电平的固定电压信号以及控制所述驱动信号端输出具有所述第一电平的固定电压信号；
    其中，所述控制时钟脉冲信号具有第一电平和第二电平以及第一时钟周期；所述第一设定信号具有第一设定电平；其中，所述第一时钟周期包括所述控制时钟脉冲信号中的一个所述第一电平的时长和一个所述第二电平的时长，所述控制时钟脉冲信号中的所述第一电平和所述第二电平中的一个为控制时钟脉冲电平，所述控制时钟脉冲电平和所述第一设定电平相同，且所述第一设定电平在所述第一时钟周期中的维持时长大于所述控制时钟脉冲电平在所述第一时钟周期中的维持时长；和/或，
    所述降噪时钟脉冲信号具有第一电平和第二电平以及第二时钟周期；所述第二设定信号具有第二设定电平；其中，所述第二时钟周期包括所述降噪时钟脉冲信号中的一个所述第一电平的时长和一个所述第二电平的时长，所述降噪时钟脉冲信号中的所述第一电平和所述第二电平中的一个为降噪时钟脉冲电平，所述降噪时钟脉冲电平和所述第二设定电平相同，且所述第二设定电平在所述第二时钟周期中的维持时长大于所述降噪时钟脉冲电平在所述第二时钟周期中的维持时长。
  13. 如权利要求12所述的驱动电路，其中，在第二刷新频率时，一个显示帧包括数据刷新阶段；
    所述驱动电路进一步被配置为：
    在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载具有第一电平的固定电压信号，对第二参考信号端加载具有第二电平的固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号。
  14. 一种显示面板，其中，包括栅极驱动电路和如权利要求12或13所 述的驱动电路；其中，所述栅极驱动电路包括级联的多个移位寄存器；
    所述驱动电路与所述多个移位寄存器电连接。
  15. 一种显示装置，其中，包括如权利要求14所述的显示面板。
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