WO2021223565A1 - 移位寄存器、驱动方法、驱动控制电路及显示装置 - Google Patents

移位寄存器、驱动方法、驱动控制电路及显示装置 Download PDF

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Publication number
WO2021223565A1
WO2021223565A1 PCT/CN2021/086119 CN2021086119W WO2021223565A1 WO 2021223565 A1 WO2021223565 A1 WO 2021223565A1 CN 2021086119 W CN2021086119 W CN 2021086119W WO 2021223565 A1 WO2021223565 A1 WO 2021223565A1
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Prior art keywords
transistor
signal terminal
signal
noise reduction
coupled
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PCT/CN2021/086119
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English (en)
French (fr)
Inventor
商广良
张洁
黄硕
刘利宾
史世明
刘浩
郑皓亮
姚星
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/628,779 priority Critical patent/US11862098B2/en
Publication of WO2021223565A1 publication Critical patent/WO2021223565A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register, a driving method, a driving control circuit, and a display device.
  • GOA Gate Driver on Array, array substrate row drive
  • TFT Thin Film Transistor, thin film transistor
  • the drive control circuit is usually composed of multiple cascaded shift registers.
  • the output of the shift register is unstable, which can cause display abnormalities.
  • the driving method of the shift register includes: at the first refresh frequency, one display frame includes a data refresh phase and a data retention phase; the data retention phase includes alternately arranged denoising retention phases and denoising retention phases Strengthening stage
  • an input signal with a pulse level is applied to the input signal terminal, a control clock pulse signal is applied to the control clock signal terminal, a noise reduction clock pulse signal is applied to the noise reduction clock signal terminal, and a noise reduction clock pulse signal is applied to the first reference signal terminal.
  • Load a fixed voltage signal load a fixed voltage signal to the second reference signal terminal, control the cascade signal terminal of the shift register to output a cascade signal with a pulse level, and control the drive signal terminal of the shift register to output a pulse Level of drive signal;
  • a fixed voltage signal is applied to the input signal terminal, a fixed voltage signal is applied to the control clock signal terminal, a fixed voltage signal is applied to the noise reduction clock signal terminal, and a fixed voltage signal is applied to the first reference signal terminal.
  • Load a fixed voltage signal load a fixed voltage signal to the second reference signal terminal, control the cascade signal terminal to output a fixed voltage signal, and control the drive signal terminal to output a fixed voltage signal;
  • a fixed voltage signal is applied to the input signal terminal, a fixed voltage signal is applied to the control clock signal terminal, a clock pulse signal is applied to the noise reduction clock signal terminal, and a clock pulse signal is applied to the first reference signal terminal.
  • a fixed voltage signal is applied, a fixed voltage signal is applied to the second reference signal terminal, the cascade signal terminal is controlled to output a fixed voltage signal, and the driving signal terminal is controlled to output a fixed voltage signal.
  • the noise reduction clock signal terminal includes a first noise reduction clock signal terminal and a second noise reduction clock signal terminal;
  • the noise reduction clock signal includes a first noise reduction clock signal And the second noise reduction clock pulse signal; wherein the first noise reduction clock pulse signal and the second noise reduction clock pulse signal have the same period and a phase difference of 1/2 period;
  • loading the noise reduction clock signal terminal with a noise reduction clock signal specifically includes: loading the first noise reduction clock signal terminal on the first noise reduction clock signal terminal, and loading the second noise reduction clock signal terminal.
  • the noise reduction clock signal terminal loads the second noise reduction clock pulse signal;
  • applying a fixed voltage signal to the noise reduction clock signal terminal specifically includes: applying a fixed voltage signal with a first level to the first noise reduction clock signal terminal, and applying a fixed voltage signal to the second noise reduction clock signal terminal The noise reduction clock signal terminal loads a fixed voltage signal with the first level;
  • loading a clock pulse signal on the noise reduction clock signal terminal specifically includes: loading the first noise reduction clock signal on the first noise reduction clock signal terminal, and loading the first noise reduction clock signal on the first noise reduction clock signal terminal.
  • the second noise reduction clock signal terminal loads the second noise reduction clock pulse signal; wherein, the first level of the first noise reduction clock pulse signal in the denoise enhancement phase is different from the first level of the first noise reduction clock signal that occurs before the denoise enhancement phase
  • the denoising holding stage is adjacent, and the second level of the second noise reduction clock pulse signal in the denoising enhancement stage is adjacent to the denoising holding stage appearing before the denoising enhancement stage.
  • the number of clock cycles of the first noise reduction clock signal and the second noise reduction clock signal are the same, and the clock cycle The number is at least one.
  • the falling edge of the first noise reduction clock signal and the falling edge of the second noise reduction clock signal are respectively different from the falling edge of the second noise reduction clock signal.
  • the start time of the denoising holding phase appearing after the denoising enhancement phase is aligned, and the rising edge of the second noise reduction clock pulse signal is aligned with the end time of the denoising holding phase appearing before the denoising enhancement stage;
  • the sustaining duration of the second level of the second noise reduction clock pulse signal is the same.
  • the number of clock cycles of the first noise reduction clock pulse signal is an even number
  • the falling edge of the first denoising clock pulse signal is aligned with the start time of the denoising holding phase appearing after the denoising enhancement phase, and the first noise reduction clock pulse
  • the signal between the rising edge of the denoising holding phase appearing before the denoising enhancement phase and the signal between the denoising holding phase appearing before the denoising enhancement stage is the first level
  • the rising edge of the second denoising clock pulse signal is aligned with the end time of the denoising holding phase occurring before the denoising enhancement phase, and the second denoising clock pulse
  • the signal in the signal between the falling edge of the denoising holding phase appearing after the denoising enhancement phase and the denoising holding phase appearing after the denoising enhancement stage is at the first level.
  • control clock signal terminal includes a first control clock signal terminal and a second control clock signal terminal;
  • control clock pulse signal includes a first control clock signal and a second control clock Pulse signal; wherein, the period of the first control clock pulse signal and the second control clock pulse signal are the same and the phase difference is 1/2 period;
  • the pulse level of the input signal and the cascade signal is a first level
  • the pulse level of the driving signal is the second level
  • the fixed voltage signal of the first reference signal terminal is the first level
  • the fixed voltage signal of the second reference signal terminal is the second level
  • the loading of the control clock signal terminal with the control clock signal specifically includes: loading the first control clock signal terminal with the first control clock signal terminal, and loading the second control clock signal terminal with the second control clock signal terminal.
  • Control clock pulse signal
  • the loading a fixed voltage signal to the control clock signal terminal specifically includes: loading a fixed voltage signal with the second level to the first control clock signal terminal, and loading a fixed voltage signal with the second control clock signal terminal to the second control clock signal terminal.
  • the fixed voltage signal of the second level specifically includes: loading a fixed voltage signal with the second level to the first control clock signal terminal, and loading a fixed voltage signal with the second control clock signal terminal to the second control clock signal terminal.
  • the applying a fixed voltage signal to the input signal terminal specifically includes: applying a fixed voltage signal having the second level to the input signal terminal;
  • the controlling the cascaded signal terminal to output a fixed voltage signal and the driving signal terminal to output a fixed voltage signal specifically includes: controlling the cascaded signal terminal to output a fixed voltage signal with the second level and controlling the The driving signal terminal outputs a fixed voltage signal having the first level.
  • the driving method further includes: at the second refresh frequency, one display frame includes a data refresh phase;
  • an input signal with a pulse level is applied to the input signal terminal, a control clock pulse signal is applied to the control clock signal terminal, a noise reduction clock pulse signal is applied to the noise reduction clock signal terminal, and a noise reduction clock pulse signal is applied to the first reference signal terminal.
  • Load a fixed voltage signal load a fixed voltage signal to the second reference signal terminal, control the cascade signal terminal of the shift register to output a cascade signal with a pulse level, and control the drive signal terminal of the shift register to output a pulse Level of drive signal.
  • the input control circuit is respectively coupled to the input signal terminal, the first control clock signal terminal, the second control clock signal terminal, the first reference signal terminal, the second reference signal terminal, the pull-down node, and the first pull-up node;
  • the input The circuit is configured to provide the signal of the input signal terminal to the first pull-up node in response to the signal of the first control clock signal terminal, and to respond to the signal of the pull-down node and the second control clock signal
  • the signal of the first pull-up node, the signal of the first pull-up node, the signal of the first control clock signal, and the first reference signal The signal of the terminal, which controls the signal of the pull-down node;
  • the gate of the first transistor is configured to be coupled to a first reference signal terminal, and the first pole of the first transistor is configured to be coupled to the first pull-up node, so The second electrode of the first transistor is configured to be coupled to the second pull-up node;
  • the cascade output circuit is respectively coupled to the pull-down node, the second pull-up node, the second reference signal terminal, the second control clock signal terminal, and the cascade signal terminal;
  • the cascade output circuit It is configured to provide the signal of the second control clock signal terminal to the cascade signal terminal under the control of the signal of the second pull-up node, and under the control of the signal of the pull-down node, Providing the signal of the second reference signal terminal to the cascade signal terminal;
  • Drive output circuit respectively coupled to the cascade signal terminal, the first noise reduction clock signal terminal, the second noise reduction clock signal terminal, the first reference signal terminal, the second reference signal terminal, and the drive signal terminal
  • the drive output circuit is configured to respond to the signal of the cascade signal terminal, provide the signal of the second reference signal terminal to the drive signal terminal, and respond to the first noise reduction clock signal terminal and the The signal of the second noise reduction clock signal terminal provides the signal of the first reference signal terminal to the drive signal terminal.
  • the drive output circuit includes: a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor, and a second capacitor;
  • the gate of the second transistor is coupled to the cascade signal terminal, the first electrode of the second transistor is coupled to the second reference signal terminal, and the second electrode of the second transistor is coupled to the The gate of the fifth transistor is coupled;
  • the gate of the third transistor is coupled to the first noise reduction clock signal terminal, the first pole of the third transistor is coupled to the first reference signal terminal, and the second pole of the third transistor is Coupled to the gate of the fifth transistor;
  • the gate of the fourth transistor is coupled to the cascade signal terminal, the first electrode of the fourth transistor is coupled to the second reference signal terminal, and the second electrode of the fourth transistor is coupled to the The drive signal terminal is coupled;
  • a first electrode of the fifth transistor is coupled to the first reference signal terminal, and a second electrode of the fifth transistor is coupled to the driving signal terminal;
  • the first electrode of the first capacitor is coupled to the second noise reduction clock signal terminal, and the second electrode of the first capacitor is coupled to the gate of the fifth transistor;
  • the first electrode of the second capacitor is coupled to the gate of the fifth transistor, and the second electrode of the first capacitor is coupled to the driving signal terminal.
  • the cascade output circuit includes: a sixth transistor, a seventh transistor, a third capacitor, and a fourth capacitor;
  • the gate of the sixth transistor is coupled to the second pull-up node, the first electrode of the sixth transistor is coupled to the second control clock signal terminal, and the second electrode of the sixth transistor is coupled to the The cascade signal terminal is coupled;
  • the gate of the seventh transistor is coupled to the pull-down node, the first pole of the seventh transistor is coupled to the second reference signal terminal, and the second pole of the seventh transistor is coupled to the cascade Signal terminal coupling;
  • the first electrode of the third capacitor is coupled to the second pull-up node, and the second electrode of the third capacitor is coupled to the cascade signal terminal;
  • the first electrode of the fourth capacitor is coupled to the pull-down node, and the second electrode of the fourth capacitor is coupled to the second reference signal terminal.
  • the input control circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;
  • the gate of the eighth transistor is coupled to the first control clock signal terminal, the first pole of the eighth transistor is coupled to the input signal terminal, and the second pole of the eighth transistor is coupled to the The first pull-up node is coupled;
  • the gate of the ninth transistor is coupled to the first control clock signal terminal, the first pole of the ninth transistor is coupled to the first reference signal terminal, and the second pole of the ninth transistor is coupled to the The pull-down node is coupled;
  • the gate of the tenth transistor is coupled to the first pull-up node, the first pole of the tenth transistor is coupled to the first control clock signal terminal, and the second pole of the tenth transistor is coupled to the The pull-down node is coupled;
  • the gate of the eleventh transistor is coupled to the pull-down node, the first pole of the eleventh transistor is coupled to the second reference signal terminal, and the second pole of the eleventh transistor is coupled to the pull-down node.
  • the first pole of the twelfth transistor is coupled;
  • the gate of the twelfth transistor is coupled to the second control clock signal terminal, and the second electrode of the twelfth transistor is coupled to the first pull-up node.
  • the aspect ratio of the channel region of the active layer of at least one of the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor is greater than that of the first transistor, The aspect ratio of the channel region of the active layer of at least one of the second, third, eighth, ninth, tenth, eleventh, and twelfth transistors.
  • the width and length of the channel region of the active layer of at least one of the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor is 10 ⁇ m/2 ⁇ m ⁇ 100 ⁇ m/10 ⁇ m;
  • the range of the aspect ratio of the channel region of the active layer of the at least one transistor is 2 ⁇ m/2 ⁇ m to 20 ⁇ m/10 ⁇ m.
  • the capacitance value of at least one of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor ranges from 10 fF to 1 pF.
  • the drive control circuit provided by the embodiment of the present disclosure includes a plurality of cascaded shift registers described above;
  • the input signal terminal of the first stage shift register is coupled to the frame trigger signal terminal;
  • the input signal terminal of the next stage shift register is coupled to the cascade signal terminal of the previous stage shift register.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned drive control circuit.
  • FIG. 1 is a schematic structural diagram of a shift register provided by an embodiment of the disclosure
  • FIG. 2 is a flowchart of a driving method provided by an embodiment of the disclosure
  • FIG. 3 is a timing diagram of some signals provided by the embodiments of the disclosure.
  • FIG. 4 is some simulation diagrams provided by the embodiments of the disclosure.
  • FIG. 5 is a timing diagram of other signals provided by the embodiments of the disclosure.
  • FIG. 6 is a timing diagram of other signals provided by the embodiments of the disclosure.
  • FIG. 7 is some other simulation diagrams provided by the embodiments of the disclosure.
  • FIG. 8 is a schematic diagram of the structure of some drive control circuits provided by the embodiments of the disclosure.
  • FIG. 9 is a schematic structural diagram of some display devices provided by the embodiments of the present disclosure.
  • FIG. 10 is a schematic structural diagram of other display devices provided by the embodiments of the present disclosure.
  • the display device can be driven with a lower refresh frequency (such as 1 Hz). Due to the accumulation of long-term leakage of the transistor, the signal output by the driving signal terminal is abnormal.
  • the embodiments of the present disclosure provide some shift registers, as shown in FIG. 1, which may include:
  • the input control circuit 10 is respectively connected with the input signal terminal IP, the first control clock signal terminal CK, the second control clock signal terminal CKB, the first reference signal terminal VREF1, the second reference signal terminal VREF2, the pull-down node PD, and the first pull-up The node PU_1 is coupled; the input control circuit is configured to respond to the signal of the first control clock signal terminal CK, provide the signal of the input signal terminal IP to the first pull-up node PU_1, and respond to the signal of the pull-down node PD and the second
  • the signal of the control clock signal terminal CKB provides the signal of the second reference signal terminal VREF2 to the signal of the first pull-up node PU_1, and the signal of the first pull-up node PU_1, the signal of the first control clock signal terminal CK, and the first pull-up node PU_1.
  • a reference signal terminal VREF1 signal to control the signal of the pull-down node PD;
  • the first transistor M1 the gate of the first transistor M1 is configured to be coupled to the first reference signal terminal VREF1, the first pole of the first transistor M1 is configured to be coupled to the first pull-up node PU_1, and the first transistor M1
  • the second pole of is configured to be coupled to the second pull-up node PU_2;
  • the cascade output circuit 20 is respectively coupled to the pull-down node PD, the second pull-up node PU_2, the second reference signal terminal VREF2, the second control clock signal terminal CKB, and the cascade signal terminal GP; the cascade output circuit 20 is configured as Under the control of the signal of the second pull-up node PU_2, the signal of the second control clock signal terminal CKB is provided to the cascade signal terminal GP, and under the control of the signal of the pull-down node PD, the signal of the second reference signal terminal VREF2 The signal is provided to the cascaded signal terminal GP;
  • the drive output circuit 30 is respectively coupled to the cascade signal terminal GP, the first noise reduction clock signal terminal CKO, the second noise reduction clock signal terminal CKBO, the first reference signal terminal VREF1, the second reference signal terminal VREF2, and the drive signal terminal OP.
  • the drive output circuit 30 is configured to respond to the signal of the cascade signal terminal GP, provide the signal of the second reference signal terminal VREF2 to the drive signal terminal OP, and respond to the first noise reduction clock signal terminal CKO and the second reduction
  • the signal of the noisy clock signal terminal CKBO provides the signal of the first reference signal terminal VREF1 to the driving signal terminal OP.
  • the input control circuit, the first transistor, and the drive output circuit cooperate with each other by loading the corresponding signal to each signal terminal, so that the cascade signal terminal and the drive signal terminal can respectively output corresponding signals. signal of.
  • the shift register can be supplemented with charge in the noise enhancement stage to ensure the output denoising ability and keep the output of the drive signal terminal stable, which can facilitate the application of the shift register in this application to a display device with a lower refresh frequency. middle.
  • the first pull-up node PU_1 is coupled between the second pole of the eighth transistor M8 and the first pole of the first transistor M1 in the input control circuit 10.
  • the second pull-up node PU_2 is coupled between the gate of the sixth transistor M6 in the cascode output circuit 20 and the second electrode of the first transistor M1.
  • the pull-down node PD is coupled between the second pole of the ninth transistor M9 in the input control circuit 10 and the gate of the seventh transistor M7 in the cascade output circuit 20.
  • the first pull-up node PU_1, the second pull-up node PU_2, and the pull-down node PD are respectively virtual nodes in the shift register. These three nodes are only used to facilitate the structure and signal transmission of the shift register. For description, the specific structure of the shift register and signal transmission can be determined according to the coupling mode between each transistor in the shift register and the capacitor.
  • the driving output circuit 30 may include: a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first capacitor C1, and The second capacitor C2;
  • the gate of the second transistor M2 is coupled to the cascade signal terminal GP, the first pole of the second transistor M2 is coupled to the second reference signal terminal VREF2, the second pole of the second transistor M2 is coupled to the gate of the fifth transistor M5 Coupling
  • the gate of the third transistor M3 is coupled to the first noise reduction clock signal terminal CKO, the first pole of the third transistor M3 is coupled to the first reference signal terminal VREF1, and the second pole of the third transistor M3 is coupled to the fifth transistor M5 ⁇ grid coupling;
  • the gate of the fourth transistor M4 is coupled to the cascade signal terminal GP, the first pole of the fourth transistor M4 is coupled to the second reference signal terminal VREF2, and the second pole of the fourth transistor M4 is coupled to the driving signal terminal OP;
  • the first electrode of the fifth transistor M5 is coupled to the first reference signal terminal VREF1, and the second electrode of the fifth transistor M5 is coupled to the driving signal terminal OP;
  • the first electrode of the first capacitor C1 is coupled to the second noise reduction clock signal terminal CKBO, and the second electrode of the first capacitor C1 is coupled to the gate of the fifth transistor M5;
  • the first electrode of the second capacitor C2 is coupled to the gate of the fifth transistor M5, and the second electrode of the first capacitor C1 is coupled to the driving signal terminal OP.
  • the cascade output circuit 20 may include: a sixth transistor M6, a seventh transistor M7, a third capacitor C3, and a fourth capacitor C4;
  • the gate of the sixth transistor M6 is coupled to the second pull-up node PU_2, the first pole of the sixth transistor M6 is coupled to the second control clock signal terminal CKB, and the second pole of the sixth transistor M6 is coupled to the cascade signal terminal GP Coupling
  • the gate of the seventh transistor M7 is coupled to the pull-down node PD, the first pole of the seventh transistor M7 is coupled to the second reference signal terminal VREF2, and the second pole of the seventh transistor M7 is coupled to the cascade signal terminal GP;
  • the first electrode of the third capacitor C3 is coupled to the second pull-up node PU_2, and the second electrode of the third capacitor C3 is coupled to the cascade signal terminal GP;
  • the first electrode of the fourth capacitor C4 is coupled to the pull-down node PD, and the second electrode of the fourth capacitor C4 is coupled to the second reference signal terminal VREF2.
  • the input control circuit 10 may include: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12;
  • the gate of the eighth transistor M8 is coupled to the first control clock signal terminal CK, the first pole of the eighth transistor M8 is coupled to the input signal terminal IP, and the second pole of the eighth transistor M8 is coupled to the first pull-up node PU_1 catch;
  • the gate of the ninth transistor M9 is coupled to the first control clock signal terminal CK, the first pole of the ninth transistor M9 is coupled to the first reference signal terminal VREF1, and the second pole of the ninth transistor M9 is coupled to the pull-down node PD ;
  • the gate of the tenth transistor M10 is coupled to the first pull-up node PU_1, the first pole of the tenth transistor M10 is coupled to the first control clock signal terminal CK, and the second pole of the tenth transistor M10 is coupled to the pull-down node PD ;
  • the gate of the eleventh transistor M11 is coupled to the pull-down node PD, the first pole of the eleventh transistor M11 is coupled to the second reference signal terminal VREF2, and the second pole of the eleventh transistor M11 is coupled to the twelfth transistor M12.
  • the gate of the twelfth transistor M12 is coupled to the second control clock signal terminal CKB, and the second pole of the twelfth transistor M12 is coupled to the first pull-up node PU_1.
  • the first electrode of the above-mentioned transistor can be used as its source and the second electrode can be used as its drain; alternatively, the first electrode can be used as its drain and the second electrode can be used as its source. No specific distinction is made here.
  • the transistor mentioned in the foregoing embodiments of the present disclosure may be a TFT, or a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor, MOS), which is not limited herein.
  • MOS Metal Oxide Semiconductor
  • all transistors can be P-type transistors.
  • the P-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs ⁇ V th .
  • the third transistor M3 is a P-type transistor
  • the relationship between the voltage difference V gs3 between the gate and the source of the third transistor M3 and its threshold voltage V th3 satisfies the formula: V gs3 ⁇ V th3 Pass.
  • the transistor is a P-type transistor as an example for description.
  • the transistor is an N-type transistor
  • the design principle is the same as that of the present disclosure, and it also falls within the protection scope of the present disclosure.
  • the N-type transistor is turned on when the voltage difference V gs between its gate and its source and its threshold voltage V th satisfy the relationship V gs >V th .
  • the third transistor M3 is an N-type transistor
  • the relationship between the voltage difference V gs3 between the gate and the source of the third transistor M3 and the threshold voltage V th3 satisfies the formula: V gs3 >V th3 is turned on.
  • the P-type transistor is turned off under the action of a high-level signal, and turned on under the action of a low-level signal.
  • the N-type transistor is turned on under the action of a high-level signal, and cut off under the action of a low-level signal.
  • the aspect ratio of the channel region of the active layer of at least one of the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may be greater than that of the first transistor M1 and the second transistor M7.
  • the aspect ratio of the channel region of the active layer of the fourth transistor M4, the aspect ratio of the channel region of the active layer of the fifth transistor M5, and the channel region of the active layer of the sixth transistor M6 may be adjusted to The aspect ratio of the channel region and the aspect ratio of the channel region of the active layer of the seventh transistor M7 are greater than the aspect ratio of the channel region of the active layer of the first transistor M1 and the active layer of the second transistor M2.
  • the aspect ratio of the channel region, the aspect ratio of the channel region of the active layer of the third transistor M3, the aspect ratio of the channel region of the active layer of the eighth transistor M8, the active layer of the ninth transistor M9 The aspect ratio of the channel region of the tenth transistor M10, the aspect ratio of the channel region of the active layer of the tenth transistor M10, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the aspect ratio of the twelfth transistor M12 The width-to-length ratio of the channel region of the active layer.
  • the width-to-length ratio of the channel region of the active layer of at least one of the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may be in the range of 10 ⁇ m/2 ⁇ m ⁇ 100 ⁇ m/10 ⁇ m.
  • the aspect ratio of the channel region of the active layer of the fourth transistor M4, the aspect ratio of the channel region of the active layer of the fifth transistor M5, and the channel region of the active layer of the sixth transistor M6 may be set
  • the range of the aspect ratio of the track region and the aspect ratio of the channel region of the active layer of the seventh transistor M7 is 10 ⁇ m/2 ⁇ m to 100 ⁇ m/10 ⁇ m, respectively.
  • the aspect ratio of the channel region of the active layer of the fourth transistor M4, the aspect ratio of the channel region of the active layer of the fifth transistor M5, and the channel region of the active layer of the sixth transistor M6 may be set
  • the range of the aspect ratio of and the aspect ratio of the channel region of the active layer of the seventh transistor M7 are 10 ⁇ m/2 ⁇ m, respectively. It is also possible to set the aspect ratio of the channel region of the active layer of the fourth transistor M4, the aspect ratio of the channel region of the active layer of the fifth transistor M5, and the channel region of the active layer of the sixth transistor M6.
  • the range of the aspect ratio and the aspect ratio of the channel region of the active layer of the seventh transistor M7 are respectively 100 ⁇ m/10 ⁇ m.
  • the aspect ratio of the channel region of the active layer of the fourth transistor M4 is set by setting the aspect ratio of the channel region of the active layer of the fourth transistor M4, the aspect ratio of the channel region of the active layer of the fifth transistor M5, and the channel region of the active layer of the sixth transistor M6.
  • the range of the aspect ratio and the aspect ratio of the channel region of the active layer of the seventh transistor M7 are respectively 50 ⁇ m/5 ⁇ m.
  • the values of the aspect ratio of the channel region of the active layer of the sixth transistor M6 and the channel region of the active layer of the seventh transistor M7 are not limited here.
  • the first transistor M1, the second transistor M2, the third transistor M3, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 can be
  • the range of the aspect ratio of the channel region of the active layer of at least one transistor is 2 ⁇ m/2 ⁇ m to 20 ⁇ m/10 ⁇ m.
  • the aspect ratio of the channel region of the active layer of the first transistor M1, the aspect ratio of the channel region of the active layer of the second transistor M2, and the channel region of the active layer of the third transistor M3 may be set The aspect ratio of the channel region, the aspect ratio of the channel region of the active layer of the eighth transistor M8, the aspect ratio of the channel region of the active layer of the ninth transistor M9, the aspect ratio of the active layer of the tenth transistor M10
  • the range of the aspect ratio of the channel region, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the aspect ratio of the channel region of the active layer of the twelfth transistor M12 is 2 ⁇ m/2 ⁇ m ⁇ 20 ⁇ m/10 ⁇ m.
  • the aspect ratio of the channel region of the active layer of the first transistor M1, the aspect ratio of the channel region of the active layer of the second transistor M2, and the channel region of the active layer of the third transistor M3 may be set The aspect ratio of the channel region of the active layer of the eighth transistor M8, the aspect ratio of the channel region of the active layer of the ninth transistor M9, the channel of the active layer of the tenth transistor M10
  • the range of the aspect ratio of the region, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the aspect ratio of the channel region of the active layer of the twelfth transistor M12 is 2 ⁇ m/2 ⁇ m.
  • Aspect ratio, aspect ratio of the channel region of the active layer of the eighth transistor M8, aspect ratio of the channel region of the active layer of the ninth transistor M9, channel region of the active layer of the tenth transistor M10 The range of the aspect ratio of, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the aspect ratio of the channel region of the active layer of the twelfth transistor M12 is 20 ⁇ m/10 ⁇ m.
  • Aspect ratio, aspect ratio of the channel region of the active layer of the eighth transistor M8, aspect ratio of the channel region of the active layer of the ninth transistor M9, channel region of the active layer of the tenth transistor M10 The range of the aspect ratio of, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the aspect ratio of the channel region of the active layer of the twelfth transistor M12 is 10 ⁇ m/5 ⁇ m.
  • the width-to-length ratio of the channel region of the active layer of the first transistor M1, the width-to-length ratio of the channel region of the active layer of the second transistor M2, and the first transistor M2 can be specifically designed according to actual application requirements.
  • the aspect ratio of the channel region of the active layer of the tenth transistor M10, the aspect ratio of the channel region of the active layer of the eleventh transistor M11, and the width of the channel region of the active layer of the twelfth transistor M12 The value of the aspect ratio is not limited here.
  • the capacitance value of at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 may be in the range of 10 fF to 1 pF.
  • the capacitance value of at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 may be in the range of 10 fF. It is also possible to set the capacitance value of at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 to a range of 50 fF.
  • the capacitance value of at least one of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 may also be in the range of 1 pF.
  • the capacitance value of the first capacitor C1, the capacitance value of the second capacitor C2, the capacitance value of the third capacitor C3, and the capacitance value of the fourth capacitor C4 can be specifically designed according to the requirements of the actual application. limited.
  • the driving method may include: at the first refresh frequency, one display frame includes a data refresh stage T10 and a data retention stage T20:
  • the data retention phase T20 includes alternate denoising retention phases and denoising enhancement phases.
  • a fixed voltage signal is applied to the input signal terminal IP, a fixed voltage signal is applied to the control clock signal terminal, a clock pulse signal is applied to the noise reduction clock signal terminal, and a fixed voltage signal is applied to the first reference signal terminal VREF1 , Load a fixed voltage signal on the second reference signal terminal VREF2, control the cascade signal terminal GP to output a fixed voltage signal, and control the drive signal terminal OP to output a fixed voltage signal.
  • the input signal terminal IP in the data refresh stage T10, can be loaded with an input signal with a pulse level, and the control clock signal terminal can be loaded with a control clock pulse signal.
  • the signal terminal is loaded with a noise reduction clock pulse signal
  • the first reference signal terminal VREF1 is loaded with a fixed voltage signal
  • the second reference signal terminal VREF2 is loaded with a fixed voltage signal to control the cascade signal terminal GP to output a cascade signal with a pulse level
  • the drive signal terminal OP is controlled to output a drive signal with a pulse level, so that the cascade output and drive output of the shift register can be realized, so that the display device can refresh the data.
  • a fixed voltage signal can be applied to the input signal terminal IP, a fixed voltage signal to the control clock signal terminal, a fixed voltage signal to the noise reduction clock signal terminal, and a fixed voltage signal to the first reference signal terminal VREF1 Load a fixed voltage signal to the second reference signal terminal VREF2 to control the cascade signal terminal GP to output a fixed voltage signal and the drive signal terminal OP to output a fixed voltage signal, so that the shift register output can be maintained.
  • a fixed voltage signal can be applied to the input signal terminal IP, a fixed voltage signal is applied to the control clock signal terminal, a clock pulse signal is applied to the noise reduction clock signal terminal, and a fixed voltage signal is applied to the first reference signal terminal VREF1.
  • a general display device may be in a static image display state or a standby state for a long time.
  • the display device can be operated with a lower refresh frequency (for example, 1 Hz, 30 Hz).
  • the shift register in the embodiment of the present disclosure can supplement the charge of the shift register in the denoising enhancement stage to ensure the output denoising ability and keep the output of the driving signal terminal OP stable, which can be beneficial to the shift in this application.
  • the bit register is used in a display device with a lower refresh frequency.
  • the first level may be a low level, and the second level may be a high level.
  • the first level may also be a high level, and the second level may also be a low level.
  • it can be designed and determined according to actual application requirements, which is not limited here.
  • the driving method further includes: at the second refresh frequency, one display frame includes a data refresh stage T10; wherein, in the data refresh stage T10, the input signal terminal IP is loaded with a pulse voltage Flat input signal, load control clock pulse signal to the control clock signal terminal, load noise reduction clock pulse signal to the noise reduction clock signal terminal, load a fixed voltage signal to the first reference signal terminal VREF1, and load a fixed voltage signal to the second reference signal terminal VREF2
  • the voltage signal controls the cascade signal terminal GP of the shift register to output a cascade signal with a pulse level and the drive signal terminal OP of the control shift register to output a drive signal with a pulse level.
  • the display device may be in a static image display state or a standby state for a long time.
  • the display device can be operated with a lower refresh frequency (for example, 1 Hz, 30 Hz).
  • the display device can also display a video screen.
  • the display device can be made to work with a higher refresh frequency (for example, 60 Hz, 120 Hz).
  • the first refresh frequency may be a lower refresh frequency, such as 1 Hz or 30 Hz.
  • the second refresh frequency may be a higher refresh frequency, such as 60 Hz or 120 Hz.
  • the control clock signal terminal includes a first control clock signal terminal CK and a second control clock signal terminal CKB; the control clock pulse signal includes a first control clock pulse signal and a second control clock pulse Signal; wherein the first control clock signal and the second control clock signal have the same period and the phase difference is 1/2 period.
  • loading the control clock signal terminal with the control clock pulse signal may specifically include: loading the first control clock signal terminal CK with the first control clock signal terminal CK, and loading the second control clock signal terminal CKB with the first control clock signal terminal CKB. 2. Control the clock pulse signal.
  • ck represents the signal loaded by the first control clock signal terminal CK
  • ckb represents the signal loaded by the second control clock signal terminal CKB.
  • the first control clock pulse signal loaded on the first control clock signal terminal CK is a clock pulse signal that switches between high and low levels
  • the second control clock pulse signal loaded on the second control clock signal terminal CKB is also high and low.
  • Clock pulse signal for level switching the first control clock signal and the second control clock signal have the same period and have a phase difference of 1/2 period.
  • the duty ratio of the first control clock signal and the second control clock signal are the same, and the duty ratio is greater than 50%.
  • the specific implementations of the first control clock pulse signal and the second control clock pulse signal can be designed and determined according to the requirements of the actual application, and are not limited herein.
  • applying a fixed voltage signal to the control clock signal terminal may specifically include: loading the first control clock signal terminal CK with the first control clock signal terminal CK.
  • a two-level fixed voltage signal is applied to the second control clock signal terminal CKB with a fixed voltage signal of the second level.
  • FIGS. 1 and 3 when the transistor in the shift register is a P-type transistor, a fixed voltage signal with a high level may be applied to the first control clock signal terminal CK, and the second control clock The signal terminal CKB loads a fixed voltage signal with a high level.
  • the transistor in the shift register is an N-type transistor, a fixed voltage signal with a low level can be applied to the first control clock signal terminal CK, and a fixed voltage signal with a low level can be applied to the second control clock signal terminal CKB.
  • applying a fixed voltage signal to the input signal terminal IP may specifically include: loading the input signal terminal IP with a second level Fixed voltage signal.
  • ip represents the signal loaded by the input signal terminal IP.
  • the transistor in the shift register is a P-type transistor, a fixed voltage signal with a high level can be applied to the input signal terminal IP.
  • the transistor in the shift register is an N-type transistor, a fixed voltage signal with a low level can be applied to the input signal terminal IP.
  • controlling the cascade signal terminal GP to output a fixed voltage signal and the driving signal terminal OP to output a fixed voltage signal may specifically include:
  • the cascade signal terminal GP is controlled to output a fixed voltage signal with a second level and the driving signal terminal OP is controlled to output a fixed voltage signal with a first level.
  • gp represents the signal output by the cascade signal terminal GP
  • op represents the signal output by the driving signal terminal OP.
  • the cascade signal terminal GP can be controlled to output a fixed voltage signal with a high level and the drive signal terminal OP can be controlled to output a fixed voltage signal with a low level.
  • the cascade signal terminal GP can be controlled to output a fixed voltage signal with a low level and the drive signal terminal OP can be controlled to output a fixed voltage signal with a high level.
  • the pulse level of the input signal can be set to the first level.
  • the eighth transistor M8 when the eighth transistor M8 is turned on, the pulse level of the input signal can be input to the first pull-up node PU_1, so that the level of the first pull-up node PU_1 is the first level, which can pass through the first pull-up node PU_1.
  • Pulling the level of node PU_1 controls the tenth transistor M10 to turn on.
  • FIGS. 1 and 3 when the transistor in the shift register is a P-type transistor, the pulse level of the input signal is low.
  • the transistor in the shift register is an N-type transistor, the pulse level of the input signal is high.
  • the pulse level of the cascaded signal can be set to the first level.
  • the fourth transistor M4 can be turned on under the control of the pulse level of the cascade signal to provide the signal of the second reference signal terminal VREF2 to the driving signal terminal OP.
  • the pulse level of the cascade signal is low.
  • the pulse level of the cascade signal is high.
  • the fixed voltage signal of the first reference signal terminal VREF1 can be set to a first level
  • the fixed voltage signal of the second reference signal terminal VREF2 can be set to a second level
  • the pulse of the driving signal The level is the second level.
  • the first level is a low level
  • the second level is a high level
  • the transistor in the shift register is an N-type transistor
  • the first level is a high level and the second level is a low level.
  • the noise reduction clock signal terminal may include a first noise reduction clock signal terminal CKO and a second noise reduction clock signal terminal CKBO.
  • the noise reduction clock signal includes a first noise reduction clock signal and a second noise reduction clock signal; wherein the first noise reduction clock signal and the second noise reduction clock signal have the same period and the phase difference is 1/2 period .
  • loading the noise reduction clock signal terminal on the noise reduction clock signal terminal may specifically include: loading the first noise reduction clock signal terminal CKO on the first noise reduction clock signal terminal CKO, and loading the second noise reduction clock signal terminal CKO.
  • the signal terminal CKBO is loaded with the second noise reduction clock pulse signal.
  • cko represents the signal loaded by the first noise reduction clock signal terminal CKO
  • ckbo represents the signal loaded by the second noise reduction clock signal terminal CKBO.
  • the first noise reduction clock pulse signal loaded by the first noise reduction clock signal terminal CKO is a high-low level switching clock pulse signal
  • the second noise reduction clock signal terminal CKBO loads the second noise reduction clock pulse signal It is also a clock pulse signal for switching between high and low levels.
  • the period of the first noise reduction clock signal and the second noise reduction clock signal are the same and the phase difference is 1/2 period.
  • the duty cycle of the first noise reduction clock signal and the second noise reduction clock signal are the same, and the duty cycle is greater than 50%.
  • the specific implementation of the first noise reduction clock signal and the second noise reduction clock signal can be designed and determined according to the requirements of the actual application, and is not limited here.
  • the period of the first noise reduction clock signal may be the same as the period of the first control clock signal.
  • the duty ratio of the first noise reduction clock signal and the duty ratio of the first control clock signal can be made the same.
  • the falling edge of the first noise reduction clock signal is aligned with the rising edge of the second clock signal.
  • the falling edge of the second noise reduction clock signal is aligned with the rising edge of the first control clock signal.
  • the relationship between the first noise reduction clock signal, the second noise reduction clock signal, the first control clock signal, and the second control clock signal can be determined according to actual requirements. This is not limited.
  • applying a fixed voltage signal to the noise reduction clock signal terminal may specifically include: loading a fixed voltage signal with a first level on the first noise reduction clock signal terminal CKO.
  • the voltage signal loads the second noise reduction clock signal terminal CKBO with a fixed voltage signal with the first level.
  • a fixed voltage signal with a low level is applied to the first noise reduction clock signal terminal CKO , Load a fixed voltage signal with a low level to the second noise reduction clock signal terminal CKBO.
  • the transistor in the shift register is an N-type transistor
  • a fixed voltage signal with a high level is applied to the first noise reduction clock signal terminal CKO
  • a fixed voltage signal with a high level is applied to the second noise reduction clock signal terminal CKBO.
  • Level of fixed voltage signal is applied to the transistor in the shift register.
  • loading the clock pulse signal to the noise reduction clock signal terminal specifically includes: loading the first noise reduction clock pulse signal to the first noise reduction clock signal terminal CKO, And load the second noise reduction clock signal to the second noise reduction clock signal terminal CKBO; wherein, the first level of the first noise reduction clock pulse signal in the denoising enhancement stage is maintained with the denoising that occurred before the denoising enhancement stage
  • the stages are adjacent, and the second level of the second noise reduction clock pulse signal in the denoising enhancement stage is adjacent to the denoising holding stage that occurs before the denoising enhancement stage.
  • the first noise reduction clock signal loaded by the first noise reduction clock signal terminal CKO is a high and low level switching clock pulse signal
  • the second noise reduction The second noise reduction clock pulse signal loaded on the clock signal terminal CKBO is also a high and low level switching clock pulse signal.
  • the transistor in the shift register is a P-type transistor
  • the low level of the first noise reduction clock pulse signal in the denoising enhancement stage is adjacent to the denoising holding stage that occurs before the denoising enhancement stage
  • the denoising enhancement stage The high level of the second denoising clock pulse signal in the phase is adjacent to the denoising holding phase that occurs before the denoising enhancement phase.
  • the transistor in the shift register is an N-type transistor
  • the high level of the first denoising clock pulse signal in the denoising enhancement stage is adjacent to the denoising holding stage that appears before the denoising enhancement stage, and in the denoising enhancement stage
  • the low level of the second noise reduction clock pulse signal is adjacent to the denoising hold phase that occurs before the denoising enhancement phase.
  • the number of clock cycles of the first noise reduction clock signal and the second noise reduction clock signal are the same, and the number of clock cycles is at least one.
  • the number of clock cycles of the first noise reduction clock signal and the second noise reduction clock signal is one.
  • the number of clock cycles of the first noise reduction clock signal and the second noise reduction clock signal can also be two, three, four or more, which is not limited here.
  • the falling edge of the first noise reduction clock signal and the falling edge of the second noise reduction clock signal are respectively The start time of the denoising holding phase appearing after the noise enhancement phase is aligned, and the rising edge of the second noise reduction clock pulse signal is aligned with the end time of the denoising holding phase appearing before the denoising enhancement stage.
  • the duration of the second level of the second noise reduction clock signal is the same.
  • the high level of the second noise reduction clock signal is maintained for the same duration
  • the low level of the second noise reduction clock signal is also maintained for the same duration.
  • 1 represents a high-level signal
  • 0 represents a low-level signal.
  • 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. It is not the voltage applied to the gate of each transistor during specific implementation.
  • one display frame may include a data refresh phase T10 and a data retention phase T20; the data refresh phase T10 includes alternately arranged denoising retention phases T21-1 and denoising enhancement Stage T22-1.
  • the signal timing diagram shown in FIG. 3 is only a working process of a shift register in a current display frame.
  • the working process of the shift register in other display frames is basically the same as the working process in the current display frame, and will not be repeated here.
  • the data refresh stage T10 includes a stage T11, a stage T12, a stage T13, and a stage T14.
  • the transistor M10 is turned on, thereby providing the low-level signal of the first control clock signal terminal CK to the pull-down node PD, and further makes the signal of the pull-down node PD a low-level signal.
  • the first transistor M1 Since the first transistor M1 satisfies V gs1 ⁇ V th1 , the first transistor M1 is turned on.
  • the turned-on first transistor M1 turns on the second pull-up node PU_2 and the first pull-up node PU_1, so that the signal of the second pull-up node PU_2 can be a low-level signal in time to control the sixth transistor M6 to turn on Therefore, the high-level signal of the second control clock signal terminal CKB is provided to the cascade signal terminal GP, so that the cascade signal terminal GP outputs a high-level cascade signal. Since the cascade signal terminal GP outputs a high-level signal, the second transistor M2 and the fourth transistor M4 can be controlled to be turned off.
  • the third transistor M3 is turned on to provide the low-level signal of the first reference signal terminal VREF1 to the gate of the fifth transistor M5, thereby controlling the fifth transistor M5 to turn on to turn on the first reference signal terminal VREF1.
  • the low-level signal of the signal terminal VREF1 is provided to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the second pull-up node PU_2 maintains a low-level signal under the action of the third capacitor C3 to control the sixth transistor M6 to turn on, so as to provide the low-level signal of the second control clock signal terminal CKB to the cascade signal terminal GP, make the cascade signal terminal GP output a low-level cascade signal.
  • the cascade signal terminal GP outputs a low-level cascade signal.
  • one pole of the first transistor M1 coupled to the first pull-up node PU_1 serves as its source, so that the first transistor M1 cannot satisfy V gs1 ⁇ V th1 , so that the first transistor M1 is turned off.
  • the level of the second pull-up node PU_2 can be kept stable, and the situation that the level of the second pull-up node PU_2 rises due to electric leakage can be avoided, and the output of the cascaded signal terminal GP is unstable.
  • the tenth transistor M10 provides a high-level signal of the first control clock signal terminal CK to the pull-down node PD under the control of the signal of the first pull-up node PU_1, so as to control the seventh transistor M7 to be turned off, so as to avoid interference with the cascade signal.
  • the turned-on second transistor M2 can provide the high-level signal of the second reference signal terminal VREF2 to the gate of the fifth transistor M5 to control the fifth transistor M5 to turn off.
  • the turned-on fourth transistor M4 can provide the high-level signal of the second reference signal terminal VREF2 to the driving signal terminal OP, so that the driving signal terminal OP outputs a high-level driving signal.
  • the second pull-up node PU_2 maintains a low-level signal under the action of the third capacitor C3 to control the sixth transistor M6 to turn on, so as to provide the high-level signal of the second control clock signal terminal CKB to the cascade signal terminal GP, make the cascade signal terminal GP output a high-level cascade signal to control both the second transistor M2 and the fourth transistor M4 to be turned off.
  • the third transistor M3 Since the signal cko of the first noise reduction clock signal terminal CKO changes from high level to low level, the third transistor M3 is turned on, so that the low level signal of the first reference signal terminal VREF1 can be provided to the fifth transistor M5 And control the fifth transistor M5 to turn on to provide the low-level signal of the first reference signal terminal VREF1 to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the turned-on eighth transistor M8 provides the high-level signal of the input signal terminal IP to the first pull-up node PU_1, and makes the first pull-up node PU_1 a high-level signal to control the tenth transistor M10 to turn off. Since the first reference signal terminal VREF1 is a low-level signal, the first transistor M1 is turned on to provide the high-level signal of the first pull-up node PU_1 to the second pull-up node PU_2 to control the sixth transistor M6 to turn off .
  • the turned-on ninth transistor M9 provides the low-level signal of the first reference signal terminal VREF1 to the pull-down node PD, so that the signal of the pull-down node PD is a low-level signal to control the seventh transistor M7 to turn on.
  • the turned-on seventh transistor M7 provides the high-level signal of the second reference signal terminal VREF2 to the cascade signal terminal GP, so that the cascade signal terminal GP outputs a high-level signal to control the second transistor M2 and the fourth transistor M4 is all cut off.
  • the third transistor M3 is turned on, so that the low-level signal of the first reference signal terminal VREF1 can be provided to the gate of the fifth transistor M5, and then the fifth transistor M5 is controlled to be turned on to turn on the first reference signal terminal VREF1.
  • the low-level signal of the reference signal terminal VREF1 is provided to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the first capacitor C1 and the second capacitor C2 maintain a stable voltage difference across them.
  • the eighth transistor M8 and the ninth transistor M9 are both turned off, and the signal of the pull-down node PD can be maintained as a low-level signal due to the function of the fourth capacitor C4, and the seventh transistor M7 is controlled to be turned on to turn on
  • the high-level signal of the second reference signal terminal VREF2 is provided to the cascaded signal terminal GP, so that the cascaded signal terminal GP outputs a high-level signal to control both the second transistor M2 and the fourth transistor M4 to be turned off.
  • the third transistor M3 is turned on, so that the low-level signal of the first reference signal terminal VREF1 can be provided to the gate of the fifth transistor M5, and then the fifth transistor M5 is controlled to be turned on to turn on the first reference signal terminal VREF1.
  • the low-level signal of the reference signal terminal VREF1 is provided to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the eleventh transistor M11 and the twelfth transistor M12 are both turned on, so that the first pull-up node PU_1 can be a high-level signal, and the second pull-up node PU_2 can be a high-level signal to control the sixth The transistor M6 is off.
  • the eighth transistor M8 and the ninth transistor M9 are both turned off, and the signal of the pull-down node PD can be maintained as a low-level signal due to the function of the fourth capacitor C4, and the seventh transistor M7 is controlled to be turned on to turn on
  • the high-level signal of the second reference signal terminal VREF2 is provided to the cascaded signal terminal GP, so that the cascaded signal terminal GP outputs a high-level signal to control both the second transistor M2 and the fourth transistor M4 to be turned off.
  • the third transistor M3 is turned on, so that the low-level signal of the first reference signal terminal VREF1 can be provided to the gate of the fifth transistor M5, and then the fifth transistor M5 is controlled to be turned on to turn on the first reference signal terminal VREF1.
  • the low-level signal of the reference signal terminal VREF1 is provided to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the threshold of the third transistor M3 will drift, because the first reference signal terminal VREF1 is also at a low level, and the third transistor M3 Therefore, the gate-source voltage difference of the third transistor M3 cannot be less than the threshold voltage of the third transistor M3, so that the third transistor M3 is turned off, and the gate voltage of the fifth transistor M5 may increase. In turn, the turn-on degree of the fifth transistor M5 is reduced, so that the low level output by the driving signal terminal OP appears to be pulled up by noise.
  • the first noise reduction clock signal terminal CKO is loaded with the first noise reduction clock pulse signal
  • the second noise reduction clock signal terminal CKBO is loaded with the second noise reduction clock pulse signal.
  • the third transistor M3 can be turned on normally, so that the gate of the fifth transistor M5 is discharged, the opening degree of the fifth transistor M5 is improved, and the stability of the output of the driving signal terminal OP is improved.
  • the gate voltage of the fifth transistor M5 is pulled up due to the coupling effect of the first capacitor C1.
  • the fifth transistor M5 is also controlled to be turned on to provide the low-level signal of the first reference signal terminal VREF1 to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the eighth transistor M8 and the ninth transistor M9 are both turned off, and the signal of the pull-down node PD can be maintained as a low-level signal due to the function of the fourth capacitor C4, and the seventh transistor M7 is controlled to be turned on to turn on
  • the gate voltage of the fifth transistor M5 is further pulled down due to the coupling effect of the first capacitor C1, so as to control the fifth transistor M5 to be fully turned on as much as possible to turn on
  • the low-level signal of the first reference signal terminal VREF1 is provided to the driving signal terminal OP without voltage loss as much as possible, so that the driving signal terminal OP outputs a low-level driving signal.
  • the working processes of the denoising holding stage T21-1 and the denoising enhancement stage T22-1 are repeatedly executed until the signal level of the input signal terminal IP becomes high again.
  • the data refresh phase T10 there are buffer phases (for example, signal ckb, signal ck, signal cko, and signal cko) between T11 and T12, between T12 and T13, and between T13 and T14.
  • the signal ckbo is a high level stage).
  • the buffering stage the characteristics of the transistors in the shift register can be stabilized, so as to enter the next working stage after stabilization.
  • the rising and falling edges of the signal ckb and the signal ck do not completely correspond, and the rising and falling edges of the signal ckbo and the signal cko do not completely correspond.
  • the signal cko and the signal ckbo also have a buffering stage (that is, the signal cko and the signal ckbo are both high-level stages), in the buffering stage , The characteristics of the transistors in the shift register can be stabilized to enter the next working stage after stabilization. Moreover, due to the existence of the buffer phase, the rising and falling edges of the signal ckbo and the signal cko will not completely correspond.
  • the falling edge of the signal cko can be prevented from being aligned with the rising edge of the signal ckbo, and the rising edge of the signal cko can be prevented from being aligned with the falling edge of the signal ckbo, thereby improving the stability of the shift register.
  • the signal cko and the signal ckbo have a buffer stage, the signal cko will have a peak with a smaller duration at the end of the denoising enhancement stage T22-1.
  • the signal output by the driving signal terminal OP of the shift register shown in FIG. 1 is simulated, and the simulation diagram is shown in FIG. 4.
  • the abscissa represents time
  • the ordinate represents voltage
  • S1 represents a signal used to simulate the driving signal terminal OP of the shift register shown in FIG. 1 using the signal timing diagram shown in FIG. 3.
  • S0 represents a signal that is simulated by the drive signal terminal OP of the shift register when there is only a noise reduction hold phase in the data hold phase T20. It can be seen in conjunction with FIG. 3 that, by setting the noise reduction enhancement stage in the embodiment of the present disclosure, a stable output signal of the driving signal terminal OPGP can be made, so that the problem of instability due to leakage can be improved.
  • the shift register shown in FIG. 1 is driven to work according to the signal timing diagram shown in FIG. 3, and the power consumption of the shift register is detected to be 0.5 mW when the work is performed in the data holding phase T20. Therefore, it can be seen that even if a clock pulse is inserted in the data holding phase T20, the power consumption of the shift register can be within an acceptable range.
  • 1 represents a high-level signal
  • 0 represents a low-level signal.
  • 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. It is not the voltage applied to the gate of each transistor during specific implementation.
  • one display frame may include the data refresh stage T10.
  • the signal timing diagram shown in FIG. 5 is only the working process of a shift register in a current display frame.
  • the working process of the shift register in other display frames is basically the same as the working process in the current display frame, and will not be repeated here.
  • the data refresh stage T10 includes a stage T11, a stage T12, a stage T13, and a stage T14.
  • the working process of the above-mentioned shift register provided in the embodiment of the present disclosure in the signal timing diagram shown in FIG. 5 is basically the same as the working process in the data refresh phase T10 in the signal timing diagram shown in FIG. 3, and will not be repeated here.
  • the embodiments of the present disclosure provide other driving methods, which are modified with respect to the implementation in the above-mentioned embodiments.
  • the differences between this embodiment and the above-mentioned embodiment will be described, and the similarities will not be repeated here.
  • the number of clock cycles of the first denoising clock pulse signal is an even number.
  • the number of clock cycles of the first noise reduction clock pulse signal may be set to two.
  • the number of clock cycles of the first noise reduction clock pulse signal can also be 4, 6 or more, which is not limited here.
  • the falling edge of the first denoising clock pulse signal is aligned with the start time of the denoising holding phase that appears after the denoising enhancement phase, and the first In the noise reduction clock pulse signal, the signal close to the rising edge of the denoising holding phase appearing before the denoising enhancement phase and the signal between the denoising holding phase appearing before the denoising enhancement stage is at the first level.
  • the signal close to the rising edge of the denoising holding phase appearing before the denoising enhancement phase and the signal between the denoising holding phase appearing before the denoising enhancement stage is at the first level.
  • the falling edge of the first noise reduction clock pulse signal of the signal cko and the denoising occurring after the denoising enhancement stage T22-1 can be maintained
  • the start time of stage T21-2 is aligned, and the first noise reduction clock pulse signal of signal cko is close to the rising edge of the denoising holding stage T21-1 that occurs before the denoising enhancement stage T22-1 and the rising edge of the denoising enhancement stage T22
  • the signal between the denoising holding phase T21-1 that occurred before -1 is low.
  • the rising edge of the second denoising clock pulse signal is aligned with the end time of the denoising holding phase that occurs before the denoising enhancement phase, and the second In the noise reduction clock pulse signal, the signal close to the falling edge of the denoising holding phase appearing after the denoising enhancement phase and the denoising holding phase appearing after the denoising enhancement stage is at the first level.
  • the rising edge of the second noise reduction clock pulse signal of the signal ckbo and the denoising holding phase T21- appearing before the denoising enhancement phase T22-1 can be made.
  • the end time of 1 is aligned, and the second noise reduction clock pulse signal of the signal ckbo is close to the falling edge of the denoising holding stage T21-2 that appears after the denoising enhancement stage T22-1 and after the denoising enhancement stage T22-1
  • the signal between the appearing denoising holding stage T21-2 is low.
  • 1 represents a high-level signal
  • 0 represents a low-level signal.
  • 1 and 0 are logic levels, which are only used to better explain the specific working process of the embodiments of the present disclosure. It is not the voltage applied to the gate of each transistor during specific implementation.
  • one display frame may include a data refresh phase T10 and a data retention phase T20; the data refresh phase T10 includes a denoising retention phase and a denoising enhancement phase alternately arranged.
  • the signal timing diagram shown in FIG. 6 is only the working process of a shift register in a current display frame.
  • the working process of the shift register in other display frames is basically the same as the working process in the current display frame, and will not be repeated here.
  • the eighth transistor M8 and the ninth transistor M9 are both turned off, and the signal of the pull-down node PD can be maintained as a low-level signal due to the function of the fourth capacitor C4, and the seventh transistor M7 is controlled to be turned on to turn on
  • the high-level signal of the second reference signal terminal VREF2 is provided to the cascaded signal terminal GP, so that the cascaded signal terminal GP outputs a high-level signal to control both the second transistor M2 and the fourth transistor M4 to be turned off.
  • the gate voltage of the fifth transistor M5 is pulled up due to the coupling effect of the first capacitor C1.
  • the fifth transistor M5 is also controlled to be turned on to provide the low-level signal of the first reference signal terminal VREF1 to the driving signal terminal OP, so that the driving signal terminal OP outputs a low-level driving signal.
  • the eighth transistor M8 and the ninth transistor M9 are both turned off, and the signal of the pull-down node PD can be maintained as a low-level signal due to the function of the fourth capacitor C4, and the seventh transistor M7 is controlled to be turned on to turn on
  • the gate voltage of the fifth transistor M5 is further pulled down due to the coupling effect of the first capacitor C1, so as to control the fifth transistor M5 to be fully turned on as much as possible to turn on
  • the low-level signal of the first reference signal terminal VREF1 is provided to the driving signal terminal OP without voltage loss as much as possible, so that the driving signal terminal OP outputs a low-level driving signal.
  • the signal output by the drive signal terminal OP of the shift register shown in FIG. 1 is simulated and the simulation diagram is shown in FIG. 7.
  • the abscissa represents time
  • the ordinate represents voltage
  • S2 represents a signal used to simulate the driving signal terminal OP of the shift register shown in FIG. 1 by using the signal timing diagram shown in FIG. 6.
  • S0 represents a signal that is simulated by the drive signal terminal OP of the shift register when there is only a noise reduction hold phase in the data hold phase T20. It can be seen in conjunction with FIG. 6 that, by setting the noise reduction enhancement stage in the embodiment of the present disclosure, a stable output signal of the driving signal terminal OPGP can be made, so that the problem of instability due to leakage can be improved.
  • the shift register shown in FIG. 1 is driven to work according to the signal timing chart shown in FIG. 6, and the power consumption of the shift register is detected to be 0.5 mW when working in the data holding phase T20. Therefore, it can be seen that even if a clock pulse is inserted in the data holding phase T20, the power consumption of the shift register can be within an acceptable range.
  • an embodiment of the present disclosure also provides a drive control circuit, as shown in FIG. 8, including any of the above-mentioned shift registers SR(1), SR(2)...SR provided by multiple cascaded embodiments of the present disclosure.
  • (n-1), SR(n)...SR(N-1), SR(N) (a total of N shift registers, 1 ⁇ n ⁇ N, n is an integer); among them, the first stage shift register SR (1)
  • the input signal terminal IP is configured to be coupled to the frame trigger signal terminal STV;
  • the input signal terminal IP of the next stage shift register SR(n) is configured to be coupled to the cascaded signal output terminal GP of the previous stage shift register SR(n-1) .
  • each shift register in the above-mentioned drive control circuit is the same in function and structure as the above-mentioned shift register of the present disclosure, and the repetition will not be repeated.
  • the drive control circuit can be configured in a liquid crystal display panel or in an electroluminescent display panel, which is not limited here.
  • the first reference signal terminal VREF1 of the shift register of each stage is coupled to the same first DC signal terminal
  • the second reference signal of the shift register of each stage is The terminals VREF2 are both coupled to the same second DC signal terminal.
  • the first control clock signal terminal CK of the shift register of the odd-numbered stage and the second control clock signal terminal CKB of the shift register of the even-numbered stage are both the same as the same clock terminal. That is, the first control clock terminal is coupled.
  • the second control clock signal terminal CKB of the odd-numbered shift register and the first control clock signal terminal CK of the even-numbered shift register are both coupled to the same clock terminal, that is, the second control clock terminal.
  • the first noise reduction clock signal terminal CKO of the odd-numbered shift register and the second noise reduction clock signal terminal CKBO of the even-numbered shift register are the same
  • the clock terminal is coupled to the first noise reduction clock terminal.
  • the second noise reduction clock signal terminal CKBO of the odd-number stage shift register and the first noise reduction clock signal terminal CKO of the even-number stage shift register are both coupled to the same clock terminal, that is, the second noise reduction clock terminal.
  • embodiments of the present disclosure also provide a display device, including the above-mentioned gate drive control circuit provided by the embodiments of the present disclosure.
  • the problem-solving principle of the display device is similar to that of the aforementioned shift register. Therefore, the implementation of the display device can refer to the implementation of the aforementioned shift register, and the repetition will not be repeated here.
  • the above-mentioned display device may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the display device may include multiple pixel units, multiple gate lines and data lines, and each pixel unit may include multiple sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be an organic light-emitting display device, or may also be a liquid crystal display device, which is not limited herein.
  • a row of sub-pixels spx is coupled to a gate line GA, and a column of sub-pixels spx is coupled to a data line DA.
  • the sub-pixel spx may include a scan transistor N00 and a pixel electrode 200.
  • the gate of the scan transistor N00 can be coupled to the gate line GA, the source of the scan transistor N00 is coupled to the data line DA, and the drain of the scan transistor N00 is coupled to the pixel electrode 200.
  • the drive signal terminal OP of a shift register is coupled to a gate line GA, so that the drive signal terminal OP of the shift register can provide a signal to the gate of the scanning transistor N00 in the sub-pixel, and make the stage of the shift register
  • the connection signal terminal GP is used to transmit the start signal for the next stage shift register.
  • the above-mentioned drive control circuit can be used as a gate drive control circuit for providing the gate scanning signal of the scanning transistor N00.
  • the scan transistor N00 can be an N-type transistor or a P-type transistor, which is not limited herein.
  • the display device may include a plurality of first gate lines GA1 and a plurality of second gate lines GA2.
  • a row of sub-pixels is coupled to a first gate line GA1 and a second gate line GA2.
  • the sub-pixel spx may include a first scan transistor N01, a second scan transistor P01, and a pixel electrode 200.
  • the first scan transistor N01 is an N-type transistor
  • the second scan transistor P01 is a P-type transistor.
  • the gate of the first scan transistor N01 is coupled to the first gate line GA1, and the second scan transistor P01 is coupled to the second gate line GA2.
  • the source of the second scan transistor P01 is coupled to the data line DA
  • the drain of the second scan transistor P01 is coupled to the source of the first scan transistor N01
  • the drain of the first scan transistor N01 is coupled to the pixel electrode 200.
  • the driving signal terminal OP of a shift register is coupled to a first gate line GA1
  • the cascade signal terminal GP of a shift register is coupled to a second gate line GA2. In this way, the drive signal terminal OP of the shift register can provide a signal to the gate of the N-type transistor in the sub-pixel.
  • the cascade signal terminal GP of the shift register is used to provide a signal to the gate of the P-type transistor in the sub-pixel, and the cascade signal terminal GP is also used to transmit a start signal to the shift register of the next stage.
  • the above-mentioned display device provided by the embodiment of the present disclosure is a liquid crystal display device
  • the above-mentioned drive control circuit can be used as a gate drive control circuit for providing gate scanning signals.
  • an organic light emitting display device a plurality of organic light emitting diodes and a pixel circuit connected to each organic light emitting diode are generally provided.
  • a pixel circuit is provided with a light emission control transistor for controlling the light emission of an organic light emitting diode and a scan control transistor for controlling data signal input.
  • the organic light-emitting display device may include the above-mentioned drive control circuit provided by the embodiment of the present disclosure, and the drive control circuit may be used as a light-emitting drive control circuit.
  • the circuit is used to provide the light-emitting control signal of the light-emitting control transistor; or, the drive control circuit can also be used as a gate drive control circuit to provide the gate scan signal of the scan control transistor.
  • the organic light-emitting display device may also include two of the above-mentioned drive control circuits provided in the embodiments of the present disclosure.
  • the control circuit is applied to provide the gate scan signal of the scan control transistor, which is not limited here.

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Abstract

一种移位寄存器、驱动方法、驱动控制电路及显示装置，在数据刷新阶段（T10），对输入信号端（IP）加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号；在去噪保持阶段（T21-1），对输入信号端（IP）加载固定电压信号，对控制时钟信号端加载固定电压信号，对降噪时钟信号端加载固定电压信号；在去噪加强阶段（T22-1），对输入信号端（IP）加载固定电压信号，对控制时钟信号端加载固定电压信号，对降噪时钟信号端加载时钟脉冲信号。

Description

移位寄存器、驱动方法、驱动控制电路及显示装置
相关申请的交叉引用
本申请要求在2020年05月08日提交中国专利局、申请号为202010382849.5、申请名称为“移位寄存器、驱动方法、驱动控制电路及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及移位寄存器、驱动方法、驱动控制电路及显示装置。
背景技术
随着显示技术的飞速发展，显示装置越来越向着高集成度和低成本的方向发展。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)驱动控制电路集成在显示装置的阵列基板上以形成对显示装置的扫描驱动。其中，驱动控制电路通常由多个级联的移位寄存器构成。然而，移位寄存器输出不稳定，会导致显示异常。
发明内容
本公开实施例提供的移位寄存器的驱动方法，包括：在第一刷新频率时，一个显示帧包括数据刷新阶段和数据保持阶段；所述数据保持阶段包括交替设置的去噪保持阶段和去噪加强阶段；
在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载固定电压信号，对第二参考信号端加载固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号；
在所述去噪保持阶段，对所述输入信号端加载固定电压信号，对所述控制时钟信号端加载固定电压信号，对所述降噪时钟信号端加载固定电压信号，对第一参考信号端加载固定电压信号，对第二参考信号端加载固定电压信号，控制所述级联信号端输出固定电压信号以及控制所述驱动信号端输出固定电压信号；
在所述去噪加强阶段，对所述输入信号端加载固定电压信号，对所述控制时钟信号端加载固定电压信号，对所述降噪时钟信号端加载时钟脉冲信号，对第一参考信号端加载固定电压信号，对第二参考信号端加载固定电压信号，控制所述级联信号端输出固定电压信号以及控制所述驱动信号端输出固定电压信号。
可选地，在本公开实施例中，所述降噪时钟信号端包括第一降噪时钟信号端和第二降噪时钟信号端；所述降噪时钟脉冲信号包括第一降噪时钟脉冲信号和第二降噪时钟脉冲信号；其中，所述第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的周期相同且相位差为1/2周期；
在所述数据刷新阶段，对降噪时钟信号端加载降噪时钟脉冲信号，具体包括：对所述第一降噪时钟信号端加载所述第一降噪时钟脉冲信号，以及对所述第二降噪时钟信号端加载所述第二降噪时钟脉冲信号；
在所述去噪保持阶段，对所述降噪时钟信号端加载固定电压信号，具体包括：对所述第一降噪时钟信号端加载具有第一电平的固定电压信号，对所述第二降噪时钟信号端加载具有所述第一电平的固定电压信号；
在所述去噪加强阶段，对所述降噪时钟信号端加载时钟脉冲信号，具体包括：对所述第一降噪时钟信号端加载所述第一降噪时钟脉冲信号，以及对所述第二降噪时钟信号端加载所述第二降噪时钟脉冲信号；其中，所述去噪加强阶段中所述第一降噪时钟脉冲信号的第一电平与在所述去噪加强阶段之前出现的去噪保持阶段相邻，所述去噪加强阶段中所述第二降噪时钟脉冲信号的第二电平与在所述去噪加强阶段之前出现的去噪保持阶段相邻。
可选地，在本公开实施例中，在所述去噪加强阶段中，所述第一降噪时 钟脉冲信号和所述第二降噪时钟脉冲信号的时钟周期数目相同，且所述时钟周期数目至少为一个。
可选地，在本公开实施例中，同一所述去噪加强阶段中，所述第一降噪时钟脉冲信号的下降沿、所述第二降噪时钟脉冲信号的下降沿分别与在所述去噪加强阶段之后出现的去噪保持阶段的开始时刻对齐，且所述第二降噪时钟脉冲信号的上升沿与在所述去噪加强阶段之前出现的去噪保持阶段的结束时刻对齐；
所述数据刷新阶段和所述去噪加强阶段中，所述第二降噪时钟脉冲信号的第二电平的维持时长相同。
可选地，在本公开实施例中，在所述去噪加强阶段中，所述第一降噪时钟脉冲信号的时钟周期数目为偶数个；
同一所述去噪加强阶段中，所述第一降噪时钟脉冲信号的下降沿与在所述去噪加强阶段之后出现的去噪保持阶段的开始时刻对齐，以及所述第一降噪时钟脉冲信号中靠近在所述去噪加强阶段之前出现的去噪保持阶段的上升沿与在所述去噪加强阶段之前出现的去噪保持阶段之间的信号为第一电平；
同一所述去噪加强阶段中，所述第二降噪时钟脉冲信号的上升沿与在所述去噪加强阶段之前出现的去噪保持阶段的结束时刻对齐，以及所述第二降噪时钟脉冲信号中靠近在所述去噪加强阶段之后出现的去噪保持阶段的下降沿与在所述去噪加强阶段之后出现的去噪保持阶段之间的信号为第一电平。
可选地，在本公开实施例中，所述控制时钟信号端包括第一控制时钟信号端和第二控制时钟信号端；所述控制时钟脉冲信号包括第一控制时钟脉冲信号和第二控制时钟脉冲信号；其中，所述第一控制时钟脉冲信号和第二控制时钟脉冲信号的周期相同且相位差为1/2周期；
所述输入信号和所述级联信号的脉冲电平为第一电平；
所述驱动信号的脉冲电平为第二电平；
所述第一参考信号端的固定电压信号为所述第一电平；
所述第二参考信号端的固定电压信号为所述第二电平；
所述对控制时钟信号端加载控制时钟脉冲信号，具体包括：对所述第一控制时钟信号端加载所述第一控制时钟脉冲信号，以及对所述第二控制时钟信号端加载所述第二控制时钟脉冲信号；
所述对所述控制时钟信号端加载固定电压信号，具体包括：对所述第一控制时钟信号端加载具有所述第二电平的固定电压信号，对所述第二控制时钟信号端加载具有所述第二电平的固定电压信号；
所述对所述输入信号端加载固定电压信号，具体包括：对所述输入信号端加载具有所述第二电平的固定电压信号；
所述控制所述级联信号端输出固定电压信号以及控制所述驱动信号端输出固定电压信号，具体包括：控制所述级联信号端输出具有所述第二电平的固定电压信号以及控制所述驱动信号端输出具有所述第一电平的固定电压信号。
可选地，在本公开实施例中，所述驱动方法还包括：在第二刷新频率时，一个显示帧包括数据刷新阶段；
在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载固定电压信号，对第二参考信号端加载固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号。
本公开实施例提供的移位寄存器，包括：
输入控制电路，分别与输入信号端、第一控制时钟信号端、第二控制时钟信号端、第一参考信号端、第二参考信号端、下拉节点以及第一上拉节点耦接；所述输入电路被配置为响应于所述第一控制时钟信号端的信号，将所述输入信号端的信号提供给所述第一上拉节点，并响应于所述下拉节点的信号和所述第二控制时钟信号端的信号，将所述第二参考信号端的信号提供给所述第一上拉节点的信号，以及根据所述第一上拉节点的信号、第一控制时钟信号端的信号以及所述第一参考信号端的信号，控制所述下拉节点的信号；
所述第一晶体管，所述第一晶体管的栅极被配置为与第一参考信号端耦接，所述第一晶体管的第一极被配置为与所述第一上拉节点耦接，所述第一晶体管的第二极被配置为与第二上拉节点耦接；
级联输出电路，分别与所述下拉节点、所述第二上拉节点、所述第二参考信号端、所述第二控制时钟信号端以及级联信号端耦接；所述级联输出电路被配置为在所述第二上拉节点的信号的控制下，将所述第二控制时钟信号端的信号提供给所述级联信号端，并在所述下拉节点的信号的控制下，将所述第二参考信号端的信号提供给所述级联信号端；
驱动输出电路，分别与所述级联信号端、第一降噪时钟信号端、第二降噪时钟信号端、所述第一参考信号端、所述第二参考信号端以及驱动信号端耦接；所述驱动输出电路被配置为响应于所述级联信号端的信号，将所述第二参考信号端的信号提供给所述驱动信号端，并响应于所述第一降噪时钟信号端和所述第二降噪时钟信号端的信号，将所述第一参考信号端的信号提供给所述驱动信号端。
可选地，在本公开实施例中，所述驱动输出电路包括：第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一电容以及第二电容；
所述第二晶体管的栅极与所述级联信号端耦接，所述第二晶体管的第一极与所述第二参考信号端耦接，所述第二晶体管的第二极与所述第五晶体管的栅极耦接；
所述第三晶体管的栅极与所述第一降噪时钟信号端耦接，所述第三晶体管的第一极与所述第一参考信号端耦接，所述第三晶体管的第二极与所述第五晶体管的栅极耦接；
所述第四晶体管的栅极与所述级联信号端耦接，所述第四晶体管的第一极与所述第二参考信号端耦接，所述第四晶体管的第二极与所述驱动信号端耦接；
所述第五晶体管的第一极与所述第一参考信号端耦接，所述第五晶体管的第二极与所述驱动信号端耦接；
所述第一电容的第一电极与所述第二降噪时钟信号端耦接，所述第一电容的第二电极与所述第五晶体管的栅极耦接；
所述第二电容的第一电极与所述第五晶体管的栅极耦接，所述第一电容的第二电极与所述驱动信号端耦接。
可选地，在本公开实施例中，所述级联输出电路包括：第六晶体管、第七晶体管、第三电容以及第四电容；
所述第六晶体管的栅极与所述第二上拉节点耦接，所述第六晶体管的第一极与所述第二控制时钟信号端耦接，所述第六晶体管的第二极与所述级联信号端耦接；
所述第七晶体管的栅极与所述下拉节点耦接，所述第七晶体管的第一极与所述第二参考信号端耦接，所述第七晶体管的第二极与所述级联信号端耦接；
所述第三电容的第一电极与所述第二上拉节点耦接，所述第三电容的第二电极与所述级联信号端耦接；
所述第四电容的第一电极与所述下拉节点耦接，所述第四电容的第二电极与所述第二参考信号端耦接。
可选地，在本公开实施例中，所述输入控制电路包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管；
所述第八晶体管的栅极与所述第一控制时钟信号端耦接，所述第八晶体管的第一极与所述输入信号端耦接，所述第八晶体管的第二极与所述第一上拉节点耦接；
所述第九晶体管的栅极与所述第一控制时钟信号端耦接，所述第九晶体管的第一极与所述第一参考信号端耦接，所述第九晶体管的第二极与所述下拉节点耦接；
所述第十晶体管的栅极与所述第一上拉节点耦接，所述第十晶体管的第一极与所述第一控制时钟信号端耦接，所述第十晶体管的第二极与所述下拉节点耦接；
所述第十一晶体管的栅极与所述下拉节点耦接，所述第十一晶体管的第一极与所述第二参考信号端耦接，所述第十一晶体管的第二极与所述第十二晶体管的第一极耦接；
所述第十二晶体管的栅极与所述第二控制时钟信号端耦接，所述第十二晶体管的第二极与所述第一上拉节点耦接。
可选地，在本公开实施例中，第四晶体管、第五晶体管、第六晶体管以及第七晶体管中的至少一个晶体管的有源层的沟道区的宽长比大于所述第一晶体管、第二晶体管、第三晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管中的至少一个晶体管的有源层的沟道区的宽长比。
可选地，在本公开实施例中，所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管中的至少一个晶体管的有源层的沟道区的宽长比的范围为10μm/2μm～100μm/10μm；
所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管以及所述第十二晶体管中的至少一个晶体管的有源层的沟道区的宽长比的范围为2μm/2μm～20μm/10μm。
可选地，在本公开实施例中，所述第一电容、所述第二电容、第三电容以及第四电容中的至少一个电容的电容值的范围为10fF～1pF。
本公开实施例提供的驱动控制电路，包括多个级联的上述移位寄存器；
第一级移位寄存器的输入信号端与帧触发信号端耦接；
每相邻两级移位寄存器中，下一级移位寄存器的输入信号端与上一级移位寄存器的级联信号端耦接。
本公开实施例提供的显示装置，包括上述驱动控制电路。
附图说明
图1为本公开实施例提供的移位寄存器的结构示意图；
图2为本公开实施例提供的驱动方法的流程图；
图3为本公开实施例提供的一些信号时序图；
图4为本公开实施例提供的一些仿真模拟图；
图5为本公开实施例提供的另一些信号时序图；
图6为本公开实施例提供的又一些信号时序图；
图7为本公开实施例提供的另一些仿真模拟图；
图8为本公开实施例提供的一些驱动控制电路的结构示意图；
图9为本公开实施例提供的一些显示装置的结构示意图；
图10为本公开实施例提供的另一些显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
通常情况下为了降低显示装置的功耗，可以使显示装置采用较低刷新频率(如1Hz)进行驱动，由于晶体管长时间漏电积累，从而导致驱动信号端输出的信号出现异常。
本公开实施例提供了一些移位寄存器，如图1所示，可以包括：
输入控制电路10，分别与输入信号端IP、第一控制时钟信号端CK、第二控制时钟信号端CKB、第一参考信号端VREF1、第二参考信号端VREF2、下拉节点PD以及第一上拉节点PU_1耦接；输入控制电路被配置为响应于第一控制时钟信号端CK的信号，将输入信号端IP的信号提供给第一上拉节点PU_1，并响应于下拉节点PD的信号和第二控制时钟信号端CKB的信号，将第二参考信号端VREF2的信号提供给第一上拉节点PU_1的信号，以及根据第一上拉节点PU_1的信号、第一控制时钟信号端CK的信号以及第一参考信号端VREF1的信号，控制下拉节点PD的信号；
第一晶体管M1，第一晶体管M1的栅极被配置为与第一参考信号端VREF1耦接，第一晶体管M1的第一极被配置为与第一上拉节点PU_1耦接，第一晶体管M1的第二极被配置为与第二上拉节点PU_2耦接；
级联输出电路20，分别与下拉节点PD、第二上拉节点PU_2、第二参考信号端VREF2、第二控制时钟信号端CKB以及级联信号端GP耦接；级联输出电路20被配置为在第二上拉节点PU_2的信号的控制下，将第二控制时钟信号端CKB的信号提供给级联信号端GP，并在下拉节点PD的信号的控制下，将第二参考信号端VREF2的信号提供给级联信号端GP；
驱动输出电路30，分别与级联信号端GP、第一降噪时钟信号端CKO、第二降噪时钟信号端CKBO、第一参考信号端VREF1、第二参考信号端VREF2以及驱动信号端OP耦接；驱动输出电路30被配置为响应于级联信号端GP的信号，将第二参考信号端VREF2的信号提供给驱动信号端OP，并响应于第一降噪时钟信号端CKO和第二降噪时钟信号端CKBO的信号，将第一参考信号端VREF1的信号提供给驱动信号端OP。
本公开实施例提供的移位寄存器，通过对各信号端加载相应的信号，以 使输入控制电路、第一晶体管以及驱动输出电路相互配合工作，可以使级联信号端和驱动信号端分别输出相应的信号。并且，还可以使移位寄存器在噪加强阶段补充电荷，使其确保输出去噪能力，保持驱动信号端的输出稳定，从而可以有利于本申请中的移位寄存器应用于较低刷新频率的显示装置中。
在具体实施时，如图1所示，第一上拉节点PU_1耦接于输入控制电路10中的第八晶体管M8的第二极与第一晶体管M1的第一极之间。第二上拉节点PU_2耦接于级联输出电路20中的第六晶体管M6的栅极与第一晶体管M1的第二极之间。下拉节点PD耦接于输入控制电路10中的第九晶体管M9的第二极与级联输出电路20中的第七晶体管M7的栅极之间。需要说明的是，第一上拉节点PU_1、第二上拉节点PU_2以及下拉节点PD分别是移位寄存器中的虚拟节点，这三个节点仅是为了方便对移位寄存器的结构和信号的传输进行描述，而针对移位寄存器的具体结构和信号的传输，可以根据移位寄存器中的各晶体管与电容之间的耦接方式来进行确定。
在具体实施时，在本公开实施例中，如图1所示，驱动输出电路30可以包括：第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第一电容C1以及第二电容C2；
第二晶体管M2的栅极与级联信号端GP耦接，第二晶体管M2的第一极与第二参考信号端VREF2耦接，第二晶体管M2的第二极与第五晶体管M5的栅极耦接；
第三晶体管M3的栅极与第一降噪时钟信号端CKO耦接，第三晶体管M3的第一极与第一参考信号端VREF1耦接，第三晶体管M3的第二极与第五晶体管M5的栅极耦接；
第四晶体管M4的栅极与级联信号端GP耦接，第四晶体管M4的第一极与第二参考信号端VREF2耦接，第四晶体管M4的第二极与驱动信号端OP耦接；
第五晶体管M5的第一极与第一参考信号端VREF1耦接，第五晶体管M5的第二极与驱动信号端OP耦接；
第一电容C1的第一电极与第二降噪时钟信号端CKBO耦接，第一电容C1的第二电极与第五晶体管M5的栅极耦接；
第二电容C2的第一电极与第五晶体管M5的栅极耦接，第一电容C1的第二电极与驱动信号端OP耦接。
在具体实施时，在本公开实施例中，如图1所示，级联输出电路20可以包括：第六晶体管M6、第七晶体管M7、第三电容C3以及第四电容C4；
第六晶体管M6的栅极与第二上拉节点PU_2耦接，第六晶体管M6的第一极与第二控制时钟信号端CKB耦接，第六晶体管M6的第二极与级联信号端GP耦接；
第七晶体管M7的栅极与下拉节点PD耦接，第七晶体管M7的第一极与第二参考信号端VREF2耦接，第七晶体管M7的第二极与级联信号端GP耦接；
第三电容C3的第一电极与第二上拉节点PU_2耦接，第三电容C3的第二电极与级联信号端GP耦接；
第四电容C4的第一电极与下拉节点PD耦接，第四电容C4的第二电极与第二参考信号端VREF2耦接。
在具体实施时，在本公开实施例中，如图1所示，输入控制电路10可以包括：第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11以及第十二晶体管M12；
第八晶体管M8的栅极与第一控制时钟信号端CK耦接，第八晶体管M8的第一极与输入信号端IP耦接，第八晶体管M8的第二极与第一上拉节点PU_1耦接；
第九晶体管M9的栅极与第一控制时钟信号端CK耦接，第九晶体管M9的第一极与第一参考信号端VREF1耦接，第九晶体管M9的第二极与下拉节点PD耦接；
第十晶体管M10的栅极与第一上拉节点PU_1耦接，第十晶体管M10的第一极与第一控制时钟信号端CK耦接，第十晶体管M10的第二极与下拉节 点PD耦接；
第十一晶体管M11的栅极与下拉节点PD耦接，第十一晶体管M11的第一极与第二参考信号端VREF2耦接，第十一晶体管M11的第二极与第十二晶体管M12的第一极耦接；
第十二晶体管M12的栅极与第二控制时钟信号端CKB耦接，第十二晶体管M12的第二极与第一上拉节点PU_1耦接。
在具体实施时，根据信号的流通方向，上述晶体管的第一极可以作为其源极，第二极可以作为其漏极；或者，第一极作为其漏极，第二极作为其源极，在此不作具体区分。
需要说明的是，本公开上述实施例中提到的晶体管可以是TFT，也可以是金属氧化物半导体场效应管(Metal Oxide Semiconductor，MOS)，在此不作限定。
为了简化制备工艺，在具体实施时，在本公开实施例中，如图1与图3所示，可以使所有晶体管均为P型晶体管。其中，P型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系V gs<V th时导通。例如，第三晶体管M3为P型晶体管时，则第三晶体管M3在其栅极与其源极之间的电压差V gs3与其阈值电压V th3之间的关系满足公式：V gs3<V th3时导通。当然，在本公开实施例中，仅是以晶体管为P型晶体管为例进行说明的，对于晶体管为N型晶体管的情况，设计原理与本公开相同，也属于本公开保护的范围。并且，N型晶体管在其栅极与其源极之间的电压差V gs与其阈值电压V th满足关系V gs>V th时导通。例如第三晶体管M3为N型晶体管时，第三晶体管M3在其栅极与其源极之间的电压差V gs3与其阈值电压V th3之间的关系满足公式：V gs3>V th3时导通。
进一步的，在具体实施时，P型晶体管在高电平信号作用下截止，在低电平信号作用下导通。N型晶体管在高电平信号作用下导通，在低电平信号作用下截止。
在具体实施时，可以使第四晶体管M4、第五晶体管M5、第六晶体管 M6以及第七晶体管M7中的至少一个晶体管的有源层的沟道区的宽长比大于第一晶体管M1、第二晶体管M2、第三晶体管M3、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11以及第十二晶体管M12中的至少一个晶体管的有源层的沟道区的宽长比。示例性地，可以使第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比大于第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比。
在具体实施时，可以使第四晶体管M4、第五晶体管M5、第六晶体管M6以及第七晶体管M7中的至少一个晶体管的有源层的沟道区的宽长比的范围为10μm/2μm～100μm/10μm。示例性地，可以使第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比的范围分别为10μm/2μm～100μm/10μm。例如，可以使第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比的范围分别为10μm/2μm。也可以使第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比的范围分别为100μm/10μm。也可以使第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比的范围分别为50μm/5μm。
当然，在实际应用中，可以根据实际应用的需求具体设计第四晶体管M4的有源层的沟道区的宽长比、第五晶体管M5的有源层的沟道区的宽长比、第六晶体管M6的有源层的沟道区的宽长比以及第七晶体管M7的有源层的沟道区的宽长比的数值，在此不作限定。
在具体实施时，可以使第一晶体管M1、第二晶体管M2、第三晶体管M3、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11以及第十二晶体管M12中的至少一个晶体管的有源层的沟道区的宽长比的范围为2μm/2μm～20μm/10μm。示例性地，可以使第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比的范围为2μm/2μm～20μm/10μm。例如，可以使第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比的范围为2μm/2μm。也可以使第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比的范围为20μm/10μm。也可以使第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟 道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比的范围为10μm/5μm。
当然，在实际应用中，可以根据实际应用的需求具体设计第一晶体管M1的有源层的沟道区的宽长比、第二晶体管M2的有源层的沟道区的宽长比、第三晶体管M3的有源层的沟道区的宽长比、第八晶体管M8的有源层的沟道区的宽长比、第九晶体管M9的有源层的沟道区的宽长比、第十晶体管M10的有源层的沟道区的宽长比、第十一晶体管M11的有源层的沟道区的宽长比以及第十二晶体管M12的有源层的沟道区的宽长比的数值，在此不作限定。
在具体实施时，可以使第一电容C1、第二电容C2、第三电容C3以及第四电容C4中的至少一个电容的电容值的范围为10fF～1pF。示例性地，可以使第一电容C1、第二电容C2、第三电容C3以及第四电容C4中的至少一个电容的电容值的范围为10fF。也可以使第一电容C1、第二电容C2、第三电容C3以及第四电容C4中的至少一个电容的电容值的范围为50fF。也可以使第一电容C1、第二电容C2、第三电容C3以及第四电容C4中的至少一个电容的电容值的范围为1pF。当然，在实际应用中，可以根据实际应用的需求具体设计第一电容C1的电容值、第二电容C2的电容值、第三电容C3的电容值以及第四电容C4的电容值，在此不作限定。
以上仅是举例说明本公开实施例提供的移位寄存器的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
基于同一发明构思，本公开实施例还提供了移位寄存器的驱动方法，结合图2所示，该驱动方法可以包括：在第一刷新频率时，一个显示帧包括数据刷新阶段T10和数据保持阶段T20；数据保持阶段T20包括交替设置的去噪保持阶段和去噪加强阶段。
S210、在数据刷新阶段T10，对输入信号端IP加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端VREF1加载固定电压信号，对第二参考 信号端VREF2加载固定电压信号，控制移位寄存器的级联信号端GP输出具有脉冲电平的级联信号以及控制移位寄存器的驱动信号端OP输出具有脉冲电平的驱动信号；
S220、在去噪保持阶段，对输入信号端IP加载固定电压信号，对控制时钟信号端加载固定电压信号，对降噪时钟信号端加载固定电压信号，对第一参考信号端VREF1加载固定电压信号，对第二参考信号端VREF2加载固定电压信号，控制级联信号端GP输出固定电压信号以及控制驱动信号端OP输出固定电压信号；
S230、在去噪加强阶段，对输入信号端IP加载固定电压信号，对控制时钟信号端加载固定电压信号，对降噪时钟信号端加载时钟脉冲信号，对第一参考信号端VREF1加载固定电压信号，对第二参考信号端VREF2加载固定电压信号，控制级联信号端GP输出固定电压信号以及控制驱动信号端OP输出固定电压信号。
本公开实施例提供的移位寄存器的驱动方法，在数据刷新阶段T10，可以通过对输入信号端IP加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端VREF1加载固定电压信号，对第二参考信号端VREF2加载固定电压信号，以控制级联信号端GP输出具有脉冲电平的级联信号以及控制驱动信号端OP输出具有脉冲电平的驱动信号，这样可以实现移位寄存器的级联输出和驱动输出，从而可以使显示装置进行数据刷新。在去噪保持阶段，可以通过对输入信号端IP加载固定电压信号，对控制时钟信号端加载固定电压信号，对降噪时钟信号端加载固定电压信号，对第一参考信号端VREF1加载固定电压信号，对第二参考信号端VREF2加载固定电压信号，以控制级联信号端GP输出固定电压信号以及控制驱动信号端OP输出固定电压信号，这样可以实现移位寄存器输出保持。在去噪加强阶段，可以通过对输入信号端IP加载固定电压信号，对控制时钟信号端加载固定电压信号，对降噪时钟信号端加载时钟脉冲信号，对第一参考信号端VREF1加载固定电压信号，对第二参考 信号端VREF2加载固定电压信号，以控制级联信号端GP输出固定电压信号以及控制驱动信号端OP输出固定电压信号，这样可以使移位寄存器补充电荷，使其确保输出去噪能力，保持驱动信号端OP的输出稳定。
并且，一般显示装置可能会长时间处于静态画面显示状态，或者待机状态，为了降低功耗，可以使显示装置采用较低的刷新频率(例如1Hz、30Hz)工作。本公开实施例中的移位寄存器，通过在去噪加强阶段，可以使移位寄存器补充电荷，使其确保输出去噪能力，保持驱动信号端OP的输出稳定，可以有利于本申请中的移位寄存器应用于较低刷新频率的显示装置中。
在具体实施时，在本公开实施例中，第一电平可以为低电平，第二电平可以为高电平。或者，第一电平也可以为高电平，第二电平也可以为低电平。在实际应用中，可以根据实际应用需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，驱动方法还包括：在第二刷新频率时，一个显示帧包括数据刷新阶段T10；其中，在数据刷新阶段T10，对输入信号端IP加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端VREF1加载固定电压信号，对第二参考信号端VREF2加载固定电压信号，控制移位寄存器的级联信号端GP输出具有脉冲电平的级联信号以及控制移位寄存器的驱动信号端OP输出具有脉冲电平的驱动信号。
一般显示装置可能会长时间处于静态画面显示状态，或者待机状态，为了降低功耗，可以使显示装置采用较低的刷新频率(例如1Hz、30Hz)工作。当然，显示装置也可以显示视频画面，为了提高视频画面的显示效果，可以使显示装置采用较高的刷新频率(例如60Hz、120Hz)进行工作。在具体实施时，在本公开实施例中，第一刷新频率可以为较低刷新频率，例如1Hz、30Hz。第二刷新频率可以为较高刷新频率，例如60Hz、120Hz。
在具体实施时，在本公开实施例中，控制时钟信号端包括第一控制时钟信号端CK和第二控制时钟信号端CKB；控制时钟脉冲信号包括第一控制时钟脉冲信号和第二控制时钟脉冲信号；其中，第一控制时钟脉冲信号和第二 控制时钟脉冲信号的周期相同且相位差为1/2周期。并且，在数据刷新阶段T10，对控制时钟信号端加载控制时钟脉冲信号，具体可以包括：对第一控制时钟信号端CK加载第一控制时钟脉冲信号，以及对第二控制时钟信号端CKB加载第二控制时钟脉冲信号。
示例性地，如图1与图3所示，ck代表第一控制时钟信号端CK加载的信号，ckb代表第二控制时钟信号端CKB加载的信号。在数据刷新阶段T10，第一控制时钟信号端CK加载的第一控制时钟脉冲信号为高低电平切换的时钟脉冲信号，第二控制时钟信号端CKB加载的第二控制时钟脉冲信号也为高低电平切换的时钟脉冲信号。并且，第一控制时钟脉冲信号和第二控制时钟脉冲信号的周期相同且相位差为1/2周期。例如，第一控制时钟脉冲信号和第二控制时钟脉冲信号的占空比相同，且占空比大于50％。当然，在实际应用中，第一控制时钟脉冲信号和第二控制时钟脉冲信号的具体实施方式可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，在去噪保持阶段和在去噪加强阶段中，对控制时钟信号端加载固定电压信号，具体可以包括：对第一控制时钟信号端CK加载具有第二电平的固定电压信号，对第二控制时钟信号端CKB加载具有第二电平的固定电压信号。示例性地，如图1与图3所示，在移位寄存器中的晶体管为P型晶体管时，可以对第一控制时钟信号端CK加载具有高电平的固定电压信号，对第二控制时钟信号端CKB加载具有高电平的固定电压信号。在移位寄存器中的晶体管为N型晶体管时，可以对第一控制时钟信号端CK加载具有低电平的固定电压信号，对第二控制时钟信号端CKB加载具有低电平的固定电压信号。
在具体实施时，在本公开实施例中，在去噪保持阶段和在去噪加强阶段中，对输入信号端IP加载固定电压信号，具体可以包括：对输入信号端IP加载具有第二电平的固定电压信号。示例性地，如图1与图3所示，ip代表输入信号端IP加载的信号。在移位寄存器中的晶体管为P型晶体管时，可以对输入信号端IP加载具有高电平的固定电压信号。在移位寄存器中的晶体管为 N型晶体管时，可以对输入信号端IP加载具有低电平的固定电压信号。
在具体实施时，在本公开实施例中，在去噪保持阶段和在去噪加强阶段中，控制级联信号端GP输出固定电压信号以及控制驱动信号端OP输出固定电压信号，具体可以包括：控制级联信号端GP输出具有第二电平的固定电压信号以及控制驱动信号端OP输出具有第一电平的固定电压信号。示例性地，如图1与图3所示，gp代表级联信号端GP输出的信号，op代表驱动信号端OP输出的信号。在移位寄存器中的晶体管为P型晶体管时，可以控制级联信号端GP输出具有高电平的固定电压信号以及控制驱动信号端OP输出具有低电平的固定电压信号。在移位寄存器中的晶体管为N型晶体管时，可以控制级联信号端GP输出具有低电平的固定电压信号以及控制驱动信号端OP输出具有高电平的固定电压信号。
在具体实施时，在本公开实施例中，可以使输入信号的脉冲电平为第一电平。这样在第八晶体管M8导通时，可以将输入信号的脉冲电平输入到第一上拉节点PU_1，以使第一上拉节点PU_1的电平为第一电平，从而可以通过第一上拉节点PU_1的电平控制第十晶体管M10导通。示例性地，如图1与图3所示，在移位寄存器中的晶体管为P型晶体管时，输入信号的脉冲电平为低电平。在移位寄存器中的晶体管为N型晶体管时，输入信号的脉冲电平为高电平。
在具体实施时，在本公开实施例中，可以使级联信号的脉冲电平为第一电平。这样可以使第四晶体管M4在级联信号的脉冲电平的控制下导通，以将第二参考信号端VREF2的信号提供给驱动信号端OP。示例性地，如图1与图3所示，在移位寄存器中的晶体管为P型晶体管时，级联信号的脉冲电平为低电平。在移位寄存器中的晶体管为N型晶体管时，级联信号的脉冲电平为高电平。
在具体实施时，在本公开实施例中，可以使第一参考信号端VREF1的固定电压信号为第一电平，第二参考信号端VREF2的固定电压信号为第二电平，驱动信号的脉冲电平为第二电平。示例性地，如图1与图3所示，在移位寄 存器中的晶体管为P型晶体管时，第一电平为低电平且第二电平为高电平。在移位寄存器中的晶体管为N型晶体管时，第一电平为高电平且第二电平为低电平。
在具体实施时，在本公开实施例中，降噪时钟信号端可以包括第一降噪时钟信号端CKO和第二降噪时钟信号端CKBO。降噪时钟脉冲信号包括第一降噪时钟脉冲信号和第二降噪时钟脉冲信号；其中，第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的周期相同且相位差为1/2周期。并且，在数据刷新阶段T10，对降噪时钟信号端加载降噪时钟脉冲信号，具体可以包括：对第一降噪时钟信号端CKO加载第一降噪时钟脉冲信号，以及对第二降噪时钟信号端CKBO加载第二降噪时钟脉冲信号。
示例性地，如图1与图3所示，cko代表第一降噪时钟信号端CKO加载的信号，ckbo代表第二降噪时钟信号端CKBO加载的信号。在数据刷新阶段T10，第一降噪时钟信号端CKO加载的第一降噪时钟脉冲信号为高低电平切换的时钟脉冲信号，第二降噪时钟信号端CKBO加载的第二降噪时钟脉冲信号也为高低电平切换的时钟脉冲信号。并且，第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的周期相同且相位差为1/2周期。例如，第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的占空比相同，且占空比大于50％。当然，在实际应用中，第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的具体实施方式可以根据实际应用的需求进行设计确定，在此不作限定。
在一些示例中，如图3所示，可以使第一降噪时钟脉冲信号的周期和第一控制时钟脉冲信号的周期相同。进一步地，可以使第一降噪时钟脉冲信号的占空比和第一控制时钟脉冲信号的占空比相同。示例性地，第一降噪时钟脉冲信号的下降沿与第二时钟脉冲信号的上升沿对齐。第二降噪时钟脉冲信号的下降沿与第一控制时钟脉冲信号的上升沿对齐。当然，在实际应用中，第一降噪时钟脉冲信号、第二降噪时钟脉冲信号、第一控制时钟脉冲信号以及第二控制时钟脉冲信号之间的关系，可以根据实际需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，在去噪保持阶段，对降噪时钟信号端加载固定电压信号，具体可以包括：对第一降噪时钟信号端CKO加载具有第一电平的固定电压信号，对第二降噪时钟信号端CKBO加载具有第一电平的固定电压信号。示例性地，如图1与图3所示，在移位寄存器中的晶体管为P型晶体管时，在去噪保持阶段，对第一降噪时钟信号端CKO加载具有低电平的固定电压信号，对第二降噪时钟信号端CKBO加载具有低电平的固定电压信号。在移位寄存器中的晶体管为N型晶体管时，在去噪保持阶段，对第一降噪时钟信号端CKO加载具有高电平的固定电压信号，对第二降噪时钟信号端CKBO加载具有高电平的固定电压信号。
在具体实施时，在本公开实施例中，在去噪加强阶段，对降噪时钟信号端加载时钟脉冲信号，具体包括：对第一降噪时钟信号端CKO加载第一降噪时钟脉冲信号，以及对第二降噪时钟信号端CKBO加载第二降噪时钟脉冲信号；其中，去噪加强阶段中第一降噪时钟脉冲信号的第一电平与在去噪加强阶段之前出现的去噪保持阶段相邻，去噪加强阶段中第二降噪时钟脉冲信号的第二电平与在去噪加强阶段之前出现的去噪保持阶段相邻。
示例性地，如图1与图3所示，在去噪加强阶段，第一降噪时钟信号端CKO加载的第一降噪时钟脉冲信号为高低电平切换的时钟脉冲信号，第二降噪时钟信号端CKBO加载的第二降噪时钟脉冲信号也为高低电平切换的时钟脉冲信号。并且，在移位寄存器中的晶体管为P型晶体管时，去噪加强阶段中第一降噪时钟脉冲信号的低电平与在去噪加强阶段之前出现的去噪保持阶段相邻，去噪加强阶段中第二降噪时钟脉冲信号的高电平与在去噪加强阶段之前出现的去噪保持阶段相邻。在移位寄存器中的晶体管为N型晶体管时，去噪加强阶段中第一降噪时钟脉冲信号的高电平与在去噪加强阶段之前出现的去噪保持阶段相邻，去噪加强阶段中第二降噪时钟脉冲信号的低电平与在去噪加强阶段之前出现的去噪保持阶段相邻。
在具体实施时，在本公开实施例中，在去噪加强阶段中，第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的时钟周期数目相同，且时钟周期数目至 少为一个。示例性地，如图3所示，在去噪加强阶段中，第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的时钟周期数目为一个。也可以使第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的时钟周期数目为两个、三个、四个或更多个，在此不作限定。
在具体实施时，在本公开实施例中，如图3所示，同一去噪加强阶段中，第一降噪时钟脉冲信号的下降沿、第二降噪时钟脉冲信号的下降沿分别与在去噪加强阶段之后出现的去噪保持阶段的开始时刻对齐，且第二降噪时钟脉冲信号的上升沿与在去噪加强阶段之前出现的去噪保持阶段的结束时刻对齐。数据刷新阶段T10和去噪加强阶段中，第二降噪时钟脉冲信号的第二电平的维持时长相同。例如，数据刷新阶段T10和去噪加强阶段中，第二降噪时钟脉冲信号的高电平的维持时长相同，并且，第二降噪时钟脉冲信号的低电平的维持时长也相同。
下面以图1所示的移位寄存器为例，结合图3所示的信号时序图对本公开实施例提供的上述移位寄存器在第一刷新频率时的工作过程作以描述。下述描述中以1表示高电平信号，0表示低电平信号，需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是在具体实施时施加在各晶体管的栅极上的电压。
具体地，如图3所示，在第一刷新频率时，一个显示帧可以包括数据刷新阶段T10和数据保持阶段T20；数据刷新阶段T10包括交替设置的去噪保持阶段T21-1、去噪加强阶段T22-1。需要说明的是，图3所示的信号时序图仅是一个移位寄存器在一个当前显示帧中的工作过程。该移位寄存器在其他显示帧中的工作过程分别与该当前显示帧中的工作过程基本相同，在此不作赘述。
其中，数据刷新阶段T10包括T11阶段、T12阶段、T13阶段以及T14阶段。具体地，在T11阶段中，ip＝0，ckb＝1，ck＝0，cko＝0，ckbo＝1。由于ckb＝1，因此第十二晶体管M12截止。由于ck＝0，因此第九晶体管M9导通，以将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点 PD的信号为低电平信号，以控制第七晶体管M7导通。导通的第七晶体管M7将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号。由于ck＝0，因此第八晶体管M8导通，以将输入信号端IP的低电平信号提供给第一上拉节点PU_1，使第一上拉节点PU_1为低电平信号，以控制第十晶体管M10导通，从而将第一控制时钟信号端CK的低电平信号提供给下拉节点PD，进一步使下拉节点PD的信号为低电平信号。由于第一晶体管M1满足V gs1<V th1，以使第一晶体管M1导通。导通的第一晶体管M1将第二上拉节点PU_2与第一上拉节点PU_1导通，从而可以及时使第二上拉节点PU_2的信号为低电平信号，以控制第六晶体管M6导通，从而将第二控制时钟信号端CKB的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的级联信号。由于级联信号端GP输出高电平的信号，可以控制第二晶体管M2和第四晶体管M4截止。由于cko＝0，因此第三晶体管M3导通，以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，从而控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。
在T12阶段中，ip＝1，ckb＝0，ck＝1，cko＝1，ckbo＝0。由于ck＝1，因此第九晶体管M9和第八晶体管M8均截止。第二上拉节点PU_2在第三电容C3的作用下保持为低电平信号，以控制第六晶体管M6导通，从而将第二控制时钟信号端CKB的低电平信号提供给级联信号端GP，使级联信号端GP输出低电平的级联信号。由于第三电容C3的作用，使第二上拉节点PU_2的电平进一步拉低，以控制第六晶体管M6可以尽可能充分导通，以将第二控制时钟信号端CKB的低电平信号提供给级联信号端GP，使级联信号端GP输出低电平的级联信号。并且，此阶段中，第一晶体管M1与第一上拉节点PU_1耦接的一极作为其源极，从而可以使第一晶体管M1不能满足V gs1<V th1，以使第一晶体管M1截止，从而可以保持第二上拉节点PU_2的电平稳定，避免由于漏电导致第二上拉节点PU_2的电平升高，而导致的级联信号端GP输出不稳定的情况。
并且，第十晶体管M10在第一上拉节点PU_1的信号的控制下将第一控制时钟信号端CK的高电平信号提供给下拉节点PD，以控制第七晶体管M7截止，避免对级联信号端GP输出的信号造成不利影响。由于cko＝1，因此第三晶体管M3截止。由于级联信号端GP输出低电平的信号，可以控制第二晶体管M2和第四晶体管M4导通。导通的第二晶体管M2可以将第二参考信号端VREF2的高电平信号提供给第五晶体管M5的栅极，以控制第五晶体管M5截止。导通的第四晶体管M4可以将第二参考信号端VREF2的高电平信号提供给驱动信号端OP，使驱动信号端OP输出高电平的驱动信号。
在T12阶段之后，在T13阶段之前，由于ckb＝1，因此第十二晶体管M12截止。由于ck＝1，因此第九晶体管M9和第八晶体管M8均截止。第二上拉节点PU_2在第三电容C3的作用下保持为低电平信号，以控制第六晶体管M6导通，从而将第二控制时钟信号端CKB的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的级联信号，以控制第二晶体管M2和第四晶体管M4均截止。由于第一降噪时钟信号端CKO的信号cko由高电平转变为低电平，因此第三晶体管M3导通，从而可以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，进而控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。
在T13阶段中，ip＝1，ckb＝1，ck＝0，cko＝0，ckbo＝1。
由于ckb＝1，因此第十二晶体管M12截止。由于ck＝0，第八晶体管M8和第九晶体管M9均导通。导通的第八晶体管M8将输入信号端IP的高电平信号提供给第一上拉节点PU_1，使第一上拉节点PU_1为高电平信号，以控制第十晶体管M10截止。由于第一参考信号端VREF1为低电平信号，因此第一晶体管M1导通，以将第一上拉节点PU_1的高电平信号提供给第二上拉节点PU_2，以控制第六晶体管M6截止。导通的第九晶体管M9将第一参考信号端VREF1的低电平信号提供给下拉节点PD，使下拉节点PD的信号为低电平信号，以控制第七晶体管M7导通。导通的第七晶体管M7将第二参考信 号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号，以控制第二晶体管M2和第四晶体管M4均截止。由于cko＝0，因此第三晶体管M3导通，从而可以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，进而控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。并且，通过第一电容C1和第二电容C2保持其两端的电压差稳定。
在T14阶段中，ip＝1，ckb＝0，ck＝1，cko＝1，ckbo＝0。
由于ck＝1，因此第八晶体管M8和第九晶体管M9均截止，则由于第四电容C4的作用可以将下拉节点PD的信号保持为低电平信号，控制第七晶体管M7导通，以将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号，以控制第二晶体管M2和第四晶体管M4均截止。由于cko＝0，因此第三晶体管M3导通，从而可以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，进而控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。并且，第十一晶体管M11和第十二晶体管M12均导通，从而可以使第一上拉节点PU_1为高电平信号，进而使第二上拉节点PU_2为高电平信号，以控制第六晶体管M6截止。
在T14阶段之后，一直重复执行T13阶段和T14阶段的工作过程，直至进入去噪保持阶段T21-1。
在去噪保持阶段T21-1，ip＝1，ckb＝1，ck＝1，cko＝0，ckbo＝0。由于ck＝1，因此第八晶体管M8和第九晶体管M9均截止，则由于第四电容C4的作用可以将下拉节点PD的信号保持为低电平信号，控制第七晶体管M7导通，以将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号，以控制第二晶体管M2和第四晶体管M4均截止。由于cko＝0，因此第三晶体管M3导通，从而可以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，进而控制第五晶体管M5导通，以 将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。
然而，在实际应用中，由于去噪保持阶段T21-1中cko＝0，这样会使得第三晶体管M3的阈值进行漂移，由于第一参考信号端VREF1也为低电平，并且第三晶体管M3的第一极为源极，因此第三晶体管M3的栅源电压差不能小于第三晶体管M3的阈值电压，这样使得第三晶体管M3截止，从而导致第五晶体管M5的栅极电压可能会升高，进而导致第五晶体管M5的开启程度降低，使得驱动信号端OP输出的低电平出现拉高的噪声。基于此，在去噪加强阶段T22-1中，对第一降噪时钟信号端CKO加载第一降噪时钟脉冲信号，对第二降噪时钟信号端CKBO加载第二降噪时钟脉冲信号，可以使第三晶体管M3可以正常开启，从而使第五晶体管M5的栅极进行放电，提高第五晶体管M5的打开程度，进而提高驱动信号端OP输出的稳定性。
具体地，在去噪加强阶段T22-1中，首先，ip＝1，ckb＝1，ck＝1，cko＝0，ckbo＝1。由于ck＝1，因此第八晶体管M8和第九晶体管M9均截止，则由于第四电容C4的作用可以将下拉节点PD的信号保持为低电平信号，控制第七晶体管M7导通，以将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号，以控制第二晶体管M2和第四晶体管M4均截止。由于ckbo由低电平切换为高电平，由于第一电容C1的耦合作用，使得第五晶体管M5的栅极电压拉高。此时，第三晶体管M3的第二极为源极，由于cko＝0，因此第三晶体管M3的栅源电压差小于第三晶体管M3的阈值电压，这样使得第三晶体管M3可以开始。由于第三晶体管M3导通，可以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，从而可以将第五晶体管M5的栅极进行放电，进而使得第一电容C1的第一电极为高电平，第一电容C1的第二电极为低电平。并且，也控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。
之后，ip＝1，ckb＝1，ck＝1，cko＝1，ckbo＝0。由于ck＝1，因此第八晶体 管M8和第九晶体管M9均截止，则由于第四电容C4的作用可以将下拉节点PD的信号保持为低电平信号，控制第七晶体管M7导通，以将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号，以控制第二晶体管M2和第四晶体管M4均截止。由于cko＝1，因此第三晶体管M3截止。由于ckbo由高电平切换为低电平，由于第一电容C1的耦合作用，使得第五晶体管M5的栅极电压进一步拉低，以控制第五晶体管M5可以尽可能的完全导通，以将第一参考信号端VREF1的低电平信号尽可能无电压损失的提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。
之后，ip＝1，ckb＝1，ck＝1，cko＝0，ckbo＝1。再次重复上述ip＝1，ckb＝1，ck＝1，cko＝0，ckbo＝1时的工作过程，以将第五晶体管M5的栅极进行放电，进而使得第一电容C1的第一电极为高电平，第一电容C1的第二电极为低电平。
在去噪加强阶段T22-1之后，一直重复执行去噪保持阶段T21-1和去噪加强阶段T22-1的工作过程，直至输入信号端IP的信号的电平再次变为高电平时为止。
需要说明的是，数据刷新阶段T10中，T11阶段与T12阶段之间、T12阶段与T13阶段之间、T13阶段与T14阶段之间分别具有缓冲阶段(例如，信号ckb、信号ck、信号cko以及信号ckbo均为高电平的阶段)。在缓冲阶段中，可以使移位寄存器中的晶体管的特性进行稳定，以在稳定后进入下一个工作阶段。并且，由于缓冲阶段的存在，从而使得信号ckb和信号ck的上升沿和下降沿并不会完全对应，以及使得信号ckbo和信号cko的上升沿和下降沿也不会完全对应。这样可以避免信号ckb的下降沿与信号ck的上升沿对齐，避免信号ckb的上升沿与信号ck的下降沿对齐，避免信号cko的下降沿与信号ckbo的上升沿对齐，避免信号cko的上升沿与信号ckbo的下降沿对齐，从而可以提高移位寄存器的稳定性。
需要说明的是，数据保持阶段T20中，在去噪加强阶段T22-1内，信号 cko与信号ckbo也具有缓冲阶段(即信号cko与信号ckbo均为高电平的阶段)，在缓冲阶段中，可以使移位寄存器中的晶体管的特性进行稳定，以在稳定后进入下一个工作阶段。并且，由于缓冲阶段的存在，从而使得信号ckbo和信号cko的上升沿和下降沿也不会完全对应。这样可以避免信号cko的下降沿与信号ckbo的上升沿对齐，避免信号cko的上升沿与信号ckbo的下降沿对齐，从而可以提高移位寄存器的稳定性。以及，由于信号cko与信号ckbo具有缓冲阶段，从而使得信号cko在去噪加强阶段T22-1最后会有一个时长较小的波峰。
需要说明的是，在实际应用中，上述各信号的具体电压值可以根据实际应用环境来设计确定，在此不作限定。
并且，还根据图3所示的信号时序图，对图1所示的移位寄存器的驱动信号端OP输出的信号进行仿真模拟，仿真模拟图如图4所示。其中，横坐标代表时间，纵坐标代表电压。S1代表采用图3所示的信号时序图对图1所示的移位寄存器的驱动信号端OP进行仿真模拟的信号。S0代表在数据保持阶段T20中仅具有降噪保持阶段时，移位寄存器的驱动信号端OP进行仿真模拟的信号。结合图3可知，本公开实施例通过设置降噪加强阶段，可以使驱动信号端OPGP稳定的输出信号，从而可以改善由于漏电导致的不稳定的问题。
并且，还根据图3所示的信号时序图驱动图1所示的移位寄存器进行工作，在数据保持阶段T20进行工作时，检测到移位寄存器的功耗为0.5mW。因此可知，即使在数据保持阶段T20中插入了时钟脉冲，移位寄存器的功耗也可以在可接受范围之内。
下面以图1所示的移位寄存器为例，结合图5所示的信号时序图对本公开实施例提供的上述移位寄存器在第二刷新频率时的工作过程作以描述。下述描述中以1表示高电平信号，0表示低电平信号，需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是在具体实施时施加在各晶体管的栅极上的电压。
具体地，如图5所示，在第二刷新频率时，一个显示帧可以包括数据刷 新阶段T10。需要说明的是，图5所示的信号时序图仅是一个移位寄存器在一个当前显示帧中的工作过程。该移位寄存器在其他显示帧中的工作过程分别与该当前显示帧中的工作过程基本相同，在此不作赘述。
数据刷新阶段T10包括T11阶段、T12阶段、T13阶段以及T14阶段。并且，本公开实施例提供的上述移位寄存器在图5所示的信号时序图的工作过程与在图3所示的信号时序图中数据刷新阶段T10的工作过程基本相同，在此不作赘述。
本公开实施例又提供了另一些驱动方法，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，在去噪加强阶段中，第一降噪时钟脉冲信号的时钟周期数目为偶数个。示例性地，示例性地，如图6所示，可以使第一降噪时钟脉冲信号的时钟周期数目为2个。也可以使第一降噪时钟脉冲信号的时钟周期数目为4个、6个或更多个，在此不作限定。
在具体实施时，在本公开实施例中，同一去噪加强阶段中，第一降噪时钟脉冲信号的下降沿与在去噪加强阶段之后出现的去噪保持阶段的开始时刻对齐，以及第一降噪时钟脉冲信号中靠近在去噪加强阶段之前出现的去噪保持阶段的上升沿与在去噪加强阶段之前出现的去噪保持阶段之间的信号为第一电平。示例性地，如图6所示，可以使同一去噪加强阶段T22-1中，信号cko的第一降噪时钟脉冲信号的下降沿与在去噪加强阶段T22-1之后出现的去噪保持阶段T21-2的开始时刻对齐，以及信号cko的第一降噪时钟脉冲信号中靠近在去噪加强阶段T22-1之前出现的去噪保持阶段T21-1的上升沿与在去噪加强阶段T22-1之前出现的去噪保持阶段T21-1之间的信号为低电平。
在具体实施时，在本公开实施例中，同一去噪加强阶段中，第二降噪时钟脉冲信号的上升沿与在去噪加强阶段之前出现的去噪保持阶段的结束时刻对齐，以及第二降噪时钟脉冲信号中靠近在去噪加强阶段之后出现的去噪保持阶段的下降沿与在去噪加强阶段之后出现的去噪保持阶段之间的信号为第 一电平。示例性地，如图6所示，可以使同一去噪加强阶段中，信号ckbo的第二降噪时钟脉冲信号的上升沿与在去噪加强阶段T22-1之前出现的去噪保持阶段T21-1的结束时刻对齐，以及信号ckbo的第二降噪时钟脉冲信号中靠近在去噪加强阶段T22-1之后出现的去噪保持阶段T21-2的下降沿与在去噪加强阶段T22-1之后出现的去噪保持阶段T21-2之间的信号为低电平。
下面以图1所示的移位寄存器为例，结合图6所示的信号时序图对本公开实施例提供的上述移位寄存器在第一刷新频率时的工作过程作以描述。下述描述中以1表示高电平信号，0表示低电平信号，需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是在具体实施时施加在各晶体管的栅极上的电压。
具体地，如图6所示，在第一刷新频率时，一个显示帧可以包括数据刷新阶段T10和数据保持阶段T20；数据刷新阶段T10包括交替设置的去噪保持阶段和去噪加强阶段。需要说明的是，图6所示的信号时序图仅是一个移位寄存器在一个当前显示帧中的工作过程。该移位寄存器在其他显示帧中的工作过程分别与该当前显示帧中的工作过程基本相同，在此不作赘述。
在数据刷新阶段T10和去噪保持阶段T21-1的工作过程可以参照上述工作过程，在此不作赘述。
在去噪加强阶段T22-1，首先，ip＝1，ckb＝1，ck＝1，cko＝0，ckbo＝1。由于ck＝1，因此第八晶体管M8和第九晶体管M9均截止，则由于第四电容C4的作用可以将下拉节点PD的信号保持为低电平信号，控制第七晶体管M7导通，以将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号，以控制第二晶体管M2和第四晶体管M4均截止。由于ckbo由低电平切换为高电平，由于第一电容C1的耦合作用，使得第五晶体管M5的栅极电压拉高。此时，第三晶体管M3的第二极为源极，由于cko＝0，因此第三晶体管M3的栅源电压差小于第三晶体管M3的阈值电压，这样使得第三晶体管M3可以开始。由于第三晶体管M3导通，可以将第一参考信号端VREF1的低电平信号提供给第五晶体管M5的栅极，从而可以 将第五晶体管M5的栅极进行放电，进而使得第一电容C1的第一电极为高电平，第一电容C1的第二电极为低电平。并且，也控制第五晶体管M5导通，以将第一参考信号端VREF1的低电平信号提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。
之后，ip＝1，ckb＝1，ck＝1，cko＝1，ckbo＝0。由于ck＝1，因此第八晶体管M8和第九晶体管M9均截止，则由于第四电容C4的作用可以将下拉节点PD的信号保持为低电平信号，控制第七晶体管M7导通，以将第二参考信号端VREF2的高电平信号提供给级联信号端GP，使级联信号端GP输出高电平的信号，以控制第二晶体管M2和第四晶体管M4均截止。由于cko＝1，因此第三晶体管M3截止。由于ckbo由高电平切换为低电平，由于第一电容C1的耦合作用，使得第五晶体管M5的栅极电压进一步拉低，以控制第五晶体管M5可以尽可能的完全导通，以将第一参考信号端VREF1的低电平信号尽可能无电压损失的提供给驱动信号端OP，使驱动信号端OP输出低电平的驱动信号。
之后，再次重复上述ip＝1，ckb＝1，ck＝1，cko＝0，ckbo＝1时和ip＝1，ckb＝1，ck＝1，cko＝1，ckbo＝0时的工作过程，具体在此不作赘述。
并且，还根据图6所示的信号时序图，对图1所示的移位寄存器的驱动信号端OP输出的信号进行仿真模拟，仿真模拟图如图7所示。其中，横坐标代表时间，纵坐标代表电压。S2代表采用图6所示的信号时序图对图1所示的移位寄存器的驱动信号端OP进行仿真模拟的信号。S0代表在数据保持阶段T20中仅具有降噪保持阶段时，移位寄存器的驱动信号端OP进行仿真模拟的信号。结合图6可知，本公开实施例通过设置降噪加强阶段，可以使驱动信号端OPGP稳定的输出信号，从而可以改善由于漏电导致的不稳定的问题。
并且，还根据图6所示的信号时序图驱动图1所示的移位寄存器进行工作，在数据保持阶段T20进行工作时，检测到移位寄存器的功耗为0.5mW。因此可知，即使在数据保持阶段T20中插入了时钟脉冲，移位寄存器的功耗也可以在可接受范围之内。
需要说明的是，不同去噪保持阶段的维持时长可以相同，也可以不同，这样可以根据实际应用的需求进行设计确定，在此不作限定。
基于同一发明构思，本公开实施例还提供了驱动控制电路，如图8所示，包括级联的多个本公开实施例提供的上述任意移位寄存器SR(1)、SR(2)…SR(n-1)、SR(n)…SR(N-1)、SR(N)(共N个移位寄存器，1≤n≤N，n为整数)；其中，第一级移位寄存器SR(1)的输入信号端IP被配置为与帧触发信号端STV耦接；
每相邻两个移位寄存器中，下一级移位寄存器SR(n)的输入信号端IP被配置为与上一级移位寄存器SR(n-1)的级联信号输出端GP耦接。
具体地，上述驱动控制电路中的每个移位寄存器的具体结构与本公开上述移位寄存器在功能和结构上均相同，重复之处不再赘述。该驱动控制电路可以应被配置为液晶显示面板中，也可以应被配置为电致发光显示面板中，在此不作限定。
具体地，在本公开实施例提供的上述驱动控制电路中，各级移位寄存器的第一参考信号端VREF1均与同一第一直流信号端耦接，各级移位寄存器的第二参考信号端VREF2均与同一第二直流信号端耦接。
具体地，在本公开实施例提供的上述驱动控制电路中，第奇数级移位寄存器的第一控制时钟信号端CK和第偶数级移位寄存器的第二控制时钟信号端CKB均与同一时钟端即第一控制时钟端耦接。第奇数级移位寄存器的第二控制时钟信号端CKB和第偶数级移位寄存器的第一控制时钟信号端CK均与同一时钟端即第二控制时钟端耦接。
具体地，在本公开实施例提供的上述驱动控制电路中，第奇数级移位寄存器的第一降噪时钟信号端CKO和第偶数级移位寄存器的第二降噪时钟信号端CKBO均与同一时钟端即第一降噪时钟端耦接。第奇数级移位寄存器的第二降噪时钟信号端CKBO和第偶数级移位寄存器的第一降噪时钟信号端CKO均与同一时钟端即第二降噪时钟端耦接。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开 实施例提供的上述栅极驱动控制电路。该显示装置解决问题的原理与前述移位寄存器相似，因此该显示装置的实施可以参见前述移位寄存器的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的上述显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
在具体实施时，显示装置可以包括多个像素单元，多条栅线和数据线，每个像素单元可以包括多个子像素，例如红色子像素、绿色子像素以及蓝色子像素。本公开实施例提供的上述显示装置可以为有机发光显示装置，或者也可以为液晶显示装置，在此不作限定。
在液晶显示装置中，如图9所示，一行子像素spx耦接一条栅线GA，一列子像素spx耦接一条数据线DA。子像素spx可以包括扫描晶体管N00和像素电极200。其中，扫描晶体管N00的栅极可以与栅线GA耦接，扫描晶体管N00的源极与数据线DA耦接，扫描晶体管N00的漏极与像素电极200耦接。并且，一个移位寄存器的驱动信号端OP耦接一条栅线GA，这样可以使移位寄存器的驱动信号端OP向子像素中的扫描晶体管N00的栅极提供信号，并且使移位寄存器的级联信号端GP用于为下一级移位寄存器传递启动信号。这样在本公开实施例提供的上述显示装置为液晶显示装置时，使上述驱动控制电路可以作为栅极驱动控制电路，应用于提供扫描晶体管N00的栅极扫描信号。需要说明的是，扫描晶体管N00可以为N型晶体管或P型晶体管，在此不作限定。
进一步地，子像素中也可以设置两个不同类型的晶体管。如图10所示，显示装置可以包括多条第一栅线GA1和多条第二栅线GA2。一行子像素耦接一条第一栅线GA1和一条第二栅线GA2。子像素spx可以包括第一扫描晶体管N01、第二扫描晶体管P01以及和像素电极200。其中，第一扫描晶体管N01为N型晶体管，第二扫描晶体管P01为P型晶体管。第一扫描晶体管N01 的栅极与第一栅线GA1耦接，第二扫描晶体管P01与第二栅线GA2耦接。第二扫描晶体管P01的源极与数据线DA耦接，第二扫描晶体管P01的漏极与第一扫描晶体管N01的源极耦接，第一扫描晶体管N01的漏极与像素电极200耦接。并且，一个移位寄存器的驱动信号端OP耦接一条第一栅线GA1，一个移位寄存器的级联信号端GP耦接一条第二栅线GA2。这样可以使移位寄存器的驱动信号端OP向子像素中的N型晶体管的栅极提供信号。并且使移位寄存器的级联信号端GP向子像素中的P型晶体管的栅极提供信号，以及级联信号端GP还用于为下一级移位寄存器传递启动信号。这样在本公开实施例提供的上述显示装置为液晶显示装置时，使上述驱动控制电路可以作为栅极驱动控制电路，应用于提供栅极扫描信号。
在有机发光显示装置中，一般设置有多个有机发光二极管以及与各有机发光二极管连接的像素电路。一般像素电路中设置有用于控制有机发光二极管发光的发光控制晶体管和用于控制数据信号输入的扫描控制晶体管。在具体实施时，在本公开实施例提供的上述显示装置为有机发光显示装置时，该有机发光显示装置可以包括一个本公开实施例提供的上述驱动控制电路，该驱动控制电路可以作为发光驱动控制电路，应用于提供发光控制晶体管的发光控制信号；或者，该驱动控制电路也可以作为栅极驱动控制电路，应用于提供扫描控制晶体管的栅极扫描信号。当然，该有机发光显示装置也可以包括两个本公开实施例提供的上述驱动控制电路，其中一个驱动控制电路可以作为发光驱动控制电路，应用于提供发光控制晶体管的发光控制信号；则另一个驱动控制电路作为栅极驱动控制电路，应用于提供扫描控制晶体管的栅极扫描信号，在此不作限定。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变 型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (16)

  1. 一种移位寄存器的驱动方法，其中，包括：在第一刷新频率时，一个显示帧包括数据刷新阶段和数据保持阶段；所述数据保持阶段包括交替设置的去噪保持阶段和去噪加强阶段；
    在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载固定电压信号，对第二参考信号端加载固定电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号；
    在所述去噪保持阶段，对所述输入信号端加载固定电压信号，对所述控制时钟信号端加载固定电压信号，对所述降噪时钟信号端加载固定电压信号，对第一参考信号端加载固定电压信号，对第二参考信号端加载固定电压信号，控制所述级联信号端输出固定电压信号以及控制所述驱动信号端输出固定电压信号；
    在所述去噪加强阶段，对所述输入信号端加载固定电压信号，对所述控制时钟信号端加载固定电压信号，对所述降噪时钟信号端加载时钟脉冲信号，对第一参考信号端加载固定电压信号，对第二参考信号端加载固定电压信号，控制所述级联信号端输出固定电压信号以及控制所述驱动信号端输出固定电压信号。
  2. 如权利要求1所述的驱动方法，其中，所述降噪时钟信号端包括第一降噪时钟信号端和第二降噪时钟信号端；所述降噪时钟脉冲信号包括第一降噪时钟脉冲信号和第二降噪时钟脉冲信号；其中，所述第一降噪时钟脉冲信号和第二降噪时钟脉冲信号的周期相同且相位差为1/2周期；
    在所述数据刷新阶段，对降噪时钟信号端加载降噪时钟脉冲信号，具体包括：对所述第一降噪时钟信号端加载所述第一降噪时钟脉冲信号，以及对所述第二降噪时钟信号端加载所述第二降噪时钟脉冲信号；
    在所述去噪保持阶段，对所述降噪时钟信号端加载固定电压信号，具体包括：对所述第一降噪时钟信号端加载具有第一电平的固定电压信号，对所述第二降噪时钟信号端加载具有所述第一电平的固定电压信号；
    在所述去噪加强阶段，对所述降噪时钟信号端加载时钟脉冲信号，具体包括：对所述第一降噪时钟信号端加载所述第一降噪时钟脉冲信号，以及对所述第二降噪时钟信号端加载所述第二降噪时钟脉冲信号；其中，所述去噪加强阶段中所述第一降噪时钟脉冲信号的第一电平与在所述去噪加强阶段之前出现的去噪保持阶段相邻，所述去噪加强阶段中所述第二降噪时钟脉冲信号的第二电平与在所述去噪加强阶段之前出现的去噪保持阶段相邻。
  3. 如权利要求2所述的驱动方法，其中，在所述去噪加强阶段中，所述第一降噪时钟脉冲信号和所述第二降噪时钟脉冲信号的时钟周期数目相同，且所述时钟周期数目至少为一个。
  4. 如权利要求3所述的驱动方法，其中，同一所述去噪加强阶段中，所述第一降噪时钟脉冲信号的下降沿、所述第二降噪时钟脉冲信号的下降沿分别与在所述去噪加强阶段之后出现的去噪保持阶段的开始时刻对齐，且所述第二降噪时钟脉冲信号的上升沿与在所述去噪加强阶段之前出现的去噪保持阶段的结束时刻对齐；
    所述数据刷新阶段和所述去噪加强阶段中，所述第二降噪时钟脉冲信号的第二电平的维持时长相同。
  5. 如权利要求3所述的驱动方法，其中，在所述去噪加强阶段中，所述第一降噪时钟脉冲信号的时钟周期数目为偶数个；
    同一所述去噪加强阶段中，所述第一降噪时钟脉冲信号的下降沿与在所述去噪加强阶段之后出现的去噪保持阶段的开始时刻对齐，以及所述第一降噪时钟脉冲信号中靠近在所述去噪加强阶段之前出现的去噪保持阶段的上升沿与在所述去噪加强阶段之前出现的去噪保持阶段之间的信号为第一电平；
    同一所述去噪加强阶段中，所述第二降噪时钟脉冲信号的上升沿与在所述去噪加强阶段之前出现的去噪保持阶段的结束时刻对齐，以及所述第二降 噪时钟脉冲信号中靠近在所述去噪加强阶段之后出现的去噪保持阶段的下降沿与在所述去噪加强阶段之后出现的去噪保持阶段之间的信号为第一电平。
  6. 如权利要求1-5任一项所述的驱动方法，其中，所述控制时钟信号端包括第一控制时钟信号端和第二控制时钟信号端；所述控制时钟脉冲信号包括第一控制时钟脉冲信号和第二控制时钟脉冲信号；其中，所述第一控制时钟脉冲信号和第二控制时钟脉冲信号的周期相同且相位差为1/2周期；
    所述输入信号和所述级联信号的脉冲电平为第一电平；
    所述驱动信号的脉冲电平为第二电平；
    所述第一参考信号端的固定电压信号为所述第一电平；
    所述第二参考信号端的固定电压信号为所述第二电平；
    所述对控制时钟信号端加载控制时钟脉冲信号，具体包括：对所述第一控制时钟信号端加载所述第一控制时钟脉冲信号，以及对所述第二控制时钟信号端加载所述第二控制时钟脉冲信号；
    所述对所述控制时钟信号端加载固定电压信号，具体包括：对所述第一控制时钟信号端加载具有所述第二电平的固定电压信号，对所述第二控制时钟信号端加载具有所述第二电平的固定电压信号；
    所述对所述输入信号端加载固定电压信号，具体包括：对所述输入信号端加载具有所述第二电平的固定电压信号；
    所述控制所述级联信号端输出固定电压信号以及控制所述驱动信号端输出固定电压信号，具体包括：控制所述级联信号端输出具有所述第二电平的固定电压信号以及控制所述驱动信号端输出具有所述第一电平的固定电压信号。
  7. 如权利要求1-6任一项所述的驱动方法，其中，所述驱动方法还包括：在第二刷新频率时，一个显示帧包括数据刷新阶段；
    在所述数据刷新阶段，对输入信号端加载具有脉冲电平的输入信号，对控制时钟信号端加载控制时钟脉冲信号，对降噪时钟信号端加载降噪时钟脉冲信号，对第一参考信号端加载固定电压信号，对第二参考信号端加载固定 电压信号，控制所述移位寄存器的级联信号端输出具有脉冲电平的级联信号以及控制所述移位寄存器的驱动信号端输出具有脉冲电平的驱动信号。
  8. 一种移位寄存器，其中，包括：
    输入控制电路，分别与输入信号端、第一控制时钟信号端、第二控制时钟信号端、第一参考信号端、第二参考信号端、下拉节点以及第一上拉节点耦接；所述输入电路被配置为响应于所述第一控制时钟信号端的信号，将所述输入信号端的信号提供给所述第一上拉节点，并响应于所述下拉节点的信号和所述第二控制时钟信号端的信号，将所述第二参考信号端的信号提供给所述第一上拉节点的信号，以及根据所述第一上拉节点的信号、第一控制时钟信号端的信号以及所述第一参考信号端的信号，控制所述下拉节点的信号；
    所述第一晶体管，所述第一晶体管的栅极被配置为与第一参考信号端耦接，所述第一晶体管的第一极被配置为与所述第一上拉节点耦接，所述第一晶体管的第二极被配置为与第二上拉节点耦接；
    级联输出电路，分别与所述下拉节点、所述第二上拉节点、所述第二参考信号端、所述第二控制时钟信号端以及级联信号端耦接；所述级联输出电路被配置为在所述第二上拉节点的信号的控制下，将所述第二控制时钟信号端的信号提供给所述级联信号端，并在所述下拉节点的信号的控制下，将所述第二参考信号端的信号提供给所述级联信号端；
    驱动输出电路，分别与所述级联信号端、第一降噪时钟信号端、第二降噪时钟信号端、所述第一参考信号端、所述第二参考信号端以及驱动信号端耦接；所述驱动输出电路被配置为响应于所述级联信号端的信号，将所述第二参考信号端的信号提供给所述驱动信号端，并响应于所述第一降噪时钟信号端和所述第二降噪时钟信号端的信号，将所述第一参考信号端的信号提供给所述驱动信号端。
  9. 如权利要求8所述的移位寄存器，其中，所述驱动输出电路包括：第二晶体管、第三晶体管、第四晶体管、第五晶体管、第一电容以及第二电容；
    所述第二晶体管的栅极与所述级联信号端耦接，所述第二晶体管的第一 极与所述第二参考信号端耦接，所述第二晶体管的第二极与所述第五晶体管的栅极耦接；
    所述第三晶体管的栅极与所述第一降噪时钟信号端耦接，所述第三晶体管的第一极与所述第一参考信号端耦接，所述第三晶体管的第二极与所述第五晶体管的栅极耦接；
    所述第四晶体管的栅极与所述级联信号端耦接，所述第四晶体管的第一极与所述第二参考信号端耦接，所述第四晶体管的第二极与所述驱动信号端耦接；
    所述第五晶体管的第一极与所述第一参考信号端耦接，所述第五晶体管的第二极与所述驱动信号端耦接；
    所述第一电容的第一电极与所述第二降噪时钟信号端耦接，所述第一电容的第二电极与所述第五晶体管的栅极耦接；
    所述第二电容的第一电极与所述第五晶体管的栅极耦接，所述第一电容的第二电极与所述驱动信号端耦接。
  10. 如权利要求9所述的移位寄存器，其中，所述级联输出电路包括：第六晶体管、第七晶体管、第三电容以及第四电容；
    所述第六晶体管的栅极与所述第二上拉节点耦接，所述第六晶体管的第一极与所述第二控制时钟信号端耦接，所述第六晶体管的第二极与所述级联信号端耦接；
    所述第七晶体管的栅极与所述下拉节点耦接，所述第七晶体管的第一极与所述第二参考信号端耦接，所述第七晶体管的第二极与所述级联信号端耦接；
    所述第三电容的第一电极与所述第二上拉节点耦接，所述第三电容的第二电极与所述级联信号端耦接；
    所述第四电容的第一电极与所述下拉节点耦接，所述第四电容的第二电极与所述第二参考信号端耦接。
  11. 如权利要求8-10任一项所述的移位寄存器，其中，所述输入控制电 路包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管；
    所述第八晶体管的栅极与所述第一控制时钟信号端耦接，所述第八晶体管的第一极与所述输入信号端耦接，所述第八晶体管的第二极与所述第一上拉节点耦接；
    所述第九晶体管的栅极与所述第一控制时钟信号端耦接，所述第九晶体管的第一极与所述第一参考信号端耦接，所述第九晶体管的第二极与所述下拉节点耦接；
    所述第十晶体管的栅极与所述第一上拉节点耦接，所述第十晶体管的第一极与所述第一控制时钟信号端耦接，所述第十晶体管的第二极与所述下拉节点耦接；
    所述第十一晶体管的栅极与所述下拉节点耦接，所述第十一晶体管的第一极与所述第二参考信号端耦接，所述第十一晶体管的第二极与所述第十二晶体管的第一极耦接；
    所述第十二晶体管的栅极与所述第二控制时钟信号端耦接，所述第十二晶体管的第二极与所述第一上拉节点耦接。
  12. 如权利要求8-11任一项所述的移位寄存器，其中，第四晶体管、第五晶体管、第六晶体管以及第七晶体管中的至少一个晶体管的有源层的沟道区的宽长比大于所述第一晶体管、第二晶体管、第三晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管以及第十二晶体管中的至少一个晶体管的有源层的沟道区的宽长比。
  13. 如权利要求12所述的移位寄存器，其中，所述第四晶体管、所述第五晶体管、所述第六晶体管以及所述第七晶体管中的至少一个晶体管的有源层的沟道区的宽长比的范围为10μm/2μm～100μm/10μm；
    所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管以及所述第十二晶体管中的至少一个晶体管的有源层的沟道区的宽长比的范围为2μm/2μm～ 20μm/10μm。
  14. 如权利要求9-13任一项所述的移位寄存器，其中，所述第一电容、所述第二电容、第三电容以及第四电容中的至少一个电容的电容值的范围为10fF～1pF。
  15. 一种驱动控制电路，其中，包括多个级联的如权利要求8-14任一项所述的移位寄存器；
    第一级移位寄存器的输入信号端与帧触发信号端耦接；
    每相邻两级移位寄存器中，下一级移位寄存器的输入信号端与上一级移位寄存器的级联信号端耦接。
  16. 一种显示装置，其中，包括如权利要求15所述的驱动控制电路。
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