WO2023155137A1 - 显示面板的驱动方法及显示装置 - Google Patents

显示面板的驱动方法及显示装置 Download PDF

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Publication number
WO2023155137A1
WO2023155137A1 PCT/CN2022/076854 CN2022076854W WO2023155137A1 WO 2023155137 A1 WO2023155137 A1 WO 2023155137A1 CN 2022076854 W CN2022076854 W CN 2022076854W WO 2023155137 A1 WO2023155137 A1 WO 2023155137A1
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WIPO (PCT)
Prior art keywords
display panel
display
working state
gate
signal
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PCT/CN2022/076854
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English (en)
French (fr)
Inventor
王强
张郑欣
郭蕾
张佳立
王晔
崔军蕊
汤威
张鹏举
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/076854 priority Critical patent/WO2023155137A1/zh
Priority to CN202280000216.0A priority patent/CN116917975A/zh
Publication of WO2023155137A1 publication Critical patent/WO2023155137A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving method of a display panel and a display device.
  • Displays such as liquid crystal displays (Liquid Crystal Display, LCD) and organic light-emitting diodes (Organic Light-Emitting Diode, OLED) generally include a plurality of pixel units. Each pixel unit may include: a red sub-pixel, a green sub-pixel and a blue sub-pixel. By controlling the brightness corresponding to each sub-pixel, the required display color is mixed to display a color image.
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Diode
  • one display frame includes a data refresh phase and a blank time phase
  • the driving method of the display panel includes:
  • a clock signal including an active level and an inactive level is applied to the gate drive circuit in the display panel, the gate line is loaded with a gate open signal, and the source in the display panel is The driving circuit loads the display data, loads the data line with a data voltage, and determines the current working state of the display panel;
  • a clock signal including an inactive level is applied to the gate driving circuit in the display panel, the gate line is loaded with a gate-off signal, and the current working state of the display panel is sent.
  • the determining the current working state of the display panel includes:
  • the protection signal is smaller than the signal threshold, it is determined that the current working state of the display panel is a normal working state.
  • the driving method also includes:
  • the sending of the current working state of the display panel includes:
  • the stored normal working instruction is sent.
  • the driving method also includes:
  • a static electricity detection instruction is received, and a current working state of the display panel is determined based on the static electricity detection instruction.
  • the driving method also includes:
  • a state request instruction is received, and the current working state of the display panel is sent based on the state request instruction.
  • the effective level of the clock signal corresponding to the gate-on signal applied to the last gate line in the display panel ends, it enters a blank time period.
  • the status request command is received after a set time has elapsed after entering the blank time period.
  • each display frame of a plurality of consecutive display frames in the data refresh period, determine the current working state of the display panel, and in the blank time period, determine to send the Describe the current working status of the display panel.
  • in the display frames with intervals of at least one display frame in a plurality of consecutive display frames in the data refresh phase, determine the current working state of the display panel, and in the blank time period , to determine to send the current working state of the display panel.
  • a display panel including a gate drive circuit and a source drive circuit
  • the display driving circuit is configured to load a clock signal including an active level and an inactive level to the gate driving circuit in the display panel during the data refresh phase, load the gate lines with a gate-on signal, and
  • the source drive circuit in the display panel is loaded with display data, the data line is loaded with data voltage, and the current working state of the display panel is determined; during the blank time period, the gate drive circuit in the display panel is Loading a clock signal including an inactive level causes the gate line to load a gate-off signal, and transmits the current working state of the display panel; wherein, a display frame includes a data refresh phase and a blank time phase.
  • the main control unit is configured to send a status request instruction during the blank time period
  • the display driving circuit is further configured to receive a status request command during the blank time period, and send the current working status of the display panel to the main control unit based on the status request command.
  • the display driving circuit has a status register; the status register is configured to store an abnormal operation instruction and a normal operation instruction.
  • the main control unit is further configured to send a static electricity detection instruction during the data refresh phase
  • the display driving circuit is further configured to receive a static electricity detection instruction during the data refresh phase, and determine a current working state of the display panel based on the static electricity detection instruction.
  • the display device further includes: a signal transmission board; the signal transmission board has a plurality of signal transmission lines;
  • the display driving circuit is coupled to the display panel through the signal transmission board; and the signal transmission board is configured to transmit the clock signal sent by the display driving circuit to the display panel.
  • the signal transmission board includes a flexible circuit board.
  • FIG. 1 is some structural schematic diagrams of a display device provided by an embodiment of the present disclosure
  • FIG. 2 is some structural schematic diagrams of a display panel provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present disclosure.
  • FIG. 4a is another structural schematic diagram of the gate driving circuit provided by the embodiment of the present disclosure.
  • FIG. 4b is another structural schematic diagram of the gate driving circuit provided by the embodiment of the present disclosure.
  • FIG. 5 is a timing diagram of some signals provided by an embodiment of the present disclosure.
  • FIG. 6 is another timing diagram of signals provided by an embodiment of the present disclosure.
  • FIG. 7 is another timing diagram of signals provided by an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a method for driving a display panel provided by an embodiment of the present disclosure.
  • FIG. 9 is another timing diagram of signals provided by an embodiment of the present disclosure.
  • FIG. 10 is another structural schematic diagram of a display device provided by an embodiment of the present disclosure.
  • the display device may include a display panel 100 , a display driving circuit 200 and a main control unit 300 .
  • the display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (for example, GA1, GA2, GA3, GA4), a plurality of data lines DA (for example, DA1, DA2, DA3), gate
  • the driving circuit 110 and the source driving circuit 120 are coupled to the gate lines GA1 , GA2 , GA3 , GA4 respectively, and the source driving circuit 120 is coupled to the data lines DA1 , DA2 , DA3 respectively.
  • the main control unit 300 can receive the display data (the display data includes the digital voltage form of the data voltage carrying the corresponding grayscale value corresponding to each sub-pixel), and send the display data to the display driving circuit 200, displaying After receiving the display data, the drive circuit 200 performs corresponding processing on the display data, and the display drive circuit 200 can input a clock signal and a frame start signal to the gate drive circuit 110, so that the gate drive circuit 110 outputs a gate drive signal , to drive the gate lines GA1, GA2, GA3, GA4.
  • the display driving circuit 200 inputs the processed display data into the source driving circuit 120, so that the source driving circuit 120 can input a data voltage to the data line according to the received display data, thereby charging the sub-pixel SPX, and making the sub-pixel SPX Input the corresponding data voltage to realize the screen display function.
  • the number of source driving circuits 120 can be set to two, wherein one source driving circuit 120 is connected to half the number of data lines, and the other source driving circuit 120 is connected to the other half of the number of data lines.
  • 3, 4, or more source drive circuits 120 can also be provided, which can be designed and determined according to the requirements of practical applications, and are not limited here. In FIG. 2, only two gates are provided.
  • a gate drive circuit can also be provided on only one side of the gate line, or two gate drive circuits can be provided, wherein one gate drive circuit drives the gate lines connected to the sub-pixels in odd rows, and the other The gate drive circuit drives the gate lines connected to the sub-pixels in the even rows.
  • each pixel unit includes a plurality of sub-pixels SPX.
  • a pixel unit may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue colors can be mixed to achieve color display.
  • the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that color mixing can be performed through red, green, blue and white to achieve color display.
  • the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the practical application environment, which is not limited here.
  • each sub-pixel SPX includes a transistor 01 and a pixel electrode 02 .
  • one row of sub-pixels SPX corresponds to one gate line
  • one column of sub-pixels SPX corresponds to one data line.
  • the gate of the transistor 01 is electrically connected to the corresponding gate line
  • the source of the transistor 01 is electrically connected to the corresponding data line
  • the drain of the transistor 01 is electrically connected to the pixel electrode 02.
  • the pixel array structure of the present disclosure can also be It is a double-gate structure, that is, two gate lines are set between two adjacent rows of pixels. This arrangement can reduce half of the data lines, that is, there are data lines between two adjacent columns of pixels, and some adjacent two rows of pixels.
  • the data lines are not included between the pixels in the columns, and the specific arrangement structure of the pixels and the data lines, and the arrangement of the scanning lines are not limited.
  • the display panel in the embodiments of the present disclosure may be a liquid crystal display panel.
  • a liquid crystal display panel generally includes an upper substrate and a lower substrate that are opposed to each other, and liquid crystal molecules encapsulated between the upper substrate and the lower substrate.
  • the voltage difference can form an electric field, so that the liquid crystal molecules are under the action of the electric field to deflect.
  • the liquid crystal molecules have different degrees of deflection due to electric fields of different intensities, resulting in different transmittances of the sub-pixels SPX, so that the sub-pixels SPX can achieve brightness of different gray scales, thereby realizing image display.
  • the display panel in the embodiment of the present disclosure may be an OLED display panel, which is not limited here.
  • the gate drive circuit may include a plurality of shift registers.
  • shift registers from stage 1 to stage N SR(1), SR(2)...SR(n-1), SR(n)...SR(N-1), SR( N) (a total of N shift registers, 1 ⁇ n ⁇ N, n is an integer, SR(1)-SR(24) are taken as an example in Figure 2).
  • a plurality of shift registers in a gate driving circuit may be divided into a plurality of register groups. Wherein, the shift registers in the same register group can be set in cascade, and the frame start signal terminals connected to different register groups are different.
  • the shift register in the gate driving circuit can be divided into two register groups.
  • the first register group X1 in the two register groups includes the odd-numbered shift registers: the first-stage shift register SR (1), the third-stage shift register SR (3) , 5th stage shift register SR(5), ... 19th stage shift register SR(19), 21st stage shift register SR(21) and 23rd stage shift register SR(23).
  • the odd-numbered shift registers are electrically connected to the odd-numbered gate lines.
  • the input signal terminal IP of the first stage shift register SR (1), the input signal terminal IP of the third stage shift register SR (3), and the input signal terminal IP of the fifth stage shift register SR (5) Both are electrically connected to the frame start signal terminal STV_A.
  • the output signal terminal GO of the first-stage shift register SR(1) is electrically connected to the input signal terminal IP of the seventh-stage shift register SR(7).
  • the output signal terminal GO of the third-stage shift register SR(3) is electrically connected to the input signal terminal IP of the ninth-stage shift register SR(9).
  • the output signal terminal GO of the 15th stage shift register SR (15) is electrically connected to the input signal terminal IP of the 21st stage shift register SR (21).
  • the output signal terminal GO of the 17th stage shift register SR ( 17 ) is electrically connected to the input signal terminal IP of the 23rd stage shift register SR ( 23 ).
  • the output signal terminal GO of the ninth-stage shift register SR(9) is electrically connected to the reset signal terminal RE of the first-stage shift register SR(1).
  • the output signal terminal GO of the eleventh-stage shift register SR(11) is electrically connected to the reset signal terminal RE of the third-stage shift register SR(3).
  • the output signal terminal GO of the 21st stage shift register SR (21) is electrically connected to the reset signal terminal RE of the 13th stage shift register SR (13).
  • the output signal terminal GO of the 23rd stage shift register SR ( 23 ) is electrically connected to the reset signal terminal RE of the 15th stage shift register SR ( 15 ).
  • the second register group X2 in the two register groups includes the even-numbered shift register: the second-stage shift register SR (2), the fourth-stage shift register SR (4) , 6th stage shift register SR(6), ... 20th stage shift register SR(20), 22nd stage shift register SR(22) and 24th stage shift register SR(24).
  • the even-numbered shift register is electrically connected to the even-numbered gate line.
  • the input signal end IP of the second stage shift register SR (2), the input signal end IP of the fourth stage shift register SR (4), and the input signal end IP of the sixth stage shift register SR (6) Both are electrically connected to the frame start signal terminal STV_B.
  • the output signal terminal GO of the second-stage shift register SR(2) is electrically connected to the input signal terminal IP of the eighth-stage shift register SR(8).
  • the output signal terminal GO of the fourth-stage shift register SR(4) is electrically connected to the input signal terminal IP of the tenth-stage shift register SR(10).
  • the output signal terminal GO of the 16th stage shift register SR (16) is electrically connected to the input signal terminal IP of the 22nd stage shift register SR (22).
  • the output signal terminal GO of the 18th stage shift register SR (18) is electrically connected to the input signal terminal IP of the 24th stage shift register SR (24).
  • the output signal terminal GO of the tenth-stage shift register SR(10) is electrically connected to the reset signal terminal RE of the second-stage shift register SR(2).
  • the output signal terminal GO of the twelfth-stage shift register SR(12) is electrically connected to the reset signal terminal RE of the fourth-stage shift register SR(4).
  • the output signal terminal GO of the 22nd stage shift register SR (22) is electrically connected to the reset signal terminal RE of the 14th stage shift register SR (14).
  • the output signal terminal GO of the 24th stage shift register SR ( 24 ) is electrically connected to the reset signal terminal RE of the 16th stage shift register SR ( 16 ).
  • stv_a represents the frame start signal of the frame start signal terminal STV_A
  • stv_b represents the frame start signal of the frame start signal terminal STV_B
  • ck1 represents the clock signal transmitted on the clock signal line CK1
  • ck2 represents the clock signal transmitted on the clock signal line CK2
  • ck3 represents the clock signal transmitted on the clock signal line CK3
  • ck4 represents the clock signal transmitted on the clock signal line CK4
  • ck5 represents the clock signal transmitted on the clock signal line CK5
  • ck6 represents the clock transmitted on the clock signal line CK6
  • ck7 represents the clock signal transmitted on the clock signal line CK7
  • ck8 represents the clock signal transmitted on the clock signal line CK8
  • ck9 represents the clock signal transmitted on the clock signal line CK9
  • ck10 represents the clock signal transmitted on the clock signal line CK10
  • ck11 represents the clock signal transmitted on the clock signal line CK11
  • ck9 represents the clock signal transmitted on the clock
  • the signal ga1 represents the gate drive signal output from the output signal terminal GO of the first-stage shift register SR(1).
  • the signal ga2 represents the gate driving signal output from the output signal terminal GO of the second-stage shift register SR(2).
  • the signal ga3 represents the gate drive signal output from the output signal terminal GO of the third-stage shift register SR(3).
  • the signal ga24 represents the gate drive signal output from the output signal terminal GO of the 24th stage shift register SR (24).
  • the signal gaN represents the gate drive signal output from the output signal terminal GO of the Nth-stage shift register SR(N).
  • the shift register SR(2) of the second stage outputs the first high level of the clock signal ck2 through the output signal terminal GO to generate the high level of the signal ga2.
  • the shift register SR(3) of the third stage outputs the first high level of the clock signal ck1 through the output signal terminal GO to generate the high level of the signal ga3.
  • ...the twelfth-stage shift register SR (12) outputs the first high level of the clock signal ck12 through the output signal terminal GO to generate a high level in the signal ga12.
  • the shift register SR (13) of the thirteenth stage outputs the second high level of the clock signal ck1 through the output signal terminal GO to generate the high level of the signal ga13.
  • the shift register SR (14) of the 14th stage outputs the second high level of the clock signal ck2 through the output signal terminal GO to generate the high level of the signal ga14.
  • the 24th stage shift register SR(1) outputs the second high level of the clock signal ck12 through the output signal terminal GO to generate the high level of the signal ga12.
  • ...the Nth-stage shift register SR(N) outputs the last high level of the clock signal ck12 through the output signal terminal GO to generate a high level in the signal gaN. That is to say, the high level of the clock signal can be its active level, and the low level can be its inactive level.
  • the shift register when the shift register outputs the low level of the clock signal through the output signal terminal GO to generate a low level signal for controlling the conduction of the transistor in the signal, the low level of the clock signal can be used as its effective level, and the high level of the clock signal can be used as the effective level. level as its inactive level.
  • the shift register in the gate driving circuit is divided into two register groups as an example for illustration.
  • the shift register in the gate driving circuit can also be divided into three register groups, four register groups or more register groups, which are not limited here.
  • Grayscale generally divides the brightness change between the darkest and the brightest into several parts for easy screen brightness control.
  • the displayed image consists of three colors of red, green, and blue, each of which can show different brightness levels, and the combination of red, green, and blue at different brightness levels can form different colors.
  • the number of gray scale bits of the liquid crystal display panel is 6 bits
  • the three colors of red, green, and blue have 64 (ie, 2 6 ) gray scales respectively, and the 64 gray scale values are 0-63 respectively.
  • the number of gray scale digits of the liquid crystal display panel is 8 bits, and the three colors of red, green, and blue have 256 (ie, 2 8 ) gray scales respectively, and the 256 gray scale values are 0-255 respectively.
  • the number of gray scale digits of the liquid crystal display panel is 10 bits, so the three colors of red, green, and blue have 1024 (ie, 2 10 ) gray scales respectively, and the 1024 gray scale values are 0-1023 respectively.
  • the number of grayscale digits of the liquid crystal display panel is 12 bits, and the three colors of red, green, and blue have 4096 (ie, 2 12 ) grayscales respectively, and the 4096 grayscale values are 0-4093 respectively.
  • Vcom represents the common electrode voltage.
  • the liquid crystal molecules at the sub-pixel SPX can be positively polarized, and then the polarity corresponding to the data voltage in the sub-pixel SPX is positive polarity.
  • the common electrode voltage can be 8.3V.
  • a data voltage of 8.3V-16V is input into the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at the sub-pixel SPX can be made positive, and the voltage of 8.3V-16V
  • the data voltage is a data voltage corresponding to positive polarity. If a data voltage of 0.6V-8.3V is input into the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at the sub-pixel SPX can be negatively polarized, and the data voltage of 0.6V-8.3V is the data corresponding to the negative polarity. Voltage.
  • the sub-pixel SPX may correspond to the brightness of the maximum gray scale value of positive polarity. If a data voltage of 0.6V is input to the pixel electrode of the sub-pixel SPX, the sub-pixel SPX can correspond to the brightness of the maximum gray scale value of the negative polarity.
  • a display frame F0 of the display panel may include a data refresh phase TS and a blanking time (Blanking Time) phase TB.
  • the data refresh phase TS the sub-pixels in the display panel can be controlled to input data voltage, so that the display panel displays the picture of the display frame F0.
  • the signal ga1 is applied to the gate line GA1
  • the signal ga2 is applied to the gate line GA2
  • the signal ga3 is applied to the gate line GA3
  • the signal ga4 is applied to the gate line GA4, and gate
  • a signal is turned on (such as a high-level signal among the signals ga1 - ga4 )
  • the corresponding transistor 01 can be controlled to be turned on.
  • the source driving circuit 120 loads the data line DA1 with the corresponding data voltage da1 according to the display data, and the data line DA1 DA2 loads the corresponding data voltage da2, and the data line DA3 loads the corresponding data voltage da3, so that the pixel electrode 02 in the first row of sub-pixels inputs the corresponding data voltage, so that each sub-pixel in the first row inputs data Voltage.
  • the signal ga2 When the signal ga2 has a gate open signal, it can control the transistors 01 in the second row of sub-pixels to be turned on, and the source driving circuit 120 loads the corresponding data voltage da1 to the data line DA1 and loads the data voltage da1 to the data line DA2 according to the display data.
  • the corresponding data voltage da3 is applied to the data line DA3, so that the pixel electrode 02 in the second row of sub-pixels inputs the corresponding data voltage, so that each sub-pixel in the second row receives the data voltage.
  • the signal ga3 When the signal ga3 has a gate open signal, it can control the transistors 01 in the third row of sub-pixels to be turned on, and the source driving circuit 120 loads the corresponding data voltage da1 to the data line DA1 and loads the data voltage da1 to the data line DA2 according to the display data.
  • the corresponding data voltage da3 is applied to the data line DA3, so that the pixel electrode 02 in the third row of sub-pixels inputs the corresponding data voltage, so that each sub-pixel in the third row receives the data voltage.
  • the signal ga4 When the signal ga4 has a gate open signal, it can control the transistors 01 in the fourth row of sub-pixels to be turned on, and the source driving circuit 120 loads the corresponding data voltage da1 to the data line DA1 and loads the data voltage da1 to the data line DA2 according to the display data.
  • the corresponding data voltage da3 is applied to the data line DA3, so that the pixel electrode 02 in the sub-pixels in the fourth row receives the corresponding data voltage, so that each sub-pixel in the fourth row receives the data voltage.
  • the rest of the lines are deduced in the same way, and will not be repeated here.
  • the signals ga1 ⁇ ga4 are all low level, and the transistor 01 in each sub-pixel is in an off state, controlling the pixel electrode 02 in each sub-pixel to hold data voltage, so as to control the sub-pixels in the display panel to maintain the data voltage, so that the display panel continues to display the picture of the display frame F0.
  • the display driving circuit can detect the display panel and send the detected result to the main control unit.
  • the display drive circuit sends the detected results to the main control unit, if the display drive circuit sends a clock signal with alternating high and low levels to the gate drive circuit, it will interfere with the clock signal, resulting in a high level of the clock signal. Widen, as shown in the dashed box in Figure 7. Wherein, in FIG. 7 , L1 represents the clock signal when it is not disturbed, and L2 represents the clock signal when it is disturbed.
  • the clock signal is usually switched to an inactive level when the display driving circuit sends the detected result to the main control unit.
  • such setting causes the gate drive circuits to be unable to be cascaded for output, resulting in abnormal display on the display panel.
  • the driving method provided in the embodiments of the present disclosure can determine the current working state of the display panel during the data refresh phase.
  • the clock signal is an invalid voltage
  • the current working state of the display panel is sent, which can avoid interference to the effective level of the clock signal when sending the current working state of the display panel, and can also It is not necessary to additionally switch the clock signal to an invalid level, nor to additionally change the timing of the signal, so that the gate drive circuit can be normally cascaded and output, thereby avoiding abnormal display on the display panel.
  • the method for driving a display panel may include the following steps:
  • the display driving circuit may load the gate driving circuit in the display panel with a clock signal including an active level and an inactive level in the data refresh phase, so that the gate line is loaded with a gate-on signal, and the The source driving circuit in the display panel loads display data, loads the data line with data voltage, and determines the current working state of the display panel.
  • the main control unit may send a static electricity detection instruction during the data refresh phase.
  • the display driving circuit can receive the static electricity detection instruction in the data refresh phase, and determine the current working state of the display panel based on the static electricity detection instruction.
  • the gate drive circuit in the display panel is loaded with a clock
  • the signals ck1 - ck12 can make the gate lines GA1 - GAN transmit the signals ga1 - gaN, and the high level of the signals ga1 - ga24 can be used as the gate turn-on signal.
  • the gate turn-on signal transmitted on the gate line can control the connected transistor to be turned on, and the source drive circuit can input data voltage to the data line according to the received display data, thereby charging the sub-pixel SPX and making the sub-pixel SPX input corresponding data voltage to realize the screen display function.
  • determining the current working state of the display panel may include: collecting a protection signal output by a protection circuit set in the display panel.
  • the protection signal when the protection signal is not less than the signal threshold, it can be determined that the current working state of the display panel is an abnormal working state.
  • the protection signal is smaller than the signal threshold, it is determined that the current working state of the display panel is a normal working state.
  • the abnormal working state may be, for example, a state in which the display panel is greatly affected by static electricity, or a state in which the display panel is greatly affected by signal interference, and the like.
  • the normal working state may be a state in which the display panel is less affected by static electricity or a state not affected by static electricity, or the normal working state may be a state in which the display panel is less affected by signal interference or a state not affected by signal interference.
  • the protection signal can be set as a current
  • the protection circuit can be an electrostatic discharge (Electro Static Discharge, ESD) circuit
  • the protection signal can be the current output by the ESD circuit
  • the signal threshold can be a current threshold, so that the ESD circuit output
  • the current is not less than the current threshold, it means that the current is relatively large, which can indicate that the display panel is more likely to be damaged by static electricity, and then it can be determined that the current working state of the display panel is an abnormal working state.
  • the current output by the ESD circuit is less than the current threshold, it means that the current is small, which means that the display panel is less likely to be damaged by static electricity, and then it can be determined that the current working state of the display panel is a normal working state.
  • the protection circuit may also be a protection circuit with other functions, which is not limited here.
  • an abnormal working instruction when it is determined that the current working state of the display panel is in the abnormal working state, an abnormal working instruction may be generated and stored. While determining that the current working state of the display panel is in a normal working state, a normal working instruction is generated and stored.
  • the abnormal work instruction and the normal work instruction may be digital signals.
  • the abnormal operation instruction and the normal operation instruction may be digital signals in binary, decimal, or hexadecimal.
  • the digital signal of 9C can be used to represent the normal work instruction
  • the digital signal other than 9C (such as 9D) can be used to represent the abnormal work instruction.
  • the display driving circuit may load a clock signal including an invalid level to the gate driving circuit in the display panel during the blank time period, so that the gate line is loaded with a gate-off signal, and sends the Current working status.
  • the main control unit may send the status request command during the blank time period.
  • the display driving circuit can receive the status request command in the blank time period, and based on the status request command, send the current working status of the display panel to the main control unit.
  • the display driving circuit has a status register; the status register can store abnormal working instructions and normal working instructions.
  • sending the current working state of the display panel may include: sending a stored abnormal working instruction when it is determined that the current working state of the display panel is an abnormal working state.
  • sending the stored normal working instruction is sent.
  • the display driving circuit taking a digital signal of 9C to represent a normal operation instruction, and a digital signal other than 9C (such as 9D) to represent an abnormal operation instruction as an example, the display driving circuit is in the normal operation state when determining that the current operation state of the display panel is in the normal operation state , the stored 9C can be sent to the main control unit.
  • the main control unit can receive the normal working instruction represented by 9C, so that it can be determined that the display panel is in a normal working state, that is, it is not necessary to take protective measures and/or give an abnormal alarm to the working display panel.
  • the display driving circuit determines that the current working state of the display panel is an abnormal working state, it can send the stored 9D to the main control unit.
  • the main control unit can receive the abnormal operation command represented by 9D, so that it can be determined that the received is not 9C, and then it can be determined that the display panel is in an abnormal working state.
  • the display panel can be controlled to reset (Reset) or Restart or shut down to protect the display panel and/or give an abnormal alarm.
  • the display device is a wearable product (smart watch, virtual reality device, etc.), better protection of the product and/or abnormal alarm can be performed.
  • the blank time period may be entered after the effective level of the clock signal corresponding to the gate-on signal loaded by the last gate line in the display panel ends.
  • the blank time period TB may be entered when the falling edge of the last high level (ie active level) of the clock signal ck12 appears.
  • the status request instruction may be received after entering the blank time period and after a set time has elapsed.
  • the state request instruction may be received after entering the blank time period and after the set time td has elapsed. That is to say, after entering the blank time period and passing the set time td, the main control unit may send a status request command to the display drive circuit, and the display drive circuit may send the determined display to the main control unit after receiving the status request command.
  • the current working state of the panel Since it has just entered the blank time period, the work of the main control unit and the display driver chip may not be stable.
  • the main control unit After a certain time td, the work of the main control unit and the display driver chip tends to be stable, and the main control unit sends a status request command to the display.
  • the drive circuit after receiving the status request command, the display drive circuit sends the determined current working status of the display panel to the main control unit, so that the status request command and the abnormal working command corresponding to the current working status of the display panel can be stably transmitted and normal work instructions.
  • the current working state of the display panel in each of the multiple consecutive display frames, can be determined in the data refresh phase, and the transmission status of the display panel can be determined in the blank time phase. Current working status. In this way, the working state of the display panel can be detected for each display frame, and the working stability of the display panel can be improved.
  • in the data refresh phase determine the current working state of the display panel, and in the blank time period, determine the sending Displays the current working status of the panel.
  • the working state of the display panel can be detected in part of the display frames, which can reduce power consumption.
  • in the display frames every other display frame in a plurality of consecutive display frames determine the current working state of the display panel, and in the blank time period, determine the current working state of the display panel state.
  • the data refresh phase determines the current working state of the display panel, and in the blank time In the stage, determine the current working status of the sending display panel.
  • the even-numbered display frame such as the second display frame, the fourth display frame, the sixth display frame, etc.
  • the data refresh phase determine the current working state of the display panel, and in the blank time In the stage, determine the current working status of the sending display panel.
  • the display device further includes: a signal transmission board (for example, a flexible circuit board) 400 .
  • the display driving circuit 200 is coupled to the display panel 100 through the signal transmission board 400 .
  • the signal transmission board 200 may have multiple signal transmission lines.
  • the signal transmission board can transmit the clock signal sent by the display driving circuit to the display panel.
  • the display driving circuit 200 may be an ODOC chip, and the ODOC chip may be designed without any external auxiliary boosting module to complete the display of the display panel. That is, the 0D0C chip integrates all boost modules into the chip, so the integration degree is relatively high.
  • the ODOC chip integrates all the boost modules inside the chip, the signal transmission board 400 does not need additional capacitors and resistors, thereby reducing the cost and design difficulty of the signal transmission board.
  • the 0D0C chip it is equivalent to one chip completing the display driving work of the entire display panel, so that the burden of the 0D0C chip is heavy, the signal stability is crossed, and the output signal is more likely to be disturbed.
  • the display drive circuit sends a clock signal with alternating high and low levels to the gate drive circuit, it will interfere with the clock signal, causing the high level of the clock signal to widen, as shown in the dashed box in FIG. 7 .
  • the driving method provided in the embodiments of the present disclosure can determine the current working state of the display panel during the data refresh phase.
  • the clock signal is an invalid voltage
  • the current working state of the display panel is sent, which can avoid interference to the effective level of the clock signal when sending the current working state of the display panel, and can also It is not necessary to additionally switch the clock signal to an invalid level, nor to additionally change the timing of the signal, so that the gate drive circuit can be normally cascaded and output, thereby avoiding abnormal display on the display panel.
  • the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Accordingly, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

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Abstract

本公开实施例提供的显示面板的驱动方法及显示装置，一个显示帧包括数据刷新阶段和空白时间阶段；显示面板的驱动方法，包括：在数据刷新阶段内，对显示面板中的栅极驱动电路加载包括有效电平和无效电平的时钟信号，使栅线加载栅极开启信号，并且对显示面板中的源极驱动电路加载显示数据，使数据线加载数据电压，以及确定显示面板的当前工作状态；在空白时间阶段内，对显示面板中的栅极驱动电路加载包括无效电平的时钟信号，使栅线加载栅极关闭信号，并且发送显示面板的当前工作状态。

Description

显示面板的驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及显示面板的驱动方法及显示装置。
背景技术
在诸如液晶显示器(Liquid Crystal Display，LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器中，一般包括多个像素单元。每个像素单元可以包括：红色子像素、绿色子像素以及蓝色子像素。通过控制每个子像素对应的亮度，从而混合出所需显示的色彩来显示彩色图像。
发明内容
本发明实施例提供的显示面板的驱动方法，一个显示帧包括数据刷新阶段和空白时间阶段；
所述显示面板的驱动方法，包括：
在所述数据刷新阶段内，对所述显示面板中的栅极驱动电路加载包括有效电平和无效电平的时钟信号，使栅线加载栅极开启信号，并且对所述显示面板中的源极驱动电路加载显示数据，使数据线加载数据电压，以及确定所述显示面板的当前工作状态；
在所述空白时间阶段内，对所述显示面板中的栅极驱动电路加载包括无效电平的时钟信号，使栅线加载栅极关闭信号，并且发送所述显示面板的当前工作状态。
在一些示例中，所述确定所述显示面板的当前工作状态，包括：
采集所述显示面板中设置的保护电路输出的保护信号；
在所述保护信号不小于信号阈值时，确定所述显示面板的当前工作状态为非正常工作状态；
在所述保护信号小于所述信号阈值时，确定所述显示面板的当前工作状 态为正常工作状态。
在一些示例中，所述驱动方法还包括：
在所述确定所述显示面板的当前工作状态处于非正常工作状态的同时，生成并存储非正常工作指令；
在所述确定所述显示面板的当前工作状态处于正常工作状态的同时，生成并存储正常工作指令；
所述发送所述显示面板的当前工作状态，包括：
在确定所述显示面板的当前工作状态为非正常工作状态时，发送存储的所述非正常工作指令；
在所述确定所述显示面板的当前工作状态处于正常工作状态时，发送存储的所述正常工作指令。
在一些示例中，所述驱动方法还包括：
在所述数据刷新阶段内，接收静电检测指令，并基于所述静电检测指令确定所述显示面板的当前工作状态。
在一些示例中，所述驱动方法还包括：
在所述空白时间阶段内，接收状态请求指令，并基于所述状态请求指令发送所述显示面板的当前工作状态。
在一些示例中，在所述显示面板中最后一条栅线加载的栅极开启信号对应的时钟信号的有效电平结束后进入空白时间阶段。
在一些示例中，在进入所述空白时间阶段并经过设定时间后，接收状态请求指令。
在一些示例中，在连续的多个显示帧中的每个显示帧中，在所述数据刷新阶段内，确定所述显示面板的当前工作状态，以及在所述空白时间阶段内，确定发送所述显示面板的当前工作状态。
在一些示例中，在连续的多个显示帧中每间隔至少一个显示帧的显示帧中，在所述数据刷新阶段内，确定所述显示面板的当前工作状态，以及在所述空白时间阶段内，确定发送所述显示面板的当前工作状态。
本公开实施例提供的显示装置，包括：
显示面板，包括栅极驱动电路和源极驱动电路；
显示驱动电路，被配置为在所述数据刷新阶段内，对所述显示面板中的栅极驱动电路加载包括有效电平和无效电平的时钟信号，使栅线加载栅极开启信号，并且对所述显示面板中的源极驱动电路加载显示数据，使数据线加载数据电压，以及确定所述显示面板的当前工作状态；在所述空白时间阶段内，对所述显示面板中的栅极驱动电路加载包括无效电平的时钟信号，使栅线加载栅极关闭信号，并且发送所述显示面板的当前工作状态；其中，一个显示帧包括数据刷新阶段和空白时间阶段。
在一些示例中，还包括：主控单元；
所述主控单元被配置为在所述空白时间阶段内，发送状态请求指令；
所述显示驱动电路还被配置为在所述空白时间阶段内，接收状态请求指令，并基于所述状态请求指令，发送所述显示面板的当前工作状态给所述主控单元。
在一些示例中，所述显示驱动电路具有状态寄存器；所述状态寄存器被配置为存储非正常工作指令和正常工作指令。
在一些示例中，所述主控单元还被配置为在所述数据刷新阶段内，发送静电检测指令；
所述显示驱动电路还被配置为在所述数据刷新阶段内，接收静电检测指令，并基于所述静电检测指令确定所述显示面板的当前工作状态。
在一些示例中，所述显示装置还包括：信号传输板；所述信号传输板具有多条信号传输线；
所述显示驱动电路通过所述信号传输板与所述显示面板耦接；并且，所述信号传输板配置为将所述显示驱动电路发送的时钟信号传输给所述显示面板。
在一些示例中，所述信号传输板包括柔性电路板。
在一些示例中，所述显示驱动电路为一个。
附图说明
图1为本公开实施例提供的显示装置的一些结构示意图；
图2为本公开实施例提供的显示面板的一些结构示意图；
图3为本公开实施例提供的栅极驱动电路的一些结构示意图；
图4a为本公开实施例提供的栅极驱动电路的另一些结构示意图；
图4b为本公开实施例提供的栅极驱动电路的又一些结构示意图；
图5为本公开实施例提供的一些信号时序图；
图6为本公开实施例提供的另一些信号时序图；
图7为本公开实施例提供的又一些信号时序图；
图8为本公开实施例提供的显示面板的驱动方法的流程图；
图9为本公开实施例提供的又一些信号时序图；
图10为本公开实施例提供的显示装置的又一些结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
参见图1与图2，显示装置可以包括显示面板100、显示驱动电路200以及主控单元300。其中，显示面板100可以包括多个阵列排布的像素单元，多条栅线GA(例如，GA1、GA2、GA3、GA4)、多条数据线DA(例如，DA1、DA2、DA3)、栅极驱动电路110以及源极驱动电路120。栅极驱动电路110分别与栅线GA1、GA2、GA3、GA4耦接，源极驱动电路120分别与数据线DA1、DA2、DA3耦接。其中，主控单元300可以接收显示数据(该显示数据包括每一个子像素一一对应的携带有相应灰阶值的数据电压的数字电压形式)，并将显示数据发送给显示驱动电路200，显示驱动电路200接收到显示数据后，对显示数据进行相应的处理，并且显示驱动电路200可以向栅极驱动电路110输入时钟信号和帧起始信号，从而使栅极驱动电路110输出栅极驱动信号，以驱动栅线GA1、GA2、GA3、GA4。以及显示驱动电路200将处理后的显示数据输入源极驱动电路120，以使源极驱动电路120可以根据接收到的显示数据向数据线输入数据电压，从而对子像素SPX充电，使子像素SPX输入相应的数据电压，实现画面显示功能。示例性地，源极驱动电路120可以设置为2个，其中一个源极驱动电路120连接一半数量的数据线，另一个源极驱动电路120连接另一半数量的数据线。当然，源极驱动电路120也可以设置3个、4个、或更多个，其可以根据实际应用的需求进行设计确定，在此不作限定，图2中仅仅施例了设置有两个栅极驱动电路且双边驱动的方式，当然也可以仅仅在栅线的一侧设置栅极驱动电路或者设置两个栅极驱动电路，其中一个栅极驱动电路驱动奇数行子像素连接的栅线，另一个栅极驱动电路驱动偶数行子像素连接的栅线。
示例性地，每个像素单元包括多个子像素SPX。例如，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝 色子像素以及白色子像素，这样可以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
参见图2所示，每个子像素SPX中包括晶体管01和像素电极02。其中，一行子像素SPX对应一条栅线，一列子像素SPX对应一条数据线。晶体管01的栅极与对应的栅线电连接，晶体管01的源极与对应的数据线电连接，晶体管01的漏极与像素电极02电连接，需要说明的是，本公开像素阵列结构还可以是双栅结构，即相邻两行像素之间设置两条栅极线，此排布方式可以减少一半的数据线，即包含相邻两列像素之间有的数据线，有的相邻两列像素之间不包括数据线，具体像素排布结构和数据线，扫描线的排布方式不限定。
需要说明的是，本公开实施例中的显示面板可以为液晶显示面板。示例性地，液晶显示面板一般包括对盒的上基板和下基板，以及封装在上基板和下基板之间的液晶分子。在显示画面时，由于加载在各子像素SPX的像素电极上的数据电压和公共电极上的公共电极电压之间具有电压差，该电压差可以形成电场，从而使液晶分子在该电场的作用下进行偏转。由于不同强度的电场使液晶分子的偏转程度不同，从而导致子像素SPX的透过率不同，以使子像素SPX实现不同灰阶的亮度，进而实现画面显示。当然，本公开实施例中的显示面板可以为OLED显示面板，在此不作限定。
在一些示例中，栅极驱动电路可以包括多个移位寄存器。例如，如图3所示，第1级至第N级移位寄存器：SR(1)、SR(2)…SR(n-1)、SR(n)…SR(N-1)、SR(N)(共N个移位寄存器，1≤n≤N，n为整数，图2以SR(1)～SR(24)为例)。可以将栅极驱动电路中的多个移位寄存器分为多个寄存器组。其中，同一寄存器组中的移位寄存器可以级联设置，并且不同寄存器组连接的帧起始信号端不同。
示例性地，可以将栅极驱动电路中的移位寄存器分为两个寄存器组。结合图3与图4a所示，这两个寄存器组中的第一寄存器组X1包括第奇数个移 位寄存器：第1级移位寄存器SR(1)、第3级移位寄存器SR(3)、第5级移位寄存器SR(5)、……第19级移位寄存器SR(19)、第21级移位寄存器SR(21)以及第23级移位寄存器SR(23)。并且，第奇数级移位寄存器与第奇数条栅线电连接。其中，第1级移位寄存器SR(1)的输入信号端IP、第3级移位寄存器SR(3)的输入信号端IP、以及第5级移位寄存器SR(5)的输入信号端IP均与帧起始信号端STV_A电连接。并且，第1级移位寄存器SR(1)的输出信号端GO与第7级移位寄存器SR(7)的输入信号端IP电连接。第3级移位寄存器SR(3)的输出信号端GO与第9级移位寄存器SR(9)的输入信号端IP电连接。……第15级移位寄存器SR(15)的输出信号端GO与第21级移位寄存器SR(21)的输入信号端IP电连接。第17级移位寄存器SR(17)的输出信号端GO与第23级移位寄存器SR(23)的输入信号端IP电连接。以及，第9级移位寄存器SR(9)的输出信号端GO与第1级移位寄存器SR(1)的复位信号端RE电连接。第11级移位寄存器SR(11)的输出信号端GO与第3级移位寄存器SR(3)的复位信号端RE电连接。……第21级移位寄存器SR(21)的输出信号端GO与第13级移位寄存器SR(13)的复位信号端RE电连接。第23级移位寄存器SR(23)的输出信号端GO与第15级移位寄存器SR(15)的复位信号端RE电连接。
结合图2与图4b所示，这两个寄存器组中的第二寄存器组X2包括第偶数个移位寄存器：第2级移位寄存器SR(2)、第4级移位寄存器SR(4)、第6级移位寄存器SR(6)、……第20级移位寄存器SR(20)、第22级移位寄存器SR(22)以及第24级移位寄存器SR(24)。并且，第偶数级移位寄存器与第偶数条栅线电连接。其中，第2级移位寄存器SR(2)的输入信号端IP、第4级移位寄存器SR(4)的输入信号端IP、以及第6级移位寄存器SR(6)的输入信号端IP均与帧起始信号端STV_B电连接。并且，第2级移位寄存器SR(2)的输出信号端GO与第8级移位寄存器SR(8)的输入信号端IP电连接。第4级移位寄存器SR(4)的输出信号端GO与第10级移位寄存器SR(10)的输入信号端IP电连接。……第16级移位寄存器SR(16)的输出信号端GO与第22级移位寄存器SR(22)的输入信号端IP电连接。第18级移位寄存器SR(18)的输出信号端 GO与第24级移位寄存器SR(24)的输入信号端IP电连接。以及，第10级移位寄存器SR(10)的输出信号端GO与第2级移位寄存器SR(2)的复位信号端RE电连接。第12级移位寄存器SR(12)的输出信号端GO与第4级移位寄存器SR(4)的复位信号端RE电连接。……第22级移位寄存器SR(22)的输出信号端GO与第14级移位寄存器SR(14)的复位信号端RE电连接。第24级移位寄存器SR(24)的输出信号端GO与第16级移位寄存器SR(16)的复位信号端RE电连接。
图3所示的栅极驱动电路对应的信号时序图，如图5所示。其中，stv_a代表帧起始信号端STV_A的帧起始信号，stv_b代表帧起始信号端STV_B的帧起始信号，ck1代表时钟信号线CK1上传输的时钟信号，ck2代表时钟信号线CK2上传输的时钟信号，ck3代表时钟信号线CK3上传输的时钟信号，ck4代表时钟信号线CK4上传输的时钟信号，ck5代表时钟信号线CK5上传输的时钟信号，ck6代表时钟信号线CK6上传输的时钟信号，ck7代表时钟信号线CK7上传输的时钟信号，ck8代表时钟信号线CK8上传输的时钟信号，ck9代表时钟信号线CK9上传输的时钟信号，ck10代表时钟信号线CK10上传输的时钟信号，ck11代表时钟信号线CK11上传输的时钟信号，ck12代表时钟信号线CK12上传输的时钟信号。信号ga1代表第1级移位寄存器SR(1)的输出信号端GO输出的栅极驱动信号。信号ga2代表第2级移位寄存器SR(2)的输出信号端GO输出的栅极驱动信号。信号ga3代表第3级移位寄存器SR(3)的输出信号端GO输出的栅极驱动信号。……信号ga24代表第24级移位寄存器SR(24)的输出信号端GO输出的栅极驱动信号。……信号gaN代表第N级移位寄存器SR(N)的输出信号端GO输出的栅极驱动信号。其中，第1级移位寄存器SR(1)将时钟信号ck1的第一个高电平通过输出信号端GO输出，以产生信号ga1中的高电平。第2级移位寄存器SR(2)将时钟信号ck2的第一个高电平通过输出信号端GO输出，以产生信号ga2中的高电平。第3级移位寄存器SR(3)将时钟信号ck1的第一个高电平通过输出信号端GO输出，以产生信号ga3中的高电平。……第12级移位寄存器SR(12)将时钟信号ck12的第一 个高电平通过输出信号端GO输出，以产生信号ga12中的高电平。第13级移位寄存器SR(13)将时钟信号ck1的第二个高电平通过输出信号端GO输出，以产生信号ga13中的高电平。第14级移位寄存器SR(14)将时钟信号ck2的第二个高电平通过输出信号端GO输出，以产生信号ga14中的高电平。……第24级移位寄存器SR(1)将时钟信号ck12的第二个高电平通过输出信号端GO输出，以产生信号ga12中的高电平。……第N级移位寄存器SR(N)将时钟信号ck12的最后一个高电平通过输出信号端GO输出，以产生信号gaN中的高电平。也就是说，时钟信号的高电平可以为其有效电平，低电平为其无效电平。当然，在移位寄存器将时钟信号低电平通过输出信号端GO输出，以产生信号中控制晶体管导通的低电平信号时，可以将时钟信号的低电平作为其有效电平，高电平为其无效电平。
需要说明的是，本公开实施例中，仅是以栅极驱动电路中的移位寄存器分为两个寄存器组为例进行说明。在实际应用中，栅极驱动电路中的移位寄存器还可以分为三个寄存器组，四个寄存器组或更多个寄存器组，在此不作限定。
灰阶，一般是将最暗与最亮之间的亮度变化区分为若干份，以便于进行屏幕亮度管控。例如，以显示的图像由红、绿、蓝三种颜色组成，其中每一个颜色都可以显现出不同的亮度级别，并且不同亮度层次的红、绿、蓝组合起来，可以形成不同的色彩。例如，液晶显示面板的灰阶位数为6bit，则红、绿、蓝这三种颜色分别具有64(即2 6)个灰阶，这64个灰阶值分别为0～63。液晶显示面板的灰阶位数为8bit，则红、绿、蓝这三种颜色分别具有256(即2 8)个灰阶，这256个灰阶值分别为0～255。液晶显示面板的灰阶位数为10bit，则红、绿、蓝这三种颜色分别具有1024(即2 10)个灰阶，这1024个灰阶值分别为0～1023。液晶显示面板的灰阶位数为12bit，则红、绿、蓝这三种颜色分别具有4096(即2 12)个灰阶，这4096个灰阶值分别为0～4093。
结合图6所示，以一个子像素SPX为例，Vcom代表公共电极电压。其中，在该子像素SPX的像素电极中输入的数据电压大于公共电极电压Vcom 时，可以使该子像素SPX处的液晶分子为正极性，则该子像素SPX中的数据电压对应的极性为正极性。在子像素SPX的像素电极中输入的数据电压小于公共电极电压Vcom时，可以使该子像素SPX处的液晶分子为负极性，则该子像素SPX中的数据电压对应的极性为负极性。例如，公共电极电压可以为8.3V，若在该子像素SPX的像素电极中输入了8.3V～16V的数据电压，可以使该子像素SPX处的液晶分子为正极性，则8.3V～16V的数据电压为对应正极性的数据电压。若在该子像素SPX的像素电极中输入了0.6V～8.3V的数据电压，可以使该子像素SPX处的液晶分子为负极性，则0.6V～8.3V的数据电压为对应负极性的数据电压。示例性地，以8bit的0～255灰阶为例，若在子像素SPX的像素电极中输入16V的数据电压时，该子像素SPX可以对应正极性的最大灰阶值的亮度。若在子像素SPX的像素电极中输入0.6V的数据电压时，该子像素SPX可以对应负极性的最大灰阶值的亮度。
结合图2至图6所示，以帧翻转(也可以说点翻转、列翻转、行翻转等)为例，显示面板的一个显示帧F0可以包括数据刷新阶段TS和空白时间(Blanking Time)阶段TB。在数据刷新阶段TS中，可以控制显示面板中的子像素输入数据电压，从而使显示面板显示该显示帧F0的画面。具体地，如图6所示，对栅线GA1加载信号ga1，对栅线GA2加载信号ga2，对栅线GA3加载信号ga3，对栅线GA4加载信号ga4，在信号ga1～ga4中出现栅极开启信号(例如信号ga1～ga4中的高电平信号)时，可以控制对应的晶体管01导通。例如，在信号ga1出现栅极开启信号时，可以控制第一行子像素中的晶体管01均导通，源极驱动电路120根据显示数据，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第一行子像素中的像素电极02输入对应的数据电压，从而使第一行中的每一个子像素输入数据电压。在信号ga2出现栅极开启信号时，可以控制第二行子像素中的晶体管01均导通，源极驱动电路120根据显示数据，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第二行子像素 中的像素电极02输入对应的数据电压，从而使第二行中的每一个子像素输入数据电压。在信号ga3出现栅极开启信号时，可以控制第三行子像素中的晶体管01均导通，源极驱动电路120根据显示数据，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第三行子像素中的像素电极02输入对应的数据电压，从而使第三行中的每一个子像素输入数据电压。在信号ga4出现栅极开启信号时，可以控制第四行子像素中的晶体管01均导通，源极驱动电路120根据显示数据，对数据线DA1加载相应的数据电压da1，对数据线DA2加载相应的数据电压da2，对数据线DA3加载相应的数据电压da3，以使第四行子像素中的像素电极02输入对应的数据电压，从而使第四行中的每一个子像素输入数据电压。其余行以此类推，在此不作赘述。
如图6所示，在空白时间(Blanking Time)阶段TB中，信号ga1～ga4均为低电平，每个子像素中的晶体管01均处于截止状态，控制每个子像素中的像素电极02保持数据电压，从而控制显示面板中的子像素保持数据电压，从而使显示面板继续显示该显示帧F0的画面。
在显示面板工作时，可能会受到某些影响而导致显示面板损坏(比如：黑屏、异常显示等等)。为了保护显示面板，显示驱动电路可以对显示面板进行检测，并将检测得到的结果发送给主控单元。在显示驱动电路将检测得到的结果发送给主控单元时，若显示驱动电路向栅极驱动电路发送高低电平交替的时钟信号时，会对该时钟信号造成干扰，导致时钟信号的高电平变宽，如图7中虚线框所示。其中，图7中，L1代表未受干扰时的时钟信号，L2代表受到干扰时的时钟信号。
现有技术中，为了避免干扰时钟信号，通常在显示驱动电路将检测得到的结果发送给主控单元时，将时钟信号切换为无效电平。然而，这样设置导致栅极驱动电路不能级联输出，造成显示面板出现显示异常。本公开实施例中提供的驱动方法，可以在数据刷新阶段内，确定显示面板的当前工作状态。并由于空白时间阶段内，时钟信号为无效电压，这样在空白时间阶段内，发 送显示面板的当前工作状态，可以避免发送显示面板的当前工作状态时对时钟信号的有效电平造成干扰，也可以不用额外的将时钟信号切换为无效电平，也可以不用额外的改变信号时序，从而可以使栅极驱动电路能够正常的级联输出，进而避免显示面板出现显示异常。
如图8所示，本公开实施例提供的显示面板的驱动方法，可以包括如下步骤：
S100、在数据刷新阶段内，对显示面板中的栅极驱动电路加载包括有效电平和无效电平的时钟信号，使栅线加载栅极开启信号，并且对显示面板中的源极驱动电路加载显示数据，使数据线加载数据电压，以及确定显示面板的当前工作状态。
在本公开一些实施例中，显示驱动电路可以在数据刷新阶段内，对显示面板中的栅极驱动电路加载包括有效电平和无效电平的时钟信号，使栅线加载栅极开启信号，并且对显示面板中的源极驱动电路加载显示数据，使数据线加载数据电压，以及确定显示面板的当前工作状态。示例性地，主控单元可以在数据刷新阶段内，发送静电检测指令。显示驱动电路可以在数据刷新阶段内，接收静电检测指令，并基于静电检测指令确定显示面板的当前工作状态。
结合图9所示，以时钟信号ck1～ck12中的有效电平为高电平，无效电平为低电平为例，在数据刷新阶段TS内，对显示面板中的栅极驱动电路加载时钟信号ck1～ck12，可以使栅线GA1～GAN上传输信号ga1～gaN，并且，信号ga1～ga24中的高电平可以作为其栅极开启信号。栅线上传输的栅极开启信号可以控制连接的晶体管导通，源极驱动电路可以根据接收到的显示数据向数据线输入数据电压，从而对子像素SPX充电，使子像素SPX输入相应的数据电压，实现画面显示功能。并在驱动显示面板对子像素SPX充电的过程中，接收静电检测指令，并基于静电检测指令确定显示面板的当前工作状态。需要说明的是，该具体过程可以参见上述对数据刷新阶段TS和空白时间(Blanking Time)阶段TB的工作过程的描述，在此不作赘述。
在本公开一些实施例中，确定显示面板的当前工作状态，可以包括：采集显示面板中设置的保护电路输出的保护信号。其中，在保护信号不小于信号阈值时，可以确定显示面板的当前工作状态为非正常工作状态。在保护信号小于信号阈值时，确定显示面板的当前工作状态为正常工作状态。示例性地，非正常工作状态例如可以为显示面板受到静电影响较大的状态，或者为显示面板受到信号干扰较大的状态等。而正常工作状态可以为显示面板受到静电影响较小的状态或不受静电影响的状态，或者正常工作状态可以为显示面板受到信号干扰较小的状态或不受信号干扰的状态等。
示例性地，保护信号可以设置为电流，例如，保护电路可以为静电释放(Electro Static Discharge，ESD)电路，保护信号可以为ESD电路输出的电流，信号阈值可以为电流阈值，这样在ESD电路输出的电流不小于电流阈值时，说明该电流较大，从而可以说明显示面板受到静电影响导致损坏的可能性较大，进而可以确定显示面板的当前工作状态为非正常工作状态。在ESD电路输出的电流小于电流阈值时，说明该电流较小，从而可以说明显示面板受到静电影响导致损坏的可能性较小，进而可以确定显示面板的当前工作状态为正常工作状态。当然，保护电路也可以为其他功能的保护电路，在此不作限定。
在本公开一些实施例中，在确定显示面板的当前工作状态处于非正常工作状态的同时，可以生成并存储非正常工作指令。在确定显示面板的当前工作状态处于正常工作状态的同时，生成并存储正常工作指令。示例性地，非正常工作指令和正常工作指令可以为数字信号。例如，非正常工作指令和正常工作指令可以为采用二进制、十进制、十六进制的数字信号。例如，在非正常工作指令和正常工作指令采用十六进制时，可以采用9C的数字信号代表正常工作指令，将除9C之外的数字信号(例如9D)代表非正常工作指令。
S200、在空白时间阶段内，对显示面板中的栅极驱动电路加载包括无效电平的时钟信号，使栅线加载栅极关闭信号，并且发送显示面板的当前工作状态。示例性地，结合图9所示，在空白时间阶段TB内，对显示面板中的栅 极驱动电路加载包括低电平(即无效电平)的时钟信号ck1～ck12，可以使信号ga1～gaN均为低电平(即栅极关闭信号)。
在本公开一些实施例中，显示驱动电路可以在空白时间阶段内，对显示面板中的栅极驱动电路加载包括无效电平的时钟信号，使栅线加载栅极关闭信号，并且发送显示面板的当前工作状态。示例性地，主控单元可以在空白时间阶段内，发送状态请求指令。显示驱动电路可以在空白时间阶段内，接收状态请求指令，并基于状态请求指令，发送显示面板的当前工作状态给主控单元。可选地，显示驱动电路具有状态寄存器；状态寄存器可以存储非正常工作指令和正常工作指令。例如，以采用9C的数字信号代表正常工作指令，将除9C之外的数字信号(例如9D)代表非正常工作指令为例，在确定显示面板的当前工作状态处于非正常工作状态时，可以在状态寄存器中存储代表非正常工作指令的9D。在确定显示面板的当前工作状态处于正常工作状态时，可以在状态寄存器中存储代表正常工作指令的9C。
在本公开一些实施例中，在空白时间阶段内，接收状态请求指令，并基于状态请求指令发送显示面板的当前工作状态。其中，发送显示面板的当前工作状态，可以包括：在确定显示面板的当前工作状态为非正常工作状态时，发送存储的非正常工作指令。在确定显示面板的当前工作状态处于正常工作状态时，发送存储的正常工作指令。示例性地，以采用9C的数字信号代表正常工作指令，将除9C之外的数字信号(例如9D)代表非正常工作指令为例，显示驱动电路在确定显示面板的当前工作状态处于正常工作状态时，可以发送存储的9C给主控单元。这样可以使主控单元接收到以9C代表的正常工作指令，从而可以判定显示面板处于正常工作状态，即不需要对正在工作中的显示面板进行保护措施和/或进行异常报警。显示驱动电路在确定显示面板的当前工作状态为非正常工作状态时，可以发送存储的9D给主控单元。这样可以使主控单元接收到以9D代表的非正常工作指令，从而可以确定接收到的不是9C，则可以判定显示面板处于非正常工作状态中，此时可以控制显示面板进行复位(Reset)或重启或关机，以对显示面板进行保护和/或进行异常报警。 尤其是在显示装置为可穿戴产品(智能手表、虚拟现实设备等)时，可以对产品进行更好的保护和/或进行异常报警。
在本公开一些实施例中，可以在显示面板中最后一条栅线加载的栅极开启信号对应的时钟信号的有效电平结束后进入空白时间阶段。示例性地，结合图9所示，可以在时钟信号ck12的最后一个高电平(即有效电平)的下降沿出现时进入空白时间阶段TB。
在本公开一些实施例中，可以在进入空白时间阶段并经过设定时间后，接收状态请求指令。示例性地，结合图9所示，可以在进入空白时间阶段并经过设定时间td后，接收状态请求指令。也就是说，可以在进入空白时间阶段并经过设定时间td后，主控单元发送状态请求指令给显示驱动电路，显示驱动电路在接收到状态请求指令后，向主控单元发送确定出的显示面板的当前工作状态。由于刚进入空白时间阶段，主控单元和显示驱动芯片的工作可能还不稳定，等一定时间td后，主控单元和显示驱动芯片的工作趋于稳定后，主控单元发送状态请求指令给显示驱动电路，显示驱动电路在接收到状态请求指令后，向主控单元发送确定出的显示面板的当前工作状态，从而可以稳定的传输状态请求指令和显示面板的当前工作状态对应的非正常工作指令和正常工作指令。
在本公开一些实施例中，可以在连续的多个显示帧中的每个显示帧中，在数据刷新阶段内，确定显示面板的当前工作状态，以及在空白时间阶段内，确定发送显示面板的当前工作状态。这样可以每个显示帧均对显示面板的工作状态进行检测，提高显示面板的工作稳定性。
在本公开一些实施例中，在连续的多个显示帧中每间隔至少一个显示帧的显示帧中，在数据刷新阶段内，确定显示面板的当前工作状态，以及在空白时间阶段内，确定发送显示面板的当前工作状态。这样可以在部分显示帧对显示面板的工作状态进行检测，可以降低功耗。示例性地，在连续的多个显示帧中每间隔一个显示帧的显示帧中，在数据刷新阶段内，确定显示面板的当前工作状态，以及在空白时间阶段内，确定发送显示面板的当前工作状 态。例如，在第奇数个显示帧(如，第一个显示帧、第三个显示帧、第五个显示帧等)中，在数据刷新阶段内，确定显示面板的当前工作状态，以及在空白时间阶段内，确定发送显示面板的当前工作状态。或者，在第偶数个显示帧(如，第二个显示帧、第四个显示帧、第六个显示帧等)中，在数据刷新阶段内，确定显示面板的当前工作状态，以及在空白时间阶段内，确定发送显示面板的当前工作状态。当然，也可以使间隔三个、四个、五个、或更多个显示帧在数据刷新阶段内，确定显示面板的当前工作状态，以及在空白时间阶段内，确定发送显示面板的当前工作状态。
在显示装置中，尤其是可穿戴产品中，为了降低成本，可以将显示驱动电路设置为一个。示例性地，如图10所示，显示装置还包括：信号传输板(例如可以为柔性电路板)400。显示驱动电路200通过信号传输板400与显示面板100耦接。其中，信号传输板200可以具有多条信号传输线。并且，信号传输板可以将显示驱动电路发送的时钟信号传输给显示面板。示例性地，显示驱动电路200可以为0D0C芯片，该0D0C芯片可以为在外部不需要任何辅助升压模块设计，即可完成显示面板的显示。即该0D0C芯片将所有的升压模块都集成到芯片内部，所以集成度较高。并且，由于该0D0C芯片将所有的升压模块都集成到芯片内部，可以使信号传输板400不用额外的设置电容和电阻，从而可以降低信号传输板的成本和设计难度。
并且，对于0D0C芯片而言，相当于1颗芯片完成了整个显示面板的显示驱动工作，使得0D0C芯片的负担较重，信号稳定性交叉，其输出的信号更容易受到干扰。例如，在显示驱动电路向栅极驱动电路发送高低电平交替的时钟信号时，会对该时钟信号造成干扰，导致时钟信号的高电平变宽，如图7中虚线框所示。本公开实施例中提供的驱动方法，可以在数据刷新阶段内，确定显示面板的当前工作状态。并由于空白时间阶段内，时钟信号为无效电压，这样在空白时间阶段内，发送显示面板的当前工作状态，可以避免发送显示面板的当前工作状态时对时钟信号的有效电平造成干扰，也可以不用额外的将时钟信号切换为无效电平，也可以不用额外的改变信号时序，从而可 以使栅极驱动电路能够正常的级联输出，进而避免显示面板出现显示异常。
本领域内的技术人员应明白，本公开的实施例可提供为方法、系统、或计算机程序产品。因此，本公开可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本公开可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本公开是参照根据本公开实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变 型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (16)

  1. 一种显示面板的驱动方法，一个显示帧包括数据刷新阶段和空白时间阶段；
    所述显示面板的驱动方法，包括：
    在所述数据刷新阶段内，对所述显示面板中的栅极驱动电路加载包括有效电平和无效电平的时钟信号，使栅线加载栅极开启信号，并且对所述显示面板中的源极驱动电路加载显示数据，使数据线加载数据电压，以及确定所述显示面板的当前工作状态；
    在所述空白时间阶段内，对所述显示面板中的栅极驱动电路加载包括无效电平的时钟信号，使栅线加载栅极关闭信号，并且发送所述显示面板的当前工作状态。
  2. 如权利要求1所述的显示面板的驱动方法，其中，所述确定所述显示面板的当前工作状态，包括：
    采集所述显示面板中设置的保护电路输出的保护信号；
    在所述保护信号不小于信号阈值时，确定所述显示面板的当前工作状态为非正常工作状态；
    在所述保护信号小于所述信号阈值时，确定所述显示面板的当前工作状态为正常工作状态。
  3. 如权利要求2所述的显示面板的驱动方法，其中，所述驱动方法还包括：
    在所述确定所述显示面板的当前工作状态处于非正常工作状态的同时，生成并存储非正常工作指令；
    在所述确定所述显示面板的当前工作状态处于正常工作状态的同时，生成并存储正常工作指令；
    所述发送所述显示面板的当前工作状态，包括：
    在确定所述显示面板的当前工作状态为非正常工作状态时，发送存储的 所述非正常工作指令；
    在所述确定所述显示面板的当前工作状态处于正常工作状态时，发送存储的所述正常工作指令。
  4. 如权利要求1-3任一项所述的显示面板的驱动方法，其中，所述驱动方法还包括：
    在所述数据刷新阶段内，接收静电检测指令，并基于所述静电检测指令确定所述显示面板的当前工作状态。
  5. 如权利要求1-4任一项所述的显示面板的驱动方法，其中，所述驱动方法还包括：
    在所述空白时间阶段内，接收状态请求指令，并基于所述状态请求指令发送所述显示面板的当前工作状态。
  6. 如权利要求1-5任一项所述的显示面板的驱动方法，其中，在所述显示面板中最后一条栅线加载的栅极开启信号对应的时钟信号的有效电平结束后进入空白时间阶段。
  7. 如权利要求6所述的显示面板的驱动方法，其中，在进入所述空白时间阶段并经过设定时间后，接收状态请求指令。
  8. 如权利要求1-7任一项所述的显示面板的驱动方法，其中，在连续的多个显示帧中的每个显示帧中，在所述数据刷新阶段内，确定所述显示面板的当前工作状态，以及在所述空白时间阶段内，确定发送所述显示面板的当前工作状态。
  9. 如权利要求1-8任一项所述的显示面板的驱动方法，其中，在连续的多个显示帧中每间隔至少一个显示帧的显示帧中，在所述数据刷新阶段内，确定所述显示面板的当前工作状态，以及在所述空白时间阶段内，确定发送所述显示面板的当前工作状态。
  10. 一种显示装置，包括：
    显示面板，包括栅极驱动电路和源极驱动电路；
    显示驱动电路，被配置为在所述数据刷新阶段内，对所述显示面板中的 栅极驱动电路加载包括有效电平和无效电平的时钟信号，使栅线加载栅极开启信号，并且对所述显示面板中的源极驱动电路加载显示数据，使数据线加载数据电压，以及确定所述显示面板的当前工作状态；在所述空白时间阶段内，对所述显示面板中的栅极驱动电路加载包括无效电平的时钟信号，使栅线加载栅极关闭信号，并且发送所述显示面板的当前工作状态；其中，一个显示帧包括数据刷新阶段和空白时间阶段。
  11. 如权利要求10所述的显示装置，其中，还包括：主控单元；
    所述主控单元被配置为在所述空白时间阶段内，发送状态请求指令；
    所述显示驱动电路还被配置为在所述空白时间阶段内，接收状态请求指令，并基于所述状态请求指令，发送所述显示面板的当前工作状态给所述主控单元。
  12. 如权利要求11所述的显示装置，其中，所述显示驱动电路具有状态寄存器；所述状态寄存器被配置为存储非正常工作指令和正常工作指令。
  13. 如权利要求12所述的显示装置，其中，所述主控单元还被配置为在所述数据刷新阶段内，发送静电检测指令；
    所述显示驱动电路还被配置为在所述数据刷新阶段内，接收静电检测指令，并基于所述静电检测指令确定所述显示面板的当前工作状态。
  14. 如权利要求10-13任一项所述的显示装置，其中，所述显示装置还包括：信号传输板；所述信号传输板具有多条信号传输线；
    所述显示驱动电路通过所述信号传输板与所述显示面板耦接；并且，所述信号传输板配置为将所述显示驱动电路发送的时钟信号传输给所述显示面板。
  15. 如权利要求14所述的显示装置，其中，所述信号传输板包括柔性电路板。
  16. 如权利要求10-15任一项所述的显示装置，其中，所述显示驱动电路为一个。
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US20130135282A1 (en) * 2011-11-25 2013-05-30 Jin Young Jeon Display device
CN109272931A (zh) * 2018-11-23 2019-01-25 京东方科技集团股份有限公司 显示面板的显示控制方法、显示控制装置、显示设备
WO2021223565A1 (zh) * 2020-05-08 2021-11-11 京东方科技集团股份有限公司 移位寄存器、驱动方法、驱动控制电路及显示装置

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* Cited by examiner, † Cited by third party
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US20130135282A1 (en) * 2011-11-25 2013-05-30 Jin Young Jeon Display device
CN109272931A (zh) * 2018-11-23 2019-01-25 京东方科技集团股份有限公司 显示面板的显示控制方法、显示控制装置、显示设备
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