WO2020177541A1 - 栅极驱动单元、栅极驱动电路及其驱动方法、显示装置 - Google Patents

栅极驱动单元、栅极驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2020177541A1
WO2020177541A1 PCT/CN2020/075989 CN2020075989W WO2020177541A1 WO 2020177541 A1 WO2020177541 A1 WO 2020177541A1 CN 2020075989 W CN2020075989 W CN 2020075989W WO 2020177541 A1 WO2020177541 A1 WO 2020177541A1
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WIPO (PCT)
Prior art keywords
pull
terminal
transistor
node
circuit
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PCT/CN2020/075989
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English (en)
French (fr)
Inventor
张炜檬
王谦
王磊
张旭茹
路永全
张夺
张彦杰
江峰
孙冬雪
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Publication of WO2020177541A1 publication Critical patent/WO2020177541A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a gate driving unit and a driving method thereof, a gate driving circuit and a driving method thereof, and a display device.
  • TDDI display and touch integration
  • most of the driving methods for the integration of display and touch are to perform touch scanning after one frame of screen is displayed. For example, if the display frequency is 60 Hz and the touch frequency is 60 Hz, a touch scan is performed after each frame of the display scan is completed.
  • the present disclosure proposes a gate driving unit, a gate driving circuit and a driving method thereof, and a display device.
  • the present disclosure provides a gate driving unit including a shift register and a charging circuit.
  • the shift register includes a pull-up circuit, which is connected to a pull-up node, a clock signal terminal, and a signal output terminal, and is configured to respond to the voltage of the pull-up node at an effective level, and the clock The clock signal provided by the signal terminal is transmitted to the signal output terminal.
  • the charging circuit is connected to the charging terminal and the pull-up node, and is configured to transmit the effective level of the charging terminal in response to the voltage of the pull-up node being at an effective level and the charging terminal provides an effective level To the pull-up node to charge the pull-up node.
  • the charging circuit includes: a control sub-circuit and a gate sub-circuit.
  • the control sub-circuit is connected to the pull-up node, the charging terminal, and the gating sub-circuit, and is configured to respond to the voltage at the pull-up node being at an effective level and the charging terminal provides effective power Level, transmitting the effective level of the pull-up node to the gating sub-circuit.
  • the gating sub-circuit is connected to the pull-up node and the charging terminal, and is configured to transmit the effective level of the charging terminal to the pull-up node in response to the effective level provided by the control sub-circuit .
  • control sub-circuit includes: a first transistor and a second transistor.
  • the gate and the first electrode of the first transistor are both connected to the pull-up node, the second electrode of the first transistor is connected to the first electrode of the second transistor, and the gate of the second transistor Connected to the charging terminal, and the second electrode of the second transistor is connected to the gate sub-circuit.
  • the gate sub-circuit includes: a third transistor.
  • the gate of the third transistor is connected to the control sub-circuit, the first electrode of the third transistor is connected to the charging terminal, and the second electrode of the third transistor is connected to the pull-up node.
  • the gating sub-circuit further includes a first capacitor.
  • the first terminal of the first capacitor is connected to the gate of the third transistor, and the second terminal of the first capacitor is connected to the first electrode of the third transistor.
  • the shift register further includes: a precharge circuit, a reset circuit, a pull-up circuit, and a pull-down control circuit.
  • the precharge circuit is connected to an input terminal, the pull-up node, and a first power terminal, and is configured to transmit a signal from the first power terminal to the pull-up node in response to the input terminal providing an effective level .
  • the reset circuit is connected to the pull-up node, the reset terminal, and the second power terminal, and is configured to transmit the signal of the second power terminal to the pull-up node in response to the reset terminal providing an effective level.
  • the pull-down control circuit is connected to the pull-up node, the pull-down node, the third power terminal, and the fourth power terminal, and is configured to respond to the voltage of the pull-up node at an effective level, turn the third power terminal
  • the provided signal is transmitted to the pull-down node, and in response to the voltage of the pull-up node being at an invalid level, the signal provided by the fourth power terminal is transmitted to the pull-down node.
  • the pull-down circuit is connected to the pull-down node, the pull-up node, the signal output terminal, and the fourth power terminal, and is configured to respond to the voltage of the pull-down node at an effective level, and turn the first
  • the signals provided by the four power supply terminals are transmitted to the pull-up node and the signal output terminal.
  • the third power terminal is configured to provide an active level
  • the fourth power terminal is configured to provide an inactive level
  • one of the first power terminal and the second power terminal is configured to provide an effective level, and the other of the first power terminal and the second power terminal is configured to Provide an invalid level.
  • the precharge circuit includes a fourth transistor, the gate of the fourth transistor is connected to the input terminal, and the first electrode of the fourth transistor is connected to the first power terminal.
  • the second electrode of the fourth transistor is connected to the pull-up node.
  • the reset circuit includes a fifth transistor, the gate of the fifth transistor is connected to the reset terminal, the first electrode of the fifth transistor is connected to the pull-up node, and the second electrode of the fifth transistor is Connected to the second power supply terminal.
  • the pull-up circuit includes a sixth transistor and a second capacitor, the gate of the sixth transistor is connected to the pull-up node, the first pole of the sixth transistor is connected to the clock signal terminal, and the The second electrode of the six transistor is connected to the signal output terminal, the first terminal of the second capacitor is connected to the pull-up node, and the second terminal of the second capacitor is connected to the signal output terminal.
  • the pull-down control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor. The gate and the first electrode of the seventh transistor are both connected to the third power terminal, and the seventh transistor The second electrode of the eighth transistor is connected to the gate of the eighth transistor and the first electrode of the ninth transistor. The first electrode of the eighth transistor is connected to the third power supply terminal.
  • the two electrodes are connected to the pull-down node, the gate of the ninth transistor is connected to the pull-up node, the second electrode of the ninth transistor is connected to the fourth power terminal, and the gate of the tenth transistor is connected to the The pull-up node is connected, the first electrode of the tenth transistor is connected to the pull-down node, and the second electrode of the tenth transistor is connected to the fourth power terminal.
  • the pull-down circuit includes: an eleventh transistor and a twelfth transistor, the gate of the eleventh transistor and the gate of the twelfth transistor are both connected to the pull-down node, and the gate of the eleventh transistor
  • the first pole is connected to the signal output terminal
  • the second pole of the eleventh transistor is connected to the fourth power terminal
  • the first pole of the twelfth transistor is connected to the pull-up node
  • the The second pole of the twelfth transistor is connected to the fourth power terminal.
  • the present disclosure provides a driving method for the gate driving unit according to the present disclosure, including: providing a first signal at an inactive level through the charging terminal in a pre-charging phase;
  • the pull-up node provides a valid level to control the pull-up circuit to transmit the invalid level provided by the clock signal terminal to the signal output terminal; in the recharging phase, the charging terminal provides a second signal, so At least a part of the second signal is at an active level, and the charging circuit is used to transmit the part of the second signal at the active level to the pull-up node to control the pull-up circuit to transmit the clock signal
  • the ineffective level provided by the terminal is transmitted to the signal output terminal; in the output stage, the first signal is provided through the charging terminal to stop the charging circuit from charging the pull-up node; through the pull-up
  • the node controls the pull-up circuit to transmit the effective level provided by the clock signal terminal to the signal output terminal.
  • the second signal is one of the following signals: a signal continuously at an active level, and a square wave signal that switches between an active level and an inactive level.
  • the shift register further includes: a precharge circuit, a reset circuit, a pull-up circuit, and a pull-down control circuit.
  • the step of providing an active level to the pull-up node to control the pull-up circuit to transmit the invalid level provided by the clock signal terminal to the signal output terminal includes: providing an active level through the input terminal to The pre-charging circuit transmits the effective level provided by the first power terminal to the pull-up node, and the pull-up circuit transmits the invalid level provided by the clock signal terminal to the signal output terminal.
  • the driving method further includes: in the reset phase, providing an active level through the reset terminal, so that the reset circuit transmits the inactive level provided by the second power terminal to the upper Pull node; the pull-down control circuit transmits the effective level provided by the third power terminal to the pull-down node, and the pull-down circuit transmits the invalid level provided by the fourth power terminal to the pull-up node And the signal output terminal.
  • the present disclosure also provides a gate driving circuit including a plurality of cascaded gate driving units. At least one-stage gate driving unit other than the first-stage gate driving unit adopts the gate driving unit according to the present disclosure. Except for the last-stage gate drive unit, the signal output terminals of the other levels of gate drive units are connected to the input terminals of the next-stage gate drive units; except for the first-stage gate drive units, other levels of gate drive The signal output terminal of the unit is connected to the reset terminal of the previous gate drive unit.
  • the clock signal terminal of the odd-numbered stage gate driving unit is connected to the first clock signal line, and the clock signal terminal of the even-numbered stage gate driving unit is connected to the second clock signal line; in the display scanning phase, the A clock signal line and the second clock signal line are configured to provide clock signals of opposite phases.
  • each stage of the gate driving unit adopts the gate driving unit according to the present disclosure, and the charging terminal of each stage of the gate driving unit is connected to the same charging signal line.
  • the present disclosure also provides a driving method for the gate driving circuit according to the present disclosure.
  • At least one stage of the gate drive unit in the gate drive units of the other stages except the first stage in the gate drive circuit is the gate drive unit to be charged, and the gate drive unit to be charged is based on this
  • the gate drive unit to be charged and the previous gate drive unit form a drive unit group.
  • the driving method includes: in each display period, the plurality of cascaded gate driving units sequentially output effective levels; wherein, one of the stages in which the two-stage gate driving units of the driving unit group output effective levels There is a touch scan phase in between.
  • the driving method further includes: in the touch scan stage, providing a second signal to the charging terminal of each gate driving unit to be charged to charge the pull-up node of the gate driving unit to be charged, wherein At least a part of the second signal is at an active level.
  • the present disclosure also provides a display device including the gate driving circuit according to the present disclosure.
  • FIG. 1 is a schematic structural diagram of a gate driving unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a gate driving unit according to an embodiment of the present disclosure
  • FIG. 3 is a working timing diagram of the gate driving unit shown in FIG. 2;
  • FIG. 4 is a signal timing diagram of the charging terminal of the gate driving unit according to an embodiment of the present disclosure
  • FIG. 5 is a flowchart of a driving method of a gate driving unit according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a signal timing diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate of the pull-up transistor is connected to the pull-up node, and when the voltage of the pull-up node is at an effective level, the signal from the clock signal terminal is transmitted to the signal output terminal.
  • the touch frequency is greater than the display frequency, it is usually necessary to perform a touch scan during the display of one frame. Assuming that the display frequency is 60 Hz, the touch frequency is 120 Hz, and the gate driving circuit includes an N-stage shift register, it is necessary to perform two touch scans in each display period.
  • the first n-1 stage shift registers sequentially output scan signals for display; then enter the touch scan stage; after the touch scan stage ends, the nth and subsequent shift registers sequentially output For the displayed scan signal.
  • the pull-up node of the n-th stage shift register becomes high, and the high state of the pull-up node needs to continue until the touch scan stage End.
  • the pull-up node of the n-th shift register will be discharged.
  • the pull-up transistor of the n-th shift register is not fully turned on, which will cause the corresponding row of Pixels are not fully charged and display abnormalities occur.
  • the present disclosure provides a gate driving unit and a driving method thereof, a gate driving circuit and a driving method thereof, and a display device.
  • each transistor in the embodiments of the present disclosure may be a thin film transistor or a field effect transistor or other switching devices with the same characteristics; one of the first electrode and the second electrode of the transistor is the source of the transistor , The other is the drain of the transistor.
  • the "effective level” in the present disclosure is a level capable of turning on the transistor
  • the "inactive level” is a level capable of turning off the transistor.
  • the effective level refers to a high level
  • the ineffective level refers to a low level
  • the effective level refers to low level
  • the ineffective level refers to high Level.
  • each transistor is an N-type transistor as an example for illustrative description.
  • the effective level refers to the high level
  • the invalid level refers to the low level.
  • FIG. 1 is a schematic structural diagram of a gate driving unit according to an embodiment of the present disclosure.
  • the gate driving unit includes a shift register GOA and a charging circuit 10.
  • the charging circuit 10 is connected to the charging terminal C-CLK and the pull-up node PU of the shift register GOA, and is configured to respond to the voltage of the pull-up node PU of the shift register GOA at an effective level and the charging terminal C-CLK to provide an effective level,
  • the effective level of the charging terminal C-CLK is transmitted to the pull-up node PU to charge the pull-up node PU.
  • the pull-up circuit in the shift register GOA transmits the clock signal provided by the clock signal terminal to the output terminal of the shift register GOA in response to the voltage of the pull-up node PU being at an active level.
  • the gate driving unit of this embodiment is used in a gate driving circuit, in one display period, if the n-th stage gate driving unit outputs a scanning signal during a period of time and the n-1th stage gate driving unit outputs a scanning signal If there is a touch scan phase between the time periods of, then the effective level (ie, high level) signal can be provided to the charging terminal C-CLK of each gate driving unit, and at this time, the upper level of the nth gate driving unit The pull node PU is at a high level.
  • the charging circuit 10 can charge the pull-up node PU of the n-th gate driving unit, so that the pull-up node PU maintains the voltage before the touch scan stage, and then the touch After the scanning phase is over, the pull-up transistor controlled by the pull-up node PU in the n-th gate driving unit can be fully turned on, thereby improving poor display.
  • the charging circuit 10 may include: a control sub-circuit 11 and a gate sub-circuit 12.
  • the control sub-circuit 11 is connected to the pull-up node PU, the charging terminal C-CLK, and the gating sub-circuit 12, and is configured to respond to the voltage of the pull-up node PU being at an effective level and the charging terminal C-CLK to provide an effective level to pull up
  • the effective level of the node PU is transmitted to the gating sub-circuit 12.
  • the gating sub-circuit 12 is also connected to the pull-up node PU and the charging terminal C-CLK, and is configured to transmit the effective level at the charging terminal C-CLK to the pull-up node PU in response to the effective level provided by the control sub-circuit 11, To charge the pull-up node PU.
  • the shift register GOA may include: a precharge circuit 21, a reset circuit 22, a pull-up circuit 23, a pull-down control circuit 24, and a pull-down circuit 25.
  • the precharge circuit 21, the reset circuit 22, and the pull-up circuit 23 are connected to the pull-up node PU, and the pull-down control circuit 24 and the pull-down circuit 25 are connected to the pull-down node PD.
  • the precharge circuit 21 is connected to the input terminal INPUT of the shift register, the pull-up node PU and the first power supply terminal V1, and is configured to transmit the signal provided by the first power supply terminal V1 under the control of the effective level provided by the input terminal INPUT To the pull node PU.
  • the reset circuit 22 is connected to the pull-up node PU, the reset terminal RST, and the second power terminal V2, and is configured to transmit the signal provided by the second power terminal V2 to the pull-up node PU under the control of the effective level provided by the reset terminal RST.
  • the pull-up circuit 23 is connected to the pull-up node PU, the signal output terminal OUTPUT of the shift register GOA, and the clock signal terminal CLK, and is configured to transmit the signal provided by the clock signal terminal CLK in response to the voltage of the pull-up node PU being at an effective level To the signal output terminal OUTPUT.
  • the pull-down control circuit 24 is connected to the pull-up node PU, the pull-down node PD, the third power supply terminal V3, and the fourth power supply terminal V4, and is configured to respond to the potential at the pull-up node PU to combine the signal provided by the third power supply terminal V3 with the first One of the signals provided by the four power terminals V4 is transmitted to the pull-down node PD.
  • the pull-down control circuit 24 transmits the signal provided by the third power terminal V3 to the pull-down node PD; when the voltage of the pull-up node PU is at an invalid level, the pull-down control circuit 24 will The signal provided by the power terminal V4 is transmitted to the pull-down node PD.
  • the pull-down circuit 25 is connected to the pull-down node PD, the pull-up node PU, the signal output terminal OUTPUT, and the fourth power terminal V4, and is configured to transmit the signal provided by the fourth power terminal V4 to the upper terminal in response to the voltage of the pull-down node PD being an effective level. Pull node PU and signal output terminal OUTPUT.
  • the third power terminal V3 is configured to provide an active level (ie, a high level), and the fourth power terminal V4 is configured to provide an inactive level (ie, a low level).
  • the gate driving unit can be used in a bidirectional scanning gate driving circuit. When forward scanning is performed, the first power supply terminal V1 of the gate driving unit is configured to provide an effective level, and the second power supply terminal V2 is configured to provide an invalid power. When performing reverse scanning, the first power terminal V1 of the gate driving unit is configured to provide an inactive level, and the second power terminal V2 is configured to provide an active level.
  • FIG. 2 is a schematic structural diagram of a gate driving unit according to an embodiment of the present disclosure.
  • the circuit structure shown in FIG. 2 is a specific implementation of the gate driving unit shown in FIG. 1.
  • the charging circuit 10 includes: a control sub-circuit 11 and a gate sub-circuit 12.
  • the control sub-circuit 11 includes: a first transistor T1 and a second transistor T2.
  • the gate and the first electrode of the first transistor T1 are both connected to the pull-up node PU; the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2, and the gate of the second transistor T2 is connected to the charging terminal C- CLK is connected, and the second pole of the second transistor T2 is connected to the gate sub-circuit 12.
  • the gate sub-circuit 12 includes a third transistor T3, the gate of the third transistor T3 is connected to the control sub-circuit 11, the first electrode of the third transistor T3 is connected to the charging terminal C-CLK, and the second electrode of the third transistor T3 Connected to the pull-up node PU.
  • the gate drive unit When the gate drive unit is used in the gate drive circuit, and a contact is made between the stage when the gate drive unit of the n-1th stage outputs a high-level signal and the stage when the gate drive unit of the nth stage outputs a high-level signal.
  • the pull-up node PU of the n-th gate drive unit is in a high level state, so that the first transistor T1 is turned on.
  • the high-level signal can control the second transistor T2 to turn on, so that the gate of the third transistor T3 and the pull-up node PU are turned on, and then the third transistor T3 is turned on, and the charging terminal C-CLK is upward through the third transistor T3
  • the pull node PU is charged to prevent leakage of the pull node PU.
  • the gating sub-circuit 12 further includes a first capacitor C1.
  • the first terminal of the first capacitor C1 is connected to the gate of the third transistor T3, and the second terminal of the first capacitor C1 is connected to the first terminal of the third transistor T3. Connected.
  • the potential of the gate of the third transistor T3 in the n-th gate drive unit can be further increased, thereby ensuring the full capacity of the third transistor T3. Turning on, thereby ensuring that the charging terminal C-CLK quickly charges the pull-up node PU.
  • control sub-circuit and gating sub-circuit it is possible to locate the gate drive unit that needs to be charged, avoid charging the gate drive unit that does not need to be charged and increase additional power consumption, while ensuring a stable charging circuit and avoiding interference .
  • the shift register GOA includes: a precharge circuit 21, a reset circuit 22, a pull-up circuit 23, a pull-down control circuit 24, and a pull-down circuit 25.
  • the precharge circuit 21 includes a fourth transistor T4, the gate of the fourth transistor T4 is connected to the input terminal INPUT, the first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is connected to the pull-up The node PU is connected.
  • the reset circuit 22 includes a fifth transistor T5, the gate of the fifth transistor T5 is connected to the reset terminal RST, the first electrode of the fifth transistor T5 is connected to the pull-up node PU, and the second electrode of the fifth transistor T5 is connected to the second power supply terminal. V2 is connected.
  • the pull-up circuit 23 includes a sixth transistor T6 (ie, a pull-up transistor) and a second capacitor C2.
  • the gate of the sixth transistor T6 is connected to the pull-up node PU, and the first pole of the sixth transistor T6 is connected to the clock signal terminal CLK.
  • the second pole of the sixth transistor T6 is connected to the signal output terminal OUTPUT.
  • the first terminal of the second capacitor C2 is connected to the pull-up node PU, and the second terminal of the second capacitor C2 is connected to the signal output terminal OUTPUT.
  • the pull-down control circuit 24 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.
  • the gate and the first electrode of the seventh transistor T7 are both connected to the third power supply terminal V3, and the second electrode of the seventh transistor M7 is connected to the gate of the eighth transistor T8 and the first electrode of the ninth transistor T9.
  • the first pole of the eighth transistor T8 is connected to the third power terminal V3, and the second pole of the eighth transistor T8 is connected to the pull-down node PD.
  • the gate of the ninth transistor T9 is connected to the pull-up node PU, and the second electrode of the ninth transistor T9 is connected to the fourth power terminal V4.
  • the gate of the tenth transistor T10 is connected to the pull-up node PU, the first electrode of the tenth transistor T10 is connected to the pull-down node PD, and the second electrode of the tenth transistor T10 is connected to the fourth power terminal V4.
  • the pull-down circuit 25 includes: an eleventh transistor T11 and a twelfth transistor T12.
  • the gate of the eleventh transistor T11 and the gate of the twelfth transistor T12 are both connected to the pull-down node PD, the first electrode of the eleventh transistor T11 is connected to the signal output terminal OUTPUT, and the second electrode of the eleventh transistor T11 is connected to The fourth power terminal V4 is connected.
  • the first pole of the twelfth transistor T12 is connected to the pull-up node PU, and the second pole of the twelfth transistor T12 is connected to the fourth power terminal V4.
  • FIG. 3 is a working timing diagram of the gate driving unit shown in FIG. 2.
  • the working process of the gate driving unit for example, the n-th stage shift register unit
  • the first power terminal V1 and the third power terminal V3 are configured to provide a high-level signal
  • the second power terminal V2 and the fourth power terminal V4 are configured to provide a low-level signal.
  • the charging terminal C-CLK provides the first signal in a low level state
  • the clock signal terminal CLK provides a low level signal
  • the input terminal INPUT provides a high level signal
  • the reset terminal RST provides a low level signal.
  • the fourth transistor T4 is turned on, thereby transmitting the high-level signal provided by the first power terminal V1 to the pull-up node PU, so that the pull-up node PU is in a high-level state; because the pull-up node PU reaches a high-level state Therefore, the first transistor T1 is turned on. Since the charging terminal C-CLK provides a low-level signal, the second transistor T2 is turned off, and there is no voltage across the first capacitor C1. At the same time, the third transistor T3 is turned off, and the charging circuit 10 has no effect on the potential of the pull-up node PU.
  • the ninth transistor T9 and the tenth transistor T10 are both turned on. Therefore, the low-level signal of the fourth power supply terminal V4 is transmitted to the eighth transistor T8 through the ninth transistor T9 The gate of the eighth transistor T8 is turned off; the low-level signal of the fourth power terminal V4 is transmitted to the pull-down node PD through the tenth transistor T10, so that the eleventh transistor T11 and the twelfth transistor T12 are both turned off .
  • the sixth transistor T6 is turned on, and the low-level signal of the clock signal terminal CLK is transmitted to the signal output terminal OUTPUT through the sixth transistor T6, so that the signal output terminal OUTPUT Output low level signal.
  • the charging terminal C-CLK provides a second signal, at least a part of the second signal is in a high level state; the input terminal INPUT, the reset terminal RST and the clock signal terminal CLK all provide a low level signal.
  • the pull-up node PU is still in a high level state, so that the first transistor T1 is turned on.
  • the second transistor T2 is turned on, so that the gate of the third transistor T3 is connected to the pull-up node PU, and the potential of the gate of the third transistor T3 is pulled high, so that The third transistor T3 is turned on.
  • the potential of the gate of the third transistor T3 is further increased, thereby ensuring that the third transistor T3 is fully turned on. In this way, the high-level signal of the charging terminal C-CLK is transmitted to the pull-up node PU through the third transistor T3, so as to charge the pull-up node PU and prevent the pull-up node PU from leaking.
  • the states of the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 remain the same as those of the precharge stage, and the clock signal
  • the low-level signal of the terminal CLK is transmitted to the signal output terminal OUTPUT through the sixth transistor T6.
  • part of the second signal provided by the charging terminal C-CLK during the recharging phase is in a high-level state, and another part is in a low-level state (as shown in FIG. 3); and the second signal is The frequency of switching between high and low levels is consistent with the touch scan frequency.
  • the gate drive circuit and the touch scan circuit are arranged closer.
  • the pair of gate drive units can be reduced. Interference of touch scan signal.
  • the second signal provided by the charging terminal C-CLK during the recharging phase may also be a continuous high-level signal, as shown in FIG. 4.
  • the charging terminal C-CLK provides the first signal in a low level state, and the clock signal terminal CLK provides a high level signal.
  • the pull-up node PU still maintains the high level state during the recharging phase, so that the first transistor T1 maintains the conductive state. Since the charging terminal C-CLK is in a low level state, the second transistor T2 is turned off. Under the bootstrap action of the first capacitor C1, the potential of the gate of the third transistor T3 is reduced to a low level state, so that the third transistor T3 is turned off, and the charging circuit 10 no longer acts on the pull-up node PU.
  • the sixth transistor T6 is turned on, and the high-level signal of the clock signal terminal CLK is transmitted to the signal output terminal OUTPUT through the sixth transistor T6. Under the bootstrap action of the second capacitor C2, the potential of the pull-up node PU further rises.
  • the charging terminal C-CLK, the input terminal INPUT, and the clock signal terminal CLK all provide a low level signal, and the reset terminal RST provides a high level signal.
  • the fourth transistor T4 is turned off and the fifth transistor T5 is turned on, and the low-level signal of the second power supply terminal V2 is transmitted to the pull-up node PU through the fifth transistor T5. Since the pull-up node PU is in a low level state, the first transistor T1 is turned off. Moreover, since the charging terminal C-CLK is in a low level state, the second transistor T2 and the third transistor T3 are both turned off.
  • the ninth transistor T9 and the tenth transistor T10 are both turned off.
  • the seventh transistor T7 is equivalent to a large resistance
  • the high-level signal of the third power terminal V3 is transmitted to the gate of the eighth transistor T8 through the seventh transistor T7, so that the eighth transistor T8 is turned on; and, the third The high-level signal of the power terminal V3 is transmitted to the pull-down node PD through the eighth transistor T8, so that the eleventh transistor T11 and the twelfth transistor T12 are turned on. Therefore, the low-level signal of the fourth power terminal V4 passes through the tenth transistor.
  • a transistor T11 and a twelfth transistor T12 are respectively transmitted to the pull-up node PU and the signal output terminal OUTPUT.
  • FIG. 5 is a flowchart of a driving method of a gate driving unit according to an embodiment of the present disclosure. As shown in FIG. 3 and FIG. 5, the driving method includes step S11 to step S14.
  • Step S11 In the pre-charging phase, the first signal at the inactive level is provided through the charging terminal C-CLK; at the same time, the pull-up node PU provides an active level to control the signal output terminal OUTPUT of the shift register GOA to output an inactive level .
  • this step S11 includes: in the pre-charging phase, providing an effective level to the input terminal INPUT and providing an inactive level to the clock signal terminal CLK, so that the pre-charging circuit 21 makes the first power terminal V1 effective The level is transmitted to the pull-up node PU, and the pull-up circuit 23 transmits the invalid level provided by the clock signal terminal CLK to the signal output terminal OUTPUT.
  • Step S12 In the recharging phase, a second signal is provided through the charging terminal C-CLK, at least a part of the second signal is at an effective level, and the charging circuit 10 is used to transmit the part of the second signal at the effective level to the pull-up node PU , To control the signal output terminal OUTPUT to output an invalid level.
  • the second signal may be continuously at a high level; or, the second signal is a square wave signal that switches between a high level and a low level.
  • the step of using the charging circuit 10 to transfer the part of the second signal at the active level to the pull-up node PU to control the signal output terminal OUTPUT to output the invalid level includes: providing the invalid level through the clock signal terminal CLK to make the pull-up
  • the circuit 23 transmits the inactive level of the clock signal terminal CLK to the signal output terminal OUTPUT in response to the active level of the pull-up node PU.
  • Step S13 In the output stage, a first signal is provided through the charging terminal C-CLK to stop the charging circuit 10 from charging the pull-up node PU; and the signal output terminal OUTPUT is controlled to output an effective level.
  • the step of controlling the signal output terminal OUTPUT to output an effective level includes: providing an effective level through the clock signal terminal CLK, so that the pull-up circuit 23 responds to the effective level of the pull-up node PU to output the effective level provided by the clock signal terminal CLK Transmitted to the signal output terminal OUTPUT.
  • Step S14 In the reset phase, the reset terminal RST is used to provide an effective level, so that the reset circuit 22 transmits the invalid level provided by the second power terminal V2 to the pull-up node PU, and controls the signal output terminal OUTPUT to output the invalid level.
  • FIG. 6 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present disclosure.
  • the gate driving circuit includes a plurality of cascaded gate driving units G_DR, and at least one gate driving unit G_DR except the first-stage gate driving unit G_DR is the gate driving unit of the above-mentioned embodiment.
  • the signal output terminals OUTPUT of the other stages of the gate driving unit G_DR are all connected to the input terminal INPUT of the corresponding next-stage gate driving unit G_DR.
  • the signal output terminals OUTPUT of the other stages of the gate driving unit are connected to the reset terminal RST of the corresponding previous-stage gate driving unit G_DR.
  • the clock signal terminal CLK of the odd-numbered gate driving unit G_DR is connected to the first clock signal line CLK1
  • the clock signal terminal CLK of the even-numbered gate driving unit G_DR is connected to the second clock signal line CLK2.
  • Each display cycle includes a display scanning phase and a touch scanning phase.
  • the duty ratios of the clock signals provided by the first clock signal line CLK1 and the second clock signal line CLK2 are both 1/2
  • the phases of the two clock signals provided by the first clock signal line CLK1 and the second clock signal line CLK2 are opposite, that is, one of the two clock signals provided by the first clock signal line CLK1 and the second clock signal line CLK2 When in the high state, the other is in the low state.
  • each stage of the gate driving unit G_DR may use the gate driving unit in the above-mentioned embodiments.
  • the charging terminal C-CLK of each stage of the gate driving unit G_DR is connected to the charging signal line C-LINE.
  • the charging signal line C-LINE can be used to
  • the charging terminal C-CLK of the first-level gate driving unit G_DR provides an effective level, and since only the pull-up node PU of the n-th gate driving unit G_DR is in a high-level state at this time, only the n-th gate driving
  • the charging circuit of the unit G_DR charges the corresponding pull-up node PU, thereby preventing leakage of the pull-up node PU of the n-th gate driving unit G_DR during the touch scan process.
  • an embodiment of the present disclosure provides a method for driving a gate driving circuit.
  • the gate driving units of the above gate driving circuit other than the first-level gate driving unit at least one level of gate driving
  • the pole driving unit is a gate driving unit to be charged, and the gate driving unit to be charged adopts the gate driving unit in the above-mentioned embodiment, and the gate driving unit to be charged and the previous gate driving unit form a driving unit group .
  • the driving method of the gate driving circuit includes:
  • each display period multiple gate driving units sequentially output effective levels; among them, there is a touch scan phase between the two stages of gate driving units of at least one driving unit group outputting effective levels.
  • FIG. 7 is a signal timing diagram of the gate driving circuit, wherein the gate driving unit of the n-1th stage and the gate driving unit of the nth stage constitute a driving unit group. As shown in FIG. 7, in each display period, the steps for multiple gate driving units to output effective levels include:
  • the frame start signal is provided to the frame start end STV, the first clock signal is provided to the first clock signal line CLK1, and the second clock signal is provided to the second clock signal line CLK2; wherein, in the time period outside the touch scanning phase, The first clock signal and the second clock signal are both clock signals with a duty cycle of 1/2, and when the input terminal of each stage of the gate drive unit receives a high-level signal, the clock signal terminal CLK of the gate drive unit The received signal is at a low level signal, so that the gate driving units of each level sequentially output a high level signal.
  • the signals on the first clock signal line CLK1 and the second clock signal line CLK2 are low power Level signal, so that the gate drive units at all levels output low-level signals.
  • the driving method of the gate driving circuit further includes: providing the charging terminal C-CLK of the next-stage gate driving unit (that is, the gate driving unit to be charged) in each driving unit group in each touch scanning phase
  • the second signal, at least a part of the second signal is at an active level, so as to charge the pull-up node of the next-stage gate driving unit in the driving unit group to prevent the pull-up node from leaking during the touch scan phase.

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Abstract

一种栅极驱动单元及其驱动方法、栅极驱动电路及其驱动方法、显示装置。栅极驱动单元包括移位寄存器和充电电路。所述移位寄存器包括上拉电路，所述上拉电路与上拉节点、时钟信号端和信号输出端相连，并且构造为响应于所述上拉节点的电压处于有效电平，将所述时钟信号端提供的时钟信号传输至所述信号输出端。所述充电电路与充电端和所述上拉节点相连，并且构造为响应于所述上拉节点的电压处于有效电平且所述充电端提供有效电平，将所述充电端的有效电平传输至所述上拉节点，以对所述上拉节点进行充电。

Description

栅极驱动单元、栅极驱动电路及其驱动方法、显示装置
相关申请的交叉引用
本申请要求于2019年3月7日提交的中国专利申请No.201910172254.4的优先权，其内容通过引用方式整体并入本文。
技术领域
本公开涉及显示技术领域，具体涉及一种栅极驱动单元及其驱动方法、栅极驱动电路及其驱动方法、显示装置。
背景技术
消费电子产品的轻薄化设计使得显示与触控集成(TDDI)已经成为主流高端产品的标配。随着技术的发展，对显示和触控的性能要求也逐渐提高。
目前，显示与触控集成的驱动方式大多是在一帧画面显示完成后进行触控扫描。例如，如果显示频率为60Hz，触控频率为60Hz，则每完成一帧画面的显示扫描后，进行一次触控扫描。
发明内容
本公开提出了一种栅极驱动单元、栅极驱动电路及其驱动方法、显示装置。
一方面，本公开提供一种栅极驱动单元，包括移位寄存器和充电电路。所述移位寄存器包括上拉电路，所述上拉电路与上拉节点、时钟信号端和信号输出端相连，并且构造为响应于所述上拉节点的电压处于有效电平，将所述时钟信号端提供的时钟信号传输至所述信号输出端。所述充电电路与充电端和所述上拉节点相连，并且构造为响应于所述上拉节点的电压处于有效电平且所述充电端提供有效电平，将所述充电端的有效电平传输至所述上拉节点，以对所述上拉节点进行充电。
在一些实施例中，所述充电电路包括：控制子电路和选通子电 路。所述控制子电路与所述上拉节点、所述充电端和所述选通子电路相连，并且构造为响应于在所述上拉节点的电压处于有效电平且所述充电端提供有效电平，将所述上拉节点的有效电平传输至所述选通子电路。所述选通子电路与所述上拉节点和所述充电端相连，并且构造为响应于所述控制子电路提供的有效电平，将所述充电端的有效电平传输至所述上拉节点。
在一些实施例中，所述控制子电路包括：第一晶体管和第二晶体管。所述第一晶体管的栅极和第一极均与所述上拉节点相连，所述第一晶体管的第二极与所述第二晶体管的第一极相连，所述第二晶体管的栅极与所述充电端相连，所述第二晶体管的第二极与所述选通子电路相连。
在一些实施例中，所述选通子电路包括：第三晶体管。所述第三晶体管的栅极与所述控制子电路相连，所述第三晶体管的第一极与所述充电端相连，所述第三晶体管的第二极与所述上拉节点相连。
在一些实施例中，所述选通子电路还包括第一电容。所述第一电容的第一端与所述第三晶体管的栅极相连，所述第一电容的第二端与所述第三晶体管的第一极相连。
在一些实施例中，所述移位寄存器还包括：预充电路、复位电路、上拉电路和下拉控制电路。所述预充电路与输入端、所述上拉节点和第一电源端相连，并且构造为响应于所述输入端提供有效电平，将所述第一电源端的信号传输至所述上拉节点。所述复位电路与所述上拉节点、复位端和第二电源端相连，并且构造为响应于所述复位端提供有效电平，将所述第二电源端的信号传输至所述上拉节点。所述下拉控制电路与所述上拉节点、下拉节点、第三电源端和第四电源端相连，并且构造为响应于所述上拉节点的电压处于有效电平，将所述第三电源端提供的信号传输至所述下拉节点，以及响应于所述上拉节点的电压处于无效电平，将所述第四电源端提供的信号传输至所述下拉节点。所述下拉电路与所述下拉节点、所述上拉节点、所述信号输出端和所述第四电源端相连，并且构造为响应于所述下拉节点的电压处于有效电平，将所述第四电源端提供的信号传输至所述上拉节点和 所述信号输出端。
在一些实施例中，所述第三电源端构造为提供有效电平，所述第四电源端构造为提供无效电平。
在一些实施例中，所述第一电源端和所述第二电源端中的一者构造为提供有效电平，所述第一电源端和所述第二电源端中的另一者构造为提供无效电平。
在一些实施例中，所述预充电路括第四晶体管，所述第四晶体管的栅极与所述输入端相连，所述第四晶体管的第一极与所述第一电源端相连，所述第四晶体管的第二极与所述上拉节点相连。所述复位电路包括第五晶体管，所述第五晶体管的栅极与所述复位端相连，所述第五晶体管的第一极与所述上拉节点相连，所述第五晶体管的第二极与所述第二电源端相连。所述上拉电路包括第六晶体管和第二电容，所述第六晶体管的栅极与所述上拉节点相连，所述第六晶体管的第一极与所述时钟信号端相连，所述第六晶体管的第二极与所述信号输出端相连，所述第二电容的第一端与所述上拉节点相连，所述第二电容的第二端与所述信号输出端相连。所述下拉控制电路包括：第七晶体管、第八晶体管、第九晶体管和第十晶体管，所述第七晶体管的栅极和第一极均与所述第三电源端相连，所述第七晶体管的第二极与所述第八晶体管的栅极和所述第九晶体管的第一极相连，所述第八晶体管的第一极与所述第三电源端相连，所述第八晶体管的第二极与所述下拉节点相连，所述第九晶体管的栅极与所述上拉节点相连，第九晶体管的第二极与所述第四电源端相连，所述第十晶体管的栅极与所述上拉节点相连，所述第十晶体管的第一极与所述下拉节点相连，所述第十晶体管的第二极与所述第四电源端相连。所述下拉电路包括：第十一晶体管和第十二晶体管，所述第十一晶体管的栅极和所述第十二晶体管的栅极均与所述下拉节点相连，所述第十一晶体管的第一极与所述信号输出端相连，所述第十一晶体管的第二极与所述第四电源端相连，所述第十二晶体管的第一极与所述上拉节点相连，所述第十二晶体管的第二极与所述第四电源端相连。
另一方面，本公开提供一种用于根据本公开的栅极驱动单元的 驱动方法，包括：在预充电阶段，通过所述充电端提供处于无效电平的第一信号；同时，向所述上拉节点提供有效电平，以控制所述上拉电路将所述时钟信号端提供的无效电平传输至所述信号输出端；在再充电阶段，通过所述充电端提供第二信号，所述第二信号的至少一部分处于有效电平，利用所述充电电路将所述第二信号中处于有效电平的部分传输至所述上拉节点，以控制所述上拉电路将所述时钟信号端提供的无效电平传输至所述信号输出端；在输出阶段，通过所述充电端提供所述第一信号，以停止所述充电电路对所述上拉节点的充电；通过所述上拉节点控制所述上拉电路将所述时钟信号端提供的有效电平传输至所述信号输出端。
在一些实施例中，所述第二信号为以下信号之一：持续为有效电平的信号，以及在有效电平和无效电平之间切换的方波信号。
在一些实施例中，所述移位寄存器还包括：预充电路、复位电路、上拉电路和下拉控制电路。向所述上拉节点提供有效电平，以控制所述上拉电路将所述时钟信号端提供的无效电平传输至所述信号输出端的步骤包括：通过所述输入端提供有效电平，以使得所述预充电路将所述第一电源端提供的有效电平传输至所述上拉节点，所述上拉电路将所述时钟信号端提供的无效电平传输至所述信号输出端。
在一些实施例中，所述驱动方法还包括：在复位阶段，通过所述复位端提供有效电平，以使得所述复位电路将所述第二电源端提供的无效电平传输至所述上拉节点；所述下拉控制电路将所述第三电源端提供的有效电平传输至所述下拉节点，所述下拉电路将所述第四电源端提供的无效电平传输至所述上拉节点和所述信号输出端。
另一方面，本公开还提供一种栅极驱动电路，包括多个级联的栅极驱动单元。除第一级栅极驱动单元外的至少一级栅极驱动单元采用根据本公开的栅极驱动单元。除最后一级栅极驱动单元外，其他各级栅极驱动单元的信号输出端与后一级栅极驱动单元的输入端相连；除第一级栅极驱动单元外，其他各级栅极驱动单元的信号输出端与前一级栅极驱动单元的复位端相连。
在一些实施例中，奇数级栅极驱动单元的时钟信号端与第一时 钟信号线相连，偶数级栅极驱动单元的时钟信号端与第二时钟信号线相连；在显示扫描阶段，所述第一时钟信号线和所述第二时钟信号线构造为提供相位相反的时钟信号。
在一些实施例中，每一级栅极驱动单元采用根据本公开的栅极驱动单元，每一级栅极驱动单元的充电端均与同一充电信号线相连。
另一方面，本公开还提供一种用于根据本公开的栅极驱动电路的驱动方法。在所述栅极驱动电路中的除第一级之外的其他级栅极驱动单元中的至少一级栅极驱动单元为待充电栅极驱动单元，所述待充电栅极驱动单元采用根据本公开的栅极驱动单元，所述待充电栅极驱动单元与其前一级栅极驱动单元构成驱动单元组。所述驱动方法包括：在每个显示周期，所述多个级联的栅极驱动单元依次输出有效电平；其中，所述驱动单元组的两级栅极驱动单元输出有效电平的阶段之间存在触控扫描阶段。所述驱动方法还包括：在所述触控扫描阶段，向每个待充电栅极驱动单元的充电端提供第二信号以向所述待充电栅极驱动单元的上拉节点充电，其中，所述第二信号的至少一部分处于有效电平。
另一方面，本公开还提供一种显示装置，包括根据本公开的栅极驱动电路。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为根据本公开实施例的栅极驱动单元的结构示意图；
图2为根据本公开实施例的栅极驱动单元的结构示意图；
图3为图2所示的栅极驱动单元的工作时序图；
图4为根据本公开实施例的栅极驱动单元的充电端的信号时序图；
图5为根据本公开实施例的栅极驱动单元的驱动方法的流程图；
图6为根据本公开实施例的栅极驱动电路的结构示意图；
图7为根据本公开实施例的栅极驱动电路的信号时序图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
在移位寄存器中，上拉晶体管的栅极与上拉节点相连，并在上拉节点的电压处于有效电平时，将时钟信号端的信号传输至信号输出端。在显示与触控集成的产品中，当触控频率大于显示频率时，通常需要在一帧画面的显示期间进行触控扫描。假设显示频率为60Hz，触控频率为120Hz，栅极驱动电路包括N级移位寄存器，则需要在每个显示周期内进行两次触控扫描。例如，在显示周期内，前n-1级移位寄存器依次输出用于显示的扫描信号；之后进入触控扫描阶段；触控扫描阶段结束之后，第n级及之后的移位寄存器依次输出用于显示的扫描信号。这种情况下，第n-1级移位寄存器输出扫描信号时，第n级移位寄存器的上拉节点变为高电平，上拉节点的高电平状态需要一直持续到触控扫描阶段结束。但是，在触控扫描阶段，第n级移位寄存器的上拉节点会发生放电，从而导致触控扫描阶段结束之后，第n级移位寄存器的上拉晶体管打开不充分，进而导致相应行的像素充电不充分，发生显示异常。
为了解决上述因上拉节点在触控扫描阶段放电而导致的显示异常问题，本公开提供一种栅极驱动单元及其驱动方法、栅极驱动电路及其驱动方法、显示装置。以下结合附图对本公开的各个实施例进行详细说明，其中，此处所描述的各个实施例仅用于说明和解释本公开，并不用于限制本公开。
首先需要说明的是，本公开各实施例中的各个晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件；晶体管的第一极和第二极中的一者为该晶体管的源极，另一者为该晶体管的漏极。
另外，本公开中的“有效电平”为能够使晶体管导通的电平，“无效电平”为能够使晶体管关断的电平。当晶体管为N型晶体管 时，有效电平是指高电平，无效电平是指低电平；而当晶体管为P型晶体管时，有效电平是指低电平，无效电平是指高电平。
在本公开中以各晶体管均为N型晶体管为例进行示例性说明。此时，有效电平是指高电平，无效电平是指低电平。
图1为根据本公开实施例的栅极驱动单元的结构示意图。如图1所示，栅极驱动单元包括移位寄存器GOA和充电电路10。充电电路10与充电端C-CLK、移位寄存器GOA的上拉节点PU相连，构造为响应于移位寄存器GOA的上拉节点PU的电压处于有效电平和充电端C-CLK提供有效电平，将充电端C-CLK的有效电平传输至上拉节点PU，以对上拉节点PU进行充电。移位寄存器GOA中的上拉电路响应于所述上拉节点PU的电压处于有效电平而将时钟信号端提供的时钟信号传输至所述移位寄存器GOA的输出端。
本实施例的栅极驱动单元用于栅极驱动电路中时，在一个显示周期内，若第n级栅极驱动单元输出扫描信号的时间段与第n-1级栅极驱动单元输出扫描信号的时间段之间存在触控扫描阶段，则可以向各个栅极驱动单元的充电端C-CLK提供有效电平(即，高电平)信号，而此时第n级栅极驱动单元的上拉节点PU是处于高电平的，因此，充电电路10可以为第n级栅极驱动单元的上拉节点PU充电，从而使上拉节点PU保持触控扫描阶段前的电压，进而在触控扫描阶段结束后，第n级栅极驱动单元中受上拉节点PU控制的上拉晶体管能够充分导通，从而改善显示不良。
如图1所示，充电电路10可以包括：控制子电路11和选通子电路12。
控制子电路11与上拉节点PU、充电端C-CLK和选通子电路12相连，构造为响应于上拉节点PU的电压处于有效电平和充电端C-CLK提供有效电平，将上拉节点PU的有效电平传输至选通子电路12。
选通子电路12还与上拉节点PU、充电端C-CLK相连，构造为响应于控制子电路11提供的有效电平，将充电端C-CLK处的有效电平传输至上拉节点PU，以对上拉节点PU进行充电。
如图1所示，移位寄存器GOA可以包括：预充电路21、复位电路22、上拉电路23、下拉控制电路24和下拉电路25。预充电路21、复位电路22和上拉电路23连接于上拉节点PU，下拉控制电路24和下拉电路25连接于下拉节点PD。
预充电路21与移位寄存器的输入端INPUT、上拉节点PU和第一电源端V1相连，构造为在输入端INPUT提供的有效电平的控制下，将第一电源端V1提供的信号传输至上拉节点PU。
复位电路22与上拉节点PU、复位端RST和第二电源端V2相连，构造为在复位端RST提供的有效电平的控制下，将第二电源端V2提供的信号传输至上拉节点PU。
上拉电路23与上拉节点PU、移位寄存器GOA的信号输出端OUTPUT和时钟信号端CLK相连，构造为响应于上拉节点PU的电压处于有效电平将时钟信号端CLK所提供的信号传输至信号输出端OUTPUT。
下拉控制电路24与上拉节点PU、下拉节点PD、第三电源端V3和第四电源端V4相连，构造为响应于上拉节点PU处的电位，将第三电源端V3提供的信号和第四电源端V4提供的信号中的一者传输至下拉节点PD。在上拉节点PU的电压为有效电平时，下拉控制电路24将第三电源端V3提供的信号传输至下拉节点PD；在上拉节点PU的电压为无效电平时，下拉控制电路24将第四电源端V4提供的信号传输至下拉节点PD。
下拉电路25与下拉节点PD、上拉节点PU、信号输出端OUTPUT和第四电源端V4相连，构造为响应于下拉节点PD的电压为有效电平，将第四电源端V4提供的信号传输至上拉节点PU和信号输出端OUTPUT。
在本公开的实施例中，第三电源端V3构造为提供有效电平(即，高电平)，第四电源端V4构造为提供无效电平(即，低电平)。栅极驱动单元可以用于双向扫描的栅极驱动电路中，当进行正向扫描时，栅极驱动单元的第一电源端V1构造为提供有效电平，第二电源端V2构造为提供无效电平；当进行反向扫描时，栅极驱动单元的第一 电源端V1构造为提供无效电平，第二电源端V2构造为提供有效电平。
图2为根据本公开实施例的栅极驱动单元的结构示意图。图2所示的电路结构为图1所示的栅极驱动单元的一种具体实施方案。如图2所示，充电电路10包括：控制子电路11和选通子电路12。
控制子电路11包括：第一晶体管T1和第二晶体管T2。第一晶体管T1的栅极和第一极均与上拉节点PU相连；第一晶体管T1的第二极与第二晶体管T2的第一极相连，第二晶体管T2的栅极与充电端C-CLK相连，第二晶体管T2的第二极与选通子电路12相连。
选通子电路12包括：第三晶体管T3，第三晶体管T3的栅极与控制子电路11相连，第三晶体管T3的第一极与充电端C-CLK相连，第三晶体管T3的第二极与上拉节点PU相连。
当栅极驱动单元用于栅极驱动电路中，且在第n-1级栅极驱动单元输出高电平信号的阶段与第n级栅极驱动单元输出高电平信号的阶段之间进行触控扫描时，在触控扫描阶段的开始时刻，第n级栅极驱动单元的上拉节点PU处于高电平状态，从而使第一晶体管T1导通，此外，通过向充电端C-CLK提供高电平信号，可以控制第二晶体管T2开启，从而使得第三晶体管T3的栅极与上拉节点PU导通，进而使第三晶体管T3导通，充电端C-CLK通过第三晶体管T3向上拉节点PU充电，防止上拉节点PU发生漏电。
进一步地，选通子电路12还包括第一电容C1，第一电容C1的第一端与第三晶体管T3的栅极相连，第一电容C1的第二端与第三晶体管T3的第一极相连。这样，在触控扫描阶段，在第一电容C1的自举作用下，第n级栅极驱动单元中的第三晶体管T3的栅极的电位能够进一步升高，从而保证第三晶体管T3的充分导通，进而保证充电端C-CLK对上拉节点PU的快速充电。
通过上述控制子电路和选通子电路，可以定位需要充电的栅极驱动单元，避免对不必进行充电的栅极驱动单元进行充电而增加额外的功耗，同时可以保证稳定的充电回路并且避免干扰。
在本公开的实施例中，移位寄存器GOA包括：预充电路21、 复位电路22、上拉电路23、下拉控制电路24和下拉电路25。
预充电路21包括第四晶体管T4，第四晶体管T4的栅极与输入端INPUT相连，第四晶体管T4的第一极与第一电源端V1相连，第四晶体管T4的第二极与上拉节点PU相连。
复位电路22包括第五晶体管T5，第五晶体管T5的栅极与复位端RST相连，第五晶体管T5的第一极与上拉节点PU相连，第五晶体管T5的第二极与第二电源端V2相连。
上拉电路23包括第六晶体管T6(即，上拉晶体管)和第二电容C2，第六晶体管T6的栅极与上拉节点PU相连，第六晶体管T6的第一极与时钟信号端CLK相连，第六晶体管T6的第二极与信号输出端OUTPUT相连。第二电容C2的第一端与上拉节点PU相连，第二电容C2的第二端与信号输出端OUTPUT相连。
下拉控制电路24包括：第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10。第七晶体管T7的栅极和第一极均与第三电源端V3相连，第七晶体管M7的第二极与第八晶体管T8的栅极和第九晶体管T9的第一极相连。第八晶体管T8的第一极与第三电源端V3相连，第八晶体管T8的第二极与下拉节点PD相连。第九晶体管T9的栅极与上拉节点PU相连，第九晶体管T9的第二极与第四电源端V4相连。第十晶体管T10的栅极与上拉节点PU相连，第十晶体管T10的第一极与下拉节点PD相连，第十晶体管T10的第二极与第四电源端V4相连。
下拉电路25包括：第十一晶体管T11和第十二晶体管T12。第十一晶体管T11的栅极和第十二晶体管T12的栅极均与下拉节点PD相连，第十一晶体管T11的第一极与信号输出端OUTPUT相连，第十一晶体管T11的第二极与第四电源端V4相连。第十二晶体管T12的第一极与上拉节点PU相连，第十二晶体管T12的第二极与第四电源端V4相连。
需要说明的是，本公开对栅极驱动单元中的移位寄存器的结构不作具体限定，不限于图2中的结构。
图3为图2所示的栅极驱动单元的工作时序图。下面以栅极驱 动单元用于正向扫描的栅极驱动电路为例，结合图2和图3对栅极驱动单元(例如，第n级移位寄存器单元)的工作过程进行介绍。在该情况下，第一电源端V1和第三电源端V3构造为提供高电平信号，第二电源端V2和第四电源端V4构造为提供低电平信号。
在预充电阶段t1，充电端C-CLK提供处于低电平状态的第一信号，时钟信号端CLK提供低电平信号，输入端INPUT提供高电平信号，复位端RST提供低电平信号。
此时，第四晶体管T4导通，从而将第一电源端V1提供的高电平信号传输至上拉节点PU，使得上拉节点PU处于高电平状态；由于上拉节点PU达到高电平状态，因此，第一晶体管T1导通。而由于充电端C-CLK提供低电平信号，因此，第二晶体管T2关断，第一电容C1两端无电压。同时，第三晶体管T3关断，充电电路10并不对上拉节点PU的电位起作用。
在上拉节点PU的高电平信号的控制下，第九晶体管T9、第十晶体管T10均导通，因此，第四电源端V4的低电平信号通过第九晶体管T9传输至第八晶体管T8的栅极，从而使第八晶体管T8关断；第四电源端V4的低电平信号通过第十晶体管T10传输至下拉节点PD，从而使第十一晶体管T11和第十二晶体管T12均关断。同时，在上拉节点PU的高电平信号的控制下，第六晶体管T6导通，时钟信号端CLK的低电平信号通过第六晶体管T6传输至信号输出端OUTPUT，从而使信号输出端OUTPUT输出低电平信号。
在再充电阶段t2，充电端C-CLK提供第二信号，该第二信号的至少一部分处于高电平状态；输入端INPUT、复位端RST和时钟信号端CLK均提供低电平信号。
此时，上拉节点PU仍处于高电平状态，从而使得第一晶体管T1导通。当第二信号处于有效电平时，第二晶体管T2导通，从而使第三晶体管T3的栅极与上拉节点PU导通，进而使第三晶体管T3的栅极的电位被拉高，而使第三晶体管T3导通。并且，在第一电容C1的自举作用下，第三晶体管T3的栅极的电位进一步升高，从而保证第三晶体管T3的充分开启。这样，充电端C-CLK的高电平信号 通过第三晶体管T3传输至上拉节点PU，从而为上拉节点PU充电，防止上拉节点PU漏电。
同时，第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11和第十二晶体管T12的状态均保持与预充电阶段相同，时钟信号端CLK的低电平信号通过第六晶体管T6传输至信号输出端OUTPUT。
在本公开的实施例中，充电端C-CLK在再充电阶段提供的第二信号的一部分处于高电平状态，另一部分处于低电平状态(如图3所示)；并且第二信号在高低电平之间切换的频率与触控扫描频率一致。通常在触控显示产品中，栅极驱动电路与触控扫描电路布置得较近，当第二信号在高低电平之间切换的频率与触控扫描频率一致时，可以减少栅极驱动单元对触控扫描信号的干扰。当然，充电端C-CLK在再充电阶段提供的第二信号也可以为持续的高电平信号，如图4中所示。
在输出阶段t3，充电端C-CLK提供处于低电平状态的第一信号，时钟信号端CLK提供高电平信号。
此时，上拉节点PU仍保持再充电阶段时的高电平状态，从而使得第一晶体管T1保持导通状态。而由于充电端C-CLK处于低电平状态，因此，第二晶体管T2关断。在第一电容C1的自举作用下，第三晶体管T3栅极的电位降低至低电平状态，从而使得第三晶体管T3关断，充电电路10不再对上拉节点PU起作用。
同时，由于上拉节点PU处于高电平状态，因此，第六晶体管T6导通，时钟信号端CLK的高电平信号通过第六晶体管T6传输至信号输出端OUTPUT。而在第二电容C2的自举作用下，上拉节点PU的电位进一步升高。
在复位阶段t4，充电端C-CLK、输入端INPUT、时钟信号端CLK均提供低电平信号，复位端RST提供高电平信号。
此时，第四晶体管T4关断且第五晶体管T5导通，第二电源端V2的低电平信号通过第五晶体管T5传输至上拉节点PU。由于上拉节点PU处于低电平状态，因此第一晶体管T1关断。并且，由于充 电端C-CLK处于低电平状态，因此，第二晶体管T2和第三晶体管T3均关断。
同时，由于上拉节点PU处于低电平状态，因此，第九晶体管T9、第十晶体管T10均关断。此时，第七晶体管T7相当于大电阻，第三电源端V3的高电平信号通过第七晶体管T7传输至第八晶体管T8的栅极，以使得第八晶体管T8导通；并且，第三电源端V3的高电平信号通过第八晶体管T8传输至下拉节点PD，从而使得第十一晶体管T11和第十二晶体管T12导通，因此，第四电源端V4的低电平信号通过第十一晶体管T11和第十二晶体管T12分别传输至上拉节点PU和信号输出端OUTPUT。
图5为根据本公开实施例的栅极驱动单元的驱动方法的流程图。结合图3和图5所示，该驱动方法包括步骤S11至步骤S14。
步骤S11、在预充电阶段，通过充电端C-CLK提供处于无效电平的第一信号；同时，向上拉节点PU提供有效电平，以控制移位寄存器GOA的信号输出端OUTPUT输出无效电平。
在一些实施例中，该步骤S11包括：在预充电阶段，向输入端INPUT提供有效电平，并向时钟信号端CLK提供无效电平，以使得预充电路21将第一电源端V1的有效电平传输至上拉节点PU，并且上拉电路23将时钟信号端CLK提供的无效电平传输至信号输出端OUTPUT。
步骤S12、在再充电阶段，通过充电端C-CLK提供第二信号，第二信号的至少一部分处于有效电平，利用充电电路10将第二信号中处于有效电平的部分传输至上拉节点PU，以控制信号输出端OUTPUT输出无效电平。
在本公开的实施例中，第二信号可以持续为高电平；或者，第二信号为在高电平和低电平之间切换的方波信号。
上述利用充电电路10将第二信号中处于有效电平的部分传输至上拉节点PU，以控制信号输出端OUTPUT输出无效电平的步骤包括：通过时钟信号端CLK提供无效电平，以使得上拉电路23响应于上拉节点PU的有效电平将时钟信号端CLK的无效电平传输至信号输出 端OUTPUT。
步骤S13、在输出阶段，通过充电端C-CLK提供第一信号，以停止充电电路10对上拉节点PU的充电；并控制信号输出端OUTPUT输出有效电平。
控制信号输出端OUTPUT输出有效电平的步骤包括：通过时钟信号端CLK提供有效电平，以使得上拉电路23响应于上拉节点PU的有效电平将时钟信号端CLK所提供的有效电平传输至信号输出端OUTPUT。
步骤S14、在复位阶段，通过复位端RST提供有效电平，以使得复位电路22将第二电源端V2提供的无效电平传输至上拉节点PU，并控制信号输出端OUTPUT输出无效电平。
栅极驱动单元在各阶段的工作过程已在上文进行描述，这里不再赘述。
图6为根据本公开实施例的一种栅极驱动电路的结构示意图。如图6所示，栅极驱动电路包括多个级联的栅极驱动单元G_DR，除第一级栅极驱动单元G_DR外的至少一个栅极驱动单元G_DR为上述实施例的栅极驱动单元。在栅极驱动电路中，除最后一级栅极驱动单元G_DR外，其他各级栅极驱动单元G_DR的信号输出端OUTPUT均与对应的后一级栅极驱动单元G_DR的输入端INPUT相连。除第一级栅极驱动单元G_DR外，其他各级栅极驱动单元的信号输出端OUTPUT均与对应的前一级栅极驱动单元G_DR的复位端RST相连。
在一些实施例中，奇数级栅极驱动单元G_DR的时钟信号端CLK与第一时钟信号线CLK1相连，偶数级栅极驱动单元G_DR的时钟信号端CLK与第二时钟信号线CLK2相连。每个显示周期中包括显示扫描阶段和触控扫描阶段，在显示扫描阶段中，第一时钟信号线CLK1和第二时钟信号线CLK2所提供的时钟信号的占空比均为1/2，且第一时钟信号线CLK1和第二时钟信号线CLK2所提供的两个时钟信号相位相反，也就是说，第一时钟信号线CLK1和第二时钟信号线CLK2所提供的两个时钟信号中一者处于高电平状态时，另一者处于低电平状态。
在一些实施例中，每级栅极驱动单元G_DR均可以采用上述实施例中的栅极驱动单元。每级栅极驱动单元G_DR的充电端C-CLK均与充电信号线C-LINE相连。
这样，当在任意相邻两级(记作第n-1级和第n级)栅极驱动单元输出有效电平的阶段之间进行触控扫描时，可以通过充电信号线C-LINE向每级栅极驱动单元G_DR的充电端C-CLK提供有效电平，而由于此时只有第n级栅极驱动单元G_DR的上拉节点PU处于高电平状态，因此，只有第n级栅极驱动单元G_DR的充电电路为相应的上拉节点PU充电，从而防止触控扫描的过程中，第n级栅极驱动单元G_DR的上拉节点PU发生漏电。
另一方面，本公开实施例提供一种栅极驱动电路的驱动方法，在上述栅极驱动电路中的除第一级栅极驱动单元之外的其他级栅极驱动单元中，至少一级栅极驱动单元为待充电栅极驱动单元，所述待充电栅极驱动单元采用上述实施例中的栅极驱动单元，所述待充电栅极驱动单元与其前一级栅极驱动单元构成驱动单元组。栅极驱动电路的驱动方法包括：
在每个显示周期，多个栅极驱动单元依次输出有效电平；其中，至少一个驱动单元组的两级栅极驱动单元输出有效电平的阶段之间存在触控扫描阶段。
图7为栅极驱动电路的信号时序图，其中，第n-1级栅极驱动单元和第n级栅极驱动单元构成了驱动单元组。如图7所示，在每个显示周期，多个栅极驱动单元输出有效电平的步骤包括：
向帧起始端STV提供帧起始信号，向第一时钟信号线CLK1提供第一时钟信号，向第二时钟信号线CLK2提供第二时钟信号；其中，在触控扫描阶段之外的时间段，第一时钟信号和第二时钟信号均为占空比为1/2的时钟信号，且每级栅极驱动单元的输入端接收到高电平信号时，该栅极驱动单元的时钟信号端CLK接收到的信号处于低电平信号，从而使得各级栅极驱动单元依次输出高电平信号。
另外，在触控扫描阶段(即，每组驱动单元组中的后一级栅极驱动单元的再充电阶段)，第一时钟信号线CLK1和第二时钟信号线 CLK2上的信号均为低电平信号，从而使得各级栅极驱动单元均输出低电平信号。
栅极驱动电路的驱动方法还包括：在每个触控扫描阶段，向每个驱动单元组中的后一级栅极驱动单元(即，待充电栅极驱动单元)的充电端C-CLK提供第二信号，所述第二信号的至少一部分处于有效电平，从而向驱动单元组中的后一级栅极驱动单元的上拉节点充电，防止该上拉节点在触控扫描阶段漏电。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (18)

  1. 一种栅极驱动单元，包括移位寄存器和充电电路，
    所述移位寄存器包括上拉电路，所述上拉电路与上拉节点、时钟信号端和信号输出端相连，并且构造为响应于所述上拉节点的电压处于有效电平，将所述时钟信号端提供的时钟信号传输至所述信号输出端；
    所述充电电路与充电端和所述上拉节点相连，并且构造为响应于所述上拉节点的电压处于有效电平且所述充电端提供有效电平，将所述充电端的有效电平传输至所述上拉节点，以对所述上拉节点进行充电。
  2. 根据权利要求1所述的栅极驱动单元，其中，所述充电电路包括：控制子电路和选通子电路；
    所述控制子电路与所述上拉节点、所述充电端和所述选通子电路相连，并且构造为响应于在所述上拉节点的电压处于有效电平且所述充电端提供有效电平，将所述上拉节点的有效电平传输至所述选通子电路；
    所述选通子电路与所述上拉节点和所述充电端相连，并且构造为响应于所述控制子电路提供的有效电平，将所述充电端的有效电平传输至所述上拉节点。
  3. 根据权利要求2所述的栅极驱动单元，其中，所述控制子电路包括：第一晶体管和第二晶体管，
    所述第一晶体管的栅极和第一极均与所述上拉节点相连，所述第一晶体管的第二极与所述第二晶体管的第一极相连，所述第二晶体管的栅极与所述充电端相连，所述第二晶体管的第二极与所述选通子电路相连。
  4. 根据权利要求2或3所述的栅极驱动单元，其中，所述选通 子电路包括：第三晶体管，所述第三晶体管的栅极与所述控制子电路相连，所述第三晶体管的第一极与所述充电端相连，所述第三晶体管的第二极与所述上拉节点相连。
  5. 根据权利要求4所述的栅极驱动单元，其中，所述选通子电路还包括第一电容，所述第一电容的第一端与所述第三晶体管的栅极相连，所述第一电容的第二端与所述第三晶体管的第一极相连。
  6. 根据权利要求1至5中任一项所述的栅极驱动单元，其中，所述移位寄存器还包括：预充电路、复位电路、上拉电路和下拉控制电路，
    所述预充电路与输入端、所述上拉节点和第一电源端相连，并且构造为响应于所述输入端提供有效电平，将所述第一电源端的信号传输至所述上拉节点；
    所述复位电路与所述上拉节点、复位端和第二电源端相连，并且构造为响应于所述复位端提供有效电平，将所述第二电源端的信号传输至所述上拉节点；
    所述下拉控制电路与所述上拉节点、下拉节点、第三电源端和第四电源端相连，并且构造为响应于所述上拉节点的电压处于有效电平，将所述第三电源端提供的信号传输至所述下拉节点，以及响应于所述上拉节点的电压处于无效电平，将所述第四电源端提供的信号传输至所述下拉节点；
    所述下拉电路与所述下拉节点、所述上拉节点、所述信号输出端和所述第四电源端相连，并且构造为响应于所述下拉节点的电压处于有效电平，将所述第四电源端提供的信号传输至所述上拉节点和所述信号输出端。
  7. 根据权利要求6所述的栅极驱动单元，其中，所述第三电源端构造为提供有效电平，所述第四电源端构造为提供无效电平。
  8. 根据权利要求7所述的栅极驱动单元，其中，所述第一电源端和所述第二电源端中的一者构造为提供有效电平，所述第一电源端和所述第二电源端中的另一者构造为提供无效电平。
  9. 根据权利要求6所述的栅极驱动单元，其中，所述预充电路括第四晶体管，所述第四晶体管的栅极与所述输入端相连，所述第四晶体管的第一极与所述第一电源端相连，所述第四晶体管的第二极与所述上拉节点相连；
    所述复位电路包括第五晶体管，所述第五晶体管的栅极与所述复位端相连，所述第五晶体管的第一极与所述上拉节点相连，所述第五晶体管的第二极与所述第二电源端相连；
    所述上拉电路包括第六晶体管和第二电容，所述第六晶体管的栅极与所述上拉节点相连，所述第六晶体管的第一极与所述时钟信号端相连，所述第六晶体管的第二极与所述信号输出端相连，所述第二电容的第一端与所述上拉节点相连，所述第二电容的第二端与所述信号输出端相连；
    所述下拉控制电路包括：第七晶体管、第八晶体管、第九晶体管和第十晶体管，所述第七晶体管的栅极和第一极均与所述第三电源端相连，所述第七晶体管的第二极与所述第八晶体管的栅极和所述第九晶体管的第一极相连，所述第八晶体管的第一极与所述第三电源端相连，所述第八晶体管的第二极与所述下拉节点相连，所述第九晶体管的栅极与所述上拉节点相连，第九晶体管的第二极与所述第四电源端相连，所述第十晶体管的栅极与所述上拉节点相连，所述第十晶体管的第一极与所述下拉节点相连，所述第十晶体管的第二极与所述第四电源端相连；
    所述下拉电路包括：第十一晶体管和第十二晶体管，所述第十一晶体管的栅极和所述第十二晶体管的栅极均与所述下拉节点相连，所述第十一晶体管的第一极与所述信号输出端相连，所述第十一晶体管的第二极与所述第四电源端相连，所述第十二晶体管的第一极与所述上拉节点相连，所述第十二晶体管的第二极与所述第四电源端相连。
  10. 一种用于权利要求1至9中任一项所述的栅极驱动单元的驱动方法，包括：
    在预充电阶段，通过所述充电端提供处于无效电平的第一信号；同时，向所述上拉节点提供有效电平，以控制所述上拉电路将所述时钟信号端提供的无效电平传输至所述信号输出端；
    在再充电阶段，通过所述充电端提供第二信号，所述第二信号的至少一部分处于有效电平，利用所述充电电路将所述第二信号中处于有效电平的部分传输至所述上拉节点，以控制所述上拉电路将所述时钟信号端提供的无效电平传输至所述信号输出端；
    在输出阶段，通过所述充电端提供所述第一信号，以停止所述充电电路对所述上拉节点的充电；通过所述上拉节点控制所述上拉电路将所述时钟信号端提供的有效电平传输至所述信号输出端。
  11. 根据权利要求10所述的驱动方法，其中，所述第二信号为以下信号之一：持续为有效电平的信号，以及在有效电平和无效电平之间切换的方波信号。
  12. 根据权利要求10所述的驱动方法，其中，所述栅极驱动单元采用权利要求6所述的栅极驱动单元，
    向所述上拉节点提供有效电平，以控制所述上拉电路将所述时钟信号端提供的无效电平传输至所述信号输出端的步骤包括：
    通过所述输入端提供有效电平，以使得所述预充电路将所述第一电源端提供的有效电平传输至所述上拉节点，所述上拉电路将所述时钟信号端提供的无效电平传输至所述信号输出端。
  13. 根据权利要求12所述的驱动方法，还包括：
    在复位阶段，通过所述复位端提供有效电平，以使得所述复位电路将所述第二电源端提供的无效电平传输至所述上拉节点；所述下拉控制电路将所述第三电源端提供的有效电平传输至所述下拉节点， 所述下拉电路将所述第四电源端提供的无效电平传输至所述上拉节点和所述信号输出端。
  14. 一种栅极驱动电路，包括多个级联的栅极驱动单元，其中，除第一级栅极驱动单元外的至少一级栅极驱动单元采用权利要求1至9中任意一项所述的栅极驱动单元，
    除最后一级栅极驱动单元外，其他各级栅极驱动单元的信号输出端与后一级栅极驱动单元的输入端相连；
    除第一级栅极驱动单元外，其他各级栅极驱动单元的信号输出端与前一级栅极驱动单元的复位端相连。
  15. 根据权利要求14所述的栅极驱动电路，其中，奇数级栅极驱动单元的时钟信号端与第一时钟信号线相连，偶数级栅极驱动单元的时钟信号端与第二时钟信号线相连；在显示扫描阶段，所述第一时钟信号线和所述第二时钟信号线构造为提供相位相反的时钟信号。
  16. 根据权利要求14或15所述的栅极驱动电路，其中，每一级栅极驱动单元采用权利要求1至9中任意一项所述的栅极驱动单元，每一级栅极驱动单元的充电端均与同一充电信号线相连。
  17. 一种用于权利要求14至16中任一项所述的栅极驱动电路的驱动方法，其中，在所述栅极驱动电路中的除第一级之外的其他级栅极驱动单元中的至少一级栅极驱动单元为待充电栅极驱动单元，所述待充电栅极驱动单元采用权利要求1至9中任一项所述的栅极驱动单元，所述待充电栅极驱动单元与其前一级栅极驱动单元构成驱动单元组，
    所述驱动方法包括：
    在每个显示周期，所述多个级联的栅极驱动单元依次输出有效电平；其中，所述驱动单元组的两级栅极驱动单元输出有效电平的阶段之间存在触控扫描阶段；
    所述驱动方法还包括：
    在所述触控扫描阶段，向每个待充电栅极驱动单元的充电端提供第二信号以向所述待充电栅极驱动单元的上拉节点充电，其中，所述第二信号的至少一部分处于有效电平。
  18. 一种显示装置，包括权利要求14至16中任一项所述的栅极驱动电路。
PCT/CN2020/075989 2019-03-07 2020-02-20 栅极驱动单元、栅极驱动电路及其驱动方法、显示装置 WO2020177541A1 (zh)

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