WO2016138734A1 - 移位寄存器及其驱动方法、栅极驱动电路 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路 Download PDF

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Publication number
WO2016138734A1
WO2016138734A1 PCT/CN2015/085409 CN2015085409W WO2016138734A1 WO 2016138734 A1 WO2016138734 A1 WO 2016138734A1 CN 2015085409 W CN2015085409 W CN 2015085409W WO 2016138734 A1 WO2016138734 A1 WO 2016138734A1
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Prior art keywords
transistor
pull
pole
input terminal
level
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PCT/CN2015/085409
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English (en)
French (fr)
Inventor
周全国
祁小敬
朱亚文
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US15/021,359 priority Critical patent/US9799262B2/en
Publication of WO2016138734A1 publication Critical patent/WO2016138734A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present disclosure relates to the field of gate driving technologies, and in particular, to a shift register, a driving method thereof, and a gate driving circuit.
  • each gate line may be controlled by a gate drive circuit (GOA).
  • the gate driving circuit comprises a plurality of cascaded shift registers, wherein the output of each stage of the shift register is connected to a gate line and is also connected to the next stage shift register, so that it can provide high power for the gate line
  • the flat on signal simultaneously provides a trigger signal for the next stage shift register. In this way, driving of a plurality of gate lines can be realized by a few control signals.
  • the gate lines in the array substrate become longer and longer, and the signal delay caused by the resistors becomes larger and larger; at the same time, the on-time of each gate line (for example, The time of the high level is also getting shorter and shorter. This causes the pixels connected thereto to be insufficiently charged during the on-time of one gate line, and thus causes display defects such as afterimages.
  • the required overlap ratio of the gate line on-times is different (for example, the on-time of two adjacent gate lines has 1/2 or 2/3 overlap).
  • the circuit structure such as the cascading relationship
  • the purpose of changing the overlap ratio of the gate line conduction time cannot be achieved by simple adjustment of the control signal, so the application effect thereof is achieved. restricted.
  • the present disclosure provides a shift register, a driving method thereof, and a gate driving circuit that can simply adjust the overlap ratio of gate line on-times to at least partially alleviate or eliminate the above-mentioned problems.
  • a shift register including an input unit, a charging unit, a pull-up unit, a high-level output unit, a pull-down unit, and a low-level output unit, wherein
  • the input unit is connected between the first input end and the charging unit, and controls whether the signal of the first input end is input to the charging unit;
  • the charging unit is connected to the low level input end, the second input end, the control signal input end, and the pull-up node for charging the pull-up node;
  • a pull-up unit is connected between the second input terminal and the pull-up node for maintaining a high level of the pull-up node
  • the high-level output unit is connected to the high-level input end, the output end, and the pull-up node, and is configured to control whether the high level is output to the output end according to the level of the pull-up node;
  • the pull-down unit is connected to the low-level input terminal, the high-level input terminal, the control signal input terminal, the first input terminal, the second input terminal, the output terminal, the pull-up node, and the low-level output unit, and is used for the pull-up node
  • the level is pulled low and outputs a low level to the output;
  • the low-level output unit is connected to the low-level input terminal, the high-level input terminal, the first input terminal, the second input terminal, the output terminal, the pull-up node, and the pull-down unit, and is configured to output a low level to the output terminal.
  • the input unit may include a first transistor having a gate and a first pole connected to the first input, and a second pole connected to the charging unit.
  • the charging unit may include a second transistor, a third transistor, and a fourth transistor, wherein
  • the gate of the second transistor is connected to the second pole of the third transistor, the first pole is connected to the second pole of the first transistor, and the second pole is connected to the pull-up node;
  • the gate of the third transistor is connected to the control signal input end, and the first pole is connected to the second pole of the first transistor;
  • the gate of the fourth transistor is connected to the second input end, the first pole is connected to the second pole of the first transistor, and the second pole is connected to the low level input end.
  • the pull up unit may comprise a storage capacitor with a first pole connected to the second input and a second pole connected to the pull up node.
  • the high-level output unit may include a fifteenth transistor whose gate is connected to the pull-up node, the first pole is connected to the high-level input terminal, and the second pole is connected to the output terminal.
  • the pull-down unit may include a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a sixteenth transistor, and a seventeenth transistor, wherein
  • the gate of the five transistors and the first pole are connected to the high level input end, and the second pole is connected to the gate of the seventh transistor;
  • the gate of the sixth transistor is connected to the first input end, the first pole is connected to the gate of the seventh transistor, and the second pole is connected to the low level input end;
  • the first pole of the seventh transistor is connected to the second input end, and the second pole is connected to the first pole of the eighth transistor;
  • the gate of the eighth transistor is connected to the control signal input end, and the second pole is connected to the first pull-down node;
  • the gate of the ninth transistor is connected to the first pull-down node, the first pole is connected to the pull-up node, and the second pole is connected to the low-level input terminal;
  • the gate of the sixteenth transistor is connected to the first pull-down node, the first pole is connected to the output end, and the second pole is connected to the low-level input end;
  • the gate of the seventeenth transistor is connected to the low level output unit, the first pole is connected to the first pulldown node, and the second pole is connected to the low level input terminal.
  • the low-level output unit may include a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, wherein
  • the gate of the tenth transistor is connected to the second pull-down node, the first pole is connected to the pull-up node, and the second pole is connected to the low-level input terminal;
  • the gate of the eleventh transistor is connected to the first input end, the first pole is connected to the second pull-down node, and the second pole is connected to the low-level input end;
  • the gate of the twelfth transistor is connected to the second input end, the first pole is connected to the second pull-down node, and the second pole is connected to the low-level input end;
  • the gate of the thirteenth transistor is connected to the first pole to the high level input terminal, and the second pole is connected to the second pulldown node;
  • the gate of the fourteenth transistor is connected to the second pull-down node, the first pole is connected to the output end, and the second pole is connected to the low-level input end;
  • a gate of the seventeenth transistor of the pull-down unit is coupled to a second pull-down node of the low level output unit.
  • the five-transistor, the sixteenth transistor, and the seventeenth transistor are all N-type transistors.
  • a second aspect of the present disclosure provides a driving method of a shift register, wherein the shift register is a shift register according to the first aspect of the present disclosure, and the driving method of the shift register includes:
  • Preparation stage the high-level output unit, the pull-down unit, and the low-level output unit are all turned off, so that the output terminal outputs a low level;
  • Charging phase the input unit is charged for the pull-up unit, and the high-level output unit is turned on, so that the output terminal outputs a high level;
  • Pull-up phase the pull-up unit continues to be charged, and the high-level output unit is turned on, so that the output terminal outputs a high level;
  • Pull-down phase the pull-down unit is turned on and the pull-up unit is discharged, so that the output terminal outputs a low level;
  • Pull-down stabilization phase Turns the pull-down stabilization unit on, causing the output to output a low level.
  • the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are all N-type transistors, and the driving method of the shift register comprises:
  • Preparation stage the control signal input terminal inputs a low level, the first input terminal inputs a high level, and the second input terminal inputs a low level;
  • control signal input terminal inputs a high level, the first input terminal inputs a high level, and the second input terminal inputs a low level;
  • Pull-down stabilization phase Both the first input and the second input input input a low level.
  • the first input terminal inputs a high level in the pull-up phase, and between the pull-up phase and the pull-down phase, further includes a pull-up stabilization phase, which includes the first sub-phase and the second sub-phase , wherein: the first sub-phase: the first input and the second input are input High level; the second sub-phase: the control signal input terminal inputs a low level, the first input terminal inputs a low level, and the second input terminal inputs a high level.
  • a third aspect of the present disclosure provides a gate driving circuit including:
  • each shift register is used to connect a gate line; wherein a first input of each stage of the shift register is coupled to the upper stage shift At the output of the register, the second input of each stage of the shift register is coupled to the output of the next stage shift register.
  • a control signal input end of one shift register is connected to the first clock signal, and a control signal input end of the other shift register is connected to the second clock signal, A clock signal and a second clock signal are inverted.
  • the high level (on) time of the output thereof can be adjusted by controlling the signals of the first input terminal and the second input terminal; when the gate drive circuit is composed of the shift register, The signal at the two input terminals is the output of the upper and lower shift registers, so the high-level (on) time of each shift register is related to the high-level (on) time of the upper and lower shift registers. Therefore, as long as the signal input to the first stage shift register is adjusted, the overlapping ratio of the on-times of the respective gate lines can be changed, thereby making the function of the gate driving circuit more flexible and adapting to the needs of various display devices.
  • 1 is a circuit configuration diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 2 is a signal driving timing diagram of a shift register in accordance with an embodiment of the present disclosure
  • FIG. 3 is another signal driving timing diagram of a shift register in accordance with an embodiment of the present disclosure.
  • FIG. 5 is still another signal driving timing diagram of a shift register according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram showing a cascade relationship of shift registers in a gate driving circuit according to an embodiment of the present disclosure
  • the reference numerals are: T1, the first transistor; the T2, the second transistor; the T3, the third transistor; the T4, the fourth transistor; the T5, the fifth transistor; the T6, the sixth transistor; Seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; T14, fourteenth transistor; T15, fifteenth transistor; T16, sixteenth transistor; T17, seventeenth transistor; Cst, storage capacitor; Vg(n-1), first input terminal; Vg(n), output terminal; Vg(n+ 1), second input terminal; CK, control signal input terminal; PU, pull-up node; PD1, first pull-down node; PD2, second pull-down node; VGL, low-level input terminal; VGH, high-level input end.
  • An embodiment of the present disclosure provides a shift register including an input unit, a charging unit, a pull-up unit, a high-level output unit, a pull-down unit, and a low-level output unit, where
  • the input unit is connected between the first input end and the charging unit, and controls whether the signal of the first input end is input to the charging unit;
  • the charging unit is connected to the low level input end, the second input end, the control signal input end, and the pull-up node for charging the pull-up node;
  • a pull-up unit is connected between the second input terminal and the pull-up node for maintaining a high level of the pull-up node
  • the high-level output unit is connected to the high-level input end, the output end, and the pull-up node, and is configured to control whether the high level is output to the output end according to the level of the pull-up node;
  • the pull-down unit is connected to the low-level input terminal, the high-level input terminal, the control signal input terminal, the first input terminal, the second input terminal, the output terminal, the pull-up node, and the low-level output unit, and is used for the pull-up node
  • the level is pulled low and outputs a low level to the output;
  • the low-level output unit is connected to the low-level input terminal, the high-level input terminal, the first input terminal, the second input terminal, the output terminal, the pull-up node, and the pull-down unit, and is configured to output a low level to the output terminal.
  • a first input of each stage of the shift register is connected to an output of the shift register of the previous stage, and a second input is connected to the next The output of the stage shift register. That is to say, for each stage of the shift register, it is simultaneously controlled by the upper and lower shift registers, and simultaneously controls the upper and lower shift registers.
  • the high level (on) time of the output can be adjusted by controlling the signals of the first input end and the second input end; when the shift register is used to form the gate drive circuit,
  • the signal at the two input terminals is also the output of the upper and lower shift registers, so the high-level (on) time of each shift register is related to the high-level (on) time of the upper and lower shift registers. . Therefore, as long as the signal input to the first stage shift register is adjusted, the overlapping ratio of the on-times of the respective gate lines can be changed, thereby making the function of the gate driving circuit more flexible and adapting to the needs of various display devices.
  • the input unit includes a first transistor T1 whose gate and first pole are connected to the first input terminal Vg(n-1) (which is connected to the output terminal of the shift register of the previous stage), and the second pole is connected.
  • Charging unit As shown in FIG. 1, the input unit includes a first transistor T1 whose gate and first pole are connected to the first input terminal Vg(n-1) (which is connected to the output terminal of the shift register of the previous stage), and the second pole is connected.
  • Charging unit As shown in FIG. 1, the input unit includes a first transistor T1 whose gate and first pole are connected to the first input terminal Vg(n-1) (which is connected to the output terminal of the shift register of the previous stage), and the second pole is connected. Charging unit.
  • the charging unit comprises a second transistor T2, a third transistor T3, and a fourth transistor T4, wherein:
  • the second transistor T2 is connected to the second pole of the third transistor T3, the first pole is connected to the second pole of the first transistor T1, and the second pole is connected to the pull-up node PU;
  • the gate of the third transistor T3 is connected to the control signal input terminal CK, and the first pole is connected to the second pole of the first transistor T1;
  • the gate of the fourth transistor T4 is connected to the second input terminal Vg(n+1) (which is connected to the output terminal of the next stage shift register), the first pole is connected to the second pole of the first transistor T1, and the second pole is connected low. Level input VGL.
  • the pull up unit comprises a storage capacitor Cst, the first pole of which is connected to the second input terminal Vg(n+1) and the second pole is connected to the pullup node PU.
  • the high-level output unit comprises a fifteenth transistor T15 whose gate is connected to the pull-up node PU, the first pole is connected to the high-level input terminal VGH, and the second pole is connected to the output terminal Vg(n).
  • the pull-down unit includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a sixteenth transistor T16, and a seventeenth transistor T17, wherein:
  • the fifth transistor has a gate connected to the high level input terminal VGH and a second terminal connected to the gate of the seventh transistor T7;
  • the gate of the sixth transistor T6 is connected to the first input terminal Vg(n-1), the first pole is connected to the gate of the seventh transistor T7, and the second pole is connected to the low-level input terminal VGL;
  • the first pole of the seventh transistor T7 is connected to the second input terminal Vg(n+1), and the second pole is connected to the first pole of the eighth transistor T8;
  • the gate of the eighth transistor T8 is connected to the control signal input terminal CK, and the second pole is connected to the first pull-down node PD1;
  • the gate of the ninth transistor T9 is connected to the first pull-down node PD1, the first pole is connected to the pull-up node PU, and the second pole is connected to the low-level input terminal VGL;
  • the gate of the sixteenth transistor T16 is connected to the first pull-down node PD1, the first pole is connected to the output terminal Vg(n), and the second pole is connected to the low-level input terminal VGL;
  • the gate of the seventeenth transistor T17 is connected to the low level output unit, the first pole is connected to the first pull-down node PD1, and the second pole is connected to the low level input terminal VGL.
  • the low-level output unit includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14, wherein:
  • the gate of the tenth transistor T10 is connected to the second pull-down node PD2, the first pole is connected to the pull-up node PU, and the second pole is connected to the low-level input terminal VGL;
  • the gate of the eleventh transistor T11 is connected to the first input terminal Vg(n-1), the first pole is connected to the second pull-down node PD2, and the second pole is connected to the low-level input terminal VGL;
  • the second transistor V12 is connected to the second input terminal Vg(n+1), the first electrode is connected to the second pull-down node PD2, and the second electrode is connected to the low-level input terminal VGL;
  • the thirteenth transistor T13 has a gate and a first pole connected to a high level input terminal VGH, and a second pole is connected to the second pulldown node PD2;
  • the gate of the fourteenth transistor T14 is connected to the second pull-down node PD2, the first pole is connected to the output terminal Vg(n), and the second pole is connected to the low-level input terminal VGL;
  • the gate of the seventeenth transistor T17 of the pull-down unit is connected to the second pull-down node PD2 of the low-level output unit.
  • the transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, and the seventeenth transistor T17 may each be an N-type transistor. .
  • An embodiment of the present disclosure further provides a driving method of the above shift register, including:
  • Preparation stage the high-level output unit, the pull-down unit, and the low-level output unit are all turned off, so that the output terminal Vg(n) outputs a low level;
  • Charging phase the input unit is charged for the pull-up unit, and the high-level output unit is turned on, so that the output terminal Vg(n) outputs a high level;
  • Pull-up phase the pull-up unit continues to be charged, and the high-level output unit is turned on, so that the output terminal Vg(n) outputs a high level;
  • Pull-down phase turning on the pull-down unit and discharging the pull-up unit, so that the output terminal Vg(n) outputs a low level;
  • Pull-down stabilization phase Turns the pull-down stable unit on, causing the output terminal Vg(n) to output a low level.
  • the driving method can be as shown in FIG. 2 to FIG. 5, and includes the following steps.
  • the control signal input terminal CK is at a low level
  • the first input terminal Vg(n-1) is at a high level
  • the second input terminal Vg(n+1) is at a low level.
  • the third transistor T3, the eighth transistor T8, the fourth transistor T4, and the twelfth transistor T12 are all turned off, and the sixth transistor T6 and the eleventh transistor T11 are turned on.
  • the low level of the low level input terminal VGL can enter the second pull-down node PD2 through the eleventh transistor T11, that is, enter the second pole of the thirteenth transistor T13 (the lower one pole in the figure), thereby making the first
  • the two poles of the thirteenth transistor T13 are respectively high level and low level, so the thirteenth transistor T13 is in a high resistance state (approximately regarded as "open circuit"), that is, the second pull-down node PD2 can be kept at a low level, thereby making the first
  • the fourteen transistor T14 is turned off, and the tenth transistor T10 and the seventeenth transistor T17 are turned off.
  • the eighth transistor T8 Since the eighth transistor T8 is turned off at this time, the first pull-down node PD1 has no input, is low level, and the sixteenth transistor T16 is turned off.
  • the gate of the second transistor T2 has no input, so that the second transistor T2 is turned off, and since the tenth transistor T10 is also turned off at this time, the pull-up node PU also has no signal.
  • the input which is low, turns off the fifteenth transistor T15.
  • the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are all turned off, so the output terminal Vg(n) outputs a low level (actually no output, but this can also be driven.
  • the transistor is turned off, and this phase is very short, so it can be regarded as low level).
  • the control signal input terminal CK is at a high level
  • the first input The terminal Vg(n-1) is at a high level
  • the second input terminal Vg(n+1) is at a low level.
  • control signal input terminal CK becomes a high level, so that the third transistor T3 and the eighth transistor T8 are turned off from on.
  • the state of the second pull-down node PD2 is the same as that of the previous stage, so the fourteenth transistor T14 is still turned off.
  • the sixth transistor T6 Since the sixth transistor T6 is turned on, the two transistors of the fifth transistor T5 are respectively at a high level and a low level, and enter a high resistance state, whereby the second pole of the fifth transistor T5 (the lower side of the figure) remains Low level, thereby turning off the seventh transistor T7. Therefore, although the eighth transistor T8 is turned on, no signal enters the first pull-down node PD1, the first pull-down node PD1 is still at a low level, and the ninth transistor T9 and the sixteenth transistor T16 remain turned off.
  • the point A in FIG. 1 is a high level; and since the third transistor T3 is turned on, the high level of the point A passes.
  • the third transistor T3 is transmitted to the gate of the second transistor T2 to turn on the second transistor T2, and the high level of the A point is transmitted to the pull-up node PU via the second transistor T2, so that the fifteenth transistor T15 is turned on. Therefore, the high level of the high level input terminal VGH is transmitted to the output terminal Vg(n), and the shift register outputs a high level.
  • the first pole of the storage capacitor Cst (the upper one pole in the figure) is the low level of the second input terminal Vg(n+1), so that a voltage difference is generated between the two poles, so that the storage capacitor Cst is charged.
  • control signal input terminal CK is at a low level, and the second input terminal Vg(n+1) is at a high level.
  • the third transistor T3 and the eighth transistor T8 are turned off, and the twelfth transistor T12 and the fourth transistor T4 are turned on. through.
  • the twelfth transistor T12 since the twelfth transistor T12 is turned on, the thirteenth transistor T13 is in a high resistance state, and the low level of the low level input terminal VGL is conducted to the second pulldown node PD2 through the twelfth transistor T12, resulting in the tenth
  • the four transistors T14 are turned off; at the same time, the tenth transistor T10 and the seventeenth transistor T17 are also turned off.
  • the eighth transistor T8 is turned off (the seventeenth transistor T17 is also turned off), so that there is no input at the first pull-down node PD1, which is low, causing the ninth transistor T9 and the sixteenth transistor T16 to be turned off. Therefore, the low level of the low level input terminal VGL cannot reach the output terminal Vg(n).
  • the third transistor T3 since the third transistor T3 is turned off, the second transistor T2 is turned off again, and the ninth transistor T9 and the tenth transistor T10 are also in an off state, so the pull-up node PU and The rest of the circuit is disconnected, so that the storage capacitor Cst cannot be discharged.
  • the input of the second input terminal Vg(n+1) changes from a low level to a high level, so the level of the pull-up node PU is further increased by the bootstrap action of the storage capacitor Cst, but in effect It is still at a high level, so that the fifteenth transistor T15 is turned on, the high level of the high level input terminal VGH enters the output terminal Vg(n), and the shift register outputs a high level.
  • the states of the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are independent of the first input terminal Vg(n-1), that is, regardless of the first input at this time.
  • the terminal Vg(n-1) is a low level as shown in FIG. 2, or is a high level as shown in FIG. 3, and the working state of the shift register is unchanged, and both can output a high level.
  • a pull-up stabilization phase is further included, which includes the first sub-phase And the second sub-phase.
  • the first input terminal Vg(n-1) and the second input terminal Vg(n+1) are both high levels; in the second sub-phase, the control signal input terminal CK is at a low level.
  • the first input terminal Vg(n-1) is at a low level, and the second input terminal Vg(n+1) is at a high level.
  • This step is divided into two sub-phases.
  • the first input terminal Vg(n-1) remains high, so the first input terminal Vg(n-1) and the second input terminal Vg(n+1) are both high levels.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the twelfth transistor T12 are all turned on.
  • the eleventh transistor T11 since the eleventh transistor T11 is turned on, the low level of the low-level input terminal VGL can be transmitted to the second pull-down node PD2 via the eleventh transistor T11, thereby making the tenth transistor T10, The fourteen transistor T14 and the seventeenth transistor T17 are turned off. Moreover, since the sixth transistor T6 is turned on, the fifteenth transistor T15 is in a high resistance state, and thus the gate of the seventh transistor T7 is at a low level, so that the seventh transistor T7 is turned off. Since the seventeenth transistor T17 is also turned off, the first pull-down node PD1 has no input, is low level, and the sixteenth transistor T16 is turned off. Since the fourteenth transistor T14 and the sixteenth transistor T16 are both turned off, the low level of the low level input terminal VGL cannot enter the output terminal Vg(n).
  • the second input terminal Vg(n+1) is still at a high level, so the twelfth transistor T12 is turned on, and the low level of the low-level input terminal VGL passes through the second pull-down node PD2.
  • the fourteenth transistor T14, the tenth transistor T10, and the seventeenth transistor T17 are turned off.
  • the low level of the control signal input terminal CK turns off the eighth transistor T8, so the first pull-down node PD1 has no input, and the sixteenth transistor T16 and the ninth transistor T9 are turned off.
  • the control signal input terminal CK is at a low level
  • the third transistor T3 is turned off
  • the second transistor T2 is turned off
  • the ninth transistor T9 and the tenth transistor T10 are also turned off, so the pull-up node PU has no input.
  • the fifteenth transistor T15 remains on, and the shift register outputs a high level.
  • the second sub-phase lasts for a period of 0.5 clock signals; at the same time, the first sub-phase lasts for a period of (N + 0.5) clock signals (N is a non-negative integer).
  • N is a non-negative integer.
  • the control signal input terminal CK is at a low level before the start of the first sub-phase (ie, step S103), and the control signal input terminal CK is also at a low level after the end thereof, so that it cannot continue the period of the entire clock signal.
  • the present pull-up stabilization phase lasts for a total of a whole number of cycles (eg, one, two, three, etc.) of the clock signal.
  • the signals of the first input terminal Vg(n-1), the output terminal Vg(n), and the second input terminal Vg(n+1) are simultaneously high level.
  • the signals of the three ports are the signals of three adjacent gate lines, so the time when they are simultaneously high level is the time when the gate lines overlap and turn on; thus, by adjusting the duration of this phase ( Or the number of consecutive clock signal cycles, it is possible to adjust the overlap ratio of the gate line conduction time.
  • the second input terminal Vg(n+1) is brought to a high level while the high level of the first input terminal Vg(n-1) is ended, and the control signal input terminal CK is turned on. If it is high level, then step S103 will directly enter step S105, and the high level time (ie, on-time) of two adjacent gate lines overlaps by 1/2.
  • the second input terminal Vg(n+1) is brought to a high level when the first input terminal Vg(n-1) is kept at a high level, and continues for two clocks.
  • the high-level time (ie, the on-time) of the adjacent two gate lines overlaps by 5/6, and correspondingly, for the entire gate drive circuit, there are six
  • the gate line is simultaneously high (conducting).
  • the above pull-stabilization phase is an example of the period of two clock signals, but if the phase is as shown in FIG. 4, only one cycle of the clock signal is continued, or as shown in FIG.
  • the period of the clock signal (in the figure, taking the period of three clock signals as an example) is also feasible, and it will respectively generate the corresponding overlap ratio of the gate line on-time. That is to say, as shown in FIG. 3 to FIG. 5, as long as the time of the first sub-phase in the pull-up stabilization phase is controlled (the second sub-phase must be a period of 0.5 clock signals), the gate line conduction time can be adjusted. Overlap ratio.
  • the shift register of this embodiment only needs to adjust the signal input to the first input terminal Vg(n-1) of the first stage shift register and adjust the clock signal (ie, input) without changing the circuit configuration.
  • the frequency of the signal of the control signal input terminal CK (that is, the number of cycles of the continuous clock signal adjusted in the pull-up stabilization phase) can change the overlap ratio of the on-time of each gate line, thereby flexibly adjusting
  • the function of the shift register is adapted to the needs of various display devices.
  • control signal input terminal CK is at a high level
  • first input terminal Vg(n-1) is at a low level
  • second input terminal Vg(n+1) is at a high level
  • the step is entered when the input signal of the control signal input terminal CK becomes a high level. .
  • the high level maintains a period of one or more clock signals (ie, a pull-up stabilization phase).
  • the first input terminal Vg(n-1) becomes a low level and the control signal input terminal CK simultaneously becomes a high level, and this step is entered.
  • the first transistor T1, the sixth transistor T6, and the eleventh transistor T11 are turned off, and the twelfth transistor T12, the fourth transistor T4, the third transistor T3, and the eighth crystal
  • the body tube T8 is turned on.
  • the sixth transistor T6 since the sixth transistor T6 is turned off, the fifth transistor T5 is no longer in a high resistance state, and the high level of the high level input terminal VGH can be transmitted to the gate of the seventh transistor T7 through the fifth transistor T5, so that The seventh transistor T7 is turned on; and since the eighth transistor T8 is also turned on, the high level of the second input terminal Vg(n+1) can be transmitted to the first pull-down node via the seventh transistor T7 and the eighth transistor T8.
  • PD1 turns on the ninth transistor T9 and the sixteenth transistor T16.
  • the turn-on of the sixteenth transistor T16 causes the low level of the low-level input terminal VGL to pass through the output terminal Vg(n) thereof, so that the output of the shift register is changed to the low level again, that is, the shift register is The output is pulled low.
  • the twelfth transistor T12 since the twelfth transistor T12 is turned on, the low level of the low level input terminal VGL is transmitted to the second pull-down node PD2 through the twelfth transistor T12, so that the tenth transistor T10, the seventeenth transistor T17, and the tenth The four transistor T14 is turned off.
  • the ninth transistor T9 since the ninth transistor T9 is turned on, the low level of the low level input terminal VGL is transmitted to the pull-up node PU through it, so that the pull-up node PU discharges and becomes a low level, and then the fifteenth transistor T15 Shutdown, the high level input VGH high level can not continue to output.
  • the first input terminal Vg(n-1) and the second input terminal Vg(n+1) are both low levels.
  • the first transistor T1, the sixth transistor T6, the eleventh transistor T11, the fourth transistor T4, and the twelfth transistor T12 are turned off.
  • the thirteenth transistor T13 is stably turned on, and the high level of the high level input terminal VGH is transmitted to the second pull-down node PD2, so that the fourteenth transistor T14, tenth The seven transistors T17 and the tenth transistor T10 are turned on, so that the low level of the low level input terminal VGL is transmitted to the output terminal Vg(n) through the fourteenth transistor T14, and the shift register continues to output a low level.
  • the low level of the low level input terminal VGL is transmitted to the first pull-down node PD1 via the seventeenth transistor T17, so that the sixteenth transistor T16 and the ninth transistor T9 are turned off.
  • the tenth transistor T10 Since the tenth transistor T10 is turned on, the low level of the low level input terminal VGL can be transmitted to the pull-up node PU through the tenth transistor T10, so that the fifteenth transistor T15 is stably turned off. Moreover, since the second input terminal Vg(n+1) is also at a low level at this time, the levels of the two poles of the storage capacitor Cst are the same, and the discharge is completed, and the charge is no longer stored.
  • the first transistor T1 since the first input terminal Vg(n-1) is at a low level, the first transistor T1 is turned off, and the fourth transistor T4 is also subjected to the low level of the second input terminal Vg(n+1).
  • the control is turned off, so the A point must be kept low (no input), so regardless of the control signal input terminal CK
  • the level of the second transistor T2 remains off and the PU level of the pull-up node is unaffected.
  • the signal of CK will also affect T8, but since Vg(n+1) is low at this time, regardless of the state of T8, or whether the low level of Vg(n+1) can be transmitted to
  • the first pull-down node PD1 the first pull-down node PD1 always maintains a low state, and the sixteenth transistor T16 is always turned off.
  • the shift register enters the pull-down stabilization phase.
  • the first input terminal Vg(n-1) and the second input terminal Vg(n+1) both maintain a low level input, and at the same time, regardless of the level of the control signal input terminal CK, the shift The register is stable and outputs low level; until the next frame, as the previous shift register starts to output high level, the signal of the first input terminal Vg(n-1) of the shift register of this stage is again Going high, the shift register re-enters the preparation phase and begins work on a new cycle.
  • the embodiment provides a gate driving circuit, including:
  • each shift register is used to connect a gate line, and a first input of each stage shift register is connected to a shift register of a previous stage At the output end, the second input of each stage shift register is connected to the output of the next stage shift register.
  • each shift register in the gate driving circuit, the first input of each shift register is connected to the output of the shift register of the first stage, and the second input is connected to the output of the shift register of the next stage;
  • the output of each shift register still has to be connected to a gate line.
  • the first stage shift register since it has no upper level, its first input terminal can be connected to a separate input signal, and for the last stage shift register, there is no next stage, so the second The input can also be connected to a separate input signal (or to the output of the first stage shift register).
  • a control signal input terminal of one shift register is connected to the first clock signal, and a control signal input end of the other shift register is connected to the second clock signal, the first The clock signal and the second clock signal are inverted.
  • FIG. 6 the case of single-sided driving is shown in FIG. 6, that is, a gate driving circuit is provided only on one side of each gate line.
  • the above-mentioned gate driving circuits may be respectively disposed on both sides of each gate line, and a shift register is connected to both ends of each gate line (and the two shifts)
  • the bit register is synchronized, or "same level", so that the drive signal can be input simultaneously from both ends of the gate line, which helps to reduce signal delay and improve load capacity.

Abstract

一种移位寄存器及其驱动方法、栅极驱动电路，其可解决现有的栅极驱动电路不能改变栅线导通时间重叠比例的问题。移位寄存器包括：输入单元，其用于控制第一输入端的信号是否输入充电单元；充电单元，其用于对上拉节点（PU）充电；上拉单元用于维持上拉节点（PU）的高电平；高电平输出单元，其用于根据上拉节点（PU）的电平控制高电平是否输出到输出端；下拉单元，其用于将上拉节点（PU）的电平拉低并向输出端输出低电平；低电平输出单元，其用于向输出端输出低电平。栅极驱动电路由多个上述移位寄存器级联而成。

Description

移位寄存器及其驱动方法、栅极驱动电路 技术领域
本公开涉及栅极驱动技术领域，具体涉及一种移位寄存器及其驱动方法、栅极驱动电路。
背景技术
在液晶显示装置、有机发光二极管(OLED)显示装置等的阵列基板中，各条栅线可由栅极驱动电路(GOA)控制。栅极驱动电路包括多个级联的移位寄存器，其中，每级移位寄存器的输出端连接一条栅线，且还连接其下一级移位寄存器，故其可在为栅线提供高电平的导通信号的同时为下一级移位寄存器提供触发信号。这样，通过少数几个控制信号即可实现对多条栅线的驱动。
随着显示面板尺寸、分辨率、刷新率的提高，阵列基板中的栅线越来越长，由电阻导致的信号延迟也越来越大；同时，每条栅线的导通时间(例如为高电平的时间)也越来越短。这导致在一条栅线的导通时间内，其所连接的各像素可能无法被充分充电，并由此引发残影等显示不良。
为解决以上问题，人们提出了使栅线的导通时间重叠的技术，即在一条栅线的保持导通时，就有其他栅线开始导通，从而在对该栅线所连接的像素进行充电时，其他栅线所连接的像素会先进行“预充电”，这样可达到更好的充电效果。
显然，当显示面板的分辨率、刷新率等不同时，其所需的栅线导通时间的重叠比例也不同(例如两条相邻栅线的导通时间有1/2或2/3重叠)。但对于现有的栅极驱动电路，在其电路结构(如级联关系)不变的情况下，无法通过对控制信号的简单调整实现改变栅线导通时间重叠比例的目的，因此其应用效果受到限制。
发明内容
本公开提供一种可简单的调整栅线导通时间重叠比例的移位寄存器及其驱动方法、栅极驱动电路，以至少部分地缓解或消除以上提到的问题。
根据本公开的第一方面，提供了一种移位寄存器，包括输入单元、充电单元、上拉单元、高电平输出单元、下拉单元、低电平输出单元，其中，
输入单元连接在第一输入端和充电单元之间，其控制第一输入端的信号是否输入充电单元；
充电单元连接低电平输入端、第二输入端、控制信号输入端、上拉节点，用于对上拉节点充电；
上拉单元连接在第二输入端和上拉节点间，用于维持上拉节点的高电平；
高电平输出单元连接高电平输入端、输出端、上拉节点，用于根据上拉节点的电平控制高电平是否输出到输出端；
下拉单元连接低电平输入端、高电平输入端、控制信号输入端、第一输入端、第二输入端、输出端、上拉节点、低电平输出单元，用于将上拉节点的电平拉低并向输出端输出低电平；
低电平输出单元连接低电平输入端、高电平输入端、第一输入端、第二输入端、输出端、上拉节点、下拉单元，用于向输出端输出低电平。
根据一个实施例，所述输入单元可以包括第一晶体管，其栅极和第一极连接第一输入端，第二极连接充电单元。
根据另一实施例，所述充电单元可以包括第二晶体管、第三晶体管、第四晶体管，其中，
所述第二晶体管的栅极连接第三晶体管的第二极，第一极连接第一晶体管的第二极，第二极连接上拉节点；
所述第三晶体管的栅极连接控制信号输入端，第一极连接第一晶体管的第二极；
所述第四晶体管的栅极连接第二输入端，第一极连接第一晶体管的第二极，第二极连接低电平输入端。
根据又一实施例，所述上拉单元可以包括存储电容，其第一极连接第二输入端，第二极连接上拉节点。
根据再一实施例，所述高电平输出单元可以包括第十五晶体管，其栅极连接上拉节点，第一极连接高电平输入端，第二极连接输出端。
根据实施例，所述下拉单元可以包括第五晶体管、第六晶体管、 第七晶体管、第八晶体管、第九晶体管、第十六晶体管、第十七晶体管，其中，
所述五晶体管的栅极和第一极连接高电平输入端，第二极连接第七晶体管的栅极；
所述第六晶体管的栅极连接第一输入端，第一极连接第七晶体管的栅极，第二极连接低电平输入端；
所述第七晶体管的第一极连接第二输入端，第二极连接第八晶体管的第一极；
所述第八晶体管的栅极连接控制信号输入端，第二极连接第一下拉节点；
所述第九晶体管的栅极连接第一下拉节点，第一极连接上拉节点，第二极连接低电平输入端；
所述第十六晶体管的栅极连接第一下拉节点，第一极连接输出端，第二极连接低电平输入端；
所述第十七晶体管的栅极连接低电平输出单元，第一极连接第一下拉节点，第二极连接低电平输入端。
根据另一实施例，所述低电平输出单元可以包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管，其中，
所述第十晶体管的栅极连接第二下拉节点，第一极连接上拉节点，第二极连接低电平输入端；
所述第十一晶体管的栅极连接第一输入端，第一极连接第二下拉节点，第二极连接低电平输入端；
所述第十二晶体管的栅极连接第二输入端，第一极连接第二下拉节点，第二极连接低电平输入端；
所述第十三晶体管的栅极和第一极连接高电平输入端，第二极连接第二下拉节点；
所述第十四晶体管的栅极连接第二下拉节点，第一极连接输出端，第二极连接低电平输入端；
并且其中，
所述下拉单元的第十七晶体管的栅极连接至所述低电平输出单元的第二下拉节点。
根据又一实施例，所述第一晶体管、第二晶体管、第三晶体管、 第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管均为N型晶体管。
本公开的第二方面提供了一种移位寄存器的驱动方法，其中，所述移位寄存器为根据本公开的第一方面的移位寄存器，所述移位寄存器的驱动方法包括：
准备阶段：使高电平输出单元、下拉单元、低电平输出单元均关断，从而使输出端输出低电平；
充电阶段：使输入单元为上拉单元充电，高电平输出单元导通，从而使输出端输出高电平；
上拉阶段：使上拉单元继续充电，高电平输出单元导通，从而使输出端输出高电平；
下拉阶段：使下拉单元导通并对上拉单元放电，从而使输出端输出低电平；
下拉稳定阶段：使下拉稳定单元导通，从而使输出端输出低电平。
根据实施例，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管均为N型晶体管，所述移位寄存器的驱动方法包括：
准备阶段：控制信号输入端输入低电平，第一输入端输入高电平，第二输入端输入低电平；
充电阶段：控制信号输入端输入高电平，第一输入端输入高电平，第二输入端输入低电平；
上拉阶段：控制信号输入端输入低电平，第二输入端输入高电平；
下拉阶段：控制信号输入端输入高电平，第一输入端输入低电平，第二输入端输入高电平；
下拉稳定阶段：第一输入端和第二输入端均输入低电平。
根据另一实施例，所述上拉阶段中第一输入端输入高电平，且在上拉阶段和下拉阶段之间，还包括上拉稳定阶段，其包括第一子阶段和第二子阶段，其中：第一子阶段：第一输入端和第二输入端均输入 高电平；第二子阶段：控制信号输入端输入低电平，第一输入端输入低电平，第二输入端输入高电平。
本公开的第三方面提供了一种栅极驱动电路，包括：
多个级联的根据本公开的第一方面的移位寄存器，每个移位寄存器的输出端用于连接一条栅线；其中，每级移位寄存器的第一输入端连接上一级移位寄存器的输出端，每级移位寄存器的第二输入端连接下一级移位寄存器的输出端。
根据实施例，对于任意两级相邻的移位寄存器，其中一个移位寄存器的控制信号输入端连接第一时钟信号，另一个移位寄存器的控制信号输入端连接第二时钟信号，所述第一时钟信号和第二时钟信号是反相的。
在本公开的移位寄存器中，通过控制第一输入端和第二输入端的信号可调整其输出的高电平(导通)时间；当用该移位寄存器组成栅极驱动电路时，由于其两个输入端的信号就是其上下两级移位寄存器的输出，故每级移位寄存器的高电平(导通)时间均与其上下两级移位寄存器的高电平(导通)时间相关。因此，只要调整输入第一级移位寄存器的信号，就能改变各条栅线导通时间的重叠比例，从而使栅极驱动电路的功能更加灵活，并且能适应各种不同显示装置的需要。
附图说明
图1为根据本公开的实施例的一种移位寄存器的电路结构示意图；
图2为根据本公开的实施例的移位寄存器的信号驱动时序图；
图3为根据本公开的实施例的移位寄存器的另一种信号驱动时序图；
图4为根据本公开的实施例的移位寄存器的又一种信号驱动时序图；
图5为根据本公开的实施例的移位寄存器的再一种信号驱动时序图；
图6为根据本公开的实施例的栅极驱动电路中的移位寄存器的级联关系示意图；
其中，附图标记为：T1、第一晶体管；T2、第二晶体管；T3、第三晶体管；T4、第四晶体管；T5、第五晶体管；T6、第六晶体管；T7、 第七晶体管；T8、第八晶体管；T9、第九晶体管；T10、第十晶体管；T11、第十一晶体管；T12、第十二晶体管；T13、第十三晶体管；T14、第十四晶体管；T15、第十五晶体管；T16、第十六晶体管；T17、第十七晶体管；Cst、存储电容；Vg(n-1)、第一输入端；Vg(n)、输出端；Vg(n+1)、第二输入端；CK、控制信号输入端；PU、上拉节点；PD1、第一下拉节点；PD2、第二下拉节点；VGL、低电平输入端；VGH、高电平输入端。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
本公开的实施例提供一种移位寄存器，包括输入单元、充电单元、上拉单元、高电平输出单元、下拉单元、低电平输出单元，其中，
输入单元连接在第一输入端和充电单元之间，其控制第一输入端的信号是否输入充电单元；
充电单元连接低电平输入端、第二输入端、控制信号输入端、上拉节点，用于对上拉节点充电；
上拉单元连接在第二输入端和上拉节点间，用于维持上拉节点的高电平；
高电平输出单元连接高电平输入端、输出端、上拉节点，用于根据上拉节点的电平控制高电平是否输出到输出端；
下拉单元连接低电平输入端、高电平输入端、控制信号输入端、第一输入端、第二输入端、输出端、上拉节点、低电平输出单元，用于将上拉节点的电平拉低并向输出端输出低电平；
低电平输出单元连接低电平输入端、高电平输入端、第一输入端、第二输入端、输出端、上拉节点、下拉单元，用于向输出端输出低电平。
当多个本实施例的移位寄存器级联组成栅极驱动电路时，每级移位寄存器的第一输入端连接其上一级移位寄存器的输出端，而第二输入端连接其下一级移位寄存器的输出端。也就是说，对于每级移位寄存器，其同时受到上下两级移位寄存器的控制，并同时对上下两级移位寄存器进行控制。
在本实施例的移位寄存器中，通过控制第一输入端和第二输入端的信号可调整其输出的高电平(导通)时间；当用该移位寄存器组成栅极驱动电路时，由于其两输入端的信号也就是其上下两级移位寄存器的输出，故每级移位寄存器的高电平(导通)时间均与其上下两级移位寄存器的高电平(导通)时间相关。因此，只要调整输入第一级移位寄存器的信号，就能改变各条栅线导通时间的重叠比例，从而使栅极驱动电路的功能更加灵活，并且能适应各种不同显示装置的需要。
如图1至图6所示，下面对本实施例的移位寄存器的具体结构进行更详细的介绍。
如图1所示，输入单元包括第一晶体管T1，其栅极和第一极连接第一输入端Vg(n-1)(其连接上一级移位寄存器的输出端)，第二极连接充电单元。
根据示例，充电单元包括第二晶体管T2、第三晶体管T3、第四晶体管T4，其中：
第二晶体管T2的栅极连接第三晶体管T3的第二极，第一极连接第一晶体管T1的第二极，第二极连接上拉节点PU；
第三晶体管T3的栅极连接控制信号输入端CK，第一极连接第一晶体管T1的第二极；
第四晶体管T4的栅极连接第二输入端Vg(n+1)(其连接下一级移位寄存器的输出端)，第一极连接第一晶体管T1的第二极，第二极连接低电平输入端VGL。
根据示例，上拉单元包括存储电容Cst，其第一极连接第二输入端Vg(n+1)，第二极连接上拉节点PU。
根据示例，高电平输出单元包括第十五晶体管T15，其栅极连接上拉节点PU，第一极连接高电平输入端VGH，第二极连接输出端Vg(n)。
根据示例，下拉单元包括第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十六晶体管T16、第十七晶体管T17，其中：
第五晶体管的栅极和第一极连接高电平输入端VGH，第二极连接第七晶体管T7的栅极；
第六晶体管T6的栅极连接第一输入端Vg(n-1)，第一极连接第七晶体管T7的栅极，第二极连接低电平输入端VGL；
第七晶体管T7的第一极连接第二输入端Vg(n+1)，第二极连接第八晶体管T8的第一极；
第八晶体管T8的栅极连接控制信号输入端CK，第二极连接第一下拉节点PD1；
第九晶体管T9的栅极连接第一下拉节点PD1，第一极连接上拉节点PU，第二极连接低电平输入端VGL；
第十六晶体管T16的栅极连接第一下拉节点PD1，第一极连接输出端Vg(n)，第二极连接低电平输入端VGL；
第十七晶体管T17的栅极连接低电平输出单元，第一极连接第一下拉节点PD1，第二极连接低电平输入端VGL。
根据示例，低电平输出单元包括第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14，其中：
第十晶体管T10的栅极连接第二下拉节点PD2，第一极连接上拉节点PU，第二极连接低电平输入端VGL；
第十一晶体管T11的栅极连接第一输入端Vg(n-1)，第一极连接第二下拉节点PD2，第二极连接低电平输入端VGL；
第十二晶体管T12的栅极连接第二输入端Vg(n+1)，第一极连接第二下拉节点PD2，第二极连接低电平输入端VGL；
第十三晶体管T13的栅极和第一极连接高电平输入端VGH，第二极连接第二下拉节点PD2；
第十四晶体管T14的栅极连接第二下拉节点PD2，第一极连接输出端Vg(n)，第二极连接低电平输入端VGL；
并且其中
下拉单元的第十七晶体管T17的栅极连接至低电平输出单元的第二下拉节点PD2。
根据示例，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17均可以为N型晶体管。
本公开的实施例还提供一种上述移位寄存器的驱动方法，包括：
准备阶段：使高电平输出单元、下拉单元、低电平输出单元均关断，从而使输出端Vg(n)输出低电平；
充电阶段：使输入单元为上拉单元充电，高电平输出单元导通，从而使输出端Vg(n)输出高电平；
上拉阶段：使上拉单元继续充电，高电平输出单元导通，从而使输出端Vg(n)输出高电平；
下拉阶段：使下拉单元导通并对上拉单元放电，从而使输出端Vg(n)输出低电平；
下拉稳定阶段：使下拉稳定单元导通，从而使输出端Vg(n)输出低电平。
具体的，对于图1所示的上述移位寄存器，其驱动方法可如图2至图5所示，包括以下的步骤。
在S101处的准备阶段，控制信号输入端CK为低电平，第一输入端Vg(n-1)为高电平，第二输入端Vg(n+1)为低电平。
在本阶段中，第三晶体管T3、第八晶体管T8、第四晶体管T4、第十二晶体管T12均关断，而第六晶体管T6、第十一晶体管T11则导通。
可见，低电平输入端VGL的低电平可经过第十一晶体管T11进入第二下拉节点PD2，也就是进入第十三晶体管T13的第二极(图中下侧一极)，从而使第十三晶体管T13的两极分别为高电平和低电平，故第十三晶体管T13处于高阻状态(可近似看成“断路”)，即第二下拉节点PD2可保持低电平，从而使第十四晶体管T14关断，同时使第十晶体管T10、第十七晶体管T17关断。
由于此时第八晶体管T8关断，故第一下拉节点PD1无输入，为低电平，第十六晶体管T16关断。
同时，由于第三晶体管T3关断，故第二晶体管T2的栅极无输入，使第二晶体管T2关断，又由于第十晶体管T10此时也是关断的，故上拉节点PU也无信号输入，其为低电平，使第十五晶体管T15关断。
可见，此时第十四晶体管T14、第十五晶体管T15、第十六晶体管T16都关断，故输出端Vg(n)输出低电平(实际为无输出，但这也可使其驱动的晶体管关断，且本阶段时间很短，故可视为低电平)。
在S102处的充电阶段，控制信号输入端CK为高电平，第一输入 端Vg(n-1)为高电平，第二输入端Vg(n+1)为低电平。
在本阶段中，控制信号输入端CK变为高电平，故第三晶体管T3、第八晶体管T8由关断变为导通。
此时，第二下拉节点PD2的状态与前一阶段相同，故第十四晶体管T14仍关断。
由于第六晶体管T6是导通的，故第五晶体管T5两极分别为高电平和低电平，其进入高阻状态，由此第五晶体管T5的第二极(图中下侧一极)保持低电平，从而使第七晶体管T7关断。因此虽然第八晶体管T8导通，但仍无信号进入第一下拉节点PD1，第一下拉节点PD1仍为低电平，第九晶体管T9、第十六晶体管T16保持关断。
同时，由于第四晶体管T4保持关断，而第一晶体管T1处于导通状态，因此图1中的A点为高电平；又由于第三晶体管T3导通，故A点的高电平经过第三晶体管T3传入第二晶体管T2的栅极，使第二晶体管T2导通，进而A点的高电平经第二晶体管T2传入上拉节点PU，使第十五晶体管T15导通，从而将高电平输入端VGH的高电平传至到输出端Vg(n)，移位寄存器输出高电平。另外，此时存储电容Cst的第一极(图中上侧一极)为第二输入端Vg(n+1)的低电平，故其两极间产生电压差，使得存储电容Cst被充电。
在S103处的上拉阶段，控制信号输入端CK为低电平，第二输入端Vg(n+1)为高电平。
在本阶段中，根据控制信号输入端CK和第二输入端Vg(n+1)的状态可知，第三晶体管T3、第八晶体管T8关断，而第十二晶体管T12、第四晶体管T4导通。
此时，由于第十二晶体管T12导通，故第十三晶体管T13处于高阻状态，低电平输入端VGL的低电平经过第十二晶体管T12传导到第二下拉节点PD2，导致第十四晶体管T14关断；同时，第十晶体管T10、第十七晶体管T17也关断。而且，第八晶体管T8关断(第十七晶体管T17也关断)，故第一下拉节点PD1处无输入，为低电平，导致第九晶体管T9和第十六晶体管T16关断。因此，低电平输入端VGL的低电平不能达到输出端Vg(n)。
同时，由于第三晶体管T3关断，故第二晶体管T2再次关断，而第九晶体管T9、第十晶体管T10也处于关断状态，故上拉节点PU与 电路其他部分断开，使得存储电容Cst无法放电。而此时第二输入端Vg(n+1)的输入从低电平变为高电平，故依靠存储电容Cst的自举作用，上拉节点PU的电平进一步升高，但在作用上仍是高电平，从而使第十五晶体管T15导通，高电平输入端VGH的高电平进入输出端Vg(n)，移位寄存器输出高电平。
可见，在本阶段中，第十四晶体管T14、第十五晶体管T15、第十六晶体管T16的状态均与第一输入端Vg(n-1)无关，也就是说，此时不论第一输入端Vg(n-1)是如图2所示为低电平，还是如图3所示为高电平，移位寄存器的工作状态均不变，都可输出高电平。
根据示例，在可选的S104处，如图3所示，若上拉阶段中第一输入端Vg(n-1)为高电平，则还包括上拉稳定阶段，其包括第一子阶段和第二子阶段。在第一子阶段中第一输入端Vg(n-1)和第二输入端Vg(n+1)均为高电平；在第二子阶段中，控制信号输入端CK为低电平，第一输入端Vg(n-1)为低电平，第二输入端Vg(n+1)为高电平。
也就是说，作为本实施例的一种情况，如图2所示，若在上拉阶段中第一输入端Vg(n-1)已经变为低电平，则跳过本步骤，直接进入以下的S105步骤。
或者，作为本实施例的另一种情况，如图3至图5所示，若在上拉阶段中第一输入端Vg(n-1)仍保持高电平，则进入本步骤。
而本步骤又分为两个子阶段。在第一子阶段中，第一输入端Vg(n-1)仍保持高电平，故第一输入端Vg(n-1)和第二输入端Vg(n+1)均为高电平，由此第四晶体管T4、第六晶体管T6、第十一晶体管T11、第十二晶体管T12均导通。
在第一子阶段中，由于第十一晶体管T11导通，故低电平输入端VGL的低电平可经第十一晶体管T11传至第二下拉节点PD2，从而使第十晶体管T10、第十四晶体管T14、第十七晶体管T17关断。而且，由于第六晶体管T6导通，故第十五晶体管T15处于高阻状态，因而第七晶体管T7栅极为低电平，使得第七晶体管T7关断。由于第十七晶体管T17也是关断的，故第一下拉节点PD1无输入，为低电平，第十六晶体管T16关断。由于第十四晶体管T14和第十六晶体管T16均关断，故低电平输入端VGL的低电平无法进入输出端Vg(n)。
同时，由于第四晶体管T4导通，且第一输入端Vg(n-1)为高电平， 故第一晶体管T1处于高阻状态。由此图1中A点保持低电平。这样，当控制信号输入端CK为高电平并使第三晶体管T3导通时，A点低电平经第三晶体管T3传至第二晶体管T2栅极，使第二晶体管T2关断；当控制信号输入端CK为低电平并使第三晶体管T3关断时，第二晶体管T2栅极无输入，同样关断；此外，因为第十晶体管T10也是关断的，故上拉节点PU始终无输入，存储电容Cst无法放电，上拉节点PU一直通过存储电容Cst的作用保持高电平，使第十五晶体管T15持续导通，移位寄存器输出高电平。可见，在此阶段中，不论控制信号输入端CK的电平如何，移位寄存器都保持稳定的高电平输出。
当第一子阶段持续一定时间后，在第一输入端Vg(n+1)保持高电平的情况下，第一输入端Vg(n-1)变为低电平，且此时的控制信号输入端CK正好为低电平，从而进入第二子阶段。
在第二子阶段中，第二输入端Vg(n+1)仍为高电平，故第十二晶体管T12导通，低电平输入端VGL的低电平经其进入第二下拉节点PD2，使第十四晶体管T14、第十晶体管T10、第十七晶体管T17关断。而控制信号输入端CK的低电平使第八晶体管T8关断，故第一下拉节点PD1无输入，第十六晶体管T16、第九晶体管T9关断。
同时，控制信号输入端CK为低电平还使第三晶体管T3关断，进而第二晶体管T2关断，而第九晶体管T9、第十晶体管T10也是关断的，故上拉节点PU无输入，仍保持高电平，第十五晶体管T15保持导通，移位寄存器输出高电平。
可见，在本阶段中，第二子阶段持续0.5个时钟信号的周期；同时，第一子阶段持续(N+0.5)个时钟信号的周期(N为非负整数)。这是因为第一子阶段开始前(即S103步骤)控制信号输入端CK为低电平，而其结束后控制信号输入端CK也为低电平，故其不能持续整个时钟信号的周期。由此，本上拉稳定阶段总共持续整数个(如一个、两个、三个等)时钟信号的周期。
可见，如图3所示，在第一子阶段中，第一输入端Vg(n-1)、输出端Vg(n)、第二输入端Vg(n+1)的信号同时为高电平。如前所述，这三个端口的信号就是三条相邻栅线的信号，故它们同时为高电平的时间也就是栅线重叠导通的时间；由此，通过调整本阶段持续的时间(或者说持续的时钟信号周期的个数)，也就可调整栅线导通时间的重叠比例。
例如，如图2所示，在第一输入端Vg(n-1)的高电平结束的同时使第二输入端Vg(n+1)变为高电平，并使控制信号输入端CK为高电平，则S103步骤后会直接进入S105步骤，相邻的两条栅线的高电平时间(即导通时间)有1/2相互重叠。
再如，如图3所示，在第一输入端Vg(n-1)保持高电平的情况下使第二输入端Vg(n+1)变为高电平，并在持续两个时钟信号的周期的上拉稳定阶段期间持续，则相邻的两条栅线的高电平时间(即导通时间)有5/6相互重叠，相应的，对于整个栅极驱动电路，会有六条栅线同时为高电平(导通)。
在图3中，以上拉稳定阶段为两个时钟信号的周期为例进行说明，但若该阶段如图4所示，仅持续一个时钟信号的周期，或如图5所示，持续更多个时钟信号的周期(图中以三个时钟信号的周期为例)，也是可行的，且其会分别产生相应的栅线导通时间重叠比例。也就是说，如图3至图5所示，只要控制上拉稳定阶段中第一子阶段的时间(第二子阶段必然为0.5个时钟信号的周期)，即可调整栅线导通时间的重叠比例。
由此可见，本实施例的移位寄存器在不改变电路结构的情况下，只要调整输入第一级移位寄存器的第一输入端Vg(n-1)的信号，以及调整时钟信号(即输入控制信号输入端CK的信号)的频率(也就相当于调整了上拉稳定阶段的持续的时钟信号的周期个数)，即可改变各条栅线导通时间的重叠比例，从而灵活的调整移位寄存器的功能，适应各种不同显示装置的需要。
在S105的下拉阶段，控制信号输入端CK为高电平，第一输入端Vg(n-1)为低电平，第二输入端Vg(n+1)为高电平。
如前所述，如图2所示，若在上拉阶段中第一输入端Vg(n-1)为低电平，则当控制信号输入端CK的输入信号变为高电平时进入本步骤。
相反，如图3所示，若在上拉阶段中第一输入端Vg(n-1)为高电平，则该高电平会保持一个或多个时钟信号的周期(即上拉稳定阶段)。之后第一输入端Vg(n-1)变为低电平且控制信号输入端CK同时变为高电平，进入本步骤。
在本阶段中，第一晶体管T1、第六晶体管T6、第十一晶体管T11关断，而第十二晶体管T12、第四晶体管T4、第三晶体管T3、第八晶 体管T8导通。
此时，由于第六晶体管T6关断，故第五晶体管T5不再处于高阻状态，高电平输入端VGH的高电平可经过第五晶体管T5传至第七晶体管T7栅极，使第七晶体管T7导通；又由于第八晶体管T8也是导通的，故第二输入端Vg(n+1)的高电平可经第七晶体管T7和第八晶体管T8传入第一下拉节点PD1，使第九晶体管T9和第十六晶体管T16导通。其中，第十六晶体管T16的导通使低电平输入端VGL的低电平通过其传入输出端Vg(n)，使移位寄存器的输出重新变为低电平，即将移位寄存器的输出“拉低”。另外，由于第十二晶体管T12导通，故低电平输入端VGL的低电平经过第十二晶体管T12传入第二下拉节点PD2，使第十晶体管T10、第十七晶体管T17、第十四晶体管T14关断。
同时，由于第九晶体管T9导通，故低电平输入端VGL的低电平通过其传入上拉节点PU，使上拉节点PU处放电并变为低电平，进而第十五晶体管T15关断，高电平输入端VGH的高电平不能继续输出。
在S106处的下拉稳定阶段，第一输入端Vg(n-1)和第二输入端Vg(n+1)均为低电平。
在本阶段中，第一晶体管T1、第六晶体管T6、第十一晶体管T11、第四晶体管T4、第十二晶体管T12关断。
此时，由于第十二晶体管T12关断，故第十三晶体管T13稳定导通，将高电平输入端VGH的高电平传入第二下拉节点PD2，使第十四晶体管T14、第十七晶体管T17、第十晶体管T10导通，从而使得低电平输入端VGL的低电平通过第十四晶体管T14传至输出端Vg(n)，移位寄存器持续输出低电平。同时，低电平输入端VGL的低电平经第十七晶体管T17传至第一下拉节点PD1，使第十六晶体管T16、第九晶体管T9关断。
由于第十晶体管T10导通，故低电平输入端VGL的低电平可通过第十晶体管T10传至上拉节点PU，使第十五晶体管T15稳定关断。又由于此时第二输入端Vg(n+1)也为低电平，故存储电容Cst两极的电平相同，其完成放电，不再存储电荷。
在本阶段中，由于第一输入端Vg(n-1)为低电平，故第一晶体管T1关断，同时第四晶体管T4也受第二输入端Vg(n+1)的低电平的控制而关断，故A点必然保持低电平(无输入)，故无论控制信号输入端CK的 电平如何，第二晶体管T2都保持关断，上拉节点PU电平不受影响。同时，CK的信号还会对T8产生影响，但由于此时Vg(n+1)为低电平，故不论T8状态如何，或者说不论Vg(n+1)的低电平是否能传至第一下拉节点PD1，第一下拉节点PD1都始终保持低电平状态，第十六晶体管T16始终关断。
由此可见，在下拉阶段之后，当第二输入端Vg(n+1)变为低电平时，移位寄存器进入下拉稳定阶段。在此阶段中，第一输入端Vg(n-1)和第二输入端Vg(n+1)均保持低电平的输入，同时，不论控制信号输入端CK的电平如何变化，移位寄存器都稳定的输出低电平；直到下一帧画面时，随着上一级移位寄存器开始输出高电平，即本级移位寄存器的第一输入端Vg(n-1)的信号再次变为高电平，移位寄存器重新进入准备阶段，并且开始新一个周期的工作。
如图6所示，本实施例提供一种栅极驱动电路，包括：
多个级联的根据上述实施例的移位寄存器，其中，每个移位寄存器的输出端用于连接一条栅线，同时每级移位寄存器的第一输入端连接上一级移位寄存器的输出端，每级移位寄存器的第二输入端连接下一级移位寄存器的输出端。
也就是说，在栅极驱动电路中，每个移位寄存器的第一输入端均连接上一级移位寄存器的输出端，而第二输入端则连接下一级移位寄存器的输出端；当然，每个移位寄存器的输出端仍要连接一条栅线。
应当理解，对于第一级移位寄存器，由于其没有上一级，故其第一输入端可以连接单独的输入信号，而对于最后一级移位寄存器，其没有下一级，故其第二输入端也可连接单独的输入信号(或连接第一级移位寄存器的输出端)。
根据示例，对于任意两级相邻的移位寄存器，其中一个移位寄存器的控制信号输入端连接第一时钟信号，另一个移位寄存器的控制信号输入端连接第二时钟信号，所述第一时钟信号和第二时钟信号是反相的。
如前所述，从图2、图3可见，由于相邻两级移位寄存器的工作状态相差1/2个时钟信号周期，因此，可设置两个正好相位相反(即相差1/2个时钟信号周期)的时钟信号，并用它们依次轮流控制各移位寄存器，这样即可用最少的控制线实现对栅极驱动电路的控制。
具体的，在图6中示出的是单边驱动的情况，即仅在各条栅线的一侧设有栅极驱动电路。但是，若采用双边驱动的方式也是可行的，即可在各条栅线的两侧分别设置上述的栅极驱动电路，每条栅线的两端均连接一个移位寄存器(且这两个移位寄存器的工作同步，或者说“同级”)，从而使驱动信号可从栅线的两端同时输入，这样有利于降低信号延迟，提高负载能力。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (14)

  1. 一种移位寄存器，包括输入单元、充电单元、上拉单元、高电平输出单元、下拉单元、低电平输出单元，其中，
    所述输入单元连接在第一输入端和所述充电单元之间，其控制所述第一输入端的信号是否输入所述充电单元；
    所述充电单元连接低电平输入端、第二输入端、控制信号输入端、上拉节点，用于对所述上拉节点充电；
    所述上拉单元连接在所述第二输入端和所述上拉节点间，用于维持所述上拉节点的高电平；
    所述高电平输出单元连接高电平输入端、输出端、所述上拉节点，用于根据所述上拉节点的电平控制高电平是否输出到所述输出端；
    所述下拉单元连接所述低电平输入端、所述高电平输入端、控制信号输入端、所述第一输入端、所述第二输入端、所述输出端、所述上拉节点、所述低电平输出单元，用于将所述上拉节点的电平拉低并向所述输出端输出低电平；
    所述低电平输出单元连接所述低电平输入端、所述高电平输入端、所述第一输入端、所述第二输入端、所述输出端、所述上拉节点、所述下拉单元，用于向所述输出端输出低电平。
  2. 根据权利要求1所述的移位寄存器，其中，所述输入单元包括：
    第一晶体管，所述第一晶体管的栅极和所述第一晶体管的第一极连接所述第一输入端，所述第一晶体管的第二极连接所述充电单元。
  3. 根据权利要求2所述的移位寄存器，其中，所述充电单元包括第二晶体管、第三晶体管、第四晶体管，其中：
    所述第二晶体管的栅极连接第三晶体管的第二极，所述第二晶体管的第一极连接所述第一晶体管的所述第二极，所述第二晶体管的第二极连接所述上拉节点；
    所述第三晶体管的栅极连接控制信号输入端，所述第三晶体管的第一极连接所述第一晶体管的所述第二极；
    所述第四晶体管的栅极连接第二输入端，所述第四晶体管的第一极连接所述第一晶体管的所述第二极，所述第四晶体管的第二极连接所述低电平输入端。
  4. 根据权利要求3所述的移位寄存器，其中，所述上拉单元包括：
    存储电容，其第一极连接所述第二输入端，第二极连接所述上拉节点。
  5. 根据权利要求4所述的移位寄存器，其中，所述高电平输出单元包括：
    第十五晶体管，其栅极连接所述上拉节点，第一极连接所述高电平输入端，第二极连接所述输出端。
  6. 根据权利要求5所述的移位寄存器，其中，所述下拉单元包括第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十六晶体管、第十七晶体管，其中：
    所述第五晶体管的栅极和第一极连接所述高电平输入端，所述第五晶体管的第二极连接所述第七晶体管的栅极；
    所述第六晶体管的栅极连接所述第一输入端，所述第六晶体管的第一极连接所述第七晶体管的栅极，所述第六晶体管的第二极连接所述低电平输入端；
    所述第七晶体管的第一极连接所述第二输入端，所述第七晶体管的第二极连接所述第八晶体管的第一极；
    所述第八晶体管的栅极连接所述控制信号输入端，所述第八晶体管的第二极连接所述第一下拉节点；
    所述第九晶体管的栅极连接所述第一下拉节点，所述第九晶体管的第一极连接所述上拉节点，所述第九晶体管的第二极连接所述低电平输入端；
    所述第十六晶体管的栅极连接所述第一下拉节点，所述第十六晶体管的第一极连接所述输出端，所述第十六晶体管的第二极连接所述低电平输入端；
    所述第十七晶体管的栅极连接所述低电平输出单元，所述第十七晶体管的第一极连接所述第一下拉节点，所述第十七晶体管的第二极连接所述低电平输入端。
  7. 根据权利要求6所述的移位寄存器，其中，所述低电平输出单元包括第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管，其中：
    所述第十晶体管的栅极连接所述第二下拉节点，所述第十晶体管 的第一极连接所述上拉节点，所述第十晶体管的第二极连接所述低电平输入端；
    所述第十一晶体管的栅极连接所述第一输入端，所述第十一晶体管的第一极连接所述第二下拉节点，所述第十一晶体管的第二极连接所述低电平输入端；
    所述第十二晶体管的栅极连接第二输入端，所述第十二晶体管的第一极连接所述第二下拉节点，所述第十二晶体管的第二极连接所述低电平输入端；
    所述第十三晶体管的栅极和第一极连接所述高电平输入端，所述第十三晶体管的第二极连接所述第二下拉节点；
    所述第十四晶体管的栅极连接所述第二下拉节点，所述第十四晶体管的第一极连接所述输出端，所述第十四晶体管的第二极连接所述低电平输入端；
    并且其中
    所述下拉单元的第十七晶体管的栅极连接至所述低电平输出单元的所述第二下拉节点。
  8. 根据权利要求7所述的移位寄存器，其中，
    所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管、第十六晶体管、第十七晶体管均为N型晶体管。
  9. 一种移位寄存器的驱动方法，其中，所述移位寄存器为根据权利要求1至8中任意一项所述的移位寄存器，所述移位寄存器的驱动方法包括：
    准备阶段：使高电平输出单元、下拉单元、低电平输出单元均关断，从而使输出端输出低电平；
    充电阶段：使输入单元为上拉单元充电，所述高电平输出单元导通，从而使所述输出端输出高电平；
    上拉阶段：使上拉单元继续充电，所述高电平输出单元导通，从而使所述输出端输出高电平；
    下拉阶段：使所述下拉单元导通并对所述上拉单元放电，从而使所述输出端输出低电平；
    下拉稳定阶段：使下拉稳定单元导通，从而使所述输出端输出低电平。
  10. 根据权利要求9所述的移位寄存器的驱动方法，其中，所述移位寄存器为根据权利要求8所述的移位寄存器，所述移位寄存器的驱动方法包括：
    准备阶段：控制信号输入端输入低电平，第一输入端输入高电平，第二输入端输入低电平；
    充电阶段：所述控制信号输入端输入高电平，所述第一输入端输入高电平，所述第二输入端输入低电平；
    上拉阶段：所述控制信号输入端输入低电平，所述第二输入端输入高电平；
    下拉阶段：所述控制信号输入端输入高电平，所述第一输入端输入低电平，所述第二输入端输入高电平；
    下拉稳定阶段：所述第一输入端和所述第二输入端均输入低电平。
  11. 根据权利要求10所述的移位寄存器的驱动方法，其中，在所述上拉阶段中所述第一输入端输入高电平，且在所述上拉阶段和所述下拉阶段之间，还包括上拉稳定阶段，其包括第一子阶段和第二子阶段，其中：
    所述第一子阶段：所述第一输入端和所述第二输入端均输入高电平；
    所述第二子阶段：所述控制信号输入端输入低电平，所述第一输入端输入低电平，所述第二输入端输入高电平。
  12. 一种栅极驱动电路，包括：
    多个级联的根据权利要求1至8中任意一项所述的移位寄存器，每个移位寄存器的输出端用于连接一条栅线；其中，每级移位寄存器的第一输入端连接上一级移位寄存器的输出端，每级移位寄存器的第二输入端连接下一级移位寄存器的输出端。
  13. 根据权利要求12所述的栅极驱动电路，其中，
    对于任意两级相邻的移位寄存器，其中一个移位寄存器的控制信号输入端连接第一时钟信号，另一个移位寄存器的控制信号输入端连接第二时钟信号，所述第一时钟信号和所述第二时钟信号是反相的。
  14. 一种显示装置，包括根据权利要求12或13所述的栅极驱动电路。
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