WO2017110389A1 - Substrat multicouche et procédé de fabrication de substrat multicouche - Google Patents

Substrat multicouche et procédé de fabrication de substrat multicouche Download PDF

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Publication number
WO2017110389A1
WO2017110389A1 PCT/JP2016/085488 JP2016085488W WO2017110389A1 WO 2017110389 A1 WO2017110389 A1 WO 2017110389A1 JP 2016085488 W JP2016085488 W JP 2016085488W WO 2017110389 A1 WO2017110389 A1 WO 2017110389A1
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WIPO (PCT)
Prior art keywords
land
layer
ground
transmission line
line
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PCT/JP2016/085488
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English (en)
Japanese (ja)
Inventor
清和 秋山
康成 柳場
Original Assignee
株式会社デンソー
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Filing date
Publication date
Application filed by 株式会社デンソー filed Critical 株式会社デンソー
Priority to US16/065,140 priority Critical patent/US10356897B2/en
Priority to CN201680075289.0A priority patent/CN108476592B/zh
Priority to KR1020187017788A priority patent/KR20180086228A/ko
Priority to DE112016005916.7T priority patent/DE112016005916T5/de
Publication of WO2017110389A1 publication Critical patent/WO2017110389A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09618—Via fence, i.e. one-dimensional array of vias

Definitions

  • the present invention relates to a multilayer substrate having a transmission line for transmitting a signal, and a method for manufacturing the multilayer substrate.
  • a multilayer printed board described in Patent Document 1 is conventionally known.
  • a cavity is provided between the signal via and the ground pattern.
  • the change of the capacitance component of the signal via is suppressed and the impedance of the signal via is adjusted.
  • deterioration of transmission characteristics due to signal reflection at the signal via is prevented.
  • the multilayer printed board of Patent Document 1 is provided with a cavity as described above, the strength of the multilayer printed board is reduced due to the cavity. Moreover, due to distortion of the multilayer printed circuit board when the cavity is processed, there is a possibility that poor conduction in the multilayer printed circuit board may occur.
  • the present invention has been made in view of the above points, and an object of the present invention is to provide a multilayer substrate capable of preventing deterioration of transmission characteristics without requiring a cavity and a method for manufacturing the multilayer substrate.
  • the multilayer substrate is a multilayer substrate having a plurality of conductor layers laminated in the thickness direction.
  • the multilayer substrate includes a first line inclusion layer having a first transmission line for transmitting a signal and a first land to which the first transmission line is connected, a second transmission line for transmitting a signal, and the second transmission line for connection.
  • a second line inclusion layer having a second land, an adjacent insulating layer adjacent to one side in the thickness direction with respect to the first line inclusion layer, and a first line inclusion layer sandwiched between the adjacent insulation layers,
  • a ground inclusion layer having a ground pattern extending in a planar shape, and a signal via disposed between the first land and the second land and connecting the first land and the second land.
  • the first line inclusion layer, the second line inclusion layer, and the ground inclusion layer are included in the plurality of conductor layers, and the signal via, the first land, and the second land have an inductance component due to the provision of the signal via. Is included in the via portion changing with respect to the first transmission line.
  • the first land and the ground pattern generate parasitic capacitance by capacitive coupling across the adjacent insulating layer, and the parasitic capacitance is the impedance of the via portion due to the change in the inductance component of the via portion with respect to the first transmission line. It is a predetermined capacity that suppresses changes.
  • the impedance of the via portion can be matched with the impedance of the first transmission line by adjusting the parasitic capacitance generated by the first land and the ground pattern. Therefore, it is possible to prevent the transmission characteristics from being deteriorated in the multilayer substrate without requiring a cavity in the multilayer substrate.
  • the method for manufacturing a multilayer substrate comprises a first transmission line that forms a layer of a plurality of conductor layers stacked in the thickness direction, and transmits a signal, and the first transmission line.
  • a second line inclusion layer having a second land, an adjacent insulating layer adjacent to one side in the thickness direction with respect to the first line inclusion layer, and a first line inclusion layer and a second line inclusion among a plurality of conductor layers
  • the first layer and the second land are disposed between the first land and the second land, which is a layer different from the first layer and is stacked with the adjacent insulating layer sandwiched between the first line inclusion layer and having a ground pattern extending in a planar shape.
  • a signal via connecting the first land and the second land A method for manufacturing a multilayer substrate provided with.
  • the signal via, the first land, and the second land are included in the via portion where the inductance component is changed with respect to the first transmission line due to the provision of the signal via, and the first land and the ground pattern are Parasitic capacitance is generated by capacitive coupling between adjacent insulating layers. Furthermore, the manufacturing method of the multilayer substrate is such that the parasitic capacitance becomes the capacitance of such a size that the change in the impedance of the via portion due to the change in the inductance component of the via portion with respect to the first transmission line is suppressed. Determining the target area and forming the first land so that the land area of the first land becomes the target area after determining the target area.
  • the first land can be formed so that the impedance of the via portion matches the impedance of the first transmission line. Therefore, it is possible to prevent the transmission characteristics from being deteriorated in the multilayer substrate without requiring a cavity in the multilayer substrate.
  • symbol in the parenthesis described by the claim is an example which shows a corresponding relationship with the specific content as described in embodiment mentioned later.
  • FIG. 1 is a cross-sectional view of a multilayer substrate in a first embodiment. II-II sectional drawing in FIG. 1 is shown.
  • FIG. 3 is a sectional view taken along line III-III in FIG.
  • substrate thickness direction, ie, the IV arrow directional view in FIG. 1 schematically shows a cross section of the multilayer substrate shown in FIG. 1, and also schematically shows a capacitance component and an inductance component generated in the multilayer substrate.
  • the figure which showed the transmission characteristic for every diameter of a 1st land is shown.
  • FIG. 10 is a sectional view taken along line IX-IX in FIG.
  • FIG. 10 is a sectional view taken along line IX-IX in FIG.
  • FIG. 10 is a sectional view taken along line IX-IX in FIG.
  • FIG. 10 is a sectional drawing taken along line IX-IX in FIG.
  • FIG. 10 is a sectional drawing taken along line IX-IX in FIG.
  • FIG. 10 of 3rd Embodiment is shown.
  • FIG. 10 of 3rd Embodiment is shown.
  • FIG. 1 is a cross-sectional view showing a cross section of the multilayer substrate 10 cut along a plane along the thickness direction DRt of the multilayer substrate 10 of the present embodiment.
  • the multilayer substrate 10 includes a plurality of conductor layers 12, 13, 14, 15, 16, 17 (hereinafter abbreviated as a plurality of conductor layers 12 to 17) including a conductor pattern made of, for example, copper foil. And a plurality of insulating layers 21, 22, 23, 24, 25, 26 (hereinafter sometimes abbreviated as a plurality of insulating layers 21 to 26) made of an insulator. .
  • the plurality of conductor layers 12 to 17 and the plurality of insulating layers 21 to 26 are alternately stacked in the substrate thickness direction DRt that is the thickness direction DRt of the multilayer substrate 10.
  • the multilayer substrate 10 also has a plurality of vias 34, 36 and 38.
  • the plurality of conductor layers 12 to 17 include a first ground inclusion layer 12 as a first conductor layer, a first line inclusion layer 13 as a second conductor layer, a third conductor layer 14, and a fourth conductor layer. It includes a conductor layer 15, a second ground inclusion layer 16 as a fifth conductor layer, and a second line inclusion layer 17 as a sixth conductor layer.
  • the conductor patterns included in the conductor layers 12 to 17 have the same thickness, for example.
  • the plurality of insulating layers 21 to 26 include a first insulating layer 21, a second insulating layer 22, a third insulating layer 23, a fourth insulating layer 24, a fifth insulating layer 25, and a sixth insulating layer 26. Yes.
  • the plurality of conductor layers 12 to 17 and the plurality of insulating layers 21 to 26 include the first ground inclusion layer 12, the first insulation layer 21, the first line inclusion layer 13, the second insulation layer 22, and the third conductor.
  • the layers are stacked in order from one side to the other side in the thickness direction DRt. For this reason, the substrate thickness direction DRt is also the stacking direction of the plurality of conductor layers 12 to 17 and the stacking direction of the plurality of insulating layers 21 to 26.
  • the first line inclusion layer 13 includes a first transmission line 131 and a first land 132 as shown in FIG.
  • the first transmission line 131 is a conductor pattern that transmits, for example, a high-frequency electrical signal exceeding 1 GHz (hereinafter also simply referred to as “signal”).
  • the width w 1 orthogonal to the longitudinal direction of the first transmission line 131, that is, the line width w 1 of the first transmission line 131 is constant over the entire length of the first transmission line 131.
  • the first transmission line 131 extends linearly with the line width w1.
  • the first land 132 is a conductor pattern to which the first transmission line 131 is connected.
  • the first land 132 has a circular shape with a diameter d1, for example.
  • the diameter d1 of the first land 132 is larger than the line width w1 of the first transmission line 131.
  • the first line inclusion layer 13 includes two intermediate ground patterns 133 and 134 as shown in FIG.
  • the second line inclusion layer 17 has a second transmission line 171 and a second land 172 as shown in FIG.
  • the second transmission line 171 is a conductor pattern that transmits a high-frequency signal exceeding 1 GHz (that is, a high-frequency AC signal), for example, like the first transmission line 131.
  • the width w2 perpendicular to the longitudinal direction of the second transmission line 171, that is, the line width w2 of the second transmission line 171 is constant over the entire length of the second transmission line 171.
  • the second transmission line 171 extends linearly with the line width w2.
  • the second land 172 is a conductor pattern to which the second transmission line 171 is connected.
  • the second land 172 has, for example, a circular shape with a diameter d2.
  • the diameter d2 of the second land 172 is larger than the line width w2 of the second transmission line 171.
  • the diameter d1 of the first land 132 is smaller than the diameter d2 of the second land 172. That is, the land area S1 of the first land 132 is smaller than the land area S2 of the second land 172.
  • the first land 132 is disposed so that the center position of the first land 132 is provided so as to overlap the center position of the second land 172 in the substrate thickness direction DRt.
  • the first lands 132 are arranged such that the center positions of the lands 132 and 172 in the planar direction DRp of the multilayer substrate 10 coincide with each other. Accordingly, the first land 132 is arranged so that the projected outer shape of the first land 132 falls within the range of the projected outer shape obtained by projecting the second land 172 in the substrate thickness direction DRt.
  • the plane direction DRp of the multilayer substrate 10, that is, the substrate plane direction DRp, is a direction along the surfaces 101 and 102 of the multilayer substrate 10, and is a direction intersecting the substrate thickness direction DRt, strictly speaking, the substrate thickness direction DRt. It is a direction orthogonal to.
  • the substrate plane direction DRp is also the plane direction DRp of each of the conductor layers 12 to 17 and also the plane direction DRp of each of the insulating layers 21 to 26.
  • the first ground inclusion layer 12 has a first ground pattern 121.
  • the first ground pattern 121 is a conductor pattern extending in a planar shape. For example, as shown in FIGS. 1 and 4, the first ground pattern 121 is formed so as to spread over the entire surface of the multilayer substrate 10 in the substrate plane direction DRp.
  • first ground pattern 121 is electrically connected to a member having a ground potential (not shown), whereby the first ground pattern 121 is maintained at the ground potential. In short, the first ground pattern 121 is grounded.
  • the third conductor layer 14 includes one intermediate signal pattern 141 and two intermediate ground patterns 142 and 143 as conductor patterns.
  • the fourth conductor layer 15 also includes one intermediate signal pattern 151 and two intermediate ground patterns 152 and 153 as conductor patterns.
  • the first insulating layer 21 is an adjacent insulating layer adjacent to the first line inclusion layer 13 on one side in the substrate thickness direction DRt. Therefore, the first insulating layer 21 is disposed between the first ground inclusion layer 12 and the first line inclusion layer 13. That is, the first ground inclusion layer 12 is laminated on the first line inclusion layer 13 with the first insulating layer 21 interposed therebetween.
  • the second ground inclusion layer 16 is a ground inclusion layer that is a layer different from the first ground inclusion layer 12 among the plurality of conductor layers 12 to 17.
  • the second ground inclusion layer 16 is laminated on the second line inclusion layer 17 with the fifth insulating layer 25 interposed therebetween.
  • the fifth insulating layer 25 is provided as another insulating layer different from the first insulating layer 21 described above.
  • the second ground inclusion layer 16 has a second ground pattern 161.
  • a first ground via 34 and a second ground via 36 are provided between the second ground pattern 161 and the first ground pattern 121.
  • the first ground via 34 and the second ground via 36 are joined to the first ground pattern 121 and the second ground pattern 161, whereby the second ground pattern 161 is electrically connected to the first ground pattern 121. It is connected to the.
  • the six intermediate ground patterns 133, 134, 142, 143, 152, and 153 described above are electrically connected to the first ground pattern 121 by the first ground via 34 and the second ground via 36 together with the second ground pattern 161. Connected.
  • the total of the six intermediate ground patterns 133, 134, 142, 143, 152, 153 and the second ground pattern 161 are also maintained at the ground potential similarly to the first ground pattern 121.
  • These intermediate ground patterns 133, 134, 142, 143, 152, 153, the second ground pattern 161, the first ground via 34, and the second ground via 36 are electrically connected to the first ground pattern 121 as a whole.
  • the ground connection portion 40 is configured.
  • the ground connection portion 40 and the first ground pattern 121 constitute a ground portion 42 maintained at the ground potential in the multilayer substrate 10.
  • the ground portion 42 is shown in FIG.
  • FIG. 5 is a schematic view schematically showing a cross section of the multilayer substrate 10 shown in FIG. 1 and schematically showing a capacitance component and an inductance component generated in the multilayer substrate 10.
  • the first ground via 34 is disposed at a position closer to the first land 132 than the second ground via 36, as shown in FIG.
  • the second ground inclusion layer 16 includes an intermediate signal pattern 162 as shown in FIG.
  • the signal via 38 is disposed between the first land 132 and the second land 172 in the substrate thickness direction DRt.
  • the signal via 38 electrically connects the first land 132 and the second land 172 to each other. More specifically, since the total three intermediate signal patterns 141, 151, 162 are arranged between the first land 132 and the second land 172, the signal via 38 has the total three intermediate signal patterns. 141, 151, 162, the first land 132, and the second land 172 are electrically connected to each other.
  • the signal via 38 includes first to fourth signal via forming units 38a, 38b, 38c, and 38d.
  • the first signal via forming portion 38a is disposed between the first land 132 and the intermediate signal pattern 141 of the third conductor layer 14, and connects the first land 132 and the intermediate signal pattern 141 to each other.
  • the second signal via forming part 38b is disposed between the intermediate signal pattern 141 of the third conductor layer 14 and the intermediate signal pattern 151 of the fourth conductor layer 15, and the two intermediate signal patterns 141 and 151 are connected to each other. Connecting.
  • the third signal via forming part 38c is disposed between the intermediate signal pattern 151 of the fourth conductor layer 15 and the intermediate signal pattern 162 of the second ground inclusion layer 16, and the two intermediate signal patterns 151 and 162 are connected to each other. Connect to each other.
  • the fourth signal via forming unit 38d is disposed between the intermediate signal pattern 162 of the second ground inclusion layer 16 and the second land 172, and connects the intermediate signal pattern 162 and the second land 172 to each other.
  • the second transmission line 171 includes a line portion 171a adjacent to the second ground pattern 161 with the fifth insulating layer 25 interposed therebetween, and a land connection portion 171b disposed between the line portion 171a and the second land 172. And have.
  • the line portion 171a is connected to the second land 172 via the land connection portion 171b.
  • the boundary position Pbd between the line portion 171a and the land connection portion 171b coincides with the position Pe of the edge 161a on the signal via 38 side in the second ground pattern 161.
  • the line length b2 of the land connection part 171b is the length from the connection end 171c of the land connection part 171b connected to the second land 172 to the boundary position Pbd in the longitudinal direction of the second transmission line 171.
  • the first transmission line 131, the first land 132, the signal via 38, the second land 172, and the second transmission line 171 are connected in series in the order described in the multilayer substrate 10. Yes.
  • the first transmission line 131, the first land 132, the signal via 38, the second land 172, and the second transmission line 171 are such that signals are transmitted as indicated by arrows AS1, AS2, and AS3 in FIG. This constitutes the signal transmission path of the book.
  • the signal transmission path is configured based on an impedance of 50 ⁇ , for example.
  • the signal transmission path includes the signal via 38 as described above. Therefore, the signal transmission path of the multilayer substrate 10 includes two 50 ⁇ transmission line portions 131 and 171a (hereinafter simply referred to as transmission line portions 131 and 171a) whose impedance is maintained at 50 ⁇ , and the transmission line portions 131 and 171a, It is comprised from via parts 44 other than 171a.
  • transmission line portions 131 and 171a hereinafter simply referred to as transmission line portions 131 and 171a
  • the transmission line portions 131 and 171a are portions where the impedance is maintained at 50 ⁇ as described above. Therefore, the transmission line portions 131 and 171a maintain a constant conductor cross section perpendicular to the direction of current flowing through the signal transmission path as a signal, and maintain a constant distance between the conductor cross section and the ground portion. It is a connected part. That is, in the present embodiment, the first transmission line 131 corresponds to one of the two transmission line portions 131 and 171a. The line portion 171a of the second transmission line 171 corresponds to the other of the transmission line portions 131 and 171a.
  • the via portion 44 the configuration of the transmission line portions 131 and 171a is broken. That is, in the via portion 44, the configuration in which the conductor cross section is maintained constant and the distance between the conductor cross section and the ground portion 42 is maintained constant is continued.
  • the cause of the collapse of the configuration is that the signal via 38 is provided in the signal transmission path of the multilayer substrate 10.
  • the inductance component of the via portion 44 changes with respect to the inductance component of the first transmission line 131. Therefore, the via portion 44 is, in other words, a portion where the inductance component changes with respect to the first transmission line 131 due to the provision of the signal via 38.
  • the via portion 44 includes a first land 132, a second land 172, a land connection portion 171 b of the second transmission line 171, three intermediate signal patterns 141, 151, 162, and a signal via 38. Yes.
  • the impedance Zv of the via portion 44 is calculated by the following formula F1 based on the capacitance component Cv and the inductance component Lv of the via portion 44.
  • the first land 132 and the first ground pattern 121 are parasitic capacitance C LAND by capacitive coupling with the first insulating layer 21 interposed therebetween. Has produced.
  • This parasitic capacitance C LAND is referred to as a first parasitic capacitance C LAND .
  • the via portion 44 has a capacitive coupling portion 441.
  • the capacitive coupling portion 441 is arranged side by side in the substrate plane direction DRp with respect to one portion 421 of the ground portion 42.
  • the capacitive coupling portion 441 is capacitively coupled to the ground-side capacitive portion 421 that is the partial position 421, so that the second parasitic capacitance is provided between the ground-side capacitive portion 421 and the capacitive coupling portion 441.
  • Capacitance C VIA has occurred.
  • the capacitance component Cv of the via portion 44 can be calculated as the sum of the first parasitic capacitance C LAND and the second parasitic capacitance C VIA .
  • the capacitive coupling unit 441 is provided between the first land 132, the intermediate signal pattern 162 of the second ground inclusion layer 16, and the first land 132 of the signal via 38 and the intermediate signal pattern 162. It consists of the part. Portions of the signal via 38 between the first land 132 and the intermediate signal pattern 162 are first to third signal via forming portions 38a to 38c.
  • a parasitic capacitance is generated also in a portion other than the capacitive coupling portion 441, for example, between the land connection portion 171b of the second transmission line 171 and the ground portion 42.
  • the second parasitic capacitances C LAND and C VIA are very small. Therefore, when estimating the capacitance component Cv of the via portion 44 by calculation, it is considered that it is not necessary to consider the parasitic capacitances other than the parasitic capacitances C LAND and C VIA .
  • the inductance component Lv of the via portion 44 can be calculated as the sum of the first inductance L LINE , the second inductance L VIA1, and the third inductance L VIA2 .
  • the first inductance L LINE is the inductance of the land connection portion 171b of the second transmission line 171.
  • the second inductance L VIA1 is an inductance of the via intermediate portion 442 that is a portion between the land connection portion 171b and the capacitive coupling portion 441.
  • the via intermediate portion 442 is a portion of the second land 172 and the fourth signal via that is a portion of the signal via 38 between the second land 172 and the intermediate signal pattern 162 of the second ground inclusion layer 16. It is comprised from the structure part 38d.
  • the third inductance L VIA2 is the inductance of the capacitive coupling unit 441.
  • the above equation F2 is calculated by approximating the impedance Zv of the entire via portion 44 from the main portion. Then, the closer the impedance Zv calculated from the above formula F2 is to the impedance (for example, 50 ⁇ ) of the transmission line portions 131 and 171a connected to the via portion 44, the more matched the impedance is, and the reflected signal is reflected. Less.
  • the first inductance L LINE of the above formula F2 is calculated by the following formula F3.
  • b2 is the line length of the land connection portion 171b, and its unit is “cm”.
  • w2 is the line width of the second transmission line 171, that is, the line width of the land connection portion 171b, and its unit is “cm”.
  • t2 is the copper foil thickness of the second transmission line 171 (in other words, the conductor pattern thickness), that is, the copper foil thickness of the land connection portion 171b, and its unit is “cm”.
  • all the conductor patterns have the same copper foil thickness t2.
  • ⁇ r is a relative permeability of the conductor pattern of the multilayer substrate 10, and specifically, the conductor pattern is made of a copper foil, so that ⁇ r is a relative permeability of copper.
  • T (x) is a correction term calculated from the following formulas F4 and F5.
  • the unit of the first inductance L LINE obtained from the equation F3 is “ ⁇ H”
  • the first inductance L LINE is converted into the unit “H” and substituted into the equation F2.
  • the logarithm included in the formula F3 is a natural logarithm, and the logarithms included in the calculation formulas described below are all natural logarithms.
  • symbol represents the same parameter.
  • the correction term T (x) is calculated from the equation F4 using x in the equation F5.
  • f is the frequency of the signal transmitted by the via portion 44, and its unit is “Hz”.
  • ⁇ is the conductivity of the conductor pattern and the signal via 38, that is, the conductivity of copper that is a constituent material, and the unit is “S / m”.
  • the second inductance L VIA1 is calculated by the following formula F6.
  • bt is the length of the via intermediate portion 442 in the substrate thickness direction DRt, and its unit is “cm”.
  • a is a radius of a virtual via cylinder obtained by averaging the via portions 44 so as to have a constant circular cross section, that is, a via radius, and its unit is “cm”.
  • the virtual via cylinder is assumed to have the same length as the via portion 44 and the same volume as the via portion 44 in the substrate thickness direction DRt.
  • the unit of the second inductance L VIA1 obtained from the equation F6 is “ ⁇ H”, the second inductance L VIA1 is converted into the unit “H” and substituted into the equation F2.
  • the above formulas F3 and F6 are both formulas for calculating the inductance component relating to a portion having no ground as a reference.
  • the cross-sectional shape of the land connection portion 171b is rectangular while the cross-sectional shape of the virtual via cylinder is circular, the formulas applied to each of them are different from each other.
  • the third inductance L VIA2 is calculated by the following formula F7.
  • the following formula F7 is a formula for calculating an inductance component related to a portion having a ground serving as a reference.
  • ⁇ is the magnetic permeability of the conductor pattern of the multilayer substrate 10, and specifically, since the conductor pattern is made of copper foil, ⁇ is the magnetic permeability of copper.
  • the unit of ⁇ is “H / m”.
  • h is an interval in the substrate plane direction DRp between the central axis of the virtual via cylinder in the capacitive coupling portion 441 and the ground-side capacitive portion 421. That is, h is the distance in the substrate plane direction DRp between the central axis of the signal via 38 and the ground-side capacitance portion 421, in other words, the distance between the signal via and the ground.
  • the unit of h is “cm”.
  • the unit of the third inductance L VIA2 obtained from the formula F7 is “H”. Note that the central axis of the virtual via cylinder coincides with the central axis of the signal via 38.
  • the second parasitic capacitance C VIA is calculated by the following formula F8.
  • the following formula F8 is a calculation formula for the capacitance component related to the portion having the ground serving as a reference.
  • ⁇ p is the dielectric constant of the insulating material disposed between the capacitive coupling portion 441 of the via portion 44 and the ground side capacitance portion 421 of the ground portion 42, and its unit is “F / m”. is there.
  • the insulating material and the materials of the insulating layers 21 to 26 are the same.
  • the unit of the second parasitic capacitance C VIA obtained from the formula F8 is “F”.
  • the first parasitic capacitance C LAND is calculated by the following formula F9.
  • the following formula F9 is a calculation formula that is also used for calculating the capacitance of the capacitor, and is a calculation formula for calculating the capacitance component between the parallel plates.
  • S1 is the land area of the first land 132, and its unit is “m 2 ”.
  • Dg is a distance between the first land 132 and the first ground pattern 121 in the substrate thickness direction DRt, that is, a land-ground distance.
  • the unit of Dg is “m”.
  • ⁇ t is a dielectric constant of an insulating material disposed between the first land 132 and the first ground pattern 121, that is, a dielectric constant of the first insulating layer 21 in the present embodiment.
  • ⁇ t in the formula F9 is the same value as ⁇ p in the formula F8. is there.
  • the unit of the first parasitic capacitance C LAND obtained from the above formula F9 is “F”.
  • the impedance Zv of the via portion 44 can be quantitatively obtained from the above-described formulas F2 to F9.
  • the signal transmission path includes first and second transmission lines 131 and 171, first and second lands 132 and 172, a signal via 38, and the like.
  • the transmission loss in the signal transmission path includes, for example, three of conductor loss, dielectric loss, and signal reflection.
  • the conductor loss which is one of the transmission losses, depends on the cross-sectional shape of a conductive material generally made of copper foil, the size of the conductive material, and the surface roughness.
  • the dielectric loss depends on the material characteristics of the dielectric material that is an insulator.
  • the signal reflection is caused by the fact that the signal becomes difficult to be transmitted due to the reflection generated at the impedance mismatched portion of the signal transmission path.
  • the transmission loss due to the signal reflection becomes remarkable in high-frequency signal transmission exceeding several tens of GHz. Therefore, reducing the impedance mismatch of the signal transmission path leads to improvement of the high frequency characteristics of the multilayer substrate 10.
  • L an inductance component
  • C a capacitance component.
  • the inductance component per unit length of the signal via 38 varies depending on the cross-sectional area of the signal via 38 and the distance between the signal via 38 and the ground and surrounding metal. If the inductance component can be canceled out by the change in the capacitance component, the change in the impedance value is suppressed.
  • the first parasitic capacitance C LAND generated between the first land 132 and the first ground pattern 121 shown in FIGS. 1 and 5 is used as the contribution of the via portion 44 to the capacitance component Cv. Attention is focused on the fact that the contribution of Then, the first parasitic capacitance C LAND is increased or decreased by changing the land diameter d1 of the first land 132 or by providing a missing conductor in a part of the first ground pattern 121 capacitively coupled to the first land 132. Can be made. Therefore, the impedance of the via portion 44 can be adjusted by changing the land diameter d1 as described above, providing a missing conductor in a part of the first ground pattern 121, or a combination thereof. If signal reflection is suppressed in this way, the transmission characteristics of the multilayer substrate 10 are improved.
  • the first parasitic capacitance C LAND is a predetermined capacitance.
  • the predetermined capacity is obtained by using the above formulas F2 to F9 so as to suppress the change in the impedance Zv of the via portion 44 due to the change in the inductance component Lv of the via portion 44 with respect to the first transmission line 131.
  • the capacity of the size since the capacitance components included in the right side of the formula F2 are only the first parasitic capacitance C LAND and the second parasitic capacitance C VIA , the first parasitic capacitance C LAND has the capacitance component Cv of the via portion 44.
  • the predetermined capacitance is defined as the sum of the first parasitic capacitance C LAND and the second parasitic capacitance C VIA .
  • the first parasitic capacitance C LAND is adjusted by increasing or decreasing the land area S1 of the first land 132. That is, the first land 132 has a land area S1 determined so that the first parasitic capacitance C LAND becomes the predetermined capacitance.
  • the first land 132 is formed through the following steps so that the first parasitic capacitance C LAND becomes the predetermined capacitance. That is, first, in the first step, the first to third inductances L LINE , L VIA1 , L VIA2 and the second parasitic capacitance C VIA are calculated using the above formulas F3 to F8.
  • the impedance Zv of the via portion 44 shown in the formula F2 has the same value as the characteristic impedance of the signal transmission path, that is, the impedance of the first transmission line 131.
  • the impedance Zv of the via portion 44 is 50 ⁇ .
  • the first parasitic capacitance C LAND in the formula F2 is calculated using the calculated values L LINE , L VIA1 , L VIA2 , C VIA calculated in the first step and the formula F2.
  • the target value of the calculated value of the first parasitic capacitance C LAND obtained from the formula F2 is first parasitic capacitance C LAND (hereinafter, referred to as a first parasitic capacitance target value) are.
  • the impedance Zv of the via portion 44 becomes about 50 ⁇ . . Then, a change in the impedance Zv of the via portion 44 with respect to the impedance of the first transmission line 131 is suppressed.
  • the first parasitic capacitance target value is calculated and determined in this way, because the impedance Zv of the via portion 44 due to the change in the inductance component Lv of the via portion 44 with respect to the first transmission line 131 is determined.
  • the first parasitic capacitance target value is determined so that the change is suppressed.
  • the first parasitic capacitance C LAND is a predetermined capacitance. Since the first parasitic capacitance target value is determined through such a process, the predetermined capacitance is, for example, the first capacitance. It is the parasitic capacitance target value.
  • the first parasitic capacitance target value determined in the second step is substituted into C LAND in the above formula F9.
  • the land area S1 of the first land 132 is calculated from the formula F9.
  • the calculated value of the land area S1 obtained from the equation F9 is determined as the target area of the land area S1.
  • the diameter d1 of the first land 132 from which the land area S1 is obtained is determined as the target diameter of the first land 132.
  • the target area of the first land 132 is determined based on the first parasitic capacitance target value in this way, the target area of the first land 132 is the first parasitic capacitance C LAND and the first parasitic capacitance target value. Will be determined.
  • the first land 132 is formed so that the land area S1 of the first land 132 becomes the target area. Specifically, the first land 132 is formed so that the diameter d1 of the first land 132 becomes the target diameter.
  • the steps from the first step to the third step may be completed in advance before the fourth step is performed, and are performed every time one multilayer substrate 10 is manufactured. There is no need to
  • the diameter d1 of the first land 132 is ⁇ 100 ⁇ m, ⁇ 200 ⁇ m, ⁇ 250 ⁇ m, ⁇ 300 ⁇ m, and ⁇ 350 ⁇ m, respectively.
  • the transmission characteristic in the comparative configuration example in which the diameter d1 of the first land 132 is ⁇ 100 ⁇ m is shown by a curve L10.
  • the transmission characteristic in the comparative configuration example in which the diameter d1 of the first land 132 is 200 ⁇ m is indicated by a curve L20.
  • the transmission characteristic in the comparative configuration example in which the diameter d1 of the first land 132 is ⁇ 250 ⁇ m is shown by a curve L25. Further, the transmission characteristic in the comparative configuration example in which the diameter d1 of the first land 132 is ⁇ 300 ⁇ m is indicated by a curve L30. Further, the transmission characteristic in the comparative configuration example in which the diameter d1 of the first land 132 is ⁇ 350 ⁇ m is indicated by a curve L35.
  • a ripple occurs on the high frequency side, for example, as indicated by an arrow ALP, and this ripple causes a transmission loss to increase.
  • each impedance Zv of the via portion 44 described on the horizontal axis of FIG. 7 is a calculated value obtained from the above formulas F2 to F9. is there.
  • the transmission loss is minimized in the comparative configuration example in which the diameter d1 of the first land 132 is ⁇ 250 ⁇ m among the five comparative configuration examples.
  • the impedance Zv described on the horizontal axis in FIG. 7 is 51.0 ⁇ , which is closest to the characteristic impedance 50 ⁇ . From this, it can be seen that the signal reflection is reduced and the transmission loss is suppressed by designing the impedance Zv of the via portion 44 to a value close to 50 ⁇ using the approximate expressions of the above formulas F2 to F9.
  • the first land 132 and the first ground pattern 121 have the first parasitic capacitance C by capacitive coupling with the first insulating layer 21 interposed therebetween.
  • LAND is generated.
  • the first parasitic capacitance C LAND is a predetermined capacitance that suppresses a change in the impedance Zv of the via portion 44 due to a change in the inductance component Lv of the via portion 44 with respect to the first transmission line 131.
  • the impedance Zv of the via portion 44 can be matched with the impedance of the first transmission line 131 by adjusting the first parasitic capacitance C LAND generated by the first land 132 and the first ground pattern 121. Therefore, it is possible to prevent the transmission characteristics of the multilayer substrate 10 from deteriorating without requiring a cavity such as a through hole in the multilayer substrate 10.
  • the inductance component Lv and the capacitance component Cv of the via portion 44 can be easily approximated using the above formulas F2 to F9. Therefore, it is possible to easily and quantitatively reduce the transmission loss by adjusting only the first parasitic capacitance C LAND generated by the first land 132.
  • the first land 132 has the land area S1 determined so that the first parasitic capacitance C LAND becomes the predetermined capacitance. Therefore, by appropriately determining the land area S1, the impedance Zv of the via portion 44 can be easily matched to the impedance of the first transmission line 131.
  • the second transmission line 171 includes the line portion 171a adjacent to the second ground pattern 161 with the fifth insulating layer 25 interposed therebetween, and the line portion 171a and the second land 172 between them.
  • the land connection portion 171b is disposed.
  • the land connection portion 171 b is included in the via portion 44.
  • the calculated value of the first parasitic capacitance C LAND as the first parasitic capacitance target value cannot be accurately calculated using the above formula F2. Become. Therefore, it is possible to estimate the inductance component Lv of the via portion 44 with higher accuracy than when the land connection portion 171b is not included in the via portion 44.
  • the capacitance component Cv of the via portion 44 is the sum of the first parasitic capacitance C LAND and the second parasitic capacitance C VIA, and the first parasitic capacitance C LAND is the predetermined capacitance. ing.
  • the second parasitic capacitance C VIA is easily calculated from the above equation F8. Accordingly, the capacitance component Cv of the via portion 44 can be easily calculated.
  • the first parasitic capacitance C LAND is a capacitance having a magnitude that can suppress the change in the impedance Zv of the via portion 44 due to the change in the inductance component Lv of the via portion 44 with respect to the first transmission line 131.
  • the target area of the first land 132 is determined.
  • the first land 132 is formed so that the land area S1 of the first land 132 becomes the target area.
  • the first land 132 can be formed so that the impedance Zv of the via portion 44 matches the impedance of the first transmission line 131. Therefore, it is possible to prevent the transmission characteristics of the multilayer substrate 10 from deteriorating without requiring a cavity such as a through hole in the multilayer substrate 10.
  • the first ground pattern 121 is provided with a missing portion where the conductor is partially missing.
  • the present embodiment is different from the first embodiment.
  • the size of the second land 172 of the present embodiment is the same as that of the first embodiment, but the first land 132 of the present embodiment is the same as the second land 172, unlike the first embodiment. It is formed in size.
  • the first ground pattern 121 has a land facing region 121a facing the first land 132 in the substrate thickness direction DRt.
  • the land facing area 121 a is an area occupied by the first land 132 when the first land 132 is projected in the substrate thickness direction DRt with respect to the first ground pattern 121. Therefore, the land facing region 121 a has the same outer shape as the first land 132 and the same area as the first land 132.
  • the conductor constituting the first ground pattern 121 is missing.
  • the lack corresponds to, for example, a hole or notch formed in the conductor.
  • a hole 121b as a missing conductor is formed in a part of the land facing region 121a.
  • the inside of the hole 121b is filled with, for example, the same material as the insulating material constituting the first insulating layer 21.
  • the hole 121b as a missing conductor in the land facing region 121a of the first ground pattern 121 corresponds to reducing the land area S1 of the first land 132 in terms of the above formula F9. Therefore, the first parasitic capacitance C LAND as a parameter included in the formula F2 is smaller as the hole 121b is larger.
  • the size of the hole 121b is smaller than that in the case where the impedance Zv of the via portion 44 and the impedance of the first transmission line 131 are not provided with the hole 121b. It is prescribed as follows. In other words, the hole 121b is formed in such a size that the difference between the impedances is smaller than when there is no hole 121b.
  • the first parasitic capacitance C LAND has the impedance Zv of the via portion 44 due to the change in the inductance component Lv of the via portion 44 with respect to the first transmission line 131. It is a predetermined capacity that suppresses changes.
  • the conductor is missing in a part of the land facing region 121a of the first ground pattern 121.
  • a hole 121b is formed as a lack of the conductor.
  • the mutual difference between the impedance Zv of the via portion 44 and the impedance of the first transmission line 131 is smaller than that in the case where there is no hole 121b. Accordingly, impedance matching in the signal transmission path of the multilayer substrate 10 can be easily achieved according to the shape of the first ground pattern 121.
  • impedance matching is not achieved by adjusting the land area S1 of the first land 132.
  • the land area S1 of the first land 132 may be adjusted so that the impedance of the via portion 44 matches the impedance of the transmission line portions 131 and 171a. The same applies to third to fifth embodiments described later.
  • the multilayer substrate 10 includes an adjustment insulating material 46 for adjusting the dielectric constant ⁇ t between the first land 132 and the first ground pattern 121 in the substrate thickness direction DRt. ing.
  • the present embodiment is different from the first embodiment.
  • the size of the second land 172 of the present embodiment is the same as that of the first embodiment, but the first land 132 of the present embodiment is the same as the second land 172, unlike the first embodiment. It is formed in size.
  • the adjustment insulating material 46 is an insulating material having a dielectric constant different from that of the first insulating layer 21. As shown in FIG. 10, the adjustment insulating material 46 is provided between the first insulating layer 21 and the first land 132 in the substrate thickness direction DRt. The adjustment insulating material 46 is formed, for example, by being applied to the surface of the first land 132 on the first ground pattern 121 side. Therefore, the adjustment insulating material 46 is formed in a thin film shape along the first land 132. For example, the area of the adjustment insulating material 46 is the same as or smaller than the land area S1 of the first land 132.
  • the dielectric constant ⁇ t in the above formula F9 can be increased or decreased by changing any or all of the dielectric constant, thickness, and area of the adjustment insulating material 46. Therefore, in the present embodiment, the shape of the adjustment insulating material 46 is such that the mutual difference between the impedance Zv of the via portion 44 and the impedance of the first transmission line 131 is smaller than that without the adjustment insulating material 46. And the material is selected.
  • the first parasitic capacitance C LAND is caused to change the impedance of the via portion 44 due to the change in the inductance component Lv of the via portion 44 with respect to the first transmission line 131.
  • the predetermined capacity is used to suppress the change in Zv.
  • the adjustment insulating material 46 is provided between the first insulating layer 21 and the first land 132 in the substrate thickness direction DRt.
  • the mutual difference between the impedance Zv of the via portion 44 and the impedance of the first transmission line 131 is smaller than that in the case where the adjustment insulating material 46 is not provided. Therefore, the impedance Zv of the via portion 44 can be easily matched with the impedance of the first transmission line 131 by appropriately determining the material or shape of the adjustment insulating material 46.
  • the apparent dielectric constant between the first land 132 and the first ground pattern 121 can be changed with respect to the configuration without the adjusting insulating material 46 without providing a cavity in the multilayer substrate 10. Therefore, it is possible to adjust the capacitance component Cv of the via portion 44 by the adjustment insulating material 46, and it is possible to suppress signal reflection and improve transmission characteristics as in the first embodiment.
  • this embodiment is a modification based on 1st Embodiment, it is also possible to combine this embodiment with the above-mentioned 2nd Embodiment.
  • the position where the adjustment insulating material 46 is arranged is different from that of the third embodiment.
  • the adjustment insulating material 46 is not provided between the first insulating layer 21 and the first land 132 in the substrate thickness direction DRt.
  • the adjustment insulating material 46 is provided between the first insulating layer 21 and the first ground pattern 121 in the substrate thickness direction DRt.
  • the adjustment insulating material 46 is disposed at a position where at least a part of the adjustment insulating material 46 faces the first land 132 with the first insulating layer 21 interposed therebetween.
  • this embodiment it is possible to obtain the same effect as that of the third embodiment with the same configuration as that of the third embodiment. Moreover, this embodiment can also be combined with the second embodiment described above in the same manner as the third embodiment described above.
  • the adjustment insulating material 46 is between the first insulating layer 21 and the first land 132 and between the first insulating layer 21 and the first ground pattern 121 in the substrate thickness direction DRt. Both are provided. That is, in the present embodiment, the adjustment insulating material 46 provided between the first insulating layer 21 and the first land 132 has the same arrangement as the adjustment insulating material 46 of the third embodiment. And the adjustment insulating material 46 provided between the 1st insulating layer 21 and the 1st ground pattern 121 is the same arrangement
  • this embodiment it is possible to obtain the same effect as that of the third embodiment with the same configuration as that of the third embodiment. Moreover, this embodiment can also be combined with the second embodiment described above in the same manner as the third embodiment described above.
  • the first parasitic capacitance C LAND is a predetermined capacitance
  • the predetermined capacitance is, for example, a first parasitic capacitance target value.
  • the predetermined capacitance is only required to be determined so as to suppress the change in the impedance Zv of the via portion 44 due to the change in the inductance component Lv of the via portion 44 with respect to the first transmission line 131, and is limited to the determination method. There is no.
  • the equation F2 for calculating the impedance Zv of the via portion 44 is not only the first parasitic capacitance C LAND but also the second parasitic capacitance C VIA and the first to third inductances L LINE , L VIA1 , and L VIA2 are included as parameters.
  • the virtual via cylinder for calculating the formula F6 is a cylinder obtained by averaging the via portions 44 so as to have a constant circular cross section.
  • the virtual via cylinder is assumed to have, for example, the same length as the via portion 44 and the same volume as the via portion 44 in the substrate thickness direction DRt.
  • this is only an example, and the method for averaging the via portions 44 is not limited as long as the virtual via cylinder is a cylinder in which the via portions 44 are averaged so as to have a constant circular cross section.
  • this invention is not limited to the above-mentioned embodiment, Various modifications and the deformation
  • the above embodiments are not irrelevant to each other, and can be appropriately combined unless the combination is clearly impossible.
  • elements constituting the embodiment are not necessarily essential unless explicitly stated as essential and clearly considered essential in principle. Yes.
  • numerical values such as the number, numerical value, quantity, range, etc. of the constituent elements of the embodiment are mentioned, it is clearly limited to a specific number when clearly indicated as essential and in principle. The number is not limited to the specific number except for the case.
  • the first land and the ground pattern generate parasitic capacitance by capacitive coupling with the adjacent insulating layer interposed therebetween.
  • the parasitic capacitance is a predetermined capacitance that suppresses a change in impedance of the via portion due to a change in inductance component of the via portion with respect to the first transmission line.
  • the conductor is missing in at least a part of the land facing area of the ground pattern.
  • the difference of the impedance of a via part and the impedance of a 1st transmission line is small compared with the case where there is no omission. Therefore, impedance matching can be easily achieved according to the shape of the ground pattern.
  • the first land has a land area determined so that the parasitic capacitance becomes the predetermined capacitance. Therefore, it is possible to easily match the impedance of the via portion with the impedance of the first transmission line by appropriately determining the land area.
  • the insulating material having a dielectric constant different from that of the adjacent insulating layer is formed between the adjacent insulating layer and the first land in the thickness direction, and between the adjacent insulating layer and the ground pattern. One or both of them. And the difference of the impedance of a via part and the impedance of a 1st transmission line is small compared with the case where there is no insulating material. Therefore, by appropriately determining the material or shape of the insulating material, it is possible to easily match the impedance of the via portion with the impedance of the first transmission line.
  • the second transmission line includes a line portion adjacent to the second ground pattern across another insulating layer different from the adjacent insulating layer, and between the line portion and the second land. And a land connecting portion disposed on the surface.
  • the land connection portion is included in the via portion. Therefore, it is possible to accurately estimate the inductance component between the first transmission line and the line part of the second transmission line as compared with the case where the land connection part is not included in the via part.
  • the capacitance component of the via portion is the sum of the first parasitic capacitance and the second parasitic capacitance
  • the first parasitic capacitance is the predetermined capacitance. Therefore, the capacitance component of the via portion can be easily calculated.
  • the first land is set such that the parasitic capacitance becomes a capacitance having a magnitude capable of suppressing a change in impedance of the via portion due to a change in inductance component of the via portion with respect to the first transmission line.
  • the target area is determined. After the determination of the target area, the first land is formed so that the land area of the first land becomes the target area.

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Abstract

Dans la présente invention, une première capacité parasite CLAND est produite en raison du couplage capacitif entre une première plage 132 et un premier motif de masse 121 avec une première couche isolante 21 intercalée entre ceux-ci. La première capacité parasite CLAND est définie de manière à être une capacité prescrite pour supprimer les changements d'impédance d'une partie d'interconnexion, de tels changements étant causés par des changements dans un composant d'inductance de la partie d'interconnexion par rapport à une première ligne de transmission 131. Grâce à cette configuration, la première capacité parasite CLAND produite au moyen de la première plage 132 et le premier motif de masse 121 est ajustée et, en conséquence, l'impédance de la partie d'interconnexion peut être adaptée à l'impédance de la première ligne de transmission 131. Par conséquent, sans nécessiter que des cavités telles que des trous traversants soient disposés dans un substrat multicouche 10, il est possible d'éviter une dégradation des caractéristiques de transmission du substrat multicouche 10.
PCT/JP2016/085488 2015-12-22 2016-11-30 Substrat multicouche et procédé de fabrication de substrat multicouche WO2017110389A1 (fr)

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KR1020187017788A KR20180086228A (ko) 2015-12-22 2016-11-30 다층 기판
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CN108476592A (zh) 2018-08-31
JP6424811B2 (ja) 2018-11-21
US20190008042A1 (en) 2019-01-03
KR20180086228A (ko) 2018-07-30
US10356897B2 (en) 2019-07-16
JP2017117890A (ja) 2017-06-29
DE112016005916T5 (de) 2018-09-20

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