WO2022270294A1 - Substrat multicouche, module de substrat multicouche et dispositif électronique - Google Patents

Substrat multicouche, module de substrat multicouche et dispositif électronique Download PDF

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Publication number
WO2022270294A1
WO2022270294A1 PCT/JP2022/022909 JP2022022909W WO2022270294A1 WO 2022270294 A1 WO2022270294 A1 WO 2022270294A1 JP 2022022909 W JP2022022909 W JP 2022022909W WO 2022270294 A1 WO2022270294 A1 WO 2022270294A1
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Prior art keywords
conductor layer
multilayer substrate
cavity
signal conductor
vertical direction
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PCT/JP2022/022909
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English (en)
Japanese (ja)
Inventor
敬一 市川
恒亮 西尾
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株式会社村田製作所
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Priority to CN202290000213.2U priority Critical patent/CN219981140U/zh
Publication of WO2022270294A1 publication Critical patent/WO2022270294A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a multilayer substrate having a structure in which a plurality of insulator layers are laminated.
  • the high-frequency signal line described in Patent Document 1 includes a laminate, a signal line, a first reference conductor, a second reference conductor, an interlayer connection conductor, and an external terminal.
  • the laminate has a structure in which a plurality of dielectric sheets are vertically laminated.
  • the signal line is provided inside the laminate.
  • a first reference conductor is positioned above the signal line.
  • a second reference conductor is located below the signal line.
  • the external terminals are located on the upper main surface of the laminate. The external terminals are connected to signal lines via interlayer connection conductors.
  • the signal line and the external terminal are connected by an interlayer connection conductor. At locations where such interlayer connection conductors exist, the characteristic impedance generated in the high-frequency signal transmission path is likely to fluctuate.
  • an object of the present invention is to provide a multilayer substrate, a multilayer substrate module, and an electronic device capable of adjusting the characteristic impedance of a portion where an interlayer connection conductor connecting a first signal conductor layer and a second signal conductor layer exists.
  • a multilayer substrate comprises One of the upward direction and the downward direction is the first direction, the other of the upward direction and the downward direction is the second direction,
  • a multilayer board is a laminate having a structure in which a plurality of insulator layers are stacked vertically; a first signal conductor layer provided in the laminate; A second signal conductor layer provided in the laminate and located in the second direction from the first signal conductor layer, the overlapping portion overlapping the first signal conductor layer when viewed in the vertical direction a second signal conductor layer comprising provided in the laminate, overlapping the overlapping portion when viewed in the vertical direction, and penetrating the insulating layer in the vertical direction to form the first signal conductor layer and the second signal conductor layer; an interlayer connection conductor in contact with the signal conductor layer; a first reference conductor layer provided in the laminate, positioned in the second direction from the second signal conductor layer, and overlapping at least a portion of the overlapping portion when viewed in the vertical direction; , and A high frequency signal is transmitted
  • the multilayer substrate of the present invention it is possible to adjust the characteristic impedance at the location where the interlayer connection conductor connecting the first signal conductor layer and the second signal conductor layer exists.
  • FIG. 1 is an exploded perspective view of a multilayer substrate 10.
  • FIG. FIG. 2 is a cross-sectional view of the right end portion of the multilayer substrate 10.
  • FIG. 3 is a top view of the right end portion of the multilayer substrate 10.
  • FIG. 4 is a rear view of the internal structure of the electronic device 1 including the multilayer substrate 10.
  • FIG. 5 is a cross-sectional view of the right end portion of the multilayer substrate 10a.
  • FIG. 6 is a cross-sectional view orthogonal to the left-right direction of the multilayer substrate 10a.
  • FIG. 7 is a cross-sectional view orthogonal to the horizontal direction of the multilayer substrate 10b.
  • FIG. 8 is a cross-sectional view of the right end portion of the multilayer substrate 10c.
  • FIG. 9 is a cross-sectional view of the multilayer board module 200.
  • FIG. 10 is a cross-sectional view of the multilayer board module 200a.
  • FIG. 11 is a cross-sectional view of the multilayer substrate 10d.
  • FIG. 12 is a top view of the multilayer substrate 10e. In FIG. 12, the multilayer substrate 10e is seen through.
  • FIG. 13 is a cross-sectional view of the multilayer substrate 10e.
  • FIG. 14 is a cross-sectional view of the multilayer substrate 10f.
  • FIG. 15 is a cross-sectional view of the multilayer substrate 10g.
  • FIG. 16 is a cross-sectional view of the multilayer substrate 10h.
  • FIG. 17 is a top view of the multilayer substrate 10i.
  • FIG. 18 is a top view of the multilayer substrate 10j.
  • FIG. 19 is a cross-sectional view of the multilayer substrate 10k.
  • FIG. 20 is a top view of the multilayer substrate 10k.
  • FIG. 21 is an equivalent circuit diagram near the interlayer connection conductor v4.
  • FIG. 22 is a cross-sectional view of the multilayer substrate 10l.
  • FIG. 23 is a cross-sectional view of the multilayer substrate 10m.
  • FIG. 24 is a cross-sectional view of the multilayer substrate 10n.
  • FIG. 25 is a cross-sectional view of the multilayer substrate 10o.
  • FIG. 1 is an exploded perspective view of a multilayer substrate 10.
  • FIG. 1 only representative interlayer connection conductors v1 and v2 among the plurality of interlayer connection conductors v1 and the plurality of interlayer connection conductors v2 are denoted by reference numerals.
  • FIG. 2 is a cross-sectional view of the right end portion of the multilayer substrate 10.
  • FIG. 3 is a top view of the right end portion of the multilayer substrate 10.
  • the multilayer substrate 10 is seen through.
  • the stacking direction of the laminate 12 of the multilayer substrate 10 is defined as the vertical direction.
  • One of the upward direction and the downward direction is the first direction.
  • the other of the upward direction and the downward direction is the second direction.
  • the first direction is upward.
  • the second direction is downward.
  • the first direction may be downward.
  • the second direction may be upward.
  • the direction in which the signal conductor layer 22 of the multilayer substrate 10 extends is defined as the left-right direction.
  • the line width direction of the signal conductor layer 22 is defined as the front-rear direction.
  • the up-down direction is perpendicular to the front-rear direction.
  • the left-right direction is orthogonal to the up-down direction and the front-rear direction. Note that the vertical direction, the horizontal direction, and the front-rear direction in the present embodiment do not have to match the vertical direction, the horizontal direction, and the front-rear direction when the multilayer substrate 10 is used.
  • X is a part or member of the multilayer substrate 10.
  • each part of X is defined as follows.
  • front of X is meant the front half of X.
  • Back of X means the back half of X.
  • the left part of X means the left half of X.
  • the right part of X means the right half of X.
  • Top of X means the top half of X.
  • the lower part of X means the lower half of X.
  • the leading edge of X means the leading edge of X.
  • the trailing end of X means the trailing end of X.
  • the left end of X means the end of X in the left direction.
  • the right end of X means the end of X in the right direction.
  • the upper end of X means the end of X in the upward direction.
  • the lower end of X means the lower end of X.
  • the front end of X means the front end of X and its vicinity.
  • the rear end of X means the rear end of X and its vicinity.
  • the left end of X means the left end of X and its vicinity.
  • the right end of X means the right end of X and its vicinity.
  • the upper end of X means the upper end of X and its vicinity.
  • the lower end of X means the lower end of X and its vicinity.
  • the multilayer substrate 10 transmits high frequency signals.
  • a multilayer substrate 10 is used to electrically connect two circuits in an electronic device such as a smart phone.
  • the multilayer substrate 10 includes a laminate 12, protective layers 18a and 18b, a signal conductor layer 22 (second signal conductor layer), a second reference conductor layer 24, a first reference conductor layer 26, signal electrodes 28a, a signal electrode 28b (first signal conductor layer), a plurality of interlayer connection conductors v1, a plurality of interlayer connection conductors v2, and interlayer connection conductors v3 and v4.
  • the laminate 12 has a plate shape. Therefore, the laminate 12 has an upper major surface (first major surface) and a lower major surface (second major surface).
  • the upper main surface (first main surface) of the laminate 12 is located above (first direction) the lower main surface (second main surface) of the laminate 12 .
  • the upper principal surface and the lower principal surface of the laminate 12 have a rectangular shape with long sides extending in the left-right direction. Therefore, the length of the laminate 12 in the left-right direction is longer than the length of the laminate 12 in the front-rear direction.
  • the laminate 12 has a structure in which insulator layers 16a to 16c are laminated vertically.
  • the insulator layers 16a-16c are arranged in this order from top to bottom.
  • the insulator layers 16a to 16c have the same rectangular shape as the laminate 12 when viewed in the vertical direction.
  • the insulator layers 16a-16c are flexible dielectric sheets.
  • the material of the insulator layers 16a to 16c is, for example, thermoplastic resin.
  • Thermoplastic resins are, for example, thermoplastic resins such as liquid crystal polymer and PTFE (polytetrafluoroethylene).
  • the material of the insulator layers 16a-16c may be polyimide.
  • the signal electrode 28 a is provided on the laminate 12 .
  • the signal electrode 28 a is located on the upper main surface of the laminate 12 . More specifically, the signal electrode 28a is located at the left end of the upper major surface of the insulator layer 16a.
  • the signal electrode 28a has a rectangular shape when viewed in the vertical direction. A high-frequency signal is input/output to/from the signal electrode 28a.
  • the signal electrode 28 b (first signal conductor layer) is provided on the laminate 12 .
  • the signal electrode 28 b (first signal conductor layer) is located on the upper main surface of the laminate 12 . More specifically, the signal electrode 28b is located at the right end of the upper major surface of the insulator layer 16a.
  • the signal electrode 28b has a rectangular shape when viewed in the vertical direction. A high-frequency signal is input/output to/from the signal electrode 28b (first signal conductor layer).
  • the signal conductor layer 22 (second signal conductor layer) is provided on the laminate 12 as shown in FIG.
  • the signal conductor layer 22 (second signal conductor layer) is positioned below (second direction) the signal electrodes 28a and 28b (first signal conductor layer).
  • the signal conductor layer 22 is located on the upper main surface of the insulator layer 16b. Thereby, the signal conductor layer 22 is provided within the laminate 12 .
  • the signal conductor layer 22 has a linear shape.
  • the signal conductor layer 22 extends in the left-right direction.
  • the signal conductor layer 22 is positioned at the center of the upper main surface of the insulator layer 16b in the front-rear direction.
  • the signal conductor layer 22 overlaps the signal electrode 28a when viewed in the vertical direction.
  • the right end portion of the signal conductor layer 22 overlaps the signal electrode 28b when viewed in the vertical direction. Therefore, the signal conductor layer 22 includes a linear portion 22a, an overlapping portion 22b and an overlapping portion 22c.
  • the linear portion 22a is a portion that does not overlap the signal electrodes 28a and 28b when viewed in the vertical direction.
  • the linear portion 22a has a linear shape.
  • the linear portion 22a extends in the left-right direction.
  • the overlapping portion 22b is a portion that overlaps with the signal electrode 28a when viewed in the vertical direction.
  • the overlapping portion 22b is connected to the left end of the linear portion 22a.
  • the overlapping portion 22c is a portion that overlaps with the signal electrode 28b (first signal conductor layer) when viewed in the vertical direction.
  • the overlapping portion 22c is connected to the right end of the linear portion 22a.
  • the overlapping portions 22b and 22c have a circular shape when viewed in the vertical direction.
  • the longitudinal width of the overlapping portion 22b and the longitudinal width of the overlapping portion 22c are larger than the longitudinal width of the linear portion 22a.
  • the interlayer connection conductor v3 is provided on the laminated body 12 .
  • the interlayer connection conductor v3 overlaps the overlapping portion 22b when viewed in the vertical direction.
  • the interlayer connection conductor v3 is in contact with the signal electrode 28a and the signal conductor layer 22 by vertically penetrating the insulator layer 16a. Thereby, the signal electrode 28a and the signal conductor layer 22 are electrically connected.
  • the interlayer connection conductor v4 is provided in the laminate 12.
  • the interlayer connection conductor v4 overlaps the overlapping portion 22c when viewed in the vertical direction.
  • the interlayer connection conductor v4 is in contact with the signal electrode 28b (first signal conductor layer) and the signal conductor layer 22 (second signal conductor layer) by vertically penetrating the insulator layer 16a. Thereby, the signal electrode 28b and the signal conductor layer 22 are electrically connected.
  • a high-frequency signal is transmitted to the signal electrode 28a, the signal electrode 28b (first signal conductor layer), the signal conductor layer 22 (second signal conductor layer), and the interlayer connection conductors v3 and v4 as described above.
  • the second reference conductor layer 24 is provided on the laminate 12 .
  • the second reference conductor layer 24 is positioned above (first direction) the signal conductor layer 22 (second signal conductor layer).
  • the second reference conductor layer 24 is located on the upper main surface of the insulator layer 16a.
  • the second reference conductor layer 24 covers substantially the entire upper main surface of the insulator layer 16a.
  • the second reference conductor layer 24 overlaps the signal conductor layer 22 when viewed in the vertical direction. However, the second reference conductor layer 24 is not in contact with the signal electrodes 28a and 28b.
  • a reference potential is connected to the second reference conductor layer 24 .
  • the reference potential is, for example, the ground potential.
  • the first reference conductor layer 26 is provided on the laminate 12 .
  • the first reference conductor layer 26 is positioned below (second direction) the signal conductor layer 22 (second signal conductor layer).
  • the first reference conductor layer 26 is located on the lower main surface of the insulator layer 16c.
  • the first reference conductor layer 26 covers substantially the entire lower main surface of the insulator layer 16c.
  • the first reference conductor layer 26 overlaps the signal conductor layer 22 when viewed in the vertical direction.
  • the first reference conductor layer 26 overlaps at least part of the overlapping portions 22b and 22c when viewed in the vertical direction.
  • a reference potential is connected to the first reference conductor layer 26 .
  • the reference potential is, for example, the ground potential.
  • the signal conductor layer 22, the second reference conductor layer 24, and the first reference conductor layer 26 as described above have a stripline structure.
  • a plurality of interlayer connection conductors v1 and a plurality of interlayer connection conductors v2 are provided in the laminate 12 .
  • a plurality of interlayer connection conductors v1 and v2 electrically connect the second reference conductor layer 24 and the first reference conductor layer 26 . More specifically, the plurality of interlayer connection conductors v1 and the plurality of interlayer connection conductors v2 vertically pass through the insulator layers 16a to 16c.
  • the plurality of interlayer connection conductors v1 and the plurality of interlayer connection conductors v2 are in contact with the second reference conductor layer 24 and the first reference conductor layer 26, respectively.
  • a plurality of interlayer connection conductors v1 are positioned in front of the signal conductor layer 22 .
  • the plurality of interlayer connection conductors v1 are arranged in a row at regular intervals in the horizontal direction.
  • a plurality of interlayer connection conductors v2 are positioned behind the signal conductor layer 22 .
  • the plurality of interlayer connection conductors v2 are arranged in a row at regular intervals in the horizontal direction.
  • the signal conductor layer 22, the second reference conductor layer 24, the first reference conductor layer 26, and the signal electrodes 28a and 28b as described above are provided, for example, on the upper main surface or the lower main surface of the insulator layers 16a to 16c. It is formed by etching a metal foil.
  • the metal foil is, for example, copper foil.
  • the interlayer connection conductors v1 to v4 are, for example, via-hole conductors.
  • the via-hole conductors are produced by forming through-holes in the insulating layers 16a to 16c, filling the through-holes with a conductive paste, and sintering the conductive paste.
  • the interlayer connection conductors v1 to v4 may be, for example, through-hole conductors. Through-hole conductors are produced by forming through-holes penetrating all or part of the insulator layers 16a to 16c and plating the through-holes.
  • the protective layer 18 a is laminated on the second reference conductor layer 24 . Therefore, the protective layer 18a is the uppermost insulating layer in the multilayer substrate 10. As shown in FIG. The protective layer 18 a covers substantially the entire second reference conductor layer 24 . However, openings ha to hf are provided in the protective layer 18a. The openings ha to hc are provided at the left end of the protective layer 18a. The openings hb, ha, hc are arranged in this order from front to back. The openings hd to hf are provided at the right end of the protective layer 18a. The openings he, hd, and hf are arranged in this order from front to back.
  • At least portions of the signal electrodes 28a and 28b are exposed to the outside from the multilayer substrate 10 through the openings ha and hd, respectively.
  • a portion of the second reference conductor layer 24 is exposed outside from the multilayer substrate 10 through the openings hb, hc, he, and hf.
  • the protective layer 18b is laminated under the first reference conductor layer 26. Therefore, the protective layer 18b is the lowest insulating layer in the multilayer substrate 10. As shown in FIG. The protective layer 18 b covers substantially the entire first reference conductor layer 26 .
  • the protective layers 18 a and 18 b as described above are not part of the laminate 12 .
  • the material of the protective layers 18a, 18b is different from the material of the insulator layers 16a-16c. In particular, the material of each protective layer 18a, 18b is different from the material of the adjacent insulator layers 16a, 16c.
  • the protective layers 18a and 18b are resist layers.
  • the protective layers 18a and 18b may be formed by attaching a resin sheet to the upper main surface of the insulating layer 16a and the lower main surface of the insulating layer 16c, or a liquid resin may be applied to the insulating layer. It may be formed by coating the upper main surface 16a and the lower main surface of the insulator layer 16c and solidifying.
  • the laminate 12 is provided with a first cavity Sp1 in which the insulator layers 16a to 16c do not exist.
  • the first cavity Sp1 is positioned between the signal conductor layer 22 (second signal conductor layer) and the first reference conductor layer 26 in the vertical direction.
  • the first cavity Sp1 has a hemispherical shape, as shown in FIG.
  • the first cavity Sp1 protrudes upward from the lower main surface of the insulator layer 16c.
  • the upper end of the first cavity Sp1 is positioned between the upper main surface of the insulator layer 16b and the lower main surface of the insulator layer 16b.
  • the first cavity Sp1 overlaps at least a portion of the interlayer connection conductor v4 when viewed in the vertical direction.
  • the first cavity Sp1 overlaps the entire interlayer connection conductor v4 when viewed in the vertical direction.
  • the first cavity Sp1 overlaps at least a portion of the overlapping portion 22c when viewed in the vertical direction.
  • the first cavity Sp1 overlaps the entire overlapping portion 22c when viewed in the vertical direction.
  • the first cavity Sp1 overlaps the right end of the linear portion 22a when viewed in the vertical direction.
  • the overlapping area of the first cavity Sp1 and the overlapping portion 22c is larger than the overlapping area of the first cavity Sp1 and the linear portion 22a.
  • the laminate 12 is provided with a first cavity Sp11 in which the insulator layers 16a to 16c do not exist.
  • the first cavity Sp11 has a structure that is symmetrical to the first cavity Sp1, so description thereof will be omitted.
  • one or more through holes h1 are provided in the first reference conductor layer 26 so as to penetrate the first reference conductor layer 26 in the vertical direction.
  • One or more through holes h1 are connected to the first cavity Sp1.
  • the number of one or more through-holes h1 is one.
  • the through hole h1 has a circular shape when viewed in the vertical direction.
  • the diameter of the through hole h1 is smaller than the diameter of the first cavity Sp1 and the diameter of the overlapping portion 22c.
  • the through hole h1 is located at the center of the first cavity Sp1 and the center of the overlapping portion 22c when viewed in the vertical direction.
  • the through hole h1 is positioned inside the outer edge of the first cavity Sp1 when viewed in the vertical direction. Further, the through hole h1 is positioned inside the outer edge of the overlapping portion 22c when viewed in the vertical direction. The through hole h1 overlaps the interlayer connection conductor v4 when viewed in the vertical direction.
  • the first reference conductor layer 26 is provided with a through hole (not shown) connected to the first cavity Sp11.
  • this through-hole has a structure symmetrical to the through-hole h1, the explanation is omitted.
  • the formation of the first cavity Sp1 will be described.
  • the portion of the insulator layer 16c adjacent to the through hole h1 is removed. Thereby, the first cavity Sp1 is formed.
  • FIG. 4 is a rear view of the internal structure of the electronic device 1 including the multilayer substrate 10.
  • the electronic device 1 is, for example, a mobile wireless communication terminal.
  • the electronic device 1 is, for example, a smart phone.
  • the multilayer substrate 10 includes a first section A2 and second sections A1 and A3.
  • the first section A2 is a section where the multilayer substrate 10 is bent.
  • the second sections A1 and A3 are sections in which the multilayer substrate 10 is not bent. That is, the distance rate radius of the first section A2 is smaller than the curvature radii of the second sections A1 and A3. Therefore, the multilayer substrate 10 may be bent in the second sections A1 and A3 as well.
  • the bending of the multilayer substrate 10 means that the multilayer substrate 10 receives an external force and deforms.
  • the deformation may be plastic deformation, elastic deformation, or both plastic deformation and elastic deformation.
  • the x-axis, y-axis, and z-axis in the electronic device 1 are defined as follows.
  • the x-axis is the horizontal direction in the second section A1.
  • the y-axis is the front-rear direction in the second section A1.
  • the z-axis is the vertical direction in the second section A1.
  • the second section A1, the first section A2, and the second section A3 are arranged in this order in the positive direction of the x-axis.
  • the first section A2 is bent with respect to the second section A1 in the z-axis direction (vertical direction in the second section A1). Therefore, the vertical direction and the front-rear direction differ depending on the position of the multilayer substrate 10, as shown in FIG.
  • the second section A1 for example, position (1)
  • the first section A2 for example, position (2)
  • the vertical direction and the horizontal direction do not match the z-axis direction and the x-axis direction, respectively.
  • the electronic device 1 includes a multilayer board 10, connectors 32a, 32b, 102a, 102b, and circuit boards 500, 510, as shown in FIG.
  • the circuit boards 500, 510 have a plate shape.
  • the circuit board 500 has main surfaces S105 and S106.
  • the main surface S105 is located on the negative direction side of the z-axis from the main surface S106.
  • the circuit board 510 has main surfaces S111 and S112.
  • the main surface S111 is located on the negative direction side of the z-axis from the main surface S112.
  • the circuit boards 500 and 510 include wiring conductor layers, reference conductor layers, electrodes, etc., which are not shown.
  • Each of the connectors 32a and 32b is mounted on the main surface (upper main surface) of the second section A1 and the second section A3 on the positive direction side of the z-axis. More specifically, the connector 32a is mounted on the signal electrode 28a and the second reference conductor layer 24. As shown in FIG. A connector 32 b is mounted on the signal electrode 28 b and the second reference conductor layer 24 .
  • the connectors 102a and 102b are mounted on the main surface S105 of the circuit board 500 and the main surface S111 of the circuit board 510, respectively.
  • Connectors 102a and 102b are connected to connectors 32a and 32b, respectively.
  • the multilayer board 10 electrically connects the circuit board 500 and the circuit board 510 .
  • the characteristic impedance of the portion where the interlayer connection conductor v4 connecting the signal electrode 28b (first signal conductor layer) and the signal conductor layer 22 (second signal conductor layer) is present can be adjusted. More specifically, in the multilayer substrate 10, the first cavity Sp1 overlaps at least a portion of the interlayer connection conductor v4 when viewed in the vertical direction, and also overlaps the signal conductor layer 22 (second signal conductor layer) in the vertical direction. It is located between the first reference conductor layer 26 . As a result, the dielectric constant between the portion of the signal conductor layer 22 to which the interlayer connection conductor v4 is connected and the first reference conductor layer 26 is lowered.
  • the capacitance between the portion of the signal conductor layer 22 to which the interlayer connection conductor v4 is connected and the first reference conductor layer 26 is reduced.
  • the characteristic impedance at the location where the interlayer connection conductor v4 connecting the signal electrode 28b (first signal conductor layer) and the signal conductor layer 22 (second signal conductor layer) is present becomes high.
  • the characteristic impedance of the portion where the interlayer connection conductor v4 that connects the signal electrode 28b (first signal conductor layer) and the signal conductor layer 22 (second signal conductor layer) exists can be adjusted. .
  • the thickness of the multilayer substrate 10 can be reduced. More specifically, in the multilayer substrate 10, the first cavity Sp1 overlaps at least a portion of the interlayer connection conductor v4 when viewed in the vertical direction, and also overlaps the signal conductor layer 22 (second signal conductor layer) in the vertical direction. It is located between the first reference conductor layer 26 . As a result, the dielectric constant between the portion of the signal conductor layer 22 to which the interlayer connection conductor v4 is connected and the first reference conductor layer 26 is lowered. That is, the capacitance between the portion of the signal conductor layer 22 to which the interlayer connection conductor v4 is connected and the first reference conductor layer 26 is reduced.
  • the portion of the signal conductor layer 22 to which the interlayer connection conductor v4 is connected is The capacitance with the first reference conductor layer 26 does not become too large. As a result, according to the multilayer substrate 10, the thickness of the multilayer substrate 10 can be reduced.
  • the first cavity Sp1 can be easily formed. More specifically, the first reference conductor layer 26 is provided with one or more through holes h ⁇ b>1 penetrating through the first reference conductor layer 26 in the vertical direction. As a result, the insulating layer 16c is etched using the first reference conductor layer 26 as a mask, thereby removing the portion of the insulating layer 16c adjacent to the through hole h1. Thereby, the first cavity Sp1 connected to the through hole h1 can be formed. Thus, according to the multilayer substrate 10, the first cavity Sp1 can be easily formed using the through hole h1.
  • multilayer substrate 10 high shielding properties for the signal conductor layer 22 can be obtained. More specifically, multilayer substrate 10 includes a second reference conductor layer 24 positioned above signal conductor layer 22 and a first reference conductor layer 26 positioned below signal conductor layer 22 . Therefore, the signal conductor layer 22, the second reference conductor layer 24 and the first reference conductor layer 26 have a stripline structure. Thereby, the signal conductor layer 22 is shielded by the second reference conductor layer 24 and the first reference conductor layer 26 . Therefore, according to the multilayer substrate 10, a high shielding property for the signal conductor layer 22 can be obtained. Furthermore, since the through hole h1 is smaller than the first cavity Sp1 when viewed in the vertical direction, the first reference conductor layer 26 has high shielding properties.
  • the multilayer substrate 10 since the material of the insulator layers 16a to 16c is thermoplastic resin, the multilayer substrate 10 can be easily plastically deformed. Therefore, it is easy to maintain the bent state of the multilayer substrate 10 .
  • the plastic deformation of the multilayer substrate 10 facilitates the arrangement of the multilayer substrate 10 along the narrow space formed in the electronic device.
  • FIG. 5 is a cross-sectional view of the right end portion of the multilayer substrate 10a.
  • FIG. 6 is a cross-sectional view orthogonal to the left-right direction of the multilayer substrate 10a.
  • the multilayer substrate 10a differs from the multilayer substrate 10 in that the signal conductor layer 22 and the first reference conductor layer 26 have a microstrip line structure. More specifically, in the multilayer substrate 10a, the second reference conductor layer 24 does not overlap the signal conductor layer 22 when viewed in the vertical direction. The rest of the structure of the multilayer substrate 10a is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multi-layer substrate 10a can have the same effect as the multi-layer substrate 10. FIG.
  • FIG. 7 is a cross-sectional view orthogonal to the horizontal direction of the multilayer substrate 10b.
  • FIG. 5 is used for the cross-sectional view of the right end portion of the multilayer substrate 10b.
  • the multilayer substrate 10b differs from the multilayer substrate 10a in that it further includes reference conductor layers 23a and 23b.
  • the reference conductor layers 23a and 23b are located on the upper main surface of the insulator layer 16b.
  • the reference conductor layer 23 a is positioned in front of the signal conductor layer 22 .
  • the reference conductor layer 23b is positioned behind the signal conductor layer 22.
  • the reference conductor layers 23 a and 23 b extend along the signal conductor layer 22 .
  • the signal conductor layer 22 and the reference conductor layers 23a and 23b have a coplanar structure.
  • the first reference conductor layer 26 is connected to the reference conductor layers 23a and 23b via interlayer connection conductors (not shown).
  • the rest of the structure of the multilayer substrate 10b is the same as that of the multilayer substrate 10a, so the description is omitted.
  • the multilayer substrate 10b can have the same effect as the multilayer substrate 10a.
  • FIG. 8 is a cross-sectional view of the multilayer substrate 10c.
  • the multilayer substrate 10c differs from the multilayer substrate 10 in that the second cavity Sp2 is provided in the laminate 12. More specifically, the multi-layer board 10c includes a signal conductor layer 25. As shown in FIG. The signal conductor layer 25 is located on the upper main surface of the insulator layer 16a. The signal conductor layer 25 extends in the left-right direction. The left end portion of the signal conductor layer 25 overlaps the right end portion of the signal conductor layer 22 when viewed in the vertical direction. Further, the interlayer connection conductor v4 is in contact with the signal conductor layer 25 (first signal conductor layer) and the signal conductor layer 22 (second signal conductor layer) by vertically penetrating the insulator layer 16a.
  • the laminate 12 further includes an insulator layer 16d.
  • the insulator layer 16d is laminated on the insulator layer 16a.
  • the second reference conductor layer 24 is located on the upper main surface of the insulator layer 16d. Thereby, the second reference conductor layer 24 is positioned above (in the first direction) the signal conductor layer 25 (first signal conductor layer).
  • the second reference conductor layer 24 overlaps at least a portion of the overlapping portion 22c when viewed in the vertical direction.
  • the laminate 12 is provided with a second cavity Sp2 in which the insulator layers 16a to 16d do not exist.
  • the second cavity Sp2 overlaps at least a portion of the interlayer connection conductor v4 when viewed in the vertical direction, and is between the signal conductor layer 25 (first signal conductor layer) and the second reference conductor layer 24 in the vertical direction. positioned.
  • the second reference conductor layer 24 is provided with one or more through holes h2 penetrating through the second reference conductor layer 24 in the vertical direction.
  • One or more through holes h2 are connected to the second cavity Sp2.
  • the number of one or more through-holes h2 is one.
  • the through hole h2 has a circular shape when viewed in the vertical direction.
  • the diameter of the through hole h2 is smaller than the diameter of the second cavity Sp2 and the diameter of the overlapping portion 22c.
  • the through hole h2 is positioned at the center of the second cavity Sp2 and the center of the overlapping portion 22c when viewed in the vertical direction. Thereby, the through hole h2 is positioned inside the outer edge of the second cavity Sp2 when viewed in the vertical direction.
  • the through hole h2 is located inside the outer edge of the overlapping portion 22c when viewed in the vertical direction.
  • the through hole h2 overlaps the interlayer connection conductor v4 when viewed in the vertical direction.
  • the rest of the structure of the multilayer substrate 10c is the same as that of the multilayer substrate 10, so description thereof will be omitted. According to the multilayer substrate 10c, the same effects as those of the multilayer substrate 10 can be obtained.
  • the second cavity Sp2 overlaps at least a portion of the interlayer connection conductor v4 when viewed in the vertical direction, and also overlaps with the signal conductor layer 25 (first signal conductor layer) in the vertical direction. It is located between the second reference conductor layer 24 and the second reference conductor layer 24 . As a result, the dielectric constant between the portion of the signal conductor layer 25 to which the interlayer connection conductor v4 is connected and the second reference conductor layer 24 is lowered.
  • the capacitance between the portion of the signal conductor layer 25 to which the interlayer connection conductor v4 is connected and the second reference conductor layer 24 is reduced.
  • the distance between the portion of the signal conductor layer 25 to which the interlayer connection conductor v4 is connected and the second reference conductor layer 24 is reduced.
  • the capacitance with the second reference conductor layer 24 does not become too large.
  • FIG. 9 is a cross-sectional view of the multilayer board module 200. As shown in FIG.
  • the multilayer board module 200 includes a multilayer board 10 (first multilayer board) and a multilayer board 110 (second multilayer board).
  • the multilayer substrate 110 has a vertically symmetrical structure with the multilayer substrate 10 . Therefore, the structures of the multilayer substrate 110 are given reference numerals obtained by adding 100 to the reference numerals of the structures of the multilayer substrate 10 .
  • the multilayer substrate 110 is positioned above the multilayer substrate 10 .
  • the right end portion of the multilayer substrate 10 overlaps the left end portion of the multilayer substrate 110 when viewed in the vertical direction.
  • the signal electrode 28b (first signal conductor layer) of the multilayer substrate 10 (first multilayer substrate) is fixed to the signal electrode 128b (first signal conductor layer) of the multilayer substrate 110 (second multilayer substrate) with a conductive bonding material 300.
  • the conductive bonding material 300 is, for example, solder or a conductive adhesive.
  • the first cavities Sp1 and Sp101 overlap the conductive bonding material 300 when viewed in the vertical direction.
  • the thickness of the multilayer board module 200 can be reduced. More specifically, it is difficult to reduce the thickness of the portion where the multilayer substrate 10 and the multilayer substrate 110 are connected because the conductive bonding material 300 exists. Therefore, as already explained, thinning of the multilayer substrates 10 and 110 is attempted. Multilayer substrates 10 and 110 are connected to each other at portions where multilayer substrates 10 and 110 are thinned. As a result, the thickness of the portion where the multilayer substrate 10 and the multilayer substrate 110 are connected can be reduced. As a result, according to the multilayer board module 200, the thickness of the multilayer board module 200 can be reduced.
  • FIG. 10 is a cross-sectional view of the multilayer board module 200a.
  • the multilayer board module 200a differs from the multilayer board module 200 in that the first cavity Sp101 is not provided in the multilayer board 110.
  • the rest of the structure of the multilayer board module 200a is the same as that of the multilayer board module 200, so the description is omitted.
  • the multi-layer board module 200a can have the same effects as the multi-layer board module 200. FIG.
  • FIG. 11 is a cross-sectional view of the multilayer substrate 10d.
  • the multilayer substrate 10d differs from the multilayer substrate 10 in that the laminate 12 has a first area A11 and a second area A12.
  • the first area A11 is located to the right of the second area A12.
  • the first area A11 and the second area A12 are adjacent to each other.
  • the bending rigidity of the first area A11 is higher than the bending rigidity of the second area A12.
  • the bending stiffness can be measured, for example, by the amount of deformation of each of the first area A11 and the second area A12 when the same force is applied to each of the first area A11 and the second area A12.
  • the insulator layers 16a to 16e are stacked vertically.
  • Insulator layers 16a to 16c are stacked vertically in the second region A12.
  • the size of the first area A11 in the vertical direction is larger than the size of the second area A12 in the vertical direction.
  • the bending rigidity of the first area A11 is higher than the bending rigidity of the second area A12.
  • the first cavity Sp1 is located in the first region A11.
  • the rest of the structure of the multilayer substrate 10d is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multi-layer substrate 10d can have the same effect as the multi-layer substrate 10.
  • the bending rigidity of the first area A11 is higher than the bending rigidity of the second area A12. Therefore, even if the first cavity Sp1 is located in the first region A11, it is easy to ensure sufficient bending rigidity of the first region A11. Further, since the first region A11 is difficult to deform, the first cavity Sp1 is also difficult to deform.
  • FIG. 12 is a top view of the multilayer substrate 10e.
  • the multilayer substrate 10e is seen through.
  • FIG. 13 is a cross-sectional view of the multilayer substrate 10e.
  • the multilayer substrate 10e differs from the multilayer substrate 10 in the structure of the signal electrodes 28b.
  • the overlapping portion 22c is connected to the right end of the linear portion 22a.
  • the signal electrode 28b has a rectangular shape with long sides extending in the front-rear direction.
  • the interlayer connection conductor v4 overlaps the rear portion of the signal electrode 28b when viewed in the vertical direction.
  • the interlayer connection conductor v4 is in contact with the signal electrode 28b (first signal conductor layer) and the signal conductor layer 22 (second signal conductor layer) by vertically penetrating the insulator layer 16a. Thereby, the signal electrode 28b and the signal conductor layer 22 are electrically connected.
  • the laminate 12 is provided with a third cavity Sp3 in which the insulator layers 16a to 16c do not exist.
  • the third cavity Sp3 is positioned between the signal conductor layer 22 (second signal conductor layer) and the first reference conductor layer 26 in the vertical direction.
  • the third cavity Sp3 is positioned between the signal electrode 28b (first signal conductor layer) and the first reference conductor layer 26 in the vertical direction.
  • the third cavity Sp3 does not overlap the interlayer connection conductor when viewed in the vertical direction.
  • the third cavity Sp3 partially overlaps the signal electrode 28b when viewed in the vertical direction.
  • the rest of the structure of the multilayer substrate 10e is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multilayer substrate 10 e can have the same effect as the multilayer substrate 10 .
  • first cavity Sp1 and the third cavity Sp3 may be connected.
  • the third cavity Sp3 does not overlap the interlayer connection conductor when viewed in the vertical direction.
  • FIG. 14 is a cross-sectional view of the multilayer substrate 10f.
  • the multilayer substrate 10f differs from the multilayer substrate 10 in the size of the first cavity Sp1.
  • the first cavity Sp1 of the multilayer substrate 10f is larger than the first cavity Sp1 of the multilayer substrate 10.
  • the first cavity Sp1 is in contact with the signal conductor layer 22 (second conductor layer). More precisely, the upper end of the first cavity Sp1 is in contact with the overlapping portion 22c.
  • the rest of the structure of the multilayer substrate 10f is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multi-layer board 10f can have the same effect as the multi-layer board 10. FIG.
  • the first cavity Sp1 of the multilayer substrate 10f is larger than the first cavity Sp1 of the multilayer substrate 10. As a result, the capacitance between the portion of the signal conductor layer 22 to which the interlayer connection conductor v4 is connected and the first reference conductor layer 26 is reduced.
  • FIG. 15 is a cross-sectional view of the multilayer substrate 10g.
  • the multilayer substrate 10g differs from the multilayer substrate 10 in the size of the first cavity Sp1.
  • the first cavity Sp1 of the multilayer substrate 10f is larger than the first cavity Sp1 of the multilayer substrate 10.
  • FIG. Thereby, the first cavity Sp1 is in contact with the interlayer connection conductor v4. More precisely, the upper end of the first cavity Sp1 is positioned above the overlapping portion 22c. As a result, the lower end of the interlayer connection conductor v4 is located in the first cavity Sp1.
  • the rest of the structure of the multilayer substrate 10g is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multi-layer board 10g can have the same effect as the multi-layer board 10.
  • the first cavity Sp1 of the multilayer substrate 10g is larger than the first cavity Sp1 of the multilayer substrate 10. As a result, the capacitance between the portion of the signal conductor layer 22 to which the interlayer connection conductor v4 is connected and the first reference conductor layer 26 is reduced.
  • FIG. 16 is a cross-sectional view of the multilayer substrate 10h.
  • the multilayer substrate 10h differs from the multilayer substrate 10 in the size of the first cavity Sp1.
  • the first cavity Sp ⁇ b>1 of the multilayer substrate 10 h is larger than the first cavity Sp ⁇ b>1 of the multilayer substrate 10 .
  • the first cavity Sp1 is in contact with the signal electrode 28b.
  • the rest of the structure of the multilayer substrate 10h is the same as that of the multilayer substrate 10, so the explanation is omitted.
  • the multi-layer board 10h can have the same effect as the multi-layer board 10. FIG.
  • the first cavity Sp1 of the multilayer substrate 10h is larger than the first cavity Sp1 of the multilayer substrate 10. As a result, the capacitance between the portion of the signal conductor layer 22 to which the interlayer connection conductor v4 is connected and the first reference conductor layer 26 is reduced.
  • FIG. 17 is a top view of the multilayer substrate 10i. In FIG. 17, the multilayer substrate 10i is seen through.
  • the multilayer substrate 10i differs from the multilayer substrate 10 in the number of through holes h1a to h1d.
  • the multilayer substrate 10i has a plurality of through holes h1a to h1d connected to the first cavity Sp1.
  • the number of through holes h1a to h1d is four.
  • each area of the through holes h1a to h1d is smaller than the area of the through hole h1.
  • the first cavity Sp1 has a shape in which four circles centered on the through holes h1a to h1d are superimposed when viewed in the vertical direction.
  • the rest of the structure of the multilayer substrate 10i is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multilayer substrate 10i can have the same effect as the multilayer substrate 10.
  • the number of through holes h1a to h1d connected to the first cavity Sp1 is plural. Accordingly, when viewed in the vertical direction, each area of the through holes h1a to h1d may be smaller than the area of the through hole h1. As a result, leakage of the electromagnetic field to the outside of the multilayer substrate 10i through the through holes h1a to h1d is suppressed.
  • FIG. 18 is a top view of the multilayer substrate 10j. In FIG. 18, the multilayer substrate 10j is seen through.
  • the multilayer substrate 10j differs from the multilayer substrate 10 in the shape of the through hole h1 and the shape of the first cavity Sp1.
  • the through hole h1 has an oval shape extending in the horizontal direction when viewed in the vertical direction.
  • the first cavity Sp1 has an oval shape extending in the horizontal direction when viewed in the vertical direction.
  • the rest of the structure of the multilayer substrate 10j is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multilayer substrate 10j can have the same effect as the multilayer substrate 10. FIG.
  • the oval first cavity Sp1 can be formed.
  • FIG. 19 is a cross-sectional view of the multilayer substrate 10k.
  • FIG. 20 is a top view of the multilayer substrate 10k. In FIG. 20, the multilayer substrate 10k is seen through.
  • FIG. 21 is an equivalent circuit diagram near the interlayer connection conductor v4.
  • the multilayer substrate 10k differs from the multilayer substrate 10 in the position of the first cavity Sp1 and the shape of the first cavity Sp1. More specifically, the first cavity Sp1 has an oval shape extending in the horizontal direction when viewed in the vertical direction. In addition, the center of the first cavity Sp1 is positioned to the left of the overlapping portion 22c when viewed in the vertical direction. As a result, the first cavity Sp1 overlaps the overlapping portion 22c and the linear portion 22a when viewed in the vertical direction. When viewed in the vertical direction, the length in the left-right direction of the region where the first cavity Sp1 and the linear portion 22a overlap is shorter than the length in the left-right direction of the overlap between the first cavity Sp1 and the overlapping portion 22c. .
  • the capacitance between the right end of the linear portion 22a and the first reference conductor layer 26 is reduced. That is, the linear portion 22a functions as an inductor L, as shown in FIG.
  • the capacitance between the overlapping portion 22c that does not overlap with the first cavity Sp1 and the first reference conductor layer 26 increases. That is, the portion of the overlapping portion 22c that does not overlap with the first cavity Sp1 and the first reference conductor layer 26 function as a capacitor C, as shown in FIG.
  • a low-pass filter is formed from the above.
  • the rest of the structure of the multilayer substrate 10k is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multi-layer board 10k can have the same effect as the multi-layer board 10.
  • the multilayer substrate 10k it is possible to form a low-pass filter depending on the position of the first cavity Sp1 and the shape of the first cavity Sp1. Therefore, noise can be reduced in the multilayer substrate 10k.
  • the right end portion of the signal conductor layer 22 can function as the inductor L without reducing the line width of the right end portion of the signal conductor layer 22 . Therefore, an increase in the DC resistance value of the signal conductor layer 22 can be suppressed.
  • the portion of the signal conductor layer 22 located to the right of the interlayer connection conductor v4 functions as an open stub.
  • FIG. 22 is a cross-sectional view of the multilayer substrate 10l.
  • the multilayer substrate 10l differs from the multilayer substrate 10 in that the plurality of insulator layers further includes an insulator layer 19 (first insulator layer).
  • the insulator layer 19 (first insulator layer) is positioned between the signal conductor layer 22 (second signal conductor layer) and the first cavity Sp1.
  • the insulator layer 19 is positioned between the insulator layer 16b and the insulator layer 16c.
  • the insulator layer 19 overlaps the first cavity Sp1 when viewed in the vertical direction.
  • Such an insulator layer 19 is an adhesive layer that bonds the insulator layer 16b and the insulator layer 16c.
  • the material of insulator layer 19 (first insulator layer) is more difficult to etch than the material of the remaining insulator layers 16a-16c.
  • the first cavity Sp1 is located below the insulator layer 19 and not above the insulator layer 19 .
  • the insulator layer 19 may also be positioned between the insulator layers 16a and 16b.
  • the rest of the structure of the multilayer substrate 10l is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multi-layer board 10l can have the same effect as the multi-layer board 10. FIG.
  • the insulator layer 19 (first insulator layer) is located between the signal conductor layer 22 (second signal conductor layer) and the first cavity Sp1.
  • the material of insulator layer 19 (first insulator layer) is more difficult to etch than the material of the remaining insulator layers 16a-16c.
  • the first cavity Sp ⁇ b>1 is not formed in the insulator layer 19 .
  • the material of the insulator layer 19 is, for example, Teflon (registered trademark) which is difficult to be etched by chemicals.
  • FIG. 23 is a cross-sectional view of the multilayer substrate 10m.
  • the multilayer substrate 10m differs from the multilayer substrate 10 in that it further includes a dummy conductor layer 60.
  • the dummy conductor layer 60 is located between the signal conductor layer 22 (second signal conductor layer) and the first cavity Sp1.
  • the insulator layer 16d is laminated between the insulator layers 16b and 16c.
  • the dummy conductor layer 60 is located on the lower main surface of the insulator layer 16d.
  • the dummy conductor layer 60 overlaps the first cavity Sp1 when viewed in the vertical direction.
  • the dummy conductor layer 60 is not connected to reference potential or signal potential. Therefore, the potential of the dummy conductor layer 60 is a floating potential.
  • the rest of the structure of the multilayer substrate 10m is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multi-layer board 10m can have the same effect as the multi-layer board 10. FIG.
  • the dummy conductor layer 60 is positioned between the signal conductor layer 22 (second signal conductor layer) and the first cavity Sp1.
  • the dummy conductor layer 60 is hardly etched. Accordingly, the first cavity Sp1 is not formed above the dummy conductor layer 60. As shown in FIG. As a result, manufacturing variations of the first cavity Sp1 are suppressed.
  • the dummy conductor layer 60 overlaps the interlayer connection conductor v4 when viewed in the vertical direction.
  • FIG. 24 is a cross-sectional view of the multilayer substrate 10n.
  • the multilayer substrate 10n differs from the multilayer substrate 10 in that the protective layer 18b is provided with a through hole h50.
  • the through hole h50 vertically penetrates the protective layer 18b.
  • the through hole h50 overlaps the through hole h1 and the first cavity Sp1 when viewed in the vertical direction. Thereby, the through hole h50 is connected to the through hole h1 and the first cavity Sp1.
  • the rest of the structure of the multilayer substrate 10n is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multi-layer board 10n can have the same effects as the multi-layer board 10.
  • the air in the first cavity Sp1 expands due to heat, the air can exit the first cavity Sp1 through the through holes h1 and h50. This suppresses the separation of the first reference conductor layer 26 from the insulator layer 16c.
  • FIG. 25 is a cross-sectional view of the multilayer substrate 10o.
  • the multilayer substrate 10o differs from the multilayer substrate 10 in the material of the protective layer 18b.
  • the material of the protective layer 18b is a porous material having air permeability.
  • the rest of the structure of the multilayer substrate 10o is the same as that of the multilayer substrate 10, so the description is omitted.
  • the multilayer substrate 10 o can have the same effects as the multilayer substrate 10 .
  • the air in the first cavity Sp1 expands due to heat, the air can exit the first cavity Sp1 through the protective layer 18b having air permeability. This suppresses the separation of the first reference conductor layer 26 from the insulator layer 16c. In addition, entry of foreign matter into the first cavity Sp1 is suppressed.
  • the transmission line according to the present invention is not limited to the multilayer substrates 10, 10a to 10o, and can be modified within the scope of the subject matter.
  • the structures of the multilayer substrates 10, 10a to 10o may be combined arbitrarily.
  • the second reference conductor layer 24 is not an essential component in the multilayer substrates 10, 10a to 10o.
  • the first signal conductor layer may be a conductor layer through which high frequency signals are transmitted. Therefore, the first signal conductor layer may be the signal electrode 28b having a rectangular shape, or the signal conductor layer 25 having a linear shape. Also, the first signal conductor layer may be, for example, a small conductor layer disposed between two vertically aligned interlayer connection conductors.
  • the frequency of the high-frequency signal is, for example, 10 MHz or higher.
  • the first cavity Sp1 may partially overlap the interlayer connection conductor v1 or may overlap the entire interlayer connection conductor v1 when viewed in the vertical direction.
  • the first cavity Sp1 may be located in the second region A12. In this case, the thickness of the second region A12 can be reduced.
  • the thickness of the multilayer board 10 in the vertical direction may be smaller than the thickness of the multilayer board 110 in the vertical direction.
  • the thickness of the multilayer substrate 110 can be reduced.
  • protective layers 18a and 18b are not essential constituent elements.
  • the material of the insulator layers 16a to 16c may be resin other than thermoplastic resin, or may be ceramic.
  • the multilayer substrate 10e may further include interlayer connection conductors.
  • An interlayer connection conductor is provided in the laminate 12 .
  • the interlayer connection conductor overlaps the front portion of the overlapping portion 22c when viewed in the vertical direction.
  • the interlayer connection conductor is in contact with the signal electrode 28b (first signal conductor layer) and the signal conductor layer 22 (second signal conductor layer) by vertically penetrating the insulator layer 16a. Thereby, the signal electrode 28b and the signal conductor layer 22 are electrically connected.
  • the third cavity Sp3 overlaps at least a portion of the interlayer connection conductor when viewed in the vertical direction.
  • the third cavity Sp3 may overlap the entire interlayer connection conductor when viewed in the vertical direction.
  • the laminate 12 may be provided with a plurality of third cavities Sp3 that do not overlap the interlayer connection conductors.
  • the third cavity Sp3 may be positioned between the signal electrode 28b or the signal conductor layer 22 and the first reference conductor layer 26 in the vertical direction.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

La présente invention est un substrat multicouche. Une seconde couche conductrice de signal est positionnée dans une seconde direction par rapport à une première couche conductrice de signal, et comprend une partie de chevauchement qui chevauche la première couche conductrice de signal telle qu'observée dans la direction verticale. Un conducteur de connexion intercouche chevauche la partie de chevauchement telle qu'observée dans la direction verticale, et est en contact avec les première et seconde couches de conducteur de signal. Une première couche conductrice de référence est positionnée dans la seconde direction par comparaison à la seconde couche conductrice de signal, et chevauche au moins une partie de la partie de chevauchement telle qu'observée dans la direction verticale. Une première cavité chevauche au moins une partie du conducteur de connexion intercouche, vue dans la direction verticale, et est positionnée entre la seconde couche conductrice de signal et la première couche conductrice de référence dans la direction verticale.
PCT/JP2022/022909 2021-06-25 2022-06-07 Substrat multicouche, module de substrat multicouche et dispositif électronique WO2022270294A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04116892A (ja) * 1990-09-06 1992-04-17 Fujitsu Ltd 多層セラミック基板およびその製造方法
JPH04221890A (ja) * 1990-12-25 1992-08-12 Fujitsu Ltd 多層セラミック基板とその製造方法
WO2017110389A1 (fr) * 2015-12-22 2017-06-29 株式会社デンソー Substrat multicouche et procédé de fabrication de substrat multicouche
WO2019131286A1 (fr) * 2017-12-28 2019-07-04 株式会社村田製作所 Substrat multicouche et dispositif de ligne de transmission

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04116892A (ja) * 1990-09-06 1992-04-17 Fujitsu Ltd 多層セラミック基板およびその製造方法
JPH04221890A (ja) * 1990-12-25 1992-08-12 Fujitsu Ltd 多層セラミック基板とその製造方法
WO2017110389A1 (fr) * 2015-12-22 2017-06-29 株式会社デンソー Substrat multicouche et procédé de fabrication de substrat multicouche
WO2019131286A1 (fr) * 2017-12-28 2019-07-04 株式会社村田製作所 Substrat multicouche et dispositif de ligne de transmission

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