WO2017107274A1 - 一种低温多晶硅薄膜晶体管及其制备方法 - Google Patents

一种低温多晶硅薄膜晶体管及其制备方法 Download PDF

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WO2017107274A1
WO2017107274A1 PCT/CN2016/071397 CN2016071397W WO2017107274A1 WO 2017107274 A1 WO2017107274 A1 WO 2017107274A1 CN 2016071397 W CN2016071397 W CN 2016071397W WO 2017107274 A1 WO2017107274 A1 WO 2017107274A1
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layer
thin film
film transistor
buffer layer
buffer
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卢改平
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters
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    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/425—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer having different crystal properties in different TFTs or within an individual TFT
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Definitions

  • the invention relates to the field of display technology, in particular to a low temperature polysilicon thin film transistor and a preparation method thereof.
  • Thin film transistors are used as switching elements in liquid crystal display devices. They have low power consumption, small size, and low driving voltage, making them ideal for computers, notebooks, and other devices. display screen.
  • the active layer of the thin film transistor mainly uses amorphous silicon (a-Si), but the mobility of the thin film transistor using amorphous silicon as an active layer is very low, and it is difficult to meet the driving requirements of the peripheral circuit. Therefore, the technology of using low temperature poly-silicon (LTPS) instead of amorphous silicon has emerged.
  • a-Si amorphous silicon
  • LTPS low temperature poly-silicon
  • the low-temperature polysilicon mobility can be as high as 100cm 2 /VS, which can meet the peripheral electric drive requirements, is more suitable for the active layer of the thin film transistor than amorphous silicon, and can be more compact than the amorphous silicon thin film transistor.
  • the principle of manufacturing a low-temperature polysilicon thin film transistor structure is mainly to use an excimer laser as a heat source to be projected on a glass substrate of an amorphous silicon structure, so that the amorphous silicon structure substrate absorbs the energy of the excimer laser and then transforms into a polysilicon structure.
  • the process for manufacturing a low-temperature polysilicon thin film transistor mainly includes a conventional excimer laser annealing method (ELA) without using a mask and a continuous side crystallization method using a mask to control a laser irradiation region (Sequential Lateral). Solidification, referred to as SLS).
  • ELA excimer laser annealing method
  • SLS Solidification
  • the grain size of the low-temperature polycrystalline silicon is generally 0.1 ⁇ m or less.
  • the crystallization process is induced from the end portion of the irradiation region to the inside, and finally the crystallization of the central portion of the irradiation region is performed.
  • the object of the present invention is to provide a low temperature polysilicon film crystal.
  • the tube and the preparation method thereof can finally obtain polycrystalline silicon having a large crystal grain size, improve the electron mobility of the thin film transistor, and satisfy the driving requirement of the peripheral circuit.
  • the invention provides a low temperature polysilicon thin film transistor, the thin film transistor comprising:
  • a gate insulating layer formed on the buffer layer and the semiconductor layer
  • first contact hole and a second contact hole respectively in the interior of the passivation layer, the dielectric layer and the gate insulating layer, respectively on the first contact hole and the second contact hole Forming a source and a drain;
  • the semiconductor layer is a low temperature polysilicon layer, and a reflective layer and/or a heat insulating layer is further disposed between the buffer layer and the semiconductor layer.
  • the low temperature polysilicon thin film transistor includes a pixel thin film transistor and a driving thin film transistor
  • the substrate includes a pixel region and a peripheral driving region
  • the pixel region is used to form the pixel thin film transistor
  • the peripheral driving region is used for forming The driving thin film transistor
  • the driving thin film transistor includes a substrate located in the peripheral driving region, and the buffer layer, the semiconductor layer, the gate insulating layer, the gate electrode, which are sequentially formed on the substrate in the peripheral driving region, a dielectric layer and the passivation layer; forming a first contact hole and a second contact hole in the interior of the passivation layer, the dielectric layer and the gate insulating layer, respectively, in the first A source and a drain are respectively formed on the contact hole and the second contact hole; wherein the reflective layer and/or the heat insulating layer are disposed between the buffer layer and the semiconductor layer.
  • the pixel thin film transistor includes: a substrate in the pixel region, the buffer layer, the semiconductor layer, the gate insulating layer, and the gate sequentially formed on a substrate in the pixel region a dielectric layer and the passivation layer; forming a first contact hole and a second contact hole in the interior of the passivation layer, the dielectric layer and the gate insulating layer, respectively A source and a drain are formed on a contact hole and the second contact hole, respectively.
  • a grain size of the semiconductor layer located in the driving thin film transistor is larger than a grain size of the semiconductor layer located in the pixel thin film transistor.
  • the buffer layer includes a first buffer layer formed on the substrate, and the reflective layer is formed on the first buffer layer, and the first buffer layer and the reflective layer are formed on the first buffer layer a second buffer layer, and the reflective layer is covered in the second buffer layer, and the semiconductor layer is formed on the second buffer layer.
  • the material of the reflective layer is any one or a combination of Mo, Al, AlNd, Cr, Cu, W, Ta or Ti, and more preferably, the material of the reflective layer is Mo.
  • the reflective layer is a metal molybdenum layer.
  • the material of the first buffer layer and the second buffer layer is one or a combination of silicon nitride or silicon dioxide.
  • the first buffer layer is a silicon nitride layer
  • the second buffer layer is a silicon dioxide layer.
  • the buffer layer includes a first buffer layer and a second buffer layer sequentially formed over the substrate, and the heat insulating layer is formed on the second buffer layer, and the semiconductor layer is formed on the first layer Two buffer layers, above the insulation layer.
  • the insulating layer is an aluminum oxide layer.
  • the material of the first buffer layer and the second buffer layer is one or a combination of silicon nitride or silicon dioxide.
  • the first buffer layer is a silicon nitride layer
  • the second buffer layer is a silicon dioxide layer.
  • the substrate is a glass substrate.
  • the present invention also provides a method for preparing a low temperature polysilicon thin film transistor, comprising the following steps:
  • a source and a drain are formed on the first contact hole and the second contact hole, respectively.
  • a first buffer layer is formed on the substrate, the reflective layer is formed on the first buffer layer, and a pattern of the reflective layer is defined by photolithography and etching processes; Depositing a buffer layer on the reflective layer to form a second buffer layer, and coating the reflective layer in the second buffer layer; depositing the amorphous silicon layer on the second buffer layer to perform laser Irradiation causes the amorphous silicon layer to become a polysilicon layer to obtain the semiconductor layer.
  • the material of the reflective layer is any one or a combination of Mo, Al, AlNd, Cr, Cu, W, Ta or Ti, and more preferably, the material of the reflective layer is Mo.
  • the reflective layer is a metal molybdenum layer.
  • the material of the first buffer layer and the second buffer layer is one or a combination of silicon nitride or silicon dioxide.
  • the first buffer layer is a silicon nitride layer
  • the second buffer layer is a silicon dioxide layer.
  • a first buffer layer and a second buffer layer are sequentially deposited on the substrate; the heat insulating layer is deposited on the second buffer layer, and a pattern of the heat insulating layer is defined by photolithography and etching processes. And forming the amorphous silicon layer on the second buffer layer and the heat insulating layer, and performing laser irradiation to change the amorphous silicon layer into a polysilicon layer to obtain the semiconductor layer.
  • the insulating layer is an aluminum oxide layer.
  • the material of the first buffer layer and the second buffer layer is one or a combination of silicon nitride or silicon dioxide.
  • the first buffer layer is a silicon nitride layer
  • the second buffer layer is a silicon dioxide layer.
  • the method for forming the layer structure of the low temperature thin film transistor is a chemical vapor deposition method or Physical vapor deposition method.
  • an amorphous silicon layer is formed on the buffer layer, the reflective layer, and/or the insulating layer, and laser irradiation is performed to change the amorphous silicon layer into a polysilicon layer, and the polysilicon layer is a semiconductor layer.
  • the method is an excimer laser annealing (ELA) or a solid phase crystallization (SPC) method.
  • the substrate is a glass substrate.
  • the present invention by providing a reflective layer and/or a heat insulating layer under the amorphous silicon layer, after the laser light is irradiated through the amorphous silicon layer, it is again reflected back from the reflective layer to the amorphous silicon layer to increase the crystal grain size or The crystallization time of the amorphous silicon layer is prolonged by the heat preservation effect of the heat insulating layer, and a larger-sized polycrystalline silicon crystal grain is obtained.
  • the reflective layer and/or the insulating layer are disposed only in the peripheral driving region, the polycrystalline silicon crystal size obtained by laser irradiation can be larger than the polycrystalline silicon crystal size in the pixel region, and the larger crystal grain size is beneficial to the peripheral driving region. Larger electron mobility, which in turn drives the drive efficiency of the peripheral drive area.
  • FIGS. 1 to 11 are diagrams showing a preparation process of a low temperature polysilicon thin film transistor of Embodiment 1.
  • the embodiment provides a low temperature polysilicon thin film transistor including a pixel thin film transistor and a driving thin film transistor, and the low temperature polysilicon thin film transistor is prepared as follows:
  • a glass substrate 1 which includes a pixel region 100 on the left side and a peripheral driving region 200 on the right side.
  • a pixel thin film transistor is formed in the pixel region 100, and a driving thin film transistor as a driving unit is formed in the peripheral driving region 200.
  • CVD chemical vapor deposition
  • the first buffer layer being a silicon nitride layer; then, as shown in FIG. 2, using a chemical vapor deposition method
  • a metal molybdenum layer 31 is deposited as a reflective layer on a buffer layer 21, and a pattern of a metal molybdenum layer as shown in FIG. 3 is defined by photolithography and etching processes.
  • the metal molybdenum layer located in the pixel region 100 is etched away by photolithography and etching processes, and only the metal molybdenum layer 31 is provided in the peripheral driving region 200; then, as shown in FIG. 4,
  • the chemical vapor deposition method deposits a second buffer layer 22 on the first buffer layer 21 and the metal molybdenum layer 31, and coats the metal molybdenum layer 31 in the second buffer layer 22, which is a silicon dioxide layer. .
  • an amorphous silicon layer 41 is deposited on the second buffer layer 22 by a chemical vapor deposition method, and an amorphous silicon layer is formed by excimer laser annealing (ELA) or solid phase crystallization (SPC). 41 is converted into a polysilicon layer 42 located in the pixel region 100 and a polysilicon layer 43 located in the peripheral driving region 200, and a pattern of a polysilicon layer as shown in FIG. 6 is defined by a photolithography and etching process.
  • ELA excimer laser annealing
  • SPC solid phase crystallization
  • the metal molybdenum layer is not disposed under the amorphous silicon layer in the pixel region, the size of the polycrystalline silicon crystal formed in the peripheral driving region after crystallization is larger than the polycrystalline silicon crystal size formed in the pixel region.
  • the metal molybdenum layer in this embodiment may also be replaced by other materials having reflective properties, such as any one or a combination of several of Al, AlNd, Cr, Cu, W, Ta or Ti.
  • a gate insulating layer 5 is deposited on the second buffer layer 22, the polysilicon layer 42, and the polysilicon layer 43 by a chemical vapor deposition method, and the polysilicon layer 42 and the polysilicon layer 43 are coated on the gate.
  • a gate electrode 61 located in the pixel region 100 and a gate electrode 62 located in the peripheral driving region 100 are deposited on the gate insulating layer 5 by using a chemical vapor deposition method, and are defined by a photolithography and etching process as shown in FIG. The grid pattern shown.
  • a dielectric layer 7 is deposited on the gate insulating layer 5, the gate electrode 61, and the gate electrode 62 by using a chemical vapor deposition method, and the gate electrode 61 and the gate electrode 62 are coated on the dielectric layer.
  • the dielectric layer 7 is a silicon dioxide layer.
  • a passivation layer 8 is formed over the dielectric layer 7 using a chemical vapor deposition method, and the passivation layer 8 is a silicon nitride layer.
  • the passivation layer 8, the dielectric layer 7, and the gate insulating layer 5 are defined by photolithography and etching processes to form first contact holes 91, 93 and second contact holes 92, 94 as shown in FIG. The first contact hole and the second contact hole are respectively connected to the surface of the polysilicon layer.
  • a conductive layer is deposited using a chemical vapor deposition method, and a source 95 as shown in FIG. 10 is defined by a photolithography and etching process.
  • 97 and drains 96, 98 wherein source 95 and drain 96 are located within pixel region 100, and source 97 and drain 98 are located within peripheral drive region 200.
  • photolithography refers to a process of removing a specific portion of a wafer surface film through a series of production steps. After that, the wafer surface will leave a film with a micro-pattern structure. Passing lithography The art process, which ultimately retains the feature graphics on the wafer. This technology belongs to the common process technology in the field of preparing thin film transistors, and will not be described herein.
  • the etching process refers to a technique in which a material is removed using a chemical reaction or a physical impact. This technology belongs to the common process technology in the field of preparing thin film transistors, and will not be described herein.
  • the embodiment provides a low temperature polysilicon thin film transistor including a pixel thin film transistor and a driving thin film transistor, and the low temperature polysilicon thin film transistor is prepared as follows:
  • a glass substrate 1 which includes a pixel region 100 on the left side and a peripheral driving region 200 on the right side.
  • a pixel thin film transistor is formed in the pixel region 100, and a driving thin film transistor as a driving unit is formed in the peripheral driving region 200.
  • an aluminum oxide layer 32 is deposited as a heat insulating layer on the second buffer layer 22 by a chemical vapor deposition method, and a pattern of an aluminum oxide layer as shown in FIG. 14 is defined by photolithography and etching processes.
  • the aluminum oxide layer located in the pixel region 100 is etched away by photolithography and etching processes, and only the aluminum oxide layer 32 is provided in the peripheral driving region 200.
  • an amorphous silicon layer 41 is deposited on the second buffer layer 22 and the aluminum oxide layer 32 by a chemical vapor deposition method, and the aluminum oxide layer is coated in the amorphous silicon layer.
  • the amorphous silicon layer is transformed into a polysilicon layer 42 located in the pixel region 100, a polysilicon layer 43 located in the peripheral driving region 200 by excimer laser annealing (ELA) or solid phase crystallization (SPC), and then lithographically and etched.
  • ELA excimer laser annealing
  • SPC solid phase crystallization
  • excimer laser annealing ELA
  • SPC solid phase crystallization
  • an aluminum oxide layer having a heat insulating effect is disposed under the amorphous silicon layer.
  • the amorphous silicon layer of the peripheral driving region is crystallization longer by the heat insulating effect of the aluminum oxide layer, thereby obtaining a larger grain size than the amorphous silicon layer of the pixel region.
  • the larger grain size helps the peripheral drive region to achieve greater electron mobility, which in turn increases the drive efficiency of the peripheral drive region.
  • a gate insulating layer 5 is deposited on the second buffer layer 22, the polysilicon layer 42, and the polysilicon layer 43 by a chemical vapor deposition method, and the polysilicon layer 42 and the polysilicon layer 43 are coated on the gate.
  • a shape is deposited on the gate insulating layer 5 using a chemical vapor deposition method.
  • a gate electrode 61 located in the pixel region 100, a gate electrode 62 located in the peripheral driving region, and a gate pattern as shown in FIG. 18 are defined by photolithography and etching processes.
  • a dielectric layer 7 is deposited on the gate insulating layer 5, the gate electrode 61, and the gate electrode 62 by using a chemical vapor deposition method, and the gate electrode 61 and the gate electrode 62 are coated on the dielectric layer.
  • the dielectric layer 7 is a silicon dioxide layer.
  • a passivation layer 8 is formed over the dielectric layer 7 using a chemical vapor deposition method, and the passivation layer 8 is a silicon nitride layer.
  • the passivation layer 8, the dielectric layer 7, and the gate insulating layer 6 are defined by photolithography and etching processes to form first contact holes 91, 93 and second contact holes 92, 94 as shown in FIG.
  • the first contact holes 91, 93 and the second contact holes 92, 94 are connected to the surface of the polysilicon layer 42.
  • a conductive layer is deposited using a chemical vapor deposition method, and the sources 95, 97 and the source 95, 97 as shown in FIG. 21 are defined by photolithography and etching processes.
  • photolithography refers to a process of removing a specific portion of a wafer surface film through a series of production steps. After that, the wafer surface will leave a film with a micro-pattern structure. Through the lithography process, the feature pattern portion is finally retained on the wafer.
  • This technology belongs to the common process technology in the field of preparing thin film transistors, and will not be described herein.
  • the etching process refers to a technique in which a material is removed using a chemical reaction or a physical impact. This technology belongs to the common process technology in the field of preparing thin film transistors, and will not be described herein.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

提供一种低温多晶硅薄膜晶体管及其制备方法。该薄膜晶体管包括：基板（1）；形成于基板（1）上的缓冲层（21、22）；形成于缓冲层（22）上的半导体层（42、43）；形成于缓冲层（22）、半导体层（42、43）上的栅极绝缘层（5）；形成于栅极绝缘层（5）上的栅极（61、62）；形成于栅极绝缘层（5）、栅极（61、62）上的介电层（7）；以及形成于介电层（7）上的钝化层（8）；在钝化层（8）、介电层（7）与栅极绝缘层（5）的内部分别形成有第一接触孔（91、93）和第二接触孔（92、94），在第一接触孔（91、93）与第二接触孔（92、94）上分别形成源极（95、97）与漏极（96、98）；半导体层（42、43）为低温多晶硅层，在缓冲层（22）与半导体层（43）之间还设有反射层（31）和/或保温层（32）。主要利用沉积、光刻、蚀刻、激光照射等工艺方法制得该薄膜晶体管，能够得到较大的多晶硅晶粒尺寸，有助于获得较大的电子迁移率。

Description

一种低温多晶硅薄膜晶体管及其制备方法 技术领域
本发明涉及显示技术领域，具体是一种低温多晶硅薄膜晶体管及其制备方法。
背景技术
薄膜晶体管(TFT、Thin Film Transistor)在液晶显示装置中作为开关元件使用，其具有较低的电源消耗、较小的体积和较低的驱动电压等特点，非常适用于电脑、笔记本及其它装置的显示设备。目前的液晶显示装置中，薄膜晶体管的活性层主要采用非晶硅(amorphous silicon、a-Si)，但是采用非晶硅作为活性层的薄膜晶体管迁移率很低，难以满足外围电路的驱动要求，因此采用低温多晶硅(Low Temperature Poly-silicon、LTPS)代替非晶硅的技术应运而生。
低温多晶硅的迁移率可高达至100cm2/V.S，能够满足外围电动的驱动要求，比非晶硅更加适用于薄膜晶体管的活性层，可实现比非晶硅薄膜晶体管更加小型化。制造低温多晶硅薄膜晶体管结构的原理主要是利用准分子镭射作为热源，投射于非晶硅结构的玻璃基板上，使非晶硅结构基板吸收准分子镭射的能量后，转变为多晶硅结构。
目前制造低温多晶硅薄膜晶体管的工艺方法主要包括不使用掩膜的传统性受激准分子激光退火方法(Excimer Laser Annel，简称ELA)和使用掩膜控制激光照射区域的连续侧面结晶化方法(Sequential Lateral Solidification，简称SLS)。采用传统的ELA方法时，得到低温多晶硅的晶粒尺寸一般为0.1μm以下；采用SLS方法时，结晶化过程由照射区域的端部开始向内部诱导，最后才进行照射区域中心部的结晶化。在结晶化进行期间处于熔点以下的温度时，如果中心部的温度下降，就会进行成核，致使不能得到大的晶粒。可见，采用上述两种方法制造的多晶硅晶粒尺寸均较小，使多晶硅的实际应用受到限制。
发明内容
为克服现有技术的不足，本发明的目的在于提供一种低温多晶硅薄膜晶体 管及其制备方法，通过该方法最终可制得晶粒尺寸较大的多晶硅，提高薄膜晶体管的电子迁移率，满足外围电路的驱动要求。
本发明提供一种低温多晶硅薄膜晶体管，所述薄膜晶体管包括：
基板；
形成于所述基板上的缓冲层；
形成于所述缓冲层上的半导体层；
形成于所述缓冲层、所述半导体层上的栅极绝缘层；
形成于所述栅极绝缘层上的栅极；
形成于所述栅极绝缘层、所述栅极上的介电层；
以及形成于所述介电层上的钝化层；
在所述钝化层、所述介电层与所述栅极绝缘层的内部分别形成有第一接触孔和第二接触孔，在所述第一接触孔与所述第二接触孔上分别形成源极与漏极；
其中，所述半导体层为低温多晶硅层，在所述缓冲层与所述半导体层之间还设有反射层和/或保温层。
进一步地，所述低温多晶硅薄膜晶体管包括像素薄膜晶体管和驱动薄膜晶体管，所述基板包括像素区和外围驱动区，所述像素区用于形成所述像素薄膜晶体管，所述外围驱动区用于形成所述驱动薄膜晶体管；
所述驱动薄膜晶体管包括位于所述外围驱动区内的基板，在所述外围驱动区内基板上依次形成的所述缓冲层、所述半导体层、所述栅极绝缘层、所述栅极、所述介电层以及所述钝化层；在所述钝化层、所述介电层与所述栅极绝缘层的内部分别形成第一接触孔和第二接触孔，在所述第一接触孔与所述第二接触孔上分别形成源极与漏极；其中，在所述缓冲层与所述半导体层之间设置所述反射层和/或所述保温层。
进一步地，所述像素薄膜晶体管包括：所述像素区内的基板，在所述像素区内基板上依次形成的所述缓冲层、所述半导体层、所述栅极绝缘层、所述栅极、所述介电层以及所述钝化层；在所述钝化层、所述介电层与所述栅极绝缘层的内部分别形成第一接触孔和第二接触孔，在所述第一接触孔与所述第二接触孔上分别形成源极与漏极。
进一步地，位于所述驱动薄膜晶体管内的所述半导体层的晶粒尺寸大于位于所述像素薄膜晶体管内的所述半导体层的晶粒尺寸。
进一步地，所述缓冲层包括形成于所述基板上方的第一缓冲层，在所述第一缓冲层上形成有所述反射层，在所述第一缓冲层、所述反射层上形成有第二缓冲层，且将所述反射层包覆于所述第二缓冲层内，在所述第二缓冲层上形成有所述半导体层。
优选地，所述反射层的材料为Mo、Al、AlNd、Cr、Cu、W、Ta或Ti中的任意一种或几种的组合，更优选地，所述反射层的材料为Mo，所述反射层为金属钼层。
优选地，所述第一缓冲层和所述第二缓冲层的材料为氮化硅或二氧化硅中的一种或两种组合。
优选地，所述第一缓冲层为氮化硅层，所述第二缓冲层为二氧化硅层。
进一步地，所述缓冲层包括依次形成于所述基板上方的第一缓冲层和第二缓冲层，在所述第二缓冲层上形成有所述保温层，所述半导体层形成于所述第二缓冲层、所述保温层上方。
进一步地，所述保温层为氧化铝层。
优选地，所述第一缓冲层和所述第二缓冲层的材料为氮化硅或二氧化硅中的一种或两种组合。
优选地，所述第一缓冲层为氮化硅层，所述第二缓冲层为二氧化硅层。
优选地，所述基板为玻璃基板。
除此之外，本发明还提供一种低温多晶硅薄膜晶体管的制备方法，包括以下步骤：
提供基板；
在所述基板上形成缓冲层；
在所述缓冲层上形成反射层和/或保温层；
在所述缓冲层、所述反射层和/或保温层上形成非晶硅层，进行激光照射，使所述非晶硅层变为多晶硅层，所述多晶硅层为半导体层；
在所述缓冲层、所述半导体层上形成栅极绝缘层；
在所述栅极绝缘层上形成栅极；
在所述栅极绝缘层、所述栅极上形成介电层；
在所述介电层上形成钝化层；
在所述钝化层、所述介电层、所述栅极绝缘层内部形成第一接触孔和第二接触孔；
在所述第一接触孔和所述第二接触孔上分别形成源极和漏极。
优选地，在所述基板上先形成第一缓冲层，在所述第一缓冲层上形成所述反射层，并采用光刻、蚀刻工艺定义出所述反射层的图形；在所述第一缓冲层、所述反射层上沉积形成第二缓冲层，并将所述反射层包覆于所述第二缓冲层中；在所述第二缓冲层上沉积所述非晶硅层，进行激光照射，使所述非晶硅层变为多晶硅层，得到所述半导体层。
优选地，所述反射层的材料为Mo、Al、AlNd、Cr、Cu、W、Ta或Ti中的任意一种或几种的组合，更优选地，所述反射层的材料为Mo，所述反射层为金属钼层。
优选地，所述第一缓冲层和所述第二缓冲层的材料为氮化硅或二氧化硅中的一种或两种组合。
优选地，所述第一缓冲层为氮化硅层，所述第二缓冲层为二氧化硅层。
优选地，在所述基板上依次沉积形成第一缓冲层、第二缓冲层；在所述第二缓冲层上沉积所述保温层，并采用光刻、蚀刻工艺定义出所述保温层的图形；在所述第二缓冲层、所述保温层上沉积形成所述非晶硅层，进行激光照射，使所述非晶硅层变为多晶硅层，得到所述半导体层。
进一步地，所述保温层为氧化铝层。
优选地，所述第一缓冲层和所述第二缓冲层的材料为氮化硅或二氧化硅中的一种或两种组合。
优选地，所述第一缓冲层为氮化硅层，所述第二缓冲层为二氧化硅层。
可选地，形成所述低温薄膜晶体管各层结构的方法为化学气相沉积方法或 物理气相沉积方法。
可选地，“在所述缓冲层、所述反射层和/或保温层上形成非晶硅层，进行激光照射，使所述非晶硅层变为多晶硅层，所述多晶硅层为半导体层”的步骤中，所述“进行激光照射”的方法为准分子激光退火(ELA)或固相结晶(Solid Phase Crystallization，SPC)方法。
优选地，所述基板为玻璃基板。
与现有技术相比，本发明的有益效果如下：
在本发明中，通过在非晶硅层下方设置反射层和/或保温层，使激光照射经过非晶硅层后，会从反射层再次反射回非晶硅层以增大晶粒结晶尺寸或者通过保温层的保温作用延长非晶硅层的结晶时间，获得更大尺寸的多晶硅晶粒。上述反射层和/或保温层仅设置在外围驱动区时，能够使通过激光照射得到的多晶硅晶粒尺寸大于像素区内多晶硅晶粒尺寸，而较大的晶粒尺寸有助于外围驱动区获得较大的电子迁移率，进而提升外围驱动区的驱动效率。
附图说明
图1至图11是实施例一低温多晶硅薄膜晶体管的制备流程。
图12至图21是实施例二低温多晶硅薄膜晶体管的制备流程。
具体实施方式
实施例一
本实施例提供一种低温多晶硅薄膜晶体管，该薄膜晶体管包括像素薄膜晶体管和驱动薄膜晶体管，该低温多晶硅薄膜晶体管的制备方法如下：
如图1所示，提供一玻璃基板1，该玻璃基板1包括位于左侧的像素区100和位于右侧的外围驱动区200。像素薄膜晶体管形成于像素区100内，作为驱动单元的驱动薄膜晶体管形成于外围驱动区200内。使用化学气相沉积(CVD，Chemical Vapor Deposition)方法在玻璃基板1上形成第一缓冲层21，该第一缓冲层为氮化硅层；接着，如图2所示，使用化学气相沉积方法在第一缓冲层21上沉积形成金属钼层31作为反射层，并采用光刻、蚀刻工艺定义出如图3所示的金属钼层的图形。通过光刻、蚀刻工艺，使得位于像素区100中的金属钼层被蚀刻掉，仅在外围驱动区200中设有金属钼层31；接着如图4所示，使用 化学气相沉积方法在第一缓冲层21、金属钼层31上沉积形成第二缓冲层22，并将金属钼层31包覆在第二缓冲层22中，该第二缓冲层为二氧化硅层。
接着，如图5所示，使用化学气相沉积方法在第二缓冲层22上沉积形成非晶硅层41，并采用准分子激光退火(ELA)或固相结晶(SPC)方法使非晶硅层41转变为位于像素区100内的多晶硅层42和位于外围驱动区200内的多晶硅层43，再通过光刻和蚀刻工艺定义出如图6所示的多晶硅层的图形。在本实施例中，对于设置在外围驱动区内的非晶硅层而言，由于非晶硅层下方设有金属钼层，采用准分子激光退火(ELA)或固相结晶(SPC)方法进行结晶时，激光镭射能量穿过非晶硅层后会经由金属钼层反射回来，使非晶硅层达到保温效果，从而提高其结晶效果，得到晶粒尺寸更大的多晶硅层。由于像素区内的非晶硅层下方未设有金属钼层，因此经过结晶后，在外围驱动区内形成的多晶硅晶粒尺寸要大于在像素区内形成的多晶硅晶粒尺寸。可以理解的是，本实施例中金属钼层也可采用其他具有反射性质的材料代替，例如Al、AlNd、Cr、Cu、W、Ta或Ti中的任意一种或几种的组合。
接着，如图7所示，使用化学气相沉积方法在第二缓冲层22、多晶硅层42、多晶硅层43上沉积形成栅极绝缘层5，并将多晶硅层42、多晶硅层43包覆在栅极绝缘层5中。接着，使用化学气相沉积方法在栅极绝缘层5上沉积形成位于像素区100内的栅极61和位于外围驱动区100内的栅极62，并通过光刻、蚀刻工艺定义出如图8所示的栅极图形。
接着，如图9所示，使用化学气相沉积方法在栅极绝缘层5、栅极61、栅极62上沉积形成介电层7，并将栅极61、栅极62包覆在介电层7中，该介电层7为二氧化硅层。接着，使用化学气相沉积方法在介电层7上方沉积形成钝化层8，该钝化层8为氮化硅层。接着，通过光刻、蚀刻工艺针对钝化层8、介电层7、栅极绝缘层5进行定义，形成如图10所示的第一接触孔91、93和第二接触孔92、94，使第一接触孔和第二接触孔分别连通至多晶硅层表面。
接着，在第一接触孔91、93和第二接触孔92、94的上，使用化学气相沉积方法沉积形成导电层，并通过光刻和蚀刻工艺定义出如图10所示的源极95、97和漏极96、98，其中源极95和漏极96位于像素区100内，源极97和漏极98位于外围驱动区200内。
在本发明中，光刻是指通过一系列生产步骤，将晶圆表面薄膜的特定部分除去的工艺。在此之后，晶圆表面会留下带有微图形结构的薄膜。通过光刻工 艺过程，最终在晶圆上保留的是特征图形部分。该技术属于本领域在制备薄膜晶体管时的常用工艺技术，在此不再赘述。
蚀刻工艺是指将材料使用化学反应或物理撞击作用而移除的技术。该技术属于本领域在制备薄膜晶体管时的常用工艺技术，在此不再赘述。
实施例二
本实施例提供一种低温多晶硅薄膜晶体管，该薄膜晶体管包括像素薄膜晶体管和驱动薄膜晶体管，该低温多晶硅薄膜晶体管的制备方法如下：
如图12所示，提供一玻璃基板1，该玻璃基板1包括位于左侧的像素区100和位于右侧的外围驱动区200。像素薄膜晶体管形成于像素区100内，作为驱动单元的驱动薄膜晶体管形成于外围驱动区200内。使用化学气相沉积方法在玻璃基板1上依次沉积形成第一缓冲层21、第二缓冲层22，该第一缓冲层为氮化硅层，该第二缓冲层为二氧化硅层；接着，如图13所示，使用化学气相沉积方法在第二缓冲层22上沉积形成氧化铝层32作为保温层，并采用光刻、蚀刻工艺定义出如图14所示的氧化铝层的图形。本实施例中，通过光刻、蚀刻工艺，使得位于像素区100的氧化铝层被蚀刻掉，仅在外围驱动区200中设有氧化铝层32。
接着，如图15所示，使用化学气相沉积方法在第二缓冲层22、氧化铝层32上沉积形成非晶硅层41，并将氧化铝层包覆在非晶硅层内。采用准分子激光退火(ELA)或固相结晶(SPC)方法使非晶硅层转变为位于像素区100内的多晶硅层42、位于外围驱动区200内的多晶硅层43，再通过光刻、蚀刻工艺定义出如图16所示的多晶硅层的图形，其中位于外围驱动区200中的多晶硅层42对应在氧化铝层32上方。在本实施例中，对于设置在外围驱动区的非晶硅层而言，由于非晶硅层下方设置具有保温作用的氧化铝层，采用准分子激光退火(ELA)或固相结晶(SPC)方法进行结晶时，通过氧化铝层的保温作用可使外围驱动区的非晶硅层进行结晶时间更长，从而获得比像素区的非晶硅层更大的晶粒尺寸。较大的晶粒尺寸有助于外围驱动区获得较大的电子迁移率，进而提升外围驱动区的驱动效率。
接着，如图17所示，使用化学气相沉积方法在第二缓冲层22、多晶硅层42、多晶硅层43上沉积形成栅极绝缘层5，并将多晶硅层42、多晶硅层43包覆在栅极绝缘层5中。接着，使用化学气相沉积方法在栅极绝缘层5上沉积形 成位于像素区100内的栅极61、位于外围驱动区内的栅极62，并通过光刻、蚀刻工艺定义出如图18所示的栅极图形。
接着，如图19所示，使用化学气相沉积方法在栅极绝缘层5、栅极61、栅极62上沉积形成介电层7，并将栅极61、栅极62包覆在介电层7中，该介电层7为二氧化硅层。接着，使用化学气相沉积方法在介电层7上方沉积形成钝化层8，该钝化层8为氮化硅层。接着，通过光刻、蚀刻工艺针对钝化层8、介电层7、栅极绝缘层6进行定义，形成如图20所示的第一接触孔91、93和第二接触孔92、94，使第一接触孔91、93和第二接触孔92、94连通至多晶硅层42表面。
接着，在具有第一接触孔和第三接触孔的多晶硅层表面上，使用化学气相沉积方法沉积形成导电层，并通过光刻和蚀刻工艺定义出如图21所示的源极95、97和漏极96、98，其中源极95和漏极96位于像素区100内，源极97和漏极98位于外围驱动区200内。
在本发明中，光刻是指通过一系列生产步骤，将晶圆表面薄膜的特定部分除去的工艺。在此之后，晶圆表面会留下带有微图形结构的薄膜。通过光刻工艺过程，最终在晶圆上保留的是特征图形部分。该技术属于本领域在制备薄膜晶体管时的常用工艺技术，在此不再赘述。
蚀刻工艺是指将材料使用化学反应或物理撞击作用而移除的技术。该技术属于本领域在制备薄膜晶体管时的常用工艺技术，在此不再赘述。
以上所述为本发明的具体实施方式，其目的是为了清楚说明本发明而作的举例，并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。凡在本发明的精神和原则之内所作的任何修改、
等同替换和改进等，均应包含在本发明权利要求的保护范围之内。

Claims (11)

  1. 一种低温多晶硅薄膜晶体管，其中：所述低温多晶硅薄膜晶体管包括：基板；形成于所述基板上的缓冲层；形成于所述缓冲层上的半导体层；形成于所述缓冲层、所述半导体层上的栅极绝缘层；形成于所述栅极绝缘层上的栅极；形成于所述栅极绝缘层、所述栅极上的介电层；以及形成于所述介电层上的钝化层；在所述钝化层、所述介电层与所述栅极绝缘层的内部分别形成有第一接触孔和第二接触孔，在所述第一接触孔与所述第二接触孔上分别形成源极与漏极；所述半导体层为低温多晶硅层，在所述缓冲层与所述半导体层之间还设有反射层和/或保温层。
  2. 如权利要求1所述的低温多晶硅薄膜晶体管，其中：所述低温多晶硅薄膜晶体管包括像素薄膜晶体管和驱动薄膜晶体管，所述基板包括像素区和外围驱动区，所述像素区用于形成所述像素薄膜晶体管，所述外围驱动区用于形成所述驱动薄膜晶体管；
    所述驱动薄膜晶体管包括位于所述外围驱动区内的基板，在所述外围驱动区内基板上依次形成的所述缓冲层、所述半导体层、所述栅极绝缘层、所述栅极、所述介电层以及所述钝化层；在所述钝化层、所述介电层与所述栅极绝缘层的内部分别形成第一接触孔和第二接触孔，在所述第一接触孔与所述第二接触孔上分别形成源极与漏极；其中，在所述缓冲层与所述半导体层之间设置所述反射层和/或所述保温层。
  3. 如权利要求1所述的低温多晶硅薄膜晶体管，其中：所述像素薄膜晶体管包括：所述像素区内的基板，在所述像素区内基板上依次形成的所述缓冲层、所述半导体层、所述栅极绝缘层、所述栅极、所述介电层以及所述钝化层；在所述钝化层、所述介电层与所述栅极绝缘层的内部分别形成第一接触孔和第二接触孔，在所述第一接触孔与所述第二接触孔上分别形成源极与漏极。
  4. 如权利要求2所述的低温多晶硅薄膜晶体管，其中：位于所述驱动薄膜晶体管内的所述半导体层的晶粒尺寸大于位于所述像素薄膜晶体管内的所述半导体层的晶粒尺寸。
  5. 如权利要求3所述的低温多晶硅薄膜晶体管，其中：位于所述驱动薄膜晶体管内的所述半导体层的晶粒尺寸大于位于所述像素薄膜晶体管内的所述半导体层的晶粒尺寸。
  6. 如权利要求1所述的低温多晶硅薄膜晶体管，其中：所述缓冲层包括形成于所述基板上方的第一缓冲层，在所述第一缓冲层上形成有所述反射层，在所述第一缓冲层、所述反射层上形成有第二缓冲层，且将所述反射层包覆于所述第二缓冲层内，在所述第二缓冲层上形成有所述半导体层。
  7. 如权利要求1所述的低温多晶硅薄膜晶体管，其中：所述缓冲层包括依次形成于所述基板上方的第一缓冲层和第二缓冲层，在所述第二缓冲层上形成有所述保温层，所述半导体层形成于所述第二缓冲层、所述保温层上方。
  8. 一种低温多晶硅薄膜晶体管的制备方法，其中，包括以下步骤：
    提供基板；在所述基板上形成缓冲层；在所述缓冲层上形成反射层和/或保温层；在所述缓冲层、所述反射层和/或保温层上形成非晶硅层，进行激光照射，使所述非晶硅层变为多晶硅层，所述多晶硅层为半导体层；在所述缓冲层、所述半导体层上形成栅极绝缘层；在所述栅极绝缘层上形成栅极；在所述栅极绝缘层、所述栅极上形成介电层；在所述介电层上形成钝化层；在所述钝化层、所述介电层、所述栅极绝缘层内部形成第一接触孔和第二接触孔；在所述第一接触孔和所述第二接触孔上分别形成源极和漏极。
  9. 如权利要求8所述的制备方法，其中：在所述基板上先沉积第一缓冲层，在所述第一缓冲层上沉积所述反射层，并采用光刻、蚀刻工艺定义出所述反射层的图形；在所述第一缓冲层、所述反射层上沉积第二缓冲层，并将所述反射层包覆于所述第二缓冲层中；在所述第二缓冲层上沉积所述非晶硅层，进行激光照射，使所述非晶硅层变为多晶硅层，得到所述半导体层。
  10. 如权利要求8所述的制备方法，其中：在所述基板上依次沉积形成第一缓冲层、第二缓冲层；在所述第二缓冲层上沉积所述保温层，并采用光刻、蚀刻工艺定义出所述保温层的图形；在所述第二缓冲层、所述保温层上沉积所述非晶硅层，进行激光照射，使所述非晶硅层变为多晶硅层，得到所述半导体层。
  11. 如权利要求8所述的制备方法，其中：所述进行激光照射的方法为准分子激光退火或固相结晶方法。
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