CN105097453A - 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置 - Google Patents

低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置 Download PDF

Info

Publication number
CN105097453A
CN105097453A CN201510502838.5A CN201510502838A CN105097453A CN 105097453 A CN105097453 A CN 105097453A CN 201510502838 A CN201510502838 A CN 201510502838A CN 105097453 A CN105097453 A CN 105097453A
Authority
CN
China
Prior art keywords
low
polysilicon film
temperature polysilicon
preparation
amorphous silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510502838.5A
Other languages
English (en)
Other versions
CN105097453B (zh
Inventor
李栋
陆小勇
李小龙
刘政
张帅
詹裕程
刘建宏
龙春平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201510502838.5A priority Critical patent/CN105097453B/zh
Publication of CN105097453A publication Critical patent/CN105097453A/zh
Priority to US15/518,642 priority patent/US20170236705A1/en
Priority to PCT/CN2016/071715 priority patent/WO2017028499A1/zh
Application granted granted Critical
Publication of CN105097453B publication Critical patent/CN105097453B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02488Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02592Microstructure amorphous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02678Beam shaping, e.g. using a mask
    • H01L21/0268Shape of mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1288Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置,属于显示技术领域,其可解决现有的低温多晶硅薄膜均一性差的问题。本发明的低温多晶硅薄膜的制备方法,包括:在基底上方形成非晶硅薄膜;采用掩模板对非晶硅薄膜进行激光退火,形成低温多晶硅薄膜;其中,所述掩模板包括透光区和将透光区包围的遮光区,且所述遮光区的两条相对的侧边为起伏结构。本发明的制备方法形成的低温多晶硅薄膜性能改到改善。

Description

低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置
技术领域
本发明属于显示技术领域,具体涉及一种低温多晶硅薄膜、薄膜晶体管及其各自制备方法、显示装置。
背景技术
随着显示技术的发展,人们对显示画质的需求日益增长,高画质、高分辨率的平板显示装置的需求越来越普遍,也越来越得到显示面板厂家的重视。
薄膜晶体管(ThinFilmTransistor,简称TFT)是平板显示面板的主要驱动器件,直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构,制备相应结构的薄膜晶体管的材料也具有多种,例如:非晶硅和多晶硅都是目前常用的薄膜晶体管制备材料。然而,非晶硅本身存在很多无法避免的缺点,比如:低迁移率、低稳定性等;与此相比,低温多晶硅(LowTemperaturePoly-Silicon,简称LTPS)具有较高的迁移率及稳定性,其迁移率可达非晶硅的几十甚至几百倍。因此,采用低温多晶硅材料形成薄膜晶体管的技术得到了迅速发展,由LTPS衍生的新一代液晶显示装置(LiquidCrystalDisplay:简称LCD)或有机电致发光显示装置(OrganicLight-EmittingDiode:简称OLED)成为重要的显示技术,尤其是OLED显示装置,由于OLED具有超薄、低功耗、同时自身发光等特点,备受用户的青睐。
虽然低温多晶硅薄膜晶体管具有上述优点,但是,在低温多晶硅薄膜晶体管(LTPSTFT)中的低温多晶硅薄膜(也就是有源层),是采用对非晶硅薄膜进行激光退火工艺形成的,而在激光退火过程中会引起多晶硅的晶粒尺寸不均一和多晶硅薄膜表面出现非常大的粗糙度,从而导致低温多晶硅薄膜晶体管的阈值电压和迁移率的均匀性不佳,尤其是当晶体管尺寸缩小时,阈值电压不均匀的问题将变得更为严重。
发明内容
本发明所要解决的技术问题包括,针对现有的低温多晶硅薄膜存在上述问题,提供一种均一性好、能够提高晶体管性能的一种低温多晶硅薄膜、薄膜晶体管及其各自制备方法、显示装置。
解决本发明技术问题所采用的技术方案是一种低温多晶硅薄膜的制备方法,包括如下步骤:
在基底上方形成非晶硅薄膜;
采用掩模板对非晶硅薄膜进行激光退火,形成低温多晶硅薄膜;其中,所述掩模板包括透光区和将透光区包围的遮光区,且所述遮光区的两条相对的侧边为起伏结构。
优选的是,所述采用掩模板对非晶硅薄膜进行激光退火的步骤中,激光的扫描方向平行于所述起伏结构的波峰的指向方向。
优选的是,所述采用掩模板对非晶硅薄膜进行激光退火的步骤中,激光的能量密度为350mJ/cm2至550mJ/cm2
优选的是,所述采用掩模板对非晶硅薄膜进行激光退火的步骤中,激光的脉冲宽度为30ns至200ns。
优选的是,所述在基底上方形成非晶硅薄膜之前还包括:
在基底上形成缓冲层的步骤。
进一步优选的是,所述缓冲层包括氧化硅、氮化硅中的至少一层结构。
进一步优选的是,所述缓冲层的厚度为150nm至300nm。
优选的是,在所述起伏结构中各个波峰等间距分布,且两相邻波峰之间的距离为0.3μm至2μm。
优选的是,所述起伏结构的形状为三角波或者波浪形。
优选的是,所述激光退火具体为:准分子激光退火或连续波固态激光退火。
解决本发明技术问题所采用的技术方案是一种低温多晶硅薄膜,其是采用上述制备方法制备的。
解决本发明技术问题所采用的技术方案是一种低温多晶硅薄膜晶体管的制备方法,其包括上述的低温多晶硅薄膜的制备方法。
解决本发明技术问题所采用的技术方案是一种低温多晶硅薄膜晶体管的制备方法,包括通过工艺形成包括有源层的步骤,形成所述有源层的步骤具体包括:
在基底上方形成非晶硅薄膜;
采用掩模板对非晶硅薄膜进行激光退火,形成低温多晶硅薄膜;其中,所述掩模板包括透光区和将透光区包围的遮光区,且所述遮光区的两条相对的侧边为起伏结构;
对低温多晶硅薄膜通过构图工艺,形成包括有源层的图形。
优选的是,所述在基底上方形成非晶硅薄膜之前还包括:
在基底上形成缓冲层的步骤。
优选的是,所述采用掩模板对非晶硅薄膜进行激光退火的步骤中,激光的扫描方向平行于所述起伏结构的波峰的指向方向。
进一步优选的是,所述形成包括有源层的图形之后还包括:
通过构图工艺形成包括源极和漏极的图形;其中,所述源极和所述漏极中心连线的方向与所述激光的扫描方向平行。
解决本发明技术问题所采用的技术方案是一种低温多晶硅薄膜晶体管,其是采用上述制备方法制备的。
解决本发明技术问题所采用的技术方案是一种显示装置,其包括上述低温多晶硅薄膜晶体管。
本发明具有如下有益效果:
由于本发明的低温多晶硅薄膜的制备方法中采用了掩模板对非晶硅薄膜进行激光退火以形成低温多晶硅薄膜,掩模板包括透光区和将透光区包围的遮光区,且掩模板遮光区的两条相对的侧边为起伏结构,故在通过激光退火形成的低温多晶硅薄膜将以未被照射的波峰位置的非晶硅为晶核生长,因此,形成的低温多晶硅薄膜的晶粒尺寸以及晶界位置均得到改善,将该低温多晶硅薄膜应用于晶体管中,可以提高晶体管的电学特性。
附图说明
图1为本发明的实施例1的低温多晶硅薄膜的制备方法的流程图;
图2为本发明的实施例1的低温多晶硅薄膜的制备方法所采用的掩模板的示意图;
图3为本发明的实施例1的低温多晶硅薄膜的制备方法的所制备出的低温多晶硅薄膜的示意图;
图4为本发明的实施例2的低温多晶硅薄膜晶体管的制备方法的流程图;
图5为本发明的实施例2的形成有源层的流程图;
图6为本发明的实施例2的形成源极和漏极与有源层的位置关系示意图。
其中附图标记为:10、掩模板;Q1、透光区;Q2、遮光区;20、未被照射的非晶硅薄膜;21、低温多晶硅薄膜;31、源极接触区;32、漏极接触区;33、沟道区。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明作进一步详细描述。
在本发明实施例中,构图工艺,可只包括光刻工艺,或,包括光刻工艺以及刻蚀步骤,同时还可以包括打印、喷墨等其他用于形成预定图形的工艺;光刻工艺,是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
实施例1:
如图1-3所示,本实施例提供一种低温多晶硅薄膜的制备方法,包括如下步骤:
步骤一、在基底上形成缓冲层。
在该步骤中,基底采用玻璃等透明材料制成、且经过预先清洗。具体的,在基板1上采用溅射方式、热蒸发方式、等离子体增强化学气相沉积(PlasmaEnhancedChemicalVaporDeposition:简称PECVD)方式、低压化学气相沉积(LowPressureChemicalVaporDeposition:简称LPCVD)方式、大气压化学气相沉积(AtmosphericPressureChemicalVaporDeposition:简称APCVD)方式或电子回旋谐振化学气相沉积(ElectronCyclotronResonanceChemicalVaporDeposition:简称ECR-CVD)方式形成缓冲层。
其中,缓冲层包括氧化硅、氮化硅中的至少一层结构。另外,缓冲层的厚度可以为150nm至300nm。之所以制备如此厚的缓冲层的原因是为了形成有效的阻热层,以使在后续步骤中非晶硅充分晶化形成多晶硅。
步骤二、在完成上述步骤的基底上,形成非晶硅薄膜(a-Si)。
在该步骤中,形成非晶硅薄膜的方式包括等离子体增强化学气相沉积方式、低压化学气相沉积方式。
步骤三、采用掩模板10对非晶硅薄膜进行激光退火,形成低温多晶硅薄膜;其中,所述掩模板10包括透光区Q1和将透光区Q1包围的遮光区Q2,且所述遮光区Q2的两条相对的侧边为起伏结构,如图2所示。
在该步骤具体包括:首先将掩模板10置于形成有非晶硅薄膜的基底的正上方;其中,掩模板10侧边的起伏结构中各个波峰等间距分布,且两相邻波峰之间的距离为0.3μm至2μm。该起伏结构的形状为三角波或者波浪形。当然也可以是其他的形状,例如正弦波、方波等。
之后,采用准分子激光退火工艺或者连续波固态激光退火工艺,通过掩模板10对非晶硅薄膜进行晶化;可以理解的是,激光只能通过掩模板10的透光区Q1照射至非晶硅薄膜上,此时被激光照射的非晶硅薄膜将会熔融,从固态非晶硅薄膜转化液态硅;而非晶硅薄膜的其他区域由于掩模板10遮光区Q2的遮挡作用,此处并无激光照射,该位置的非晶硅薄膜未熔融,仍处于固态,且未熔融的非晶硅薄膜20在与熔融的非晶硅薄膜交界的位置处的图形与掩模板10侧边的图形相同,同样为起伏结构。在熔融与未熔融的边界的液态硅以该边界处的固态硅为晶核率先沿波峰所在位置外延生长,形成低温多晶硅薄膜21。假设每个晶核的外延速度相同,那么对远离熔融与未熔融边界区域影响最大的位置为远离熔融与未熔融边界的波峰位置的晶核,也就是图3中所示的每个波峰位置处的小圆圈。因此在制备时可以调整未熔融的非晶硅薄膜20波峰之间的间距,以调整晶粒尺寸和晶界位置,从而提高所形成低温多晶硅薄膜21的均匀性。
其中,上述步骤中优选的激光的扫描方向平行于所述起伏结构的波峰的指向方向。也就是如图2和3所示箭头所指的方向。之所以激光按照平行于所述起伏结构的波峰的指向方向进行扫描,是因为沿这个方向为单个晶粒,将该晶粒拉成一条直线,也就是图3中所示的,从而极大的提高了载流子的迁移速率。
其中,上述的采用掩模板10对非晶硅薄膜进行激光退火的步骤中,激光的能量密度优选为350mJ/cm2至550mJ/cm2,以确保被激光照射的非晶硅薄膜完全熔融。当然也可以根据非晶硅薄膜的厚度调整激光的能量密度。
其中,上述的采用掩模板10对非晶硅薄膜进行激光退火的步骤中,激光的脉冲宽度为30ns至200ns,以确保晶核有充足的横向(也就是沿波峰的指向方向)长大时间。
需要说明的是,本实施例中所形成的低温多晶硅薄膜并非整层结构,而是在一层非晶硅薄膜上,将部分区域(激光照射的区域)形成低温多晶硅薄膜。在具体应用过程中,可以通过构图工艺将剩余非晶硅薄膜全部或部分去除。
另外,本实施例中,低温多晶硅薄膜的制备方法可以只包括步骤二和步骤三,在基底上形成缓冲层的步骤一可视设计需求予以省略。在省略步骤一的情况下,步骤二为在基底上形成非晶硅薄膜。
相应的,如图3所示,本实施例还提供了一种低温多晶硅薄膜21,该低温多晶硅薄膜21是采用上述方法制备的。因此,本实施例的低温多晶硅薄膜21的晶粒尺寸以及晶界位置均得到改善,将该低温多晶硅薄膜21应用于晶体管中,可以提高晶体管的电学特性。
实施例2:
如图4、5所示,本实施例提供一种低温多晶硅薄膜晶体管的制备方法,其包括实施例1中所述的制备低温多晶硅薄膜的步骤。具体的,以制备顶栅型晶体管为例进行说明。
步骤一、在基底上形成缓冲层。
在该步骤中,基底采用玻璃等透明材料制成、且经过预先清洗。具体的,在基板1上采用溅射方式、热蒸发方式、等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式形成缓冲层。
其中,缓冲层包括氧化硅、氮化硅中的至少一层结构,厚度为150nm至300nm。之所以制备如此厚的缓冲层的原因是为了形成有效的阻热层,以使在后续步骤中非晶硅充分晶化形成多晶硅。
步骤二、在完成上述步骤的基底上,通过构图工艺形成包括有源层的图形。
如图5所示,在该步骤中,具体包括:
S21、形成非晶硅薄膜(a-Si)。形成非晶硅薄膜的方式包括等离子体增强化学气相沉积方式、低压化学气相沉积方式。
S22、采用掩模板10对非晶硅薄膜进行激光退火,形成低温多晶硅薄膜;其中,所述掩模板10包括透光区Q1和将透光区Q1包围的遮光区Q2,且所述遮光区Q2的两条相对的侧边为起伏结构。
步骤S22具体包括:首先将掩模板10置于形成有非晶硅薄膜的基底的正上方;其中,掩模板10侧边的起伏结构中各个波峰等间距分布,且两相邻波峰之间的距离为0.3μm至2μm。该起伏结构的形状为三角波或者波浪形。当然也可以是其他的形状,例如正弦波、方波等。
之后,采用准分子激光退火工艺或者连续波固态激光退火工艺,通过掩模板10对非晶硅薄膜进行晶化;可以理解的是,激光只能通过掩模板10的透光区Q1照射至非晶硅薄膜上,此时被激光照射的非晶硅薄膜将会熔融,从固态非晶硅薄膜转化液态硅;而非晶硅薄膜的其他区域由于掩模板10遮光区Q2的遮挡作用,此处并无激光照射,该位置的非晶硅薄膜20未熔融,仍处于固态,且未熔融的非晶硅薄膜20在与熔融的非晶硅薄膜交界的位置处的图形与掩模板10侧边的图形相同,同样为起伏结构。在熔融与未熔融的边界的液态硅以该边界处的固态硅为晶核率先沿波峰所在位置外延生长,形成低温多晶硅薄膜21。假设每个晶核的外延速度相同,那么对远离熔融与未熔融边界区域影响最大的位置为远离熔融与未熔融边界的波峰位置的晶核,也就是图3中所示的每个波峰位置处的小圆圈。因此在制备时可以调整未熔融的非晶硅薄膜波峰之间的间距,以调整晶粒尺寸和晶界位置,从而提高所形成低温多晶硅薄膜21的均匀性。
其中,上述步骤中优选的激光的扫描方向平行于所述起伏结构的波峰的指向方向。也是如图2、3所示的箭头所指的方向。之所以激光按照平行于所述起伏结构的波峰的指向方向进行扫描,是因为沿这个方向为单个晶粒,将该晶粒拉成一条直线,也就是图3中所示的,从而极大的提高了载流子的迁移速率。
其中,上述的采用掩模板10对非晶硅薄膜进行激光退火的步骤中,激光的能量密度优选为350mJ/cm2至550mJ/cm2,以确保被激光照射的非晶硅薄膜完全熔融。当然也可以根据非晶硅薄膜的厚度调整激光的能量密度。
其中,上述的采用掩模板10对非晶硅薄膜进行激光退火的步骤中,激光的脉冲宽度为30ns至200ns,以确保晶核有充足的横向(也就是沿波峰的方向)长大时间。
S23、通过构图工艺,将至少部分未被激光照射的非晶硅薄膜20去除,当然最好将全部未被激光照射的非晶硅薄膜20去除,剩下的低温多晶硅薄膜作为有源层。可以理解的是,有源层可以划分为源极接触区31、漏极接触区32,以及两者之间的沟道区33;其中,假若部分未被激光照射的非晶硅薄膜20去除,要确保所形成的低温多晶硅薄膜21的宽度要大于沟道区的宽度。
步骤三、形成栅极绝缘层。
在该步骤中,采用热生长、常压化学气相沉积、低压化学气相沉积、等离子体辅助化学气相淀积、溅射等制备方法形成栅极绝缘层。
步骤四、通过构图工艺形成包括栅极的图形。
在该步骤中,采用溅射方式、热蒸发方式、等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式形成栅金属薄膜,对该栅金属薄膜进行涂覆光刻胶、曝光、显影、刻蚀、剥离光刻胶形成包括薄膜晶体管栅极。
步骤五、形成钝化层,并刻蚀钝化层和栅极绝缘层,形成与源极接触区和漏极接触区对应的过孔。
该步骤中,采用热生长、常压化学气相沉积、低压化学气相沉积、等离子体辅助化学气相淀积、溅射等制备方法形成钝化层,通过刻蚀工艺刻蚀形成贯穿钝化层和栅极绝缘层,且与源极接触区和漏极接触区对应的过孔。
步骤六、通过构图工艺形成包括源极和漏极的图形;其中,所述源极和所述漏极中心连线的方向与所述激光的扫描方向平行。
首先采用等离子体增强化学气相沉积方式、低压化学气相沉积方式沉积有源层薄膜;然后采用溅射方式、热蒸发方式、等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式形成源漏金属薄膜,对源漏金属薄膜进行涂覆光刻胶、曝光、显影、刻蚀、剥离光刻胶形成包括薄膜晶体管源极和漏极的图形,源极和漏极分别通过相应的过孔与有源层的源极接触区和漏极接触区接触。
至此完成了低温多晶硅薄膜晶体管的制备。
相应的,本实施例还提供了一种低温多晶硅薄膜晶体管,其采用上述的制备方法制备的。由于该低温多晶硅薄膜的晶粒尺寸以及晶界位置均得到改善,将该低温多晶硅薄膜作为有源层应用于低温多晶硅薄膜晶体管中,可以提高低温多晶硅薄膜晶体管的电学特性。
实施例3:
本实施例提供了在一种显示装置,其包括上述的低温多晶硅薄膜晶体管,故本实施例的显示装置的显示效果更好。
该显示装置可以为:液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。

Claims (18)

1.一种低温多晶硅薄膜的制备方法,其特征在于,包括如下步骤:
在基底上方形成非晶硅薄膜;
采用掩模板对非晶硅薄膜进行激光退火,形成低温多晶硅薄膜;其中,所述掩模板包括透光区和将透光区包围的遮光区,且所述遮光区的两条相对的侧边为起伏结构。
2.根据权利要求1所述的低温多晶硅薄膜的制备方法,其特征在于,所述采用掩模板对非晶硅薄膜进行激光退火的步骤中,激光的扫描方向平行于所述起伏结构的波峰的指向方向。
3.根据权利要求1所述的低温多晶硅薄膜的制备方法,其特征在于,所述采用掩模板对非晶硅薄膜进行激光退火的步骤中,激光的能量密度为350mJ/cm2至550mJ/cm2
4.根据权利要求1所述的低温多晶硅薄膜的制备方法,其特征在于,所述采用掩模板对非晶硅薄膜进行激光退火的步骤中,激光的脉冲宽度为30ns至200ns。
5.根据权利要求1-4中任一项所述的低温多晶硅薄膜的制备方法,其特征在于,所述在基底上方形成非晶硅薄膜之前还包括:
在基底上形成缓冲层的步骤。
6.根据权利要求5所述的低温多晶硅薄膜的制备方法,其特征在于,所述缓冲层包括氧化硅、氮化硅中的至少一层结构。
7.根据权利要求5所述的低温多晶硅薄膜的制备方法,其特征在于,所述缓冲层的厚度为150nm至300nm。
8.根据权利要求1-4中任一项所述的低温多晶硅薄膜的制备方法,其特征在于,在所述起伏结构中各个波峰等间距分布,且两相邻波峰之间的距离为0.3μm至2μm。
9.根据权利要求1-4中任一项所述的低温多晶硅薄膜的制备方法,其特征在于,所述起伏结构的形状为三角波或者波浪形。
10.根据权利要求1-4中任一项所述的低温多晶硅薄膜的制备方法,其特征在于,所述激光退火具体为:准分子激光退火或连续波固态激光退火。
11.一种低温多晶硅薄膜,其特征在于,所述低温多晶硅薄膜采用权利要求1-10中任一项所述的低温多晶硅薄膜的制备方法制成。
12.一种低温多晶硅薄膜晶体管的制备方法,其特征在于,包括权利要求1-10中任一项所述的低温多晶硅薄膜的制备方法。
13.一种低温多晶硅薄膜晶体管的制备方法,包括通过工艺形成包括有源层的步骤,其特征在于,形成所述有源层的步骤具体包括:
在基底上方形成非晶硅薄膜;
采用掩模板对非晶硅薄膜进行激光退火,形成低温多晶硅薄膜;其中,所述掩模板包括透光区和将透光区包围的遮光区,且所述遮光区的两条相对的侧边为起伏结构;
对低温多晶硅薄膜通过构图工艺,形成包括有源层的图形。
14.根据权利要求13所述的低温多晶硅薄膜晶体管的制备方法,其特征在于,所述在基底上方形成非晶硅薄膜之前还包括:
在基底上形成缓冲层的步骤。
15.根据权利要求13或14所述的低温多晶硅薄膜晶体管的制备方法,其特征在于,所述采用掩模板对非晶硅薄膜进行激光退火的步骤中,激光的扫描方向平行于所述起伏结构的波峰的指向方向。
16.根据权利要求15所述的低温多晶硅薄膜晶体管的制备方法,其特征在于,所述形成包括有源层的图形之后还包括:
通过构图工艺形成包括源极和漏极的图形;其中,所述源极和所述漏极中心连线的方向与所述激光的扫描方向平行。
17.一种低温多晶硅薄膜晶体管,其特征在于,所述低温多晶硅薄膜晶体管采用权利要求12-16中任一项所述的低温多晶硅薄膜晶体管制备方法制成。
18.一种显示装置,其特征在于,包括权利要求17所述的低温多晶硅薄膜晶体管。
CN201510502838.5A 2015-08-14 2015-08-14 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置 Active CN105097453B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201510502838.5A CN105097453B (zh) 2015-08-14 2015-08-14 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置
US15/518,642 US20170236705A1 (en) 2015-08-14 2016-01-22 Low Temperature Poly-Silicon Thin Film, Low-Temperature Poly-Silicon Thin Film Transistor and Manufacturing Methods Thereof, and Display Device
PCT/CN2016/071715 WO2017028499A1 (zh) 2015-08-14 2016-01-22 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510502838.5A CN105097453B (zh) 2015-08-14 2015-08-14 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置

Publications (2)

Publication Number Publication Date
CN105097453A true CN105097453A (zh) 2015-11-25
CN105097453B CN105097453B (zh) 2018-10-19

Family

ID=54577626

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510502838.5A Active CN105097453B (zh) 2015-08-14 2015-08-14 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置

Country Status (3)

Country Link
US (1) US20170236705A1 (zh)
CN (1) CN105097453B (zh)
WO (1) WO2017028499A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105702622A (zh) * 2016-02-01 2016-06-22 武汉华星光电技术有限公司 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
WO2017028499A1 (zh) * 2015-08-14 2017-02-23 京东方科技集团股份有限公司 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置
CN107104112A (zh) * 2017-06-20 2017-08-29 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板、显示装置
CN109473399A (zh) * 2018-11-07 2019-03-15 京东方科技集团股份有限公司 显示基板制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104900532B (zh) * 2015-06-15 2018-10-02 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1527405A (zh) * 2003-03-05 2004-09-08 ����Sdi��ʽ���� 多晶硅薄膜、其制法以及用该膜制造的薄膜晶体管
CN1670622A (zh) * 2004-03-18 2005-09-21 统宝光电股份有限公司 激光退火的制程光罩以及利用激光退火形成多晶系膜层的方法
CN1677618A (zh) * 2004-03-31 2005-10-05 日本电气株式会社 半导体薄膜制造方法及装置、光束成形掩模及薄膜晶体管
US20070001228A1 (en) * 2001-12-21 2007-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
TW200720836A (en) * 2005-08-29 2007-06-01 Sharp Kk Projection mask, laser-machining method, laser machining apparatus, and thin-film transistor element
CN101202218A (zh) * 2007-12-19 2008-06-18 友达光电股份有限公司 应用于连续性侧向长晶技术的掩膜以及激光结晶方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097453B (zh) * 2015-08-14 2018-10-19 京东方科技集团股份有限公司 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001228A1 (en) * 2001-12-21 2007-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
CN1527405A (zh) * 2003-03-05 2004-09-08 ����Sdi��ʽ���� 多晶硅薄膜、其制法以及用该膜制造的薄膜晶体管
CN1670622A (zh) * 2004-03-18 2005-09-21 统宝光电股份有限公司 激光退火的制程光罩以及利用激光退火形成多晶系膜层的方法
CN1677618A (zh) * 2004-03-31 2005-10-05 日本电气株式会社 半导体薄膜制造方法及装置、光束成形掩模及薄膜晶体管
TW200720836A (en) * 2005-08-29 2007-06-01 Sharp Kk Projection mask, laser-machining method, laser machining apparatus, and thin-film transistor element
CN101202218A (zh) * 2007-12-19 2008-06-18 友达光电股份有限公司 应用于连续性侧向长晶技术的掩膜以及激光结晶方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017028499A1 (zh) * 2015-08-14 2017-02-23 京东方科技集团股份有限公司 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置
CN105702622A (zh) * 2016-02-01 2016-06-22 武汉华星光电技术有限公司 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
CN105702622B (zh) * 2016-02-01 2019-02-01 武汉华星光电技术有限公司 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
CN107104112A (zh) * 2017-06-20 2017-08-29 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板、显示装置
WO2018233395A1 (zh) * 2017-06-20 2018-12-27 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板、显示装置
US20190172856A1 (en) * 2017-06-20 2019-06-06 Boe Technology Group Co., Ltd. Array substrate and manufacturing method therefor, display panel and display apparatus
US11101301B2 (en) * 2017-06-20 2021-08-24 Boe Technology Group Co., Ltd. Array substrate and manufacturing method therefor, display panel and display apparatus
CN109473399A (zh) * 2018-11-07 2019-03-15 京东方科技集团股份有限公司 显示基板制备方法
US11063069B2 (en) 2018-11-07 2021-07-13 Boe Technology Group Co., Ltd. Method for manufacturing display substrate

Also Published As

Publication number Publication date
US20170236705A1 (en) 2017-08-17
CN105097453B (zh) 2018-10-19
WO2017028499A1 (zh) 2017-02-23

Similar Documents

Publication Publication Date Title
CN103390592B (zh) 阵列基板制备方法、阵列基板以及显示装置
CN102969250B (zh) Ltps薄膜及薄膜晶体管的制备方法,阵列基板及显示装置
CN105097453A (zh) 低温多晶硅薄膜、薄膜晶体管及各自制备方法、显示装置
US20170184892A1 (en) Array substrate, method for manufacturing the same, and display device
US10068809B2 (en) TFT backplane manufacturing method and TFT backplane
CN104681628A (zh) 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
CN105762196B (zh) 一种薄膜晶体管、其制作方法及相应装置
CN105070727B (zh) 一种薄膜晶体管阵列基板、其制作方法及显示装置
CN104659285A (zh) 适用于amoled的tft背板制作方法及结构
CN104538352A (zh) 阵列基板及其制造方法、显示装置
CN102709241A (zh) 一种薄膜晶体管阵列基板及制作方法和显示装置
CN102654698A (zh) 液晶显示器阵列基板及其制造方法、液晶显示器
CN108447822A (zh) Ltps tft基板的制作方法
CN103887245A (zh) 一种阵列基板的制造方法
CN104678643A (zh) 显示基板及显示面板的制作方法
CN105957805A (zh) 低温多晶硅薄膜制作方法、薄膜晶体管、阵列基板和显示装置
CN110221490A (zh) 阵列基板及其制作方法和显示装置
CN104599959A (zh) 低温多晶硅tft基板的制作方法及其结构
WO2020062426A1 (zh) 阵列基板及其制备方法和显示器件
CN104733323A (zh) 一种低温多晶硅薄膜晶体管的制造方法
CN105655407A (zh) 多晶硅薄膜晶体管及其制备方法、阵列基板、显示装置
CN108336111A (zh) Oled显示面板及其制造方法
CN102709235B (zh) 阵列基板及其制造方法、显示装置
CN103700663A (zh) 一种阵列基板及其制作方法、显示装置
CN106952963B (zh) 一种薄膜晶体管及制作方法、阵列基板、显示装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant