WO2018233395A1 - 一种阵列基板及其制作方法、显示面板、显示装置 - Google Patents

一种阵列基板及其制作方法、显示面板、显示装置 Download PDF

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WO2018233395A1
WO2018233395A1 PCT/CN2018/086384 CN2018086384W WO2018233395A1 WO 2018233395 A1 WO2018233395 A1 WO 2018233395A1 CN 2018086384 W CN2018086384 W CN 2018086384W WO 2018233395 A1 WO2018233395 A1 WO 2018233395A1
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amorphous silicon
thin film
silicon layer
film transistor
array substrate
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PCT/CN2018/086384
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English (en)
French (fr)
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田雪雁
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京东方科技集团股份有限公司
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Priority to US16/320,272 priority Critical patent/US11101301B2/en
Publication of WO2018233395A1 publication Critical patent/WO2018233395A1/zh

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    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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    • G—PHYSICS
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, a display panel, and a display device.
  • the polysilicon active layer of a thin film transistor is fabricated in the LTPS backplane technology, it is mainly performed by excimer laser annealing (ELA).
  • ELA excimer laser annealing
  • the prior art generally does not consider the relationship between the orientation of the excimer laser beam and the thin film transistor, and the prior art design In the layout, the thin film transistor is usually placed in a horizontal or vertical design with a fixed arrangement, which causes a certain periodic coincidence relationship between the edge of the laser beam and the channel of the thin film transistor during laser scanning. The product will appear due to the ELA linear Mura. The effect is caused by the display of Mura.
  • ELA is a linear beam laser technology.
  • the display of Mura due to laser beam is very difficult to eliminate;
  • LTPS AMOLED or LTPS In the production of TFT-LCD, it has become a major factor affecting high-quality displays.
  • an embodiment of the present invention provides an array substrate and a manufacturing method thereof, a display panel, and a display device for reducing visual defects of the display Mura and improving the quality and yield of the array substrate.
  • An array substrate provided by an embodiment of the present invention includes a plurality of arrayed pixel units on a substrate, each of the pixel units including a thin film transistor, wherein the thin film transistor includes a polysilicon active layer, wherein The length of the channel of the thin film transistor extends in a direction parallel to the preset direction;
  • the predetermined direction is a scanning direction of an excimer laser beam used when forming the polysilicon active layer.
  • the embodiment of the present invention can eliminate the trench of the thin film transistor compared with the prior art.
  • the effect of the difference in the length extension of the track and the periodic overlap of the edge line during the excimer laser beam scanning reduces the display Mura visual defects caused by the ELA linear Mura, thereby improving the quality and yield of the array substrate. .
  • the thin film transistors located in the same column of the pixel unit are arranged in a misalignment.
  • the thin film transistors in the pixel unit in the same row are arranged in a misaligned manner.
  • the polysilicon active layer has an S-shaped cross section or a zigzag shape.
  • the embodiment of the invention further provides a display panel, which comprises the above array substrate.
  • the embodiment of the invention further provides a display device, which comprises the above display panel.
  • the display device is a liquid crystal display device or an organic electroluminescence display device.
  • the embodiment of the present invention further provides a method for fabricating an array substrate, including a method for fabricating a thin film transistor on a substrate.
  • the method for fabricating a thin film transistor includes a method for fabricating a polysilicon active layer, and specifically includes:
  • Forming an amorphous silicon layer on the base substrate forming a first amorphous silicon layer and a second amorphous silicon layer by a patterning process, wherein the position of the first amorphous silicon layer corresponds to a channel position of the thin film transistor;
  • first amorphous silicon layer and the second amorphous silicon layer Simultaneously annealing the first amorphous silicon layer and the second amorphous silicon layer with an excimer laser beam to form a first polysilicon active layer and a second polysilicon active layer;
  • the extending direction of the first amorphous silicon layer in a predetermined direction is parallel to the scanning direction of the excimer laser beam.
  • the method before the annealing of the first amorphous silicon layer and the second amorphous silicon layer by using an excimer laser beam, the method further includes:
  • the first amorphous silicon layer and the second amorphous silicon layer are subjected to heat treatment for 0.5 to 3 hours at a temperature of 400 ° C to 450 ° C.
  • the laser when the quasi-molecular laser beam is used for annealing, has a pulse frequency of 250 Hz to 350 Hz, an overlap ratio of 92% to 98%, a scan rate of 2.4 mm/s to 9.6 mm/s, and an energy density of 300 mJ/cm 2 to 500 mJ/cm 2 .
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • Embodiments of the present invention provide an array substrate, a manufacturing method thereof, a display panel, and a display device, which are used to reduce visual defects of the display Mura and improve the quality and yield of the array substrate.
  • an embodiment of the present invention provides an array substrate including a plurality of arrays of pixel units 11 disposed on a substrate 10 , each of the pixel units 11 including a thin film transistor 12 , and the thin film transistor 12 includes polysilicon.
  • An active layer (not shown), the length extension direction of the channel of the thin film transistor 12 in the embodiment of the present invention is parallel to the preset direction; wherein: the predetermined direction is an excimer used when forming the polysilicon active layer
  • the scanning direction of the laser beam which is shown by the arrow in Fig. 1, the vertical dotted line in Fig. 1 indicates the edge line when the excimer laser beam is scanned.
  • the embodiment of the present invention can eliminate the length extension direction of the channel of the thin film transistor compared with the prior art. Compared with the performance difference caused by the high degree of periodic overlap of the edge lines during excimer laser beam scanning, the display Mura visual defects caused by the ELA linear Mura are reduced, thereby improving the quality and yield of the array substrate.
  • the thin film transistor in the embodiment of the present invention includes a polysilicon active layer having an S-shaped cross section or a zigzag shape, wherein the cross section is perpendicular to the substrate, and the source of the thin film transistor is directed to the drain.
  • a polysilicon active layer having an S-shaped cross section or a zigzag shape, wherein the cross section is perpendicular to the substrate, and the source of the thin film transistor is directed to the drain.
  • the cross section of the polysilicon active layer may also be in other types of curved shapes; in the specific embodiment of the present invention, the polysilicon active layer has an S-shaped cross section or a zigzag shape, which is better.
  • the length direction of the channel of the thin film transistor is realized to be parallel to the scanning direction of the excimer laser beam.
  • the thin film transistors 12 in the same column of pixel units 11 are arranged in a misaligned manner, so that the length extension direction of the channel of the thin film transistor and the excimer laser beam scanning can be further eliminated.
  • the edge line of the time has a high degree of periodic coincidence, the performance difference effect is fundamentally, and the zero Mura control can be displayed.
  • the thin film transistors 12 in the same row of pixel units 11 are arranged in a misaligned manner.
  • the arrangement of the thin film transistors in the embodiment of the present invention is more flexible and variable, and practical. In the production process, it is more conducive to the setting of thin film transistors.
  • a specific embodiment of the present invention further provides a display panel, which includes the above array substrate provided by the specific embodiment of the present invention.
  • the arrangement of the thin film transistors included in the array substrate can reduce the display Mura visual defects caused by the ELA linear Mura. Therefore, compared with the prior art, the display panel provided by the specific embodiment of the present invention is displayed. Can greatly reduce the display of Mura visual defects.
  • a specific embodiment of the present invention further provides a display device, which includes the above display panel provided by the specific embodiment of the present invention, and the display device may be a liquid crystal display device or an organic electroluminescence display.
  • the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a liquid crystal television, an Organic Light Emitting Diode (OLED) television, a notebook computer, a digital photo frame, a navigator, and the like.
  • OLED Organic Light Emitting Diode
  • Other essential components of the display device are understood by those of ordinary skill in the art and will not be described herein.
  • a specific embodiment of the present invention further provides a method for fabricating an array substrate, including a method for fabricating a thin film transistor on a substrate, wherein the method for fabricating a thin film transistor includes a method of fabricating a polysilicon active layer, such as As shown in Figure 3, the specific includes:
  • the extending direction of the first amorphous silicon layer in a predetermined direction refers to the extending direction of the length of the channel of the formed thin film transistor. After the thin film transistor is formed, the specific direction of the length extension of the channel is determined. There are similar technologies, so I won't go into details here.
  • the specific embodiment of the present invention further includes: at a temperature of 400 ° C to 450 ° C, the first The amorphous silicon layer and the second amorphous silicon layer are subjected to heat treatment for 0.5 hours to 3 hours, so that the amorphous silicon layer can be more preferably formed into an amorphous silicon active layer after subsequent annealing using an excimer laser beam.
  • the laser when the excimer laser beam is used for annealing, the laser has a pulse frequency of 250 Hz (HZ) to 350 Hz, an overlap ratio of 92% to 98%, and a scan rate of 2.4 mm per second (mm/ s) to 9.6 mm/s, energy density is 300 mJ/cm 2 to 500 mJ/cm 2 .
  • the calculation formula of the overlap ratio of the laser in the specific embodiment of the present invention is as follows:
  • the overlap ratio of the laser [(width of the laser beam - scan pitch) / width of the laser beam] * 100%.
  • the base substrate is pre-cleaned, and the base substrate in the specific embodiment of the present invention is exemplified by a glass substrate.
  • a buffer layer is formed on the base substrate.
  • the buffer layer produced in the specific embodiment of the present invention is described by taking a two-layer structure as an example. Specifically, a method of plasma enhanced chemical vapor deposition (PECVD) is firstly deposited by depositing a layer of silicon nitride (SiN) of 50 nm to 150 nm, followed by deposition of a layer of silicon dioxide of 100 nm to 350 nm ( The SiO2) layer, the SiN layer and the SiO2 layer are used as the buffer layer of the embodiment of the present invention.
  • PECVD plasma enhanced chemical vapor deposition
  • the buffer layer is preferably formed. In other embodiments, the buffer layer may not be formed.
  • an amorphous silicon layer is deposited on the underlying substrate on which the buffer layer is formed.
  • a layer of amorphous silicon layer of 30 nm to 60 nm is deposited by PECVD; then, a first amorphous film is formed by a patterning process.
  • the silicon layer and the second amorphous silicon layer, the position of the first amorphous silicon layer corresponds to a position at which a channel of the thin film transistor needs to be formed.
  • the patterning process in the specific embodiment of the present invention includes coating, exposing, developing, etching, and removing part or all of the photoresist. In the embodiment of the present invention, the patterning process is used to pattern the amorphous silicon layer.
  • the direction of the extension of the first amorphous silicon layer formed in the predetermined direction is parallel to the scanning direction of the excimer laser beam when the subsequent excimer laser beam is annealed to eliminate the channel of the thin film transistor.
  • the first amorphous silicon layer to be formed in the same column of pixel units may be arranged in a dislocation manner, so that the subsequently formed thin film transistor is placed in each pixel unit.
  • the length extension direction of the channel of the thin film transistor and the periodic coincidence of the edge line when the excimer laser beam is scanned can be further eliminated.
  • the performance difference caused by high can fundamentally show zero Mura control.
  • the first amorphous silicon layer and the second amorphous silicon layer are subjected to heat treatment for 0.5 hours to 3 hours, and then the first amorphous silicon layer and the second amorphous silicon layer are subjected to an excimer laser annealing process to form a first polysilicon active layer and a second polysilicon active layer, the formed first polysilicon active layer and the second polysilicon active layer constitute an active layer of the thin film transistor of the embodiment of the present invention .
  • the laser when the excimer laser beam is used for excimer laser annealing, the laser has a pulse frequency of 250 Hz to 350 Hz, an overlap ratio of 92% to 98%, and a scan rate of 2.4 mm/s to 9.6 mm/s.
  • the energy density is from 300 mJ/cm 2 to 500 mJ/cm 2 .
  • a ruthenium chloride excimer laser when the excimer laser annealing is performed, and the wavelength of the laser is 308 nm.
  • the argon fluoride excimer laser the specific embodiment of the present invention is not limited to the specific type of molecular laser.
  • a source, a drain, an interlayer insulating layer, a pixel electrode and the like are formed on the formed first polysilicon active layer and the second polysilicon active layer, and the specific fabrication method of the portion of the film layer is not The improvement of the present invention will not be repeated here.
  • the thin film transistor and the array substrate are formed by the above method, and are suitable for a low temperature poly-Silicon Active Matrix Organic Light Emitting Diode (LTPS-AMOLED) and a low temperature polysilicon thin film transistor.
  • LTPS-AMOLED low temperature poly-Silicon Active Matrix Organic Light Emitting Diode
  • LTPS TFT-LCD Low Temperature Poly-Silicon Thin Film Transistor Liquid Crystal Display
  • an embodiment of the present invention provides an array substrate including a plurality of arrayed pixel units on a substrate, each pixel unit including a thin film transistor, and the thin film transistor includes a polysilicon active layer, wherein the thin film
  • the length of the channel of the transistor extends in a direction parallel to the preset direction; the predetermined direction is the scanning direction of the excimer laser beam used when forming the active layer of the polysilicon. Since the length extension direction of the channel of the thin film transistor in the embodiment of the present invention is parallel to the scanning direction of the excimer laser beam, the embodiment of the present invention can eliminate the length extension direction of the channel of the thin film transistor compared with the prior art. Compared with the performance difference caused by the high degree of periodic overlap of the edge lines during excimer laser beam scanning, the display Mura visual defects caused by the ELA linear Mura are reduced, thereby improving the quality and yield of the array substrate.

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Abstract

本发明公开了一种阵列基板及其制作方法、显示面板、显示装置，用以降低显示Mura的视觉缺陷，提高阵列基板的品质及良率。阵列基板，包括位于衬底基板上的若干阵列排列的像素单元，每一所述像素单元包括一薄膜晶体管，所述薄膜晶体管包括多晶硅有源层，其中：所述薄膜晶体管的沟道的长度延伸方向与预设方向平行；所述预设方向为形成所述多晶硅有源层时采用的准分子激光束的扫描方向。

Description

一种阵列基板及其制作方法、显示面板、显示装置
本申请要求在2017年06月20日提交中国专利局、申请号为201710468730.8、发明名称为“一种阵列基板及其制作方法、显示面板、显示装置”的中国专利申请的优先权，其全部内容以引入的方式并入本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示面板、显示装置。
背景技术
低温多晶硅(Low Temperature Poly-Silicon,LTPS)薄膜晶体管液晶显示面板(Thin Film Transistor Liquid Crystal Display，TFT-LCD)具有高分辨率、反应速度快、高亮度、高开口率等优点，由于LTPS TFT-LCD的硅结晶排列较非晶硅(a-Si)有次序，使得电子移动率相对高100倍以上，可以将外围驱动电路同时制作在玻璃基板上，能够节省空间及驱动集成电路的成本。同时由LTPS衍生的有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)凭借高画质、移动图像响应时间短、低功耗、宽视角及超轻薄等优点，成为了未来显示技术的最好选择。
LTPS背板技术中制作薄膜晶体管的多晶硅有源层时，主要采用准分子激光退火(ELA)来完成，现有技术通常不考虑准分子激光束与薄膜晶体管的放置方向的关系，现有技术设计版图时，薄膜晶体管通常为固定排列的水平或垂直的设计摆放，造成了激光扫描时，激光束边缘与薄膜晶体管的沟道存在某种周期性重合关系，产品中将会出现由于ELA线性Mura影响而导致的显示Mura。
综上所述，目前ELA的制作方法极大地影响了LTPS生产的成品率，ELA是一种直线束的激光技术，由于激光束引起的显示Mura是非常难以消除的； 另外，在LTPS AMOLED或LTPS TFT-LCD的生产中，成为影响高品质显示屏的主要因素。
发明内容
有鉴于此，本发明实施例提供了一种阵列基板及其制作方法、显示面板、显示装置，用以降低显示Mura的视觉缺陷，提高阵列基板的品质及良率。
本发明实施例提供的一种阵列基板，包括位于衬底基板上的若干阵列排列的像素单元，每一所述像素单元包括一薄膜晶体管，所述薄膜晶体管包括多晶硅有源层，其中，所述薄膜晶体管的沟道的长度延伸方向与预设方向平行；
所述预设方向为形成所述多晶硅有源层时采用的准分子激光束的扫描方向。
由本发明实施例提供的阵列基板，由于阵列基板包括的薄膜晶体管的沟道的长度延伸方向与准分子激光束的扫描方向平行，与现有技术相比，本发明实施例可以消除薄膜晶体管的沟道的长度延伸方向与准分子激光束扫描时的边缘线周期性重合度高带来的性能差异影响，减少了ELA线性Mura所导致的显示Mura视觉缺陷，从而提高了阵列基板的品质及良率。
较佳地，位于同一列所述像素单元中的所述薄膜晶体管呈错位排列。
较佳地，位于同一行所述像素单元中的所述薄膜晶体管呈错位排列。
较佳地，所述多晶硅有源层的截面呈S型，或呈Z字形。
本发明实施例还提供了一种显示面板，该显示面板包括上述的阵列基板。
本发明实施例还提供了一种显示装置，该显示装置包括上述的显示面板。
较佳地，所述显示装置为液晶显示装置，或为有机电致发光显示装置。
本发明实施例还提供了一种阵列基板的制作方法，包括在衬底基板上制作薄膜晶体管的方法，其中，所述制作薄膜晶体管的方法包括制作多晶硅有源层的方法，具体包括：
在衬底基板上形成一层非晶硅层，采用构图工艺形成第一非晶硅层和第 二非晶硅层，所述第一非晶硅层的位置对应薄膜晶体管的沟道位置；
同时对所述第一非晶硅层和所述第二非晶硅层采用准分子激光束进行退火处理，形成第一多晶硅有源层和第二多晶硅有源层；其中：所述第一非晶硅层在预设方向上的延伸方向与所述准分子激光束的扫描方向平行。
较佳地，所述同时对所述第一非晶硅层和所述第二非晶硅层采用准分子激光束进行退火处理之前，还包括：
在400℃到450℃的温度下，对所述第一非晶硅层和所述第二非晶硅层进行0.5小时到3小时的加热处理。
较佳地，所述采用准分子激光束进行退火处理时，激光的脉冲频率为250HZ到350HZ，重叠率为92％到98％，扫描速率为2.4mm/s到9.6mm/s，能量密度为300mJ/cm 2到500mJ/cm 2。
附图说明
图1为本发明实施例提供的一种阵列基板的结构示意图；
图2为本发明实施例提供的另一阵列基板的结构示意图；
图3为本发明实施例提供的一种阵列基板的制作方法流程图。
具体实施方式
本发明实施例提供了一种阵列基板及其制作方法、显示面板、显示装置，用以降低显示Mura的视觉缺陷，提高阵列基板的品质及良率。
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
下面结合附图详细介绍本发明具体实施例提供的阵列基板。
附图中各部件厚度和区域大小、形状不反应各部件的真实比例，目的只 是示意说明本发明内容。
如图1所示，本发明具体实施例提供了一种阵列基板，包括位于衬底基板10上的若干阵列排列的像素单元11，每一像素单元11包括一薄膜晶体管12，薄膜晶体管12包括多晶硅有源层(图中未示出)，本发明具体实施例中的薄膜晶体管12的沟道的长度延伸方向与预设方向平行；其中：预设方向为形成多晶硅有源层时采用的准分子激光束的扫描方向，该方向如图1中箭头所示的方式，图1中竖直的虚线表示准分子激光束扫描时的边缘线。
由于本发明具体实施例中的薄膜晶体管的沟道的长度延伸方向与准分子激光束的扫描方向平行，与现有技术相比，本发明具体实施例可以消除薄膜晶体管的沟道的长度延伸方向与准分子激光束扫描时的边缘线周期性重合度高带来的性能差异影响，减少了ELA线性Mura所导致的显示Mura视觉缺陷，从而提高了阵列基板的品质及良率。
具体地，本发明具体实施例中的薄膜晶体管包括的多晶硅有源层的截面呈S型，或呈Z字形，这里的截面指沿垂直于衬底基板，且由薄膜晶体管的源极指向漏极方向的面，当然，在实际生产过程中，多晶硅有源层的截面还可以呈其它类型的弯曲形状；本发明具体实施例多晶硅有源层的截面呈S型，或呈Z字形，能够更好的实现薄膜晶体管的沟道的长度延伸方向与准分子激光束的扫描方向平行。
优选地，如图1所示，本发明具体实施例中位于同一列像素单元11中的薄膜晶体管12呈错位排列，这样，能够进一步消除薄膜晶体管的沟道的长度延伸方向与准分子激光束扫描时的边缘线周期性重合度高带来的性能差异影响，从根本上可以做到显示零Mura控制。
具体地，如图2所示，本发明具体实施例中位于同一行像素单元11中的薄膜晶体管12呈错位排列，这样，本发明具体实施例中薄膜晶体管的设置方式更加灵活、多变，实际生产过程中，更有利于薄膜晶体管的设置。
基于同一发明构思，本发明具体实施例还提供了一种显示面板，该显示 面板包括本发明具体实施例提供的上述阵列基板。由于本发明具体实施例中上述阵列基板包括的薄膜晶体管的设置方式能够减少ELA线性Mura所导致的显示Mura视觉缺陷，因此，与现有技术相比，本发明具体实施例提供的显示面板显示时能够大大降低显示Mura视觉缺陷。
基于同一发明构思，本发明具体实施例还提供了一种显示装置，该显示装置包括本发明具体实施例提供的上述显示面板，该显示装置可以为液晶显示装置，也可以为有机电致发光显示装置；具体地，该显示装置可以为：手机、平板电脑、液晶电视、有机发光二极管(Organic Light Emitting Diode，OLED)电视、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不予赘述。
基于同一发明构思，本发明具体实施例还提供了一种阵列基板的制作方法，包括在衬底基板上制作薄膜晶体管的方法，其中，制作薄膜晶体管的方法包括制作多晶硅有源层的方法，如图3所示，具体包括：
S301、在衬底基板上形成一层非晶硅层，采用构图工艺形成第一非晶硅层和第二非晶硅层，所述第一非晶硅层的位置对应薄膜晶体管的沟道位置；
S302、同时对所述第一非晶硅层和所述第二非晶硅层采用准分子激光束进行退火处理，形成第一多晶硅有源层和第二多晶硅有源层；其中：所述第一非晶硅层在预设方向上的延伸方向与所述准分子激光束的扫描方向平行。
本发明具体实施例第一非晶硅层在预设方向上的延伸方向指形成的薄膜晶体管的沟道的长度延伸方向，薄膜晶体管形成后，其沟道的长度延伸方向的具体确定方式与现有技术类似，这里不再赘述。
优选地，本发明具体实施例在同时对第一非晶硅层和第二非晶硅层采用准分子激光束进行退火处理之前，还包括：在400℃到450℃的温度下，对第一非晶硅层和第二非晶硅层进行0.5小时到3小时的加热处理，这样，在后续 采用准分子激光束进行退火后，能够将非晶硅层更好的形成多晶硅有源层。
优选地，本发明具体实施例采用准分子激光束进行退火处理时，激光的脉冲频率为250赫兹(HZ)到350HZ，重叠率为92％到98％，扫描速率为2.4毫米每秒(mm/s)到9.6mm/s，能量密度为300毫焦每平方厘米(mJ/cm 2)到500mJ/cm 2。本发明具体实施例中激光的重叠率的计算公式如下：
激光的重叠率＝[(激光束的宽度-扫描间距)/激光束的宽度]*100％。
下面结合一个具体的实施例详细说明本发明具体实施例中阵列基板的制作方法。
首先，对衬底基板进行预清洗，本发明具体实施例中的衬底基板以玻璃基板为例。接着，在衬底基板上制作缓冲层，本发明具体实施例制作的缓冲层以双层结构为例进行介绍。具体地，采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)的方法首先沉积一层50nm到150nm的氮化硅(SiN)层，接着再沉积一层100nm到350nm的二氧化硅(SiO2)层，SiN层和SiO2层作为本发明具体实施例的缓冲层，需要说明的是制作缓冲层为优选方案，其他具体实施例中也可以不制作缓冲层。
接着，在制作有缓冲层的衬底基板上沉积一层非晶硅层，具体实施时，采用PECVD的方法沉积一层30nm到60nm的非晶硅层；之后，采用构图工艺形成第一非晶硅层和第二非晶硅层，第一非晶硅层的位置对应需要形成薄膜晶体管的沟道的位置。本发明具体实施例中的构图工艺包括光刻胶的涂覆、曝光、显影、刻蚀以及去除光刻胶的部分或全部过程，本发明具体实施例采用构图工艺对非晶硅层进行构图时，需要使得构图后形成的第一非晶硅层在预设方向上的延伸方向与后续采用准分子激光束进行退火处理时的准分子激光束的扫描方向平行，以消除薄膜晶体管的沟道的长度延伸方向与准分子激光束扫描时的边缘线周期性重合度高带来的性能差异影响。
优选地，本发明具体实施例在进行构图工艺时，可以使得位于同一列像素单元中需要形成的第一非晶硅层呈错位排列，这样后续形成的薄膜晶体管在每个像素单元中的摆放不遵循周期性排列的方式，而是以一种非周期性， 岔开的方式摆放，可以进一步消除薄膜晶体管的沟道的长度延伸方向与准分子激光束扫描时的边缘线周期性重合度高带来的性能差异影响，从根本上可以做到显示零Mura控制。
接着，对第一非晶硅层和第二非晶硅层进行0.5小时到3小时的加热处理，然后再对第一非晶硅层和第二非晶硅层进行准分子激光退火工艺，形成第一多晶硅有源层和第二多晶硅有源层，形成的第一多晶硅有源层和第二多晶硅有源层组成本发明具体实施例的薄膜晶体管的有源层。
优选地，本发明具体实施例采用准分子激光束进行准分子激光退火时，激光的脉冲频率为250HZ到350HZ，重叠率为92％到98％，扫描速率为2.4mm/s到9.6mm/s，能量密度为300mJ/cm 2到500mJ/cm 2。具体实施时，本发明具体实施例进行准分子激光退火时，采用氯化氙准分子激光器，该激光器的波长为308nm，当然，实际生产过程中，还可以采用其它类型的激光器，如：可以采用氟化氩准分子激光器，本发明具体实施例并不对准分子激光器的具体类型做限定。
最后，在形成的第一多晶硅有源层和第二多晶硅有源层上形成源极、漏极、层间绝缘层、像素电极等结构，由于这部分膜层的具体制作方法不涉及本发明的改进点，这里不再进行赘述。
本发明具体实施例通过上述方法制作形成的薄膜晶体管及阵列基板，适用于低温多晶硅有源矩阵有机发光二极管显示器(Low Temperature Poly-Silicon Active Matrix Organic Light Emitting Diode，LTPS-AMOLED)及低温多晶硅薄膜晶体管液晶显示器(Low Temperature Poly-Silicon Thin Film Transistor Liquid Crystal Display，LTPS TFT-LCD)等领域。
综上所述，本发明具体实施例提供一种阵列基板，包括位于衬底基板上的若干阵列排列的像素单元，每一像素单元包括一薄膜晶体管，薄膜晶体管包括多晶硅有源层，其中，薄膜晶体管的沟道的长度延伸方向与预设方向平行；预设方向为形成多晶硅有源层时采用的准分子激光束的扫描方向。由于 本发明具体实施例中的薄膜晶体管的沟道的长度延伸方向与准分子激光束的扫描方向平行，与现有技术相比，本发明具体实施例可以消除薄膜晶体管的沟道的长度延伸方向与准分子激光束扫描时的边缘线周期性重合度高带来的性能差异影响，减少了ELA线性Mura所导致的显示Mura视觉缺陷，从而提高了阵列基板的品质及良率。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (10)

  1. 一种阵列基板，包括位于衬底基板上的若干阵列排列的像素单元，每一所述像素单元包括一薄膜晶体管，所述薄膜晶体管包括多晶硅有源层，其特征在于，所述薄膜晶体管的沟道的长度延伸方向与预设方向平行；
    所述预设方向为形成所述多晶硅有源层时采用的准分子激光束的扫描方向。
  2. 根据权利要求1所述的阵列基板，其特征在于，位于同一列所述像素单元中的所述薄膜晶体管呈错位排列。
  3. 根据权利要求1或2所述的阵列基板，其特征在于，位于同一行所述像素单元中的所述薄膜晶体管呈错位排列。
  4. 根据权利要求1所述的阵列基板，其特征在于，所述多晶硅有源层的截面呈S型，或呈Z字形。
  5. 一种显示面板，其特征在于，包括权利要求1-4任一项所述的阵列基板。
  6. 一种显示装置，其特征在于，包括权利要求5所述的显示面板。
  7. 根据权利要求6所述的显示装置，其特征在于，所述显示装置为液晶显示装置，或为有机电致发光显示装置。
  8. 一种阵列基板的制作方法，包括在衬底基板上制作薄膜晶体管的方法，其特征在于，所述制作薄膜晶体管的方法包括制作多晶硅有源层的方法，具体包括：
    在衬底基板上形成一层非晶硅层，采用构图工艺形成第一非晶硅层和第二非晶硅层，所述第一非晶硅层的位置对应薄膜晶体管的沟道位置；
    同时对所述第一非晶硅层和所述第二非晶硅层采用准分子激光束进行退火处理，形成第一多晶硅有源层和第二多晶硅有源层；其中：所述第一非晶硅层在预设方向上的延伸方向与所述准分子激光束的扫描方向平行。
  9. 根据权利要求8所述的制作方法，其特征在于，所述同时对所述第一 非晶硅层和所述第二非晶硅层采用准分子激光束进行退火处理之前，还包括：
    在400℃到450℃的温度下，对所述第一非晶硅层和所述第二非晶硅层进行0.5小时到3小时的加热处理。
  10. 根据权利要求8所述的制作方法，其特征在于，所述采用准分子激光束进行退火处理时，激光的脉冲频率为250HZ到350HZ，重叠率为92％到98％，扫描速率为2.4mm/s到9.6mm/s，能量密度为300mJ/cm 2到500mJ/cm 2。
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