CN105609422A - 一种薄膜晶体管及其制作方法、阵列基板和显示装置 - Google Patents

一种薄膜晶体管及其制作方法、阵列基板和显示装置 Download PDF

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CN105609422A
CN105609422A CN201610124743.9A CN201610124743A CN105609422A CN 105609422 A CN105609422 A CN 105609422A CN 201610124743 A CN201610124743 A CN 201610124743A CN 105609422 A CN105609422 A CN 105609422A
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layer
film transistor
gate insulation
thin film
tft
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CN105609422B (zh
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敏健
李小龙
许正印
宋平
王有为
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BOE Technology Group Co Ltd
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Abstract

本发明提供一种薄膜晶体管及其制作方法、阵列基板和显示装置，该薄膜晶体管的制作方法包括：在基底上形成栅电极的图形；形成表面平坦的栅绝缘层；形成多晶硅半导体层的图形，其中，所述形成多晶硅半导体层的图形的步骤包括：将非晶硅层进行结晶处理，形成多晶硅半导体层的步骤；形成源电极和漏电极的图形。本发明在制作薄膜晶体管过程中，由于栅绝缘层表面平坦，因而位于栅绝缘层上方的非晶硅层也成为表面平坦的膜层，克服了现有技术中因非晶硅的不平整导致结晶效果变差的问题，提高了结晶效果，从而提升了薄膜晶体管的性能。

Description

一种薄膜晶体管及其制作方法、阵列基板和显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种薄膜晶体管及其制作方法、阵列基板和显示装置。
背景技术
底栅型低温多晶硅薄膜晶体管(LTPSTFT)通常包括：栅电极、栅绝缘层、多晶硅半导体层，源电极和漏电极。其中，形成多晶硅半导体层的工艺通常是先形成非晶硅层，然后对非晶硅层进行ELA(准分子激光退火)结晶处理，形成多晶硅半导体层。由于栅绝缘层下具有栅电极，因而会在栅电极所在部分形成凸起，由于该凸起的存在，使得非晶硅层平整度变差，在ELA结晶过程中，会因为非晶硅层的不平整使得结晶效果变差，从而造成低温多晶硅薄膜晶体管特性不稳定。
发明内容
有鉴于此，本发明提供一种薄膜晶体管及其制作方法、阵列基板和显示装置，以解决因在非晶硅结晶成多晶硅过程中，由于非晶硅层的不平整使得结晶效果变差，导致低温多晶硅半导体层晶体管特性不稳定的问题。
为解决上述技术问题，本发明提供一种薄膜晶体管的制作方法，包括：
在基底上形成栅电极的图形；
形成表面平坦的栅绝缘层；
形成多晶硅半导体层的图形，其中，所述形成多晶硅半导体层的图形的步骤包括：将非晶硅层进行结晶处理，形成多晶硅半导体层的步骤；
形成源电极和漏电极的图形。
优选地，所述形成表面平坦的栅绝缘层的步骤包括：
沉积栅绝缘层薄膜，所述栅绝缘层薄膜的厚度大于或等于所述栅绝缘层的实际所需厚度与所述栅电极的厚度之和；
将所述栅绝缘层薄膜上的凸起处理平坦，形成表面平坦的栅绝缘层。
优选地，采用化学机械研磨工艺将所述栅绝缘层薄膜上的凸起处理平坦。
优选地，形成多晶硅半导体层的图形之后，形成源电极和漏电极的图形之前，还包括：
沉积非晶硅掺杂层；
对所述非晶硅掺杂层进行构图，形成非晶硅掺杂层的图形，所述非晶硅掺杂层位于所述多晶硅半导体层上的源电极接触区域和漏电极接触区域。
优选地，所述非晶硅掺杂层为非晶硅高掺杂P+层。
优选地，所述基底为柔性基底。
本发明提供一种薄膜晶体管，包括：
基底；
栅电极，位于所述基底上；
表面平坦的栅绝缘层，位于所述栅电极上；
多晶硅半导体层，位于所述栅绝缘层上；
源电极和漏电极，位于所述多晶硅半导体层上。
优选地，所述薄膜晶体管还包括：
非晶硅掺杂层，所述非晶硅掺杂层位于所述多晶硅半导体层上的源电极接触区域和漏电极接触区域，并与所述源电极和漏电极接触。
优选地，所述非晶硅掺杂层为非晶硅高掺杂P+层。
优选地，所述基底为柔性基底。
本发明还提供一种阵列基板，包括上述薄膜晶体管。
本发明还提供一种显示装置，包括上述阵列基板。
本发明的上述技术方案的有益效果如下：
在制作多晶硅薄膜晶体管过程中，由于形成的栅绝缘层表面平坦，因而位于栅绝缘层上方的非晶硅层也成为表面平坦的膜层，克服了现有技术中因非晶硅的不平整导致结晶效果变差的问题，提高了结晶效果，从而提升了薄膜晶体管的性能。
附图说明
图1-图11为本发明实施例的低温多晶硅薄膜晶体管的制作方法示意图；
附图标记说明：
101刚性基板；102柔性基底；103缓冲层；104栅电极；105栅绝缘层薄膜；105’栅绝缘层；106非晶硅层；106’多晶硅半导体层；106”多晶硅半导体层的图形；107非晶硅高掺杂p+层的图形；108A源电极；108B漏电极。
具体实施方式
为解决因在非晶硅结晶成多晶硅过程中，由于非晶硅层的不平整使得结晶效果变差，导致低温多晶硅薄膜晶体管特性不稳定的问题，本发明提供一种薄膜晶体管的制作方法，包括：
步骤S11：在基底上形成栅电极的图形；
步骤S12：形成表面平坦的栅绝缘层；
步骤S13：形成多晶硅半导体层的图形，其中，所述形成多晶硅半导体层的图形的步骤包括：将非晶硅层进行结晶处理，形成多晶硅半导体层的步骤；
步骤S14：形成源电极和漏电极的图形。
在制作多晶硅薄膜晶体管过程中，由于形成的栅绝缘层表面平坦，因而位于栅绝缘层上方的非晶硅层也成为表面平坦的膜层，克服了现有技术中因非晶硅的不平整导致结晶效果变差的问题，提高了结晶效果，从而提升了薄膜晶体管的性能。
下面对如何形成表面平坦的栅绝缘层进行详细说明。
在本发明的一优选实施例中，所述形成表面平坦的栅绝缘层的步骤包括：
步骤S121：沉积栅绝缘层薄膜，所述栅绝缘层薄膜的厚度大于或等于所述栅绝缘层的实际所需厚度与所述栅电极的厚度之和；
步骤S122：将所述栅绝缘层薄膜上的凸起处理平坦，形成表面平坦的栅绝缘层。
也就是说，先沉积一层栅绝缘层薄膜，由于栅电极的存在，栅绝缘层薄膜在栅电极部分会形成凸起，将该部分凸起处理平坦，即可形成表面平坦的栅绝缘层。
本实施例中，在现有技术中的栅绝缘层的形成工艺的基础上，只需多沉积一定厚度的栅绝缘层薄膜，然后将栅绝缘层的凸起部分处理平坦即可，工艺改动并不大。
当然，在本发明的其他一些实施例中，也不排除采用其他方法形成具有平坦表面的栅绝缘层。
进一步优选地，可采用化学机械研磨工艺将所述栅绝缘层薄膜上的凸起处理平坦。化学机械研磨技术综合了化学研磨和机械研磨的优势。单纯的化学研磨，表面精度较高，损伤低，完整性好，不容易出现表面/亚表面损伤，但是研磨速率较慢，材料去除效率较低，不能修正表面型面精度，研磨一致性比较差；单纯的机械研磨，研磨一致性好，表面平整度高，研磨效率高，但是容易出现表面层/亚表面层损伤，表面粗糙度值比较低。化学机械研磨吸收了两者各自的优点，可以在保证材料去除效率的同时，获得较完美的表面，得到的平整度比单纯使用这两种研磨要高出1-2个数量级，并且可以实现纳米级到原子级的表面粗糙度。
当然，在本发明的其他一些实施例中，也可采用单纯的化学研磨工艺，或者单纯的机械研磨工艺，将所述栅绝缘层薄膜上的凸起处理平坦。
本发明实施例可采用以下两种方法形成多晶硅半导体层的图形。
一种方法包括以下步骤：
步骤S131：沉积形成非晶硅层；
步骤S132：对所述非晶硅层结晶处理，形成多晶硅半导体层；
步骤S133：对所述多晶硅半导体层进行构图，形成多晶硅半导体层的图形。
优选地，可采用准分子激光退火对非晶硅层进行结晶处理。
该种方法是先对非晶硅层进行结晶处理，形成多晶硅半导体层，然后对多晶硅半导体层进行构图，形成多晶硅半导体层图形，在采用准分子激光退火对非晶硅层进行结晶处理时，该种方法可以防止激光对非晶硅层下方的膜层造成影响。
另一种方法包括以下步骤：
步骤S131’：沉积形成非晶硅层；
步骤S132’：对非晶硅层进行构图，形成非晶硅层的图形；
步骤S133’：对构图后的非晶硅层进行结晶处理，形成多晶硅半导体层的图形。
优选地，可采用准分子激光退火对非晶硅层进行结晶处理。
该种方法是先对非晶硅层进行构图，形成非晶硅层的图形，然后进行结晶处理，形成多晶硅半导体层的图形。在采用准分子激光退火对非晶硅层进行结晶处理时，为防止激光对非晶硅层下方的膜层造成影响，本发明实施例中，可以在进行激光准分子退火时，采用设置遮挡板等方式遮挡住除非晶硅层之外的其他区域。
本发明实施例中，为进一步提高低温多晶硅薄膜晶体管的性能，可在源电极和漏电极与多晶硅半导体层之间形成欧姆接触层，以降低源电极和漏电极与多晶硅半导体层的接触面的电阻值。
也就是说，在形成多晶硅半导体层的图形之后，形成源电极和漏电极的图形之前，本发明实施例的薄膜晶体管的制作方法还可以包括：
步骤S21：沉积非晶硅掺杂层；
步骤S22：对所述非晶硅掺杂层进行构图，形成非晶硅掺杂层的图形，所述非晶硅掺杂层位于所述多晶硅半导体层上的源电极接触区域和漏电极接触区域。
优选地，所述非晶硅掺杂层为非晶硅高掺杂P+层。
所述非晶硅掺杂层即欧姆接触层，用于降低源电极和漏电极与多晶硅半导体层的接触面的电阻值。
在本发明的其他一些实施例中，也可先沉积非晶硅层，然后对非晶硅层进行离子注入，形成欧姆接触层，然而对非晶硅层进行离子注入后，需要进行高温活化处理，因而，该种工艺难以适用于采用柔性基底的低温多晶硅薄膜晶体管。
上述采用直接沉积非晶硅掺杂层的方法由于不需要进行高温活化，因而可适用于采用柔性基底的低温多晶硅薄膜晶体管。同时，由于增加了提高欧姆接触的非晶硅掺杂层，也可以补偿非晶硅的结晶效果不是很好的缺陷。
优选地，本发明实施例的低温多晶硅薄膜晶体管中的基底可以为柔性基底，即本发明实施例的低温多晶硅薄膜晶体管为柔性低温多晶硅薄膜晶体管，该种晶体管可应用于柔性显示器。柔性显示器是指在一定条件下可以任意弯曲或者以某种固定形状弯曲的显示器，它在可穿戴产品、医疗健康、军事等领域都有很好的应用前景。
当然，本发明实施例中的低温多晶硅薄膜晶体管中的基底可以为刚性基底。
下面将结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
请参考图1-图11，图1-图11是本发明实施例的用于制作低温多晶硅薄膜晶体管的制作方法，包括以下步骤：
步骤S31：请参考图1，在刚性基板101上制作一层柔性基底102；
所述刚性基板101可以为玻璃基板，所述柔性基底102的材料可以为聚酰亚胺等，厚度在5-15μm之间。
步骤S32：请参考图2，在柔性基底102上形成缓冲(buffer)层103。
可利用沉积方法形成缓冲层103，所述缓冲层103的材料可以为SiOx(氧化硅)或SiNx(氮化硅)，也可以同时使用两种膜层，进行堆叠沉积，厚度范围可在到之间。缓冲层103可以起到阻挡层和平坦化层的作用，同时有利于膜层之间应力的释放。
步骤S33：请参考图3，在缓冲层103上形成栅电极(Gate)104的图形。
可利用磁控溅射设备(sputter)沉积一栅金属薄膜，厚度范围可在到之间，材料可以是Al、Mo、Cu或W等金属，也可以是上述金属的合金。沉积完成后，采用构图工艺(包括曝光、显影和刻蚀工艺)对栅金属薄膜进行构图，形成栅电极104的图形。
步骤S34：请参考图4，在栅电极104上沉积栅绝缘层(GI)薄膜105，所述栅绝缘层薄膜105的厚度大于或等于所述栅绝缘层的实际所需厚度与所述栅电极104的厚度之和；
可利用PECVD(等离子体增强化学气相沉积法)沉积栅绝缘层薄膜105，栅绝缘层薄膜105的材料可以是SiOx或者SiNx，也可以是两者的叠加，厚度范围需要考虑到栅电极104的厚度，大于或等于所述栅绝缘层的实际所需厚度与所述栅电极104的厚度之和。例如，如果栅电极厚度为栅绝缘层的实际所需厚度为则沉积的栅绝缘层薄膜厚度需要大于或等于具体厚度可根据具体的工艺条件选择。
步骤S35：请参考图5和图6，采用化学机械研磨工艺将所述栅绝缘层薄膜105上的凸起处理平坦，形成表面平坦的栅绝缘层105’，以利于后续沉积的非晶硅(a-Si)的晶化。
步骤S36：请参考图7，在所述栅绝缘层105’上沉积非晶硅层106。
非晶硅层106的沉积温度可在400℃以下，厚度范围可为随后，可在接近400℃条件下对非晶硅层106进行100分钟以上时间的去氢退火。
步骤S37：请参考图8，利用准分子激光退火(ELA)工艺，对沉积的非晶硅层106进行结晶处理，形成多晶硅半导体层106’。
ELA工艺可以利用波长范围约在308nm的XeCl激光，激光重叠率在90％到98％之间。经过ELA工艺之后，非晶硅在激光能量作用下发生重构，成为多晶硅(poly-Si)。
步骤S38：请参考图9，对多晶硅半导体层106’进行构图，形成多晶硅半导体层的图形106”。
步骤S39：请参考图10，在多晶硅半导体层上沉积一层非晶硅高掺杂p+层，并对所述非晶硅高掺杂p+层进行构图，形成非晶硅高掺杂p+层的图形107。
可利用PECVD方法沉积所述非晶硅高掺杂p+层，厚度范围可在到之间，沉积温度可在400℃以下。非晶硅高掺杂p+层的作用为了使得多晶硅半导体层和后续形成的源电极和漏电极产生良好的欧姆接触。
步骤S310：请参考图11，形成源电极108A和漏电极108B的图形。
可利用磁控溅射设备(sputter)沉积源电极和漏电极。源电极和漏电极的厚度范围可在到之间，材料可以是Al、Mo、Cu或W等金属，也可以是这些金属的合金。
至此，柔性低温多晶硅薄膜晶体管就制作完成了。
本发明实施例还提供一种薄膜晶体管，包括：
基底；
栅电极，位于所述基底上；
表面平坦的栅绝缘层，位于所述栅电极上；
多晶硅半导体层，位于所述栅绝缘层上；
源电极和漏电极，位于所述多晶硅半导体层上。
优选地，所述薄膜晶体管还包括：
非晶硅掺杂层，所述非晶硅掺杂层位于所述多晶硅半导体层上的源电极接触区域和漏电极接触区域，并与所述源电极和漏电极接触。
优选地，所述非晶硅掺杂层为非晶硅高掺杂P+层。
优选地，所述基底为柔性基底。
本发明实施例还提供一种阵列基板，包括上述薄膜晶体管。
本发明实施例还提供一种显示装置，包括上述阵列基板。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (12)

1.一种薄膜晶体管的制作方法，其特征在于，包括：
在基底上形成栅电极的图形；
形成表面平坦的栅绝缘层；
形成多晶硅半导体层的图形，其中，所述形成多晶硅半导体层的图形的步骤包括：将非晶硅层进行结晶处理，形成多晶硅半导体层的步骤；
形成源电极和漏电极的图形。
2.根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，所述形成表面平坦的栅绝缘层的步骤包括：
沉积栅绝缘层薄膜，所述栅绝缘层薄膜的厚度大于或等于所述栅绝缘层的实际所需厚度与所述栅电极的厚度之和；
将所述栅绝缘层薄膜上的凸起处理平坦，形成表面平坦的栅绝缘层。
3.根据权利要求2所述的薄膜晶体管的制作方法，其特征在于，采用化学机械研磨工艺将所述栅绝缘层薄膜上的凸起处理平坦。
4.根据权利要求1所述的薄膜晶体管的制作方法，其特征在于，形成多晶硅半导体层的图形之后，形成源电极和漏电极的图形之前，还包括：
沉积非晶硅掺杂层；
对所述非晶硅掺杂层进行构图，形成非晶硅掺杂层的图形，所述非晶硅掺杂层位于所述多晶硅半导体层上的源电极接触区域和漏电极接触区域。
5.根据权利要求4所述的薄膜晶体管的制作方法，其特征在于，所述非晶硅掺杂层为非晶硅高掺杂P+层。
6.根据权利要求1-5任一项所述的薄膜晶体管的制作方法，其特征在于，所述基底为柔性基底。
7.一种薄膜晶体管，其特征在于，包括：
基底；
栅电极，位于所述基底上；
表面平坦的栅绝缘层，位于所述栅电极上；
多晶硅半导体层，位于所述栅绝缘层上；
源电极和漏电极，位于所述多晶硅半导体层上。
8.根据权利要求7所述的薄膜晶体管，其特征在于，还包括：
非晶硅掺杂层，所述非晶硅掺杂层位于所述多晶硅半导体层上的源电极接触区域和漏电极接触区域，并与所述源电极和漏电极接触。
9.根据权利要求8所述的薄膜晶体管的制作方法，其特征在于，所述非晶硅掺杂层为非晶硅高掺杂P+层。
10.根据权利要求7-9任一项所述的薄膜晶体管的制作方法，其特征在于，所述基底为柔性基底。
11.一种阵列基板，其特征在于，包括如权利要求7-10任一项所述的薄膜晶体管。
12.一种显示装置，其特征在于，包括如权利要求11所述的阵列基板。
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