WO2019028972A1 - 底栅型低温多晶硅晶体管的制备方法 - Google Patents

底栅型低温多晶硅晶体管的制备方法 Download PDF

Info

Publication number
WO2019028972A1
WO2019028972A1 PCT/CN2017/102585 CN2017102585W WO2019028972A1 WO 2019028972 A1 WO2019028972 A1 WO 2019028972A1 CN 2017102585 W CN2017102585 W CN 2017102585W WO 2019028972 A1 WO2019028972 A1 WO 2019028972A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
polysilicon
stacked structure
etch barrier
preparing
Prior art date
Application number
PCT/CN2017/102585
Other languages
English (en)
French (fr)
Inventor
李松杉
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US15/576,200 priority Critical patent/US20190123173A1/en
Publication of WO2019028972A1 publication Critical patent/WO2019028972A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a bottom gate type low temperature polysilicon transistor.
  • Low Temperature Poly-Silicon, LTPS has attracted wide attention due to its high electron mobility, good subthreshold swing, large switching current ratio, low power consumption, high pixel density PPI, and its application on flexible OLED substrates.
  • the polysilicon layer and the etch barrier layer are separately defined by using two masks, and the process flow is complicated and the fabrication cost is high.
  • the invention provides a preparation method of a bottom gate type low temperature polysilicon transistor, which can simplify the process flow and save manufacturing cost.
  • another technical solution adopted by the present invention is to provide a method for preparing a bottom gate type low temperature polysilicon transistor, the method comprising: preparing a first stacked structure on a substrate; Forming a polysilicon layer and an etch barrier layer on a stacked structure; simultaneously patterning the polysilicon layer and the etch barrier layer such that the etch barrier layer covers a portion of the polysilicon layer, including: using a semi-transparent mask Forming, by the board, the polysilicon layer and the etch barrier layer, wherein a region of the semi-transparent mask corresponding to the polysilicon layer and a region corresponding to the etch barrier layer are different; Ion implantation is performed on the polysilicon layer covered by the etch barrier layer to form a source/drain region of the low temperature polysilicon transistor, wherein the ion adopts one of boron ion, strontium ion, strontium ion and cobalt ion .
  • another technical solution adopted by the present invention is to provide a method for preparing a bottom gate type low temperature polysilicon transistor, the method comprising: preparing a first stacked structure on a substrate; Forming a polysilicon layer and an etch barrier layer on a stacked structure; simultaneously patterning the polysilicon layer and the etch stop layer such that the etch stop layer covers a portion of the polysilicon layer; without being blocked by the etch Ion implantation is performed on the layer-covered polysilicon layer to form source/drain regions of the low temperature polysilicon transistor.
  • a bottom gate type low temperature polysilicon transistor comprising: a substrate; a first stacked structure prepared on the base substrate; a patterned polysilicon layer Prepared on the first stacked structure; a patterned etch stop layer is formed on the polysilicon layer, the etch stop layer covers a portion of the polysilicon layer; and a second stacked structure is formed on the polysilicon layer and On the etch barrier layer, the second stacked structure includes a source/drain electrode layer, a planarization layer, an anode layer, a pixel definition layer, and a support layer.
  • the invention has the beneficial effects of providing a method for preparing a bottom gate type low temperature polysilicon transistor, which can simplify the process flow and save manufacturing cost by simultaneously patterning the polysilicon layer and the etching barrier layer.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for fabricating a bottom gate type low temperature polysilicon transistor according to the present invention
  • FIG. 2 is a schematic flow chart of the first embodiment of step S1 in FIG. 1 of the present invention.
  • FIG. 3 is a schematic flow chart of an embodiment of preparing a polysilicon layer according to the present invention.
  • FIG. 4 is a schematic view showing a first stacked structure, a polysilicon layer, and an etch barrier layer in a first embodiment of a method for fabricating a bottom gate type low temperature polysilicon transistor according to the present invention
  • FIG. 5 is a schematic diagram of patterning a polysilicon layer and an etch barrier layer in a first embodiment of a method for fabricating a bottom gate type low temperature polysilicon transistor according to the present invention
  • FIG. 6 is a schematic view showing a patterning process of a polysilicon layer and an etch barrier layer in a first embodiment of a method for fabricating a bottom gate type low temperature polysilicon transistor according to the present invention
  • FIG. 7 is a schematic flow chart of a second embodiment of a method for fabricating a bottom gate type low temperature polysilicon transistor according to the present invention.
  • step S26 in FIG. 7 is a schematic flow chart of an embodiment of step S26 in FIG. 7;
  • FIG. 9 is a schematic structural view of an embodiment of a bottom gate type low temperature polysilicon transistor of the present invention.
  • FIG. 1 is a schematic flow chart of an embodiment of a method for fabricating a bottom gate type low temperature polysilicon transistor according to the present invention.
  • the substrate may be a transparent material, and may be any substrate such as a glass, a ceramic substrate, or a transparent plastic.
  • the present invention is not limited thereto, and in the embodiment, the substrate used is a glass substrate. .
  • a first layered structure is prepared on the array substrate, as shown in FIG. 2, and the step S11 may specifically include the following sub-steps:
  • a buffer layer and a gate layer are sequentially deposited on the base substrate.
  • a buffer layer Buffer is deposited on the substrate, and the material of the buffer layer may be one of, but not limited to, silicon oxide (SiOx) and silicon nitride (SiNx), which is not specifically limited in this embodiment. .
  • the role of the deposition buffer layer is to prevent metal ions (aluminum, germanium, sodium, etc.) in the substrate (the glass substrate in this embodiment) from diffusing into the active region of the low-temperature polysilicon in a thermal process, through the thickness of the buffer layer or The deposition conditions can improve the quality of the back side of the polysilicon.
  • the buffer layer is advantageous for reducing heat conduction, slowing down the cooling rate of the silicon heated by the laser, and facilitating crystallization of silicon.
  • a gate layer GE is deposited on the buffer layer, and the material of the gate layer may include, but not limited to, metal molybdenum Mo.
  • the gate layer is patterned by a photolithography process, and the photolithography process may further include specific steps such as gluing, aligning, exposing, and developing.
  • specific steps such as gluing, aligning, exposing, and developing.
  • a gate insulating layer GI is deposited on the buffer layer and the patterned gate layer, and the material of the gate insulating layer may be one of, but not limited to, silicon oxide (SiOx) and silicon nitride (SiNx). Silicon oxide is used in this embodiment.
  • step S13 a polysilicon layer is first prepared on the above laminated structure.
  • the polysilicon layer may be further prepared as follows:
  • an amorphous silicon layer is deposited on the gate insulating layer GI.
  • the amorphous silicon layer is subjected to crystallization treatment so that it is converted into a polysilicon layer.
  • the amorphous silicon layer is subjected to crystallization treatment, specifically, excimer laser crystallization annealing (Excimer Laser) Annealing, EAL), the method of irradiating amorphous silicon by excimer laser to realize the transformation of a-Si film into polysilicon film.
  • crystallization treatment specifically, excimer laser crystallization annealing (Excimer Laser) Annealing, EAL), the method of irradiating amorphous silicon by excimer laser to realize the transformation of a-Si film into polysilicon film.
  • an etching stopper layer is deposited on the above polysilicon layer (Etch Stop Layer), and the material of the etch barrier layer may also be one including, but not limited to, silicon nitride and silicon oxide.
  • FIG. 4 is a first stacked structure, a polysilicon layer, and a first embodiment of the method for fabricating a bottom gate type low temperature polysilicon transistor according to the present invention.
  • FIG. 4 is a first stacked structure, a polysilicon layer, and a first embodiment of the method for fabricating a bottom gate type low temperature polysilicon transistor according to the present invention.
  • the mask used for patterning the polysilicon layer and the etch barrier layer is a semi-transparent mask
  • the area corresponding to the polysilicon layer of the semi-transparent mask is corresponding to The areas of the etch stop layer have different light transmittances.
  • the middle portion of the semi-transparent mask is a non-transparent area A, and a part of the transparent area B and the total transparent area C are respectively distributed on both sides thereof.
  • the polysilicon layer and the etch barrier layer are simultaneously patterned by using the semi-transparent mask, and the patterning process can adopt a general lithography process, that is, specific steps including glue coating, alignment, exposure, and development, so that The polysilicon layer and the etch stop layer are patterned.
  • the shape of the further patterned polysilicon layer and the etch stop layer can be seen in FIG. In FIG. 6, the polysilicon layer corresponding to the non-transmissive region A of the semi-transparent mask and the etch stop layer remain, and the portion of the transparent layer B corresponding to the semi-transparent mask is retained, corresponding to the entire semi-transparent mask.
  • the light transmitting region C both of which are etched.
  • the etch barrier layer is partially covered with the polysilicon layer.
  • the polysilicon layer and the etch barrier layer are simultaneously patterned by using a semi-transparent mask to simplify the process and save manufacturing costs.
  • ion implantation is performed on the patterned polysilicon layer.
  • ion implantation is to ionize the atoms (molecules) to be injected, and after the ions are accelerated to the solid material, a series of collisions will occur with the nuclei and electrons in the material. After a tortuous path, the incident ion energy gradually Loss, and finally stay in the material and cause changes in the surface composition, structure and properties of the material.
  • the ions used may be one of, but not limited to, boron ions, strontium ions, strontium ions, and cobalt ions. Boron implants are used on the patterned polysilicon layer in this example to form the source/drain regions P+ of the low temperature polysilicon transistors.
  • activation and hydrogenation treatment of annealing are performed.
  • the hydrogenation treatment fills the unbonded or unsaturated bonds of the polycrystalline silicon atoms with hydrogen atoms, the grain boundary state, the hydrogenation defect layer, and the interface state to reduce the number of instability, and improve electrical characteristics, mobility, and threshold voltage uniformity.
  • the process flow can be simplified, and the manufacturing cost can be saved.
  • FIG. 7 is a schematic flow chart of a second embodiment of a method for fabricating a bottom gate type low temperature polysilicon transistor according to the present invention.
  • the present embodiment is further extended on the basis of the first embodiment of the method for manufacturing the bottom-gate type low-temperature polysilicon transistor, and the same points as those of the first embodiment are not described again, and the second embodiment further includes the following sub-steps. :
  • the second stacked structure includes a source/drain electrode layer (SD), a planarization layer (PLN), an anode layer (Anode), a pixel definition layer (PDL), and a support layer (PS).
  • SD source/drain electrode layer
  • PDN planarization layer
  • Anode anode layer
  • PDL pixel definition layer
  • PS support layer
  • step S25 further includes the following sub-steps:
  • the source/drain electrode layer is deposited on the patterned polysilicon layer and the etch barrier layer, and patterned by a photolithography process to form an SD source drain, wherein the photolithography process specifically includes steps of coating, alignment, exposure, and development. .
  • a planarization layer (PLN) is deposited on the source/drain electrode layer, and the planarization layer may be an organic photoresist material and patterned by a photolithography process.
  • An anode layer (Anode) is deposited on the patterned planarization layer and patterned by a photolithography process. Further, a pixel defining layer and a supporting layer are sequentially deposited on the patterned anode layer, and the pixel defining layer and the supporting layer may also be organic photoresist materials. Through the above preparation process, the preparation of the bottom gate type low temperature polysilicon transistor is completed.
  • the process flow can be simplified, and the manufacturing cost can be saved.
  • the present invention provides a method for fabricating a bottom gate type low temperature polysilicon transistor.
  • the process flow can be simplified and the manufacturing cost can be saved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种底栅型低温多晶硅晶体管的制备方法，包括：在衬底基板上制备第一层叠结构；依次在第一层叠结构上制备多晶硅层以及蚀刻阻挡层；同时对多晶硅层及蚀刻阻挡层进行图形化处理，以使得蚀刻阻挡层覆盖部分多晶硅层；在未被蚀刻阻挡层覆盖的多晶硅层上进行离子注入，以形成低温多晶硅晶体管的源极/漏极区域。能够简化工艺流程，节省制造成本。

Description

底栅型低温多晶硅晶体管的制备方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种底栅型低温多晶硅晶体管的制备方法。
【背景技术】
低温多晶硅（Low Temperature Poly-Silicon, LTPS）因其电子迁移率高，亚阈值摆幅好，开关态电流比大，耗电低，同时可以制作高像素密度PPI，且可以应用在柔性OLED基板上等特点而引起广泛关注。
传统的制备方法，需要采用两次光罩（mask）分别对多晶硅层及蚀刻阻挡层进行图形化定义，工艺流程复杂且制作成本高。
【发明内容】
本发明提供一种底栅型低温多晶硅晶体管的制备方法，能够简化工艺流程，节省制造成本。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种底栅型低温多晶硅晶体管的制备方法，所述方法包括：在衬底基板上制备第一层叠结构；依次在所述第一层叠结构上制备多晶硅层以及蚀刻阻挡层;同时对所述多晶硅层及所述蚀刻阻挡层进行图形化处理，以使得所述蚀刻阻挡层覆盖部分所述多晶硅层，包括：采用半透视掩膜板对所述多晶硅层及所述蚀刻阻挡层进行图形化处理，所述半透视掩膜板的对应所述多晶硅层的区域与对应所述蚀刻阻挡层的区域的透光率不同；在未被所述蚀刻阻挡层覆盖的多晶硅层上进行离子注入，以形成所述低温多晶硅晶体管的源极/漏极区域，其中，所述离子采用硼离子、铋离子、锗离子及钴离子中的一种。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种底栅型低温多晶硅晶体管的制备方法，所述方法包括：在衬底基板上制备第一层叠结构；依次在所述第一层叠结构上制备多晶硅层以及蚀刻阻挡层；同时对所述多晶硅层及所述蚀刻阻挡层进行图形化处理，以使得所述蚀刻阻挡层覆盖部分所述多晶硅层；在未被所述蚀刻阻挡层覆盖的多晶硅层上进行离子注入，以形成所述低温多晶硅晶体管的源极/漏极区域。
为解决上述技术问题，本发明采用的又一个技术方案是：一种底栅型低温多晶硅晶体管，包括：衬底基板；第一层叠结构，制备于所述衬底基板上；图形化的多晶硅层，制备于所述第一层叠结构上；图形化的蚀刻阻挡层，制备于所述多晶硅层上，所述蚀刻阻挡层覆盖部分所述多晶硅层；第二层叠结构，形成于所述多晶硅层及所述蚀刻阻挡层上，所述第二层叠结构包括源/漏电极层、平坦化层、阳极层、像素定义层以及支撑层。
本发明的有益效果是：提供一种底栅型低温多晶硅晶体管的制备方法，通过同时对多晶硅层及蚀刻阻挡层进行图形化处理，能够简化工艺流程，节省制造成本。
【附图说明】
图1是本发明底栅型低温多晶硅晶体管的制备方法第一实施方式的流程示意图；
图2是本发明图1中步骤S1的第一实施方式的流程示意图；
图3是本发明制备多晶硅层一实施方式的流程示意图；
图4是本发明底栅型低温多晶硅晶体管制备方法第一实施例中制备第一层叠结构、多晶硅层及蚀刻阻挡层的示意图；
图5是本发明底栅型低温多晶硅晶体管的制备方法第一实施方式中对多晶硅层及蚀刻阻挡层进行图形化处理的示意图；
图6是本发明底栅型低温多晶硅晶体管的制备方法第一实施方式中对多晶硅层及蚀刻阻挡层进行图形化处理后的示意图；
图7是本发明底栅型低温多晶硅晶体管的制备方法第二实施方式的流程示意图；
图8是图7中步骤S26一实施方式的流程示意图；
图9是本发明底栅型低温多晶硅晶体管一实施方式的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1，图1为本发明底栅型低温多晶硅晶体管的制备方法一实施方式的流程示意图。
S11，在衬底基板上制备第一层叠结构。
该步骤中，先提供一衬底基板。该衬底基板可以为透明材质，具体可以是玻璃、陶瓷基板或者透明塑料等任意形式的基板，此处本发明不做具体限定，且在本实施例中，所采用的衬底基板为玻璃基板。
进一步，在该阵列基板上制备第一层叠结构，如图2，且该步骤S11具体可以包括如下子步骤：
S111，在衬底基板上依次沉积缓冲层及栅极层。
在上述的衬底基板上沉积两层缓冲层Buffer，且该缓冲层的材料可以为包括但不限于氧化硅（SiOx）和氮化硅（SiNx）中的一种，本实施例不做具体限定。且沉积缓冲层的作用是防止衬底基板（本实施例中采用玻璃基板）中的金属离子（铝、钡、钠等）在热工艺中扩散到低温多晶硅的有源区，通过缓冲层厚度或沉积条件可以改善多晶硅背面的质量。进一步，该缓冲层有利于降低热传导，减缓被激光加热的硅冷却速率，利于硅的结晶。
进一步，在缓冲层上沉积栅极层GE，该栅极层的材料可以采用包括但不限于金属钼Mo。
S112，对栅极层进行图形化处理。
进一步对该栅极层采用光刻工艺使之图形化，且光刻工艺可以进一步包括涂胶、对准、曝光以及显影等具体步骤，此处可以参见现有技术中光刻工艺的具体操作流程，此处不做进一步限定。
S12，在缓冲层、栅极层上沉积栅极绝缘层。
接着在缓冲层及图形化后的栅极层上沉积栅极绝缘层GI，且栅极绝缘层的材料可以为包括但不限于氧化硅（SiOx）和氮化硅（SiNx）中的一种，本实施例中采用氧化硅。
S13，依次在第一层叠结构上制备多晶硅层以及蚀刻阻挡层。
步骤S13中，先在上述层叠结构上制备多晶硅层，参见图3，且制备多晶硅层可以进一步如下步骤：
S131，在第一层叠结构上沉积非晶硅层。
该步骤中，具体来说是在栅极绝缘层GI上沉积非晶硅层（amorphous silicon）。
S132，对非晶硅层进行结晶处理，以使得其转变为多晶硅层。
进一步对该非晶硅层进行结晶处理，具体可以采用准分子镭射结晶退火（Excimer Laser Annealing, EAL）的方式，即通过准分子激光对非晶硅进行照射，实现a-Si薄膜向多晶硅薄膜的转变。
进一步，在上述多晶硅层上沉积蚀刻阻挡层（Etch Stop Layer），且该蚀刻阻挡层的材料也可以为包括但不限于为氮化硅及氧化硅的一种。
且上述关于第一层叠结构、多晶硅层及蚀刻阻挡层的结构示意图可以具体参见图4，图4为本发明底栅型低温多晶硅晶体管制备方法第一实施例中制备第一层叠结构、多晶硅层及蚀刻阻挡层的示意图。
S14，同时对多晶硅层及蚀刻阻挡层进行图形化处理，以使得蚀刻阻挡层覆盖部分多晶硅层。
参阅图5，本实施例中，对多晶硅层及蚀刻阻挡层进行图形化处理所采用的掩膜板为半透视掩膜板，所述半透视掩膜板的对应所述多晶硅层的区域与对应所述蚀刻阻挡层的区域的透光率不同。具体如图5所示，该半透视掩膜板中间部分为非透光区A，以其为中心其两侧分别分布着部分透光区B以及全透光区C。采用该半透视掩膜板同时对多晶硅层及蚀刻阻挡层进行图形化处理，且该图形化处理可以采用一般的光刻工艺，即包括涂胶、对准、曝光以及显影等具体步骤，以使得多晶硅层及蚀刻阻挡层图形化。进一步图形化后的多晶硅层以及蚀刻阻挡层的形状可以参见图6。图6中，对应半透视掩膜板的非透光区A的多晶硅层以及蚀刻阻挡层保留下来，对应半透视掩膜板的部分透光区B多晶硅层保留，对应半透视掩膜板的全透光区C，二者均被蚀刻。经过该图形化处理后，使得蚀刻阻挡层部分覆盖多晶硅层。
且本步骤中，采用半透视掩膜板同时对多晶硅层及蚀刻阻挡层进行图形化处理，可以简化工艺流程，节省制造成本。
S15，在未被蚀刻阻挡层覆盖的多晶硅层上进行离子注入，以形成低温多晶硅晶体管的源极/漏极区域。
进一步，在图形化后的多晶硅层上进行离子注入。其中，离子注入是通过使待注入的原子（分子）电离，离子经过加速射到固体材料以后，与材料中的原子核与电子将发生一系列的碰撞，经过一段曲折路径的运动，入射离子能量逐渐损失，最后停留在材料中，并引起材料表面成分、结构和性能发生变化。且采用的离子可以为包括但不限于硼离子、铋离子、锗离子及钴离子中的一种。本实例中在图形化后的多晶硅层上采用硼离子（Boron）注入，以形成低温多晶硅晶体管的源极/漏极区域P+。
进一步，在进行退火的活化和氢化处理。其中，多晶硅晶粒之间存在粒界态，多晶硅与氧化层（栅极绝缘层）间存在界面态，影响晶体管电性。氢化处理以氢原子填补多晶硅原子的未结合键或者未饱和键，粒界态、氢化缺陷层以及界面态来减少不稳定数目，提升电特性、迁移率以及阈值电压均匀性等。
上述实施方式，在底栅型低温多晶硅晶体管的制备工艺中，通过同时对多晶硅层及蚀刻阻挡层进行图形化处理，能够简化工艺流程，节省制造成本。
请参见图7，图7为本发明底栅型低温多晶硅晶体管的制备方法第二实施方式的流程示意图。且本实施例是在底栅型低温多晶硅晶体管的制备方法第一实施方式的基础上的进一步扩展，且与第一实施方式相同之处不再赘述，且该第二实施方式进一步包括如下子步骤：
S21，在衬底基板上制备第一层叠结构。
S22，依次在第一层叠结构上制备多晶硅层以及蚀刻阻挡层。
S23，同时对多晶硅层及蚀刻阻挡层进行图形化处理，以使得蚀刻阻挡层覆盖部分多晶硅层。
S24，在未被蚀刻阻挡层覆盖的多晶硅层上进行离子注入，以形成低温多晶硅晶体管的源极/漏极区域。
S25，在未被蚀刻阻挡层覆盖的多晶硅层上进行离子注入，以形成低温多晶硅晶体管的源极/漏极区域。
S26，在图形化后的多晶硅层及蚀刻阻挡层上制备第二层叠结构，以完成低温多晶硅晶体管的制备。
参见图9，其中，第二层叠结构包括源/漏电极层（SD）、平坦化层（PLN）、阳极层（Anode）、像素定义层（PDL）以及支撑层（PS）。
参见图8，步骤S25进一步包括如下子步骤：
S261，在图形化后的多晶硅层及蚀刻阻挡层上制备源/漏电极层。
在图形化后的多晶硅层及蚀刻阻挡层沉积源/漏电极层，并通过光刻工艺使其图形化形成SD源漏极，其中光刻工艺具体包括涂胶、对准、曝光以及显影等步骤。
S262，在源/漏电极层上制备图形化的平坦化层。
在源/漏电极层上沉积平坦化层（PLN），该平坦化层可以为有机光阻材料，并通过光刻工艺以使得其图形化。
S263，在图形化的平坦化层上依次沉积像素定义层及支撑层。
在图形化后的平坦化层上沉积阳极层（Anode），并通过光刻工艺以使得其图形化。进一步在在图形化后的阳极层依次沉积像素定义层及支撑层，且像素定义层及支撑层也可以为有机光阻材料。通过上述的制备工艺，该底栅型低温多晶硅晶体管的制备完成。
上述实施方式，在底栅型低温多晶硅晶体管的制备工艺中，通过同时对多晶硅层及蚀刻阻挡层进行图形化处理，能够简化工艺流程，节省制造成本。
综上所述，本领域技术人员容易理解，本发明提供底栅型低温多晶硅晶体管的制备方法，通过同时对多晶硅层及蚀刻阻挡层进行图形化处理，能够简化工艺流程，节省制造成本。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种底栅型低温多晶硅晶体管的制备方法，其中，所述制备方法包括：
    在衬底基板上制备第一层叠结构；
    依次在所述第一层叠结构上制备多晶硅层以及蚀刻阻挡层；
    同时对所述多晶硅层及所述蚀刻阻挡层进行图形化处理，以使得所述蚀刻阻挡层覆盖部分所述多晶硅层，包括：
    采用半透视掩膜板对所述多晶硅层及所述蚀刻阻挡层进行图形化处理，所述半透视掩膜板的对应所述多晶硅层的区域与对应所述蚀刻阻挡层的区域的透光率不同；
    在未被所述蚀刻阻挡层覆盖的多晶硅层上进行离子注入，以形成所述低温多晶硅晶体管的源极/漏极区域，其中，所述离子采用硼离子、铋离子、锗离子及钴离子中的一种。
  2. 根据权利要求1所述的制备方法，其中，所述在所述层叠结构上制备多晶硅层包括：
    在所述第一层叠结构上沉积非晶硅层；
    对所述非晶硅层进行结晶处理，以使得其转变为多晶硅层。
  3. 根据权利要求2所述的制备方法，其中，所述对所述非晶硅层进行结晶处理采用准分子镭射结晶退火的方式。
  4. 根据权利要求1所述的制备方法，其中，所述形成所述低温多晶硅晶体管的源极/漏极区域之后进一步包括：
    在图形化后的所述多晶硅层及所述蚀刻阻挡层上制备第二层叠结构，以完成所述低温多晶硅晶体管的制备，其中，所述第二层叠结构包括源/漏极层、平坦化层、阳极层、像素定义层以及支撑层。
  5. 根据权利要求4所述的制备方法，其中，所述在图形化后的所述多晶硅层及所述蚀刻阻挡层上制备第二层叠结构包括：
    在图形化后的所述多晶硅层及所述蚀刻阻挡层上制备源/漏电极层；
    在所述源/漏电极层上制备图形化的平坦化层；
    在所述图形化的平坦化层上依次制备阳极层、像素定义层及支撑层。
  6. 根据权利要求5所述的制备方法，其中，所述平坦化层、像素定义层及所述支撑层为有机光阻材料。
  7. 根据权利要求1所述的制备方法，其中，所述在衬底基板上制备第一层叠结构包括：
    在所述衬底基板上依次沉积缓冲层及栅极层；
    对所述栅极层进行图形化处理；
    在所述缓冲层、所述栅极层上沉积栅极绝缘层。
  8. 根据权利要求7所述的制备方法，其中，所述缓冲层、所述蚀刻阻挡层的材料为氧化硅和氮化硅中的一种。
  9. 一种底栅型低温多晶硅晶体管的制备方法，其中，所述制备方法包括：
    在衬底基板上制备第一层叠结构；
    依次在所述第一层叠结构上制备多晶硅层以及蚀刻阻挡层；
    同时对所述多晶硅层及所述蚀刻阻挡层进行图形化处理，以使得所述蚀刻阻挡层覆盖部分所述多晶硅层；
    在未被所述蚀刻阻挡层覆盖的多晶硅层上进行离子注入，以形成所述低温多晶硅晶体管的源极/漏极区域。
  10. 根据权利要求9所述的制备方法，其中，所述同时对所述多晶硅层及所述蚀刻阻挡层进行图形化处理包括：
    采用半透视掩膜板对所述多晶硅层及所述蚀刻阻挡层进行图形化处理，所述半透视掩膜板的对应所述多晶硅层的区域与对应所述蚀刻阻挡层的区域的透光率不同。
  11. 根据权利要求9所述的制备方法，其中，所述在所述层叠结构上制备多晶硅层包括：
    在所述第一层叠结构上沉积非晶硅层；
    对所述非晶硅层进行结晶处理，以使得其转变为多晶硅层。
  12. 根据权利要求11所述的制备方法，其中，所述对所述非晶硅层进行结晶处理采用准分子镭射结晶退火的方式。
  13. 根据权利要求9所述的制备方法，其中，所述形成所述低温多晶硅晶体管的源极/漏极区域之后进一步包括：
    在图形化后的所述多晶硅层及所述蚀刻阻挡层上制备第二层叠结构，以完成所述低温多晶硅晶体管的制备，其中，所述第二层叠结构包括源/漏极层、平坦化层、阳极层、像素定义层以及支撑层。
  14. 根据权利要求13所述的制备方法，其中，所述在图形化后的所述多晶硅层及所述蚀刻阻挡层上制备第二层叠结构包括：
    在图形化后的所述多晶硅层及所述蚀刻阻挡层上制备源/漏电极层；
    在所述源/漏电极层上制备图形化的平坦化层；
    在所述图形化的平坦化层上依次制备阳极层、像素定义层及支撑层。
  15. 根据权利要求14所述的制备方法，其中，所述平坦化层、像素定义层及所述支撑层为有机光阻材料。
  16. 根据权利要求9所述的制备方法，其中，所述在衬底基板上制备第一层叠结构包括：
    在所述衬底基板上依次沉积缓冲层及栅极层；
    对所述栅极层进行图形化处理；
    在所述缓冲层、所述栅极层上沉积栅极绝缘层。
  17. 根据权利要求16所述的制备方法，其中，所述缓冲层、所述蚀刻阻挡层的材料为氧化硅和氮化硅中的一种。
  18. 根据权利要求9所述的制备方法，其中，所述离子采用硼离子、铋离子、锗离子及钴离子中的一种。
  19. 一种底栅型低温多晶硅晶体管，其中，包括：
    衬底基板；
    第一层叠结构，制备于所述衬底基板上；
    图形化的多晶硅层，制备于所述第一层叠结构上；
    图形化的蚀刻阻挡层，制备于所述多晶硅层上，所述蚀刻阻挡层覆盖部分所述多晶硅层；第二层叠结构，形成于所述多晶硅层及所述蚀刻阻挡层上，所述第二层叠结构包括源/漏电极层、平坦化层、阳极层、像素定义层以及支撑层。
PCT/CN2017/102585 2017-08-07 2017-09-21 底栅型低温多晶硅晶体管的制备方法 WO2019028972A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/576,200 US20190123173A1 (en) 2017-08-07 2017-09-21 Preparation method of bottom-gate type low-temperature polysilicon transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710670222.8 2017-08-07
CN201710670222.8A CN107527819B (zh) 2017-08-07 2017-08-07 底栅型低温多晶硅晶体管的制备方法

Publications (1)

Publication Number Publication Date
WO2019028972A1 true WO2019028972A1 (zh) 2019-02-14

Family

ID=60680762

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/102585 WO2019028972A1 (zh) 2017-08-07 2017-09-21 底栅型低温多晶硅晶体管的制备方法

Country Status (3)

Country Link
US (1) US20190123173A1 (zh)
CN (1) CN107527819B (zh)
WO (1) WO2019028972A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108831895B (zh) * 2018-08-28 2023-10-13 武汉华星光电技术有限公司 显示面板及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060258064A1 (en) * 2003-10-07 2006-11-16 Industrial Technology Research Institute Method of forming poly-silicon thin film transistors
KR20080047779A (ko) * 2006-11-27 2008-05-30 엘지디스플레이 주식회사 폴리실리콘 박막 트랜지스터 기판 및 그 제조 방법
CN101256961A (zh) * 2008-04-08 2008-09-03 友达光电股份有限公司 薄膜晶体管结构、像素结构及其制造方法
CN105225953A (zh) * 2014-06-16 2016-01-06 上海和辉光电有限公司 薄膜晶体管的制造方法和阵列基板的制造方法
CN105609422A (zh) * 2016-03-04 2016-05-25 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9318614B2 (en) * 2012-08-02 2016-04-19 Cbrite Inc. Self-aligned metal oxide TFT with reduced number of masks and with reduced power consumption
CN103050410B (zh) * 2012-10-30 2015-09-16 昆山工研院新型平板显示技术中心有限公司 低温多晶硅薄膜晶体管的制造方法、低温多晶硅薄膜晶体管
CN104576387B (zh) * 2013-10-14 2017-07-25 上海和辉光电有限公司 低温多晶硅薄膜晶体管制造方法
CN105097544A (zh) * 2014-05-23 2015-11-25 上海和辉光电有限公司 一种低温多晶硅薄膜晶体管的制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060258064A1 (en) * 2003-10-07 2006-11-16 Industrial Technology Research Institute Method of forming poly-silicon thin film transistors
KR20080047779A (ko) * 2006-11-27 2008-05-30 엘지디스플레이 주식회사 폴리실리콘 박막 트랜지스터 기판 및 그 제조 방법
CN101256961A (zh) * 2008-04-08 2008-09-03 友达光电股份有限公司 薄膜晶体管结构、像素结构及其制造方法
CN105225953A (zh) * 2014-06-16 2016-01-06 上海和辉光电有限公司 薄膜晶体管的制造方法和阵列基板的制造方法
CN105609422A (zh) * 2016-03-04 2016-05-25 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置

Also Published As

Publication number Publication date
CN107527819A (zh) 2017-12-29
US20190123173A1 (en) 2019-04-25
CN107527819B (zh) 2019-08-30

Similar Documents

Publication Publication Date Title
CN105552027B (zh) 阵列基板的制作方法及阵列基板
WO2012071878A1 (zh) 一种晶体管的制造方法
WO2016201729A1 (zh) 一种阵列基板及其制作方法、液晶显示器
WO2016165186A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
WO2019000493A1 (zh) 薄膜晶体管阵列基板及其制备方法、oled显示装置
WO2017219432A1 (zh) 一种薄膜晶体管阵列基板及液晶面板
WO2014166176A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
WO2012097563A1 (zh) 一种薄膜晶体管的制作方法
US20180212061A1 (en) Dual gate oxide thin-film transistor and manufacturing method for the same
WO2015090016A1 (zh) 薄膜晶体管和阵列基板及其各自制备方法、以及显示装置
WO2016165187A1 (zh) 双栅极氧化物半导体tft基板的制作方法及其结构
WO2016074204A1 (zh) 基于双栅极结构的低温多晶硅薄膜晶体管及其制备方法
US10699905B2 (en) Low-temperature polysilicon (LTPS), thin film transistor (TFT), and manufacturing method of array substrate
WO2018120309A1 (zh) Oled显示装置的阵列基板及其制作方法
WO2019085065A1 (zh) 柔性 oled 显示面板及其制备方法
WO2015188594A1 (zh) 多晶硅层及显示基板的制备方法、显示基板
US20230352496A1 (en) Array substrate and display panel
WO2018205318A1 (zh) 一种tft阵列基板及其制作方法
WO2019029007A1 (zh) 一种tft基板的制备方法、tft基板以及oled显示面板
WO2016201725A1 (zh) 低温多晶硅tft基板的制作方法及低温多晶硅tft基板
CN102427061B (zh) 有源矩阵有机发光显示器的阵列基板制造方法
WO2017140015A1 (zh) 双栅极tft阵列基板及制作方法
WO2015168961A1 (zh) 薄膜晶体管阵列基板制造方法及薄膜晶体管阵列基板
WO2021120378A1 (zh) 一种阵列基板及其制作方法
WO2016078112A1 (zh) 薄膜晶体管基板的制作方法及制造设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17921002

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17921002

Country of ref document: EP

Kind code of ref document: A1