WO2018210041A1 - 一种阵列基板及其制作方法、显示面板 - Google Patents

一种阵列基板及其制作方法、显示面板 Download PDF

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WO2018210041A1
WO2018210041A1 PCT/CN2018/078681 CN2018078681W WO2018210041A1 WO 2018210041 A1 WO2018210041 A1 WO 2018210041A1 CN 2018078681 W CN2018078681 W CN 2018078681W WO 2018210041 A1 WO2018210041 A1 WO 2018210041A1
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gate
semiconductor layer
layer
substrate
forming
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PCT/CN2018/078681
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English (en)
French (fr)
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操彬彬
黄寅虎
杨成绍
钱海蛟
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US16/096,587 priority Critical patent/US11532643B2/en
Publication of WO2018210041A1 publication Critical patent/WO2018210041A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display panel.
  • a thin film transistor applied to a TFT LCD mainly includes an amorphous silicon thin film transistor (a-Si TFT) and a polysilicon thin film transistor (Poly-Si TFT).
  • a-Si TFT amorphous silicon thin film transistor
  • Poly-Si TFT Polysilicon thin film transistor
  • Polycrystalline silicon mainly includes HTPS (High Temperature Poly-Silicon) and LTPS (Low Temperature Poly-Silicon).
  • amorphous silicon has many unavoidable shortcomings such as low mobility and low stability
  • low-temperature polysilicon has high mobility and stability, and its mobility can reach dozens or even hundreds of times of amorphous silicon. Therefore, the technology for forming a thin film transistor using a low-temperature polysilicon material has been rapidly developed, and a new generation of LCD or OLED (Organic Light-Emitting Diode) derived from LTPS has become an important display technology, especially an OLED display device. .
  • An array substrate provided by an embodiment of the present disclosure includes: a substrate substrate; a plurality of gate lines located above the substrate substrate; and gate electrodes corresponding to and spaced apart from each of the gate lines; a gate insulating layer and a gate insulating layer over the gate line, the gate insulating layer having a first via and a second via, the first via exposing the gate electrode, the second via exposing And a gate line; a conductive connection layer over the gate insulating layer and a polysilicon semiconductor layer, the conductive connection layer filling the first via and the second via to connect the gate line and The gate electrode.
  • the array substrate further includes a source drain on the polysilicon semiconductor layer.
  • the conductive connection layer and the source drain are disposed in the same layer.
  • the gate electrode and the gate line are disposed in the same layer.
  • the polysilicon semiconductor layer is a p-type polysilicon semiconductor layer
  • the array substrate further includes: a first amorphous silicon semiconductor layer and an n-type polysilicon semiconductor layer over the polysilicon semiconductor layer.
  • an orthographic projection of the polysilicon semiconductor layer on the substrate substrate at least partially overlaps with an orthographic projection of the gate electrode on the substrate substrate.
  • Another embodiment of the present disclosure provides a display panel comprising the array substrate as described in any of the foregoing embodiments.
  • a further embodiment of the present disclosure provides a method for fabricating an array substrate, including:
  • the gate insulating layer including a first via for exposing the gate electrode and a second via for exposing the gate line ;
  • a polysilicon semiconductor layer is formed on the gate insulating layer.
  • the method further includes: forming a source drain on the polysilicon semiconductor layer; forming a conductive connection layer on the gate insulating layer, the conductive connection layer filling the first via and the second A via hole connects the gate line and the gate electrode.
  • the step of forming a gate insulating layer includes: forming a gate insulating layer including the first via and the second via by a patterning process.
  • the step of forming a gate insulating layer includes: forming an insulating film covering the gate electrode and the gate line; etching the insulating film to obtain a first via hole exposing the gate electrode, And a second via that exposes the gate line.
  • forming a polysilicon semiconductor layer on the gate insulating layer includes: forming a second amorphous silicon semiconductor layer on the gate insulating layer by a patterning process; and in the second amorphous silicon semiconductor layer A region corresponding to the gate electrode is subjected to a local laser annealing process to form the polysilicon semiconductor layer.
  • the local laser annealing process is a micro mirror array (MLA) local laser annealing process.
  • MLA micro mirror array
  • the conductive connection layer is formed on the gate insulating layer by the same patterning process while forming the source drain.
  • the polysilicon semiconductor layer is a p-type polysilicon semiconductor layer
  • the method further comprises: forming a first amorphous silicon semiconductor layer and an n-type polysilicon semiconductor layer on the p-type polycrystalline silicon semiconductor layer.
  • FIG. 1 is a partial cross-sectional view of an array substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of an active layer according to an embodiment of the present disclosure
  • FIG. 3 is a schematic flow chart of a method for fabricating an array substrate according to an embodiment of the present disclosure
  • 4a is used to illustrate a positional relationship of a gate electrode and a gate line provided according to an embodiment of the present disclosure
  • 4b is for illustrating a first via and a second via in a gate insulating layer of an array substrate according to an embodiment of the present disclosure.
  • a process of forming a polycrystalline silicon semiconductor layer includes: forming an amorphous silicon semiconductor layer, and then performing a local laser annealing process on the amorphous silicon layer such that a region corresponding to the gate electrode in the amorphous silicon semiconductor layer is converted into a polycrystalline silicon semiconductor layer.
  • the melt crystallization can be completed by one laser irradiation, thereby improving the mobility of the semiconductor device.
  • the inventors of the present application have recognized that since the heat transfer efficiency of the metal is high and the gate line connected to the gate electrode is spread over the entire display panel, heat radiated on the amorphous silicon semiconductor layer is transferred to the gate electrode, and these The heat is further dispersed to the respective regions of the display panel through the gate lines connected to the gate electrodes, so that the laser energy is low in efficiency for converting the amorphous silicon semiconductor layer, and the crystallization effect is poor.
  • an array substrate see FIG. 1, which includes: a substrate substrate 110; and a substrate substrate 110 a plurality of rows of gate lines 130 (a cross section of one gate line 130 is schematically illustrated in FIG. 1 perpendicular to a length extension direction thereof), and a gate electrode 120 corresponding to and spaced apart from each row of gate lines 130; a gate insulating layer 140 over the electrode 120 and the gate line 130, and a first via 141 and a second via 142 in the gate insulating layer 140, wherein the first via 141 exposes the gate electrode 120, The second via 142 exposes the gate line 130.
  • the array substrate further includes a conductive connection layer 150 and a polysilicon semiconductor layer 161 over the gate insulating layer 140, and a source drain 170 above the polysilicon semiconductor layer 161.
  • the conductive connection layer 150 fills the first via 141 and the second via 142 such that the gate line 130 is connected to the gate electrode 120 via a conductive connection layer.
  • each gate line 130 can drive a corresponding gate electrode 120 of the gate line (only one cross-section 120 of the gate electrode is schematically illustrated in FIG. 1), and each gate electrode 120 corresponds to a thin film transistor. TFT.
  • the array substrate further includes: a first amorphous silicon semiconductor layer 163 and an n-type polysilicon semiconductor layer 164 over the polysilicon semiconductor layer 161.
  • the array substrate may further include a second amorphous silicon semiconductor layer 162 in the same layer as the polysilicon semiconductor layer 161.
  • the orthographic projection of the polysilicon semiconductor layer 161 on the substrate substrate and the orthographic projection of the gate electrode on the substrate substrate at least partially overlap.
  • the polysilicon semiconductor layer 161, the second amorphous silicon semiconductor layer 162, the first amorphous silicon semiconductor layer 163, and the n-type polysilicon semiconductor layer 164 form the active layer 160 (see FIG. 1).
  • the first amorphous silicon semiconductor layer 163 is mainly used to reduce leakage current
  • the n-type polysilicon semiconductor layer 164 is mainly used to increase an on-state current.
  • the gate electrode and the gate line are in a non-connected state when the polysilicon semiconductor layer is formed (when the conductive connection layer 150 is not formed), thereby at least avoiding The heat is transferred to the gate line in a large amount, which can alleviate or reduce the diffusion of the laser energy of the amorphous silicon semiconductor layer, so that the laser can illuminate the amorphous silicon layer more concentratedly, and raise the temperature of the gate electrode in a short time.
  • This can improve the conversion efficiency of polysilicon and the utilization efficiency of laser energy, and realize the effect of preparing a polycrystalline silicon semiconductor having a larger crystal grain and a higher mobility by using less laser resources.
  • the polysilicon semiconductor layer 161 disposed corresponding to the gate electrode is a p-type polysilicon semiconductor layer.
  • the conductive connection layer 150 and the source and drain electrodes 170 may be simultaneously formed by the same patterning process, that is, the conductive connection layer 150 and the source and drain electrodes 170 may be disposed in the same layer, and used for The material forming the conductive connection layer 150 and the source and drain electrodes 170 may be the same conductive material.
  • the gate electrode 120 and the gate line 130 can be simultaneously prepared, that is, the gate electrode 120 and the gate line 130 are disposed in the same layer, and the material for forming the gate electrode 120 and the gate line 130 can be the same conductive. material. This further contributes to shortening the process time and improving the efficiency of the array panel preparation.
  • the "layer” in the "same layer setting" referred to herein refers to a layer structure formed by forming a film layer for a specific pattern by the same film forming process, and then forming the pattern by one patterning process using the same mask.
  • a patterning process may include multiple exposure, development, or etching processes, and the particular pattern in the resulting layer structure may be continuous or discontinuous, and these particular patterns may also be at different heights. Or have different thicknesses.
  • Another embodiment of the present disclosure provides a display panel comprising the array substrate of any of the foregoing embodiments.
  • the array substrate is a bottom gate type low temperature polysilicon substrate.
  • a further embodiment of the present disclosure provides a method for fabricating an array substrate, including:
  • the conductive connection layer may fill the first via 141 and the second via 142 in the gate insulating layer to communicate the gate line and the gate electrode; wherein the first The via hole exposes the gate electrode, the second via hole exposes the gate line, and an example of the positional relationship of the first via hole 141 and the second via hole 142 can be seen in FIG. 4b.
  • the first via and the second via in the gate insulating layer may be formed when the gate insulating layer is formed, or may be formed after the gate insulating layer is formed, which is not limited herein.
  • the conductive connection layer is formed after the polysilicon semiconductor layer is formed.
  • the method of preparing the first via and the second via includes at least two examples.
  • the first via hole and the second via hole are formed while forming the gate insulating layer, that is, a gate insulating layer including the first via hole and the second via hole is formed by a patterning process, wherein the A via exposes the gate electrode, and the second via exposes the gate line.
  • Forming the gate insulating layer including the first via and the second via by a patterning process may include the steps of: depositing an insulating material to obtain a first insulating film layer; and arranging a mask of a predetermined shape over the first insulating film layer a stencil; forming a gate insulating layer including a first via and a second via by a step of exposure and development or the like using the mask; and peeling off the mask to obtain a gate insulating layer.
  • the first via hole and the second via hole are prepared, that is, the gate insulating layer is etched to obtain an exposed device. a first via of the gate electrode and a second via exposing the gate line.
  • the method for preparing the first via hole and the second via hole according to the previous example can avoid the problem that the etching gate insulating layer forms a via hole for a long time in the latter example, improves the controllability of the process, and the array The preparation efficiency of the substrate.
  • the foregoing step S303 may include:
  • step S303 the method further includes:
  • the metal layer formed on the N-type polysilicon semiconductor layer is etched to obtain a source and a drain;
  • the etching of the N-type polysilicon semiconductor layer and the first amorphous silicon semiconductor layer is continued until the n-type polysilicon semiconductor layer is etched and the first amorphous silicon semiconductor layer is over-etched; the n-type polysilicon semiconductor is broken at this moment
  • the layer, the overetched first amorphous silicon semiconductor layer, and the p-type polysilicon semiconductor layer, and the second amorphous silicon semiconductor layer around the p-type polysilicon semiconductor layer collectively form an active layer.
  • the step of forming a conductive connection layer on the gate insulating layer in step S304 is performed after forming the polysilicon semiconductor layer.
  • a conductive connection layer is formed on the gate insulating layer by the same patterning process while forming a source drain. That is, a conductive connection layer is formed while forming a metal layer for forming a source and a drain.
  • the local laser annealing process is a MLA (Microlens Array) local laser annealing process.
  • the MLA local laser annealing technique only illuminates the corresponding area of the gate electrode of the amorphous silicon semiconductor layer, and the MLA local laser annealing technology has higher conversion efficiency than the conventional excimer laser annealing technique (ELA). The utilization efficiency of the polycrystalline silicon converted illumination laser is also higher.
  • embodiments of the present disclosure provide an array substrate, a method of fabricating the same, and a display panel.
  • the gate electrode and the gate line are spaced apart such that the gate electrode and the gate line are formed when the polysilicon semiconductor layer is prepared.
  • the non-connected state avoids or reduces the problem of laser energy diffusion occurring when the amorphous silicon layer is irradiated with a laser to form a polycrystalline silicon semiconductor layer.
  • the laser energy can concentrate on the amorphous silicon layer and raise the gate electrode in a short time.
  • the temperature, the conversion efficiency of the polysilicon, and the utilization efficiency of the laser energy are realized, and the effect of preparing a polycrystalline silicon semiconductor having a larger crystal grain and a higher mobility using less laser resources is realized.

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Abstract

一种阵列基板及其制作方法、显示面板。阵列基板，包括：衬底基板（110）；位于衬底基板（110）之上的多条栅线（130），以及与每条栅线（130）对应且间隔设置的栅电极（120）；位于栅电极（120）和栅线（130）之上的栅极绝缘层（140），栅极绝缘层（140）具有第一过孔（141）和第二过孔（142），第一过孔（141）暴露出栅电极（120），第二过孔（142）暴露出栅线（130）；位于栅极绝缘层（140）之上的导电连接层（150）和多晶硅半导体层（161），导电连接层（150）填充第一过孔（141）和第二过孔（142）以连通栅线（130）和栅电极（120）。

Description

一种阵列基板及其制作方法、显示面板
相关申请的交叉引用
本申请要求于2017年5月16日向中国专利局提交的专利申请201710344384.2的优先权利益，并且在此通过引用的方式将该在先申请的内容并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示面板。
背景技术
应用于TFT LCD(Thin Film Transistor，薄膜晶体管)(Liquid Crystal Display，液晶显示装置)的薄膜晶体管主要包括非晶硅薄膜晶体管(a-Si TFT)以及多晶硅薄膜晶体管(Poly-Si TFT)。多晶硅主要包含HTPS(High Temperature Poly-Silicon，高温多晶硅)与LTPS(Low Temperature Poly-Silicon，低温多晶硅)。
由于非晶硅存在低迁移率、低稳定性等很多无法避免的缺点，而低温多晶硅具有较高的迁移率及稳定性，其迁移率甚至可达非晶硅的几十倍甚至几百倍。因此，采用低温多晶硅材料形成薄膜晶体管的技术得到了迅速发展，由LTPS衍生的新一代LCD或OLED(Organic Light-Emitting Diode，有机电致发光显示装置)成为重要的显示技术，尤其是OLED显示装置。
公开内容
本公开实施例提供的一种阵列基板，包括：衬底基板；位于所述衬底基板之上的多条栅线，以及与每条所述栅线对应且间隔设置的栅电极；位于所述栅电极和栅线之上的栅极绝缘层，所述栅极绝缘层具有第一过孔以及第二过孔，所述第一过孔暴露出所述栅电极，所述第二过孔暴露出所述栅线；位于所述栅极绝缘层之上的导电连接层和多晶硅半导体层，所述导电连接层填充所述第一过孔和所述第二过孔以连通所述栅线和所述栅电极。
可选地，所述阵列基板还包括位于多晶硅半导体层上的源漏极。
可选地，所述导电连接层和所述源漏极同层设置。
可选地，所述栅电极和所述栅线同层设置。
可选地，多晶硅半导体层是p型多晶硅半导体层，所述阵列基板还包括：位于所述多晶硅半导体层之上的第一非晶硅半导体层和n型多晶硅半导体层。
可选地，所述多晶硅半导体层在所述衬底基板上的正投影与所述栅电极在衬底基板上的正投影至少部分重叠。
本公开的另一实施例提供了一种显示面板，其包括如前述实施例中任一实施例所述的阵列基板。
本公开的又一实施例提供了一种阵列基板的制作方法，包括：
在衬底基板上形成多条栅线和与每条所述栅线对应且间隔设置的栅电极；
在所述栅电极和所述栅线上形成栅极绝缘层，所述栅绝缘层包括用于暴露出所述栅电极的第一过孔和用于暴露出所述栅线的第二过孔；
在所述栅极绝缘层上形成多晶硅半导体层。
可选地，所述方法还包括：在所述多晶硅半导体层上形成源漏极；在所述栅极绝缘层上形成导电连接层，所述导电连接层填充所述第一过孔和第二过孔以连通所述栅线和所述栅电极。
可选地，形成栅极绝缘层的步骤包括：通过构图工艺形成包括所述第一过孔和所述第二过孔的栅极绝缘层。
可选地，形成栅极绝缘层的步骤包括：形成覆盖所述栅电极和所述栅线的绝缘膜；对所述绝缘膜进行刻蚀，得到暴露出所述栅电极的第一过孔，以及暴露出所述栅线的第二过孔。
可选地，在所述栅极绝缘层上形成多晶硅半导体层包括：在所述栅极绝缘层上通过构图工艺形成第二非晶硅半导体层；对所述第二非晶硅半导体层中所述栅电极对应的区域进行局部激光退火工艺，形成所述多晶硅半导体层。
可选地，所述局部激光退火工艺为微镜阵列(MLA)局部激光退火工艺。
可选地，在形成所述源漏极的同时，通过同一构图工艺，在所述栅极绝缘层上形成所述导电连接层。
可选地，所述多晶硅半导体层是p型多晶硅半导体层，所述方法还包括：在所述p型多晶硅半导体层上形成第一非晶硅半导体层和n型多晶硅半导体层。
附图说明
图1为本公开的一个实施例提供的阵列基板的局部截面示意图；
图2为本公开的实施例提供的有源层的结构示意图；
图3为本公开的一个实施例提供的一种阵列基板的制作方法的流程示意图；
图4a用于图示根据本公开的实施例提供的栅电极与栅线的位置关系；
图4b用于图示根据本公开实施例提供阵列基板的栅绝缘层中的第一过孔与第二过孔。
具体实施方式
下面将结合本公开实施例中的附图，对本公开中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
通常，形成多晶硅半导体层的工艺包括：形成非晶硅半导体层，然后对非晶硅层实施局部激光退火工艺，使得非晶硅半导体层中与栅电极对应的区域转化为多晶硅半导体层。通过一次激光照射即可完成熔融结晶，从而可提升半导体器件的迁移率。
本申请的发明人认识到，由于金属的传热效率很高，而且与栅电极相连的栅线遍布整个显示面板，因此，照射在非晶硅半导体层上的热量会传递给栅电极，而这些热量会再通过与栅电极连接的栅线而被分散到显示面板的各个区域，使得激光能量用于转化非晶硅半导体层的效率低，晶化效果较差。
为了提升用于转化多晶硅的激光的利用效率，增强多晶硅的转化效果，本公开的实施例提供了一种阵列基板，参见图1，其包括：衬底基板110；位于衬底基板110之上的多行栅线130(图1中示意性地示 出了一条栅线130的截面，该截面垂直于其长度延伸方向)，以及与每行栅线130对应且间隔设置的栅电极120；位于栅电极120和栅线130之上的栅极绝缘层140以及位于栅极绝缘层140中的第一过孔141以及第二过孔142，其中，所述第一过孔141暴露出栅电极120，所述第二过孔142暴露出栅线130。该阵列基板还包括位于栅极绝缘层140之上的导电连接层150和多晶硅半导体层161，以及位于多晶硅半导体层161之上的源漏极170。所述导电连接层150填充第一过孔141和第二过孔142以使得栅线130经由导电连接层而与栅电极120连接。
在一个实施例中，每一条栅线130可驱动该栅线对应的栅电极120(图1中仅示意性地示出了一个栅电极的横截面120)，每一栅电极120对应一薄膜晶体管TFT。
根据本公开的一个实施例，参见图2，所述阵列基板还包括：位于多晶硅半导体层161之上的第一非晶硅半导体层163和n型多晶硅半导体层164。在另一实施例中，阵列基板还可包括与多晶硅半导体层161同层的第二非晶硅半导体层162。具体地，多晶硅半导体层161在衬底基板上的正投影和栅电极在衬底基板上的正投影至少部分重叠。此时，多晶硅半导体层161、第二非晶硅半导体层162、第一非晶硅半导体层163和n型多晶硅半导体层164形成有源层160(参见图1)。所述第一非晶硅半导体层163主要用于降低漏电流，n型多晶硅半导体层164主要用于增加开态电流。
在本公开的实施例中，通过间隔设置栅电极和栅线，可以使得在制备多晶硅半导体层时，栅电极与栅线为不连通状态(在未形成导电连接层150时)，从而至少可以避免热量被大量地传输至栅线，可缓解或减轻转换非晶硅半导体层的激光能量的扩散问题，使激光能够更集中的对非晶硅层照射，在短时间内提升栅电极的温度，由此可提升多晶硅的转换效率以及激光能量的利用效率，实现使用较少的激光资源制备晶粒更大、迁移率更高的多晶硅半导体的效果。
在一个实施例汇总，与栅电极对应设置的多晶硅半导体层161为p型多晶硅半导体层。
在一个实施例中，为缩短制备时间，提升效率，导电连接层150和源漏极170可通过同一构图工艺同时制备形成，即导电连接层150和源漏极170可同层设置，且用于形成导电连接层150与源漏极170 的材料可为同一种导电材料。
进一步地，在一个实施例中，栅电极120和栅线130可同时制备，即栅电极120和栅线130同层设置，且用于形成栅电极120与栅线130的材料可为同一种导电材料。这也进一步有利于缩短工艺时间，提升阵列面板制备效率。这里提到的“同层设置”中的“层”指的是采用同一成膜工艺形成用于特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
本公开的另一实施例提供了一种显示面板，该显示面板包括前述的任意实施例所述的阵列基板。具体地，所述阵列基板为底栅型的低温多晶硅基板。
参见图3，本公开的又一实施例提供了一种阵列基板的制作方法，包括：
S301、在衬底基板上形成多行栅线和与每行所述栅线对应且间隔设置的栅电极；所述栅电极与所述栅线之间存在间隔，例如，如图4a所示；
S302、在所述栅电极和所述栅线上形成栅极绝缘层；
S303、在所述栅极绝缘层上形成多晶硅半导体层；
S304、在所述多晶硅半导体层上形成源漏极，在所述栅极绝缘层上形成导电连接层。
在实施例中，所述导电连接层可填充位于所述栅极绝缘层中的第一过孔141和第二过孔142而连通所述栅线和所述栅电极；其中，所述第一过孔暴露出所述栅电极，所述第二过孔暴露出所述栅线，第一过孔141与第二过孔142的位置关系的示例可参见图4b。
在实施例中，栅极绝缘层中的第一过孔和第二过孔可以在形成栅极绝缘层的时候形成，也可以在形成栅极绝缘层之后形成，本文对此不作限制。然而，导电连接层在多晶硅半导体层形成之后被形成。
也就是说，制备第一过孔和第二过孔的方法至少包括两种示例。在一个示例中，在形成栅极绝缘层的同时制备第一过孔和第二过孔，即通过构图工艺形成包括第一过孔和第二过孔的栅极绝缘层，其中， 所述第一过孔暴露出所述栅电极，所述第二过孔暴露出所述栅线。
通过构图工艺形成包括第一过孔和第二过孔的栅极绝缘层可包括以下步骤：沉积绝缘材料得到第一绝缘膜层；在所述第一绝缘膜层之上布置预设形状的掩膜版；利用所述掩膜版通过曝光显影等步骤，形成包括第一过孔和第二过孔的栅极绝缘层；剥离所述掩膜版，得到栅极绝缘层。
在另一示例中，在形成所述栅极绝缘层之后，在形成导电连接层之前，制备第一过孔和第二过孔，即对所述栅极绝缘层进行刻蚀，得到暴露出所述栅电极的第一过孔，以及暴露出所述栅线的第二过孔。
根据前一示例的制备第一过孔和第二过孔的方法可避免后一示例存在的刻蚀栅极绝缘层形成过孔的时间较长的问题，提高了工艺的可控性，以及阵列基板的制备效率。在实施例中，上述的步骤S303可包括：
在所述栅极绝缘层上通过构图工艺形成第二非晶硅半导体层；
对所述第二非晶硅半导体层中所述栅电极对应的区域进行局部激光退火工艺，形成P型多晶硅半导体层。
在另一实施例中，在步骤S303之后，该方法还包括：
在P型多晶硅半导体层上通过构图工艺依次形成第一非晶硅半导体层和N型多晶硅半导体层；
在N型多晶硅半导体层上通过沉积形成用于形成源漏极的金属层；
此时，对N型多晶硅半导体层上形成的金属层进行刻蚀得到源漏极；
继续对N型多晶硅半导体层和第一非晶硅半导体层进行刻蚀，直到将n型多晶硅半导体层刻断，且对第一非晶硅半导体层过刻；，此时刻断的n型多晶硅半导体层、过刻的第一非晶硅半导体层，以及p型多晶硅半导体层、处于p型多晶硅半导体层周围的第二非晶硅半导体层共同形成有源层。
在实施例中，步骤S304中在所述栅极绝缘层上形成导电连接层这一步骤在形成多晶硅半导体层之后被执行。
在一个实施例中，在形成源漏极的同时，通过同一构图工艺，在所述栅极绝缘层上形成导电连接层。即在形成用于形成源漏极的金属层的同时形成导电连接层。所述局部激光退火工艺为可以MLA (Microlens Array)局部激光退火工艺。MLA局部激光退火技术只对非晶硅半导体层的栅电极对应的区域集中照射，相比常规的准分子激光退火技术(ELA)对整块基板进行照射，MLA局部激光退火技术转换效率更高，多晶硅转换的照射激光的利用效率也更高。
综上所述，本公开实施例提供了一种阵列基板及其制作方法、显示面板，在这些实施例中，间隔设置栅电极和栅线，使得在制备多晶硅半导体层时，栅电极与栅线为未连通状态，从而避免或减轻了在用激光对非晶硅层照射以制作多晶硅半导体层时发生的激光能量的扩散问题，激光能量能够集中对非晶硅层照射，短时间内提升栅电极的温度，提升多晶硅的转换效率以及激光能量的利用效率，实现使用较少的激光资源制备晶粒更大，迁移率更高的多晶硅半导体的效果。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本公开的这些修改和变型属于本公开所附权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
在权利要求中，词语“包括”并不排除其他部件或步骤的存在，并且“一”或“一个”并不排除复数。在相互不同的从属权利要求中陈述了若干技术手段这一事实并不意味着这些技术手段的组合不能有利地加以利用。

Claims (16)

  1. 一种阵列基板，包括：
    衬底基板；
    位于所述衬底基板之上的多条栅线，以及与每条所述栅线对应且间隔设置的栅电极；
    位于所述栅电极和栅线之上的栅极绝缘层，所述栅极绝缘层具有第一过孔以及第二过孔，所述第一过孔暴露出所述栅电极，所述第二过孔暴露出所述栅线；
    位于所述栅极绝缘层之上的导电连接层和多晶硅半导体层，所述导电连接层填充所述第一过孔和所述第二过孔以连通所述栅线和所述栅电极。
  2. 根据权利要求1所述的阵列基板，其中所述阵列基板还包括位于多晶硅半导体层上的源漏极。
  3. 根据权利要求2所述的阵列基板，其中所述导电连接层和所述源漏极同层设置。
  4. 根据权利要求1所述的阵列基板，其中所述栅电极和所述栅线同层设置。
  5. 根据权利要求1所述的阵列基板，其中所述多晶硅半导体层是p型多晶硅半导体层，所述阵列基板还包括：位于所述多晶硅半导体层之上的第一非晶硅半导体层和n型多晶硅半导体层。
  6. 根据权利要求1所述的阵列基板，其中所述多晶硅半导体层在所述衬底基板上的正投影与所述栅电极在衬底基板上的正投影至少部分重叠。
  7. 一种显示面板，包括：权利要求1-6任一项所述的阵列基板。
  8. 一种阵列基板的制作方法，包括：
    在衬底基板上形成多条栅线和与每条所述栅线对应且间隔设置的栅电极；
    在所述栅电极和所述栅线上形成栅极绝缘层，所述栅绝缘层包括用于暴露出所述栅电极的第一过孔和用于暴露出所述栅线的第二过孔；
    在所述栅极绝缘层上形成多晶硅半导体层。
  9. 根据权利要求8所述的方法，其中所述方法还包括：
    在所述多晶硅半导体层上形成源漏极；
    在所述栅极绝缘层上形成导电连接层，所述导电连接层填充所述第一过孔和第二过孔以连通所述栅线和所述栅电极。
  10. 根据权利要求8所述的方法，其中形成栅极绝缘层的步骤包括：
    通过构图工艺形成包括所述第一过孔和所述第二过孔的栅极绝缘层。
  11. 根据权利要求8所述的制作方法，其中形成栅极绝缘层的步骤包括：
    形成覆盖所述栅电极和所述栅线的绝缘膜；
    对所述绝缘膜进行刻蚀，得到暴露出所述栅电极的第一过孔，以及暴露出所述栅线的第二过孔。
  12. 根据权利要求8-11中任一项所述的制作方法，其中在所述栅极绝缘层上形成多晶硅半导体层包括：
    在所述栅极绝缘层上通过构图工艺形成第二非晶硅半导体层；
    对所述第二非晶硅半导体层中所述栅电极对应的区域进行局部激光退火工艺，形成所述多晶硅半导体层。
  13. 根据权利要求12所述的制作方法，其中所述局部激光退火工艺为微镜阵列(MLA)局部激光退火工艺。
  14. 根据权利要求9所述的制作方法，其中在形成所述源漏极的同时，通过同一构图工艺，在所述栅极绝缘层上形成所述导电连接层。
  15. 根据权利要求8所述的制作方法，其中所述多晶硅半导体层是p型多晶硅半导体层，所述方法还包括：
    在所述p型多晶硅半导体层上形成第一非晶硅半导体层和n型多晶硅半导体层。
  16. 根据权利要求8所述的制作方法，其中所述多晶硅半导体层在所述衬底基板上的正投影与所述栅电极在衬底基板上的正投影至少部分重叠。
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