WO2021088912A1 - 薄膜晶体管及其制备方法、阵列基板及其制备方法、显示面板 - Google Patents

薄膜晶体管及其制备方法、阵列基板及其制备方法、显示面板 Download PDF

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WO2021088912A1
WO2021088912A1 PCT/CN2020/126674 CN2020126674W WO2021088912A1 WO 2021088912 A1 WO2021088912 A1 WO 2021088912A1 CN 2020126674 W CN2020126674 W CN 2020126674W WO 2021088912 A1 WO2021088912 A1 WO 2021088912A1
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gate
substrate
insulating layer
layer
doped region
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PCT/CN2020/126674
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English (en)
French (fr)
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程鸿飞
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Priority to US17/417,514 priority Critical patent/US11699761B2/en
Publication of WO2021088912A1 publication Critical patent/WO2021088912A1/zh

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    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a thin film transistor and a preparation method thereof, an array substrate and a preparation method thereof, and a display panel.
  • Display devices such as liquid crystal displays (LCD) and organic light emitting diodes (OLED) have been widely used.
  • LCD and OLED display devices use thin film transistors (TFT) to control the pixels in the display panel.
  • TFTs include amorphous silicon TFTs, polycrystalline silicon TFTs, single crystal silicon TFTs, and metal oxide TFTs.
  • the present disclosure provides a method for manufacturing a thin film transistor, including: forming an active layer on a substrate, the active layer including a first region, a second region, and a third region; A gate insulating layer is formed on one side of the substrate; a gate is formed on the side of the gate insulating layer away from the active layer, wherein the orthographic projection of the first region of the active layer on the substrate is the same as that of the gate.
  • the orthographic projection of the insulating layer on the substrate and the orthographic projection of the gate on the substrate do not overlap, and the orthographic projection of the second region of the active layer on the substrate is similar to the orthographic projection of the gate insulating layer on the substrate.
  • the orthographic projection on the substrate overlaps, but does not overlap with the orthographic projection of the gate electrode on the substrate, and the orthographic projection of the third region of the active layer on the substrate is the same as that of the gate insulating layer.
  • the orthographic projection on the substrate and the orthographic projection of the gate on the substrate overlap; and ion implantation of the active layer from the side of the gate away from the active layer,
  • the first region of the active layer is formed as a heavily doped region
  • the second region of the active layer is formed as a lightly doped region
  • the third region of the active layer is formed as an active region.
  • the energy of the ion implantation is 10-100 KeV, and the dose of the ion implantation is less than 2 ⁇ 10 18 atom/cm 3 .
  • the doping concentration of the lightly doped region is 1 ⁇ 10 12 -1 ⁇ 10 14 atom/cm 2
  • the doping concentration of the heavily doped region is 1 ⁇ 10 14 -1 ⁇ 10 16 atom/cm 2 .
  • the active layer is made of low-temperature polysilicon material.
  • forming the gate insulating layer further includes forming a plurality of gate insulating layers that pass through the thickness of the gate insulating layer in a region of the gate insulating layer that does not overlap with the gate in a direction perpendicular to the substrate. Through holes, the pore diameter of the through holes ranges from 1 to 4 ⁇ m.
  • the plurality of through holes are evenly distributed, and the total open area of all through holes is less than 30% of the area of the lightly doped region.
  • the width between the border of the lightly doped region close to the active region and the border of the lightly doped region close to the heavily doped region ranges from 1.5 to 6 ⁇ m.
  • the boundary between the lightly doped region and the active region is formed to be aligned with a boundary of the gate.
  • the boundary between the heavily doped region and the lightly doped region is formed to be aligned with a boundary of the gate insulating layer.
  • the gate is made of one or more alloy materials among copper, aluminum, molybdenum, titanium, chromium, and tungsten; the gate insulating layer is made of silicon nitride or silicon oxide material .
  • forming the active layer on the substrate includes:
  • a laser is used to crystallize the pattern of the active layer film of amorphous silicon to form an active layer of low-temperature polysilicon.
  • forming a gate insulating layer on the side of the active layer away from the substrate, and forming a gate on the side of the gate insulating layer away from the active layer includes: A gate insulating layer film is formed on the side away from the substrate; a gate layer film is formed on the side of the gate insulating layer film away from the active layer; on the side of the gate layer film away from the gate insulating layer film A first photoresist layer is formed on one side; the gate layer film and the gate insulating layer film are etched to remove the gate layer film and the gate insulating layer film that are not blocked by the first photoresist layer Forming the gate insulating layer; forming a second photoresist layer on the side of the gate layer film away from the gate insulating layer; and etching the gate layer film to remove the gate The part of the film that is not blocked by the second photoresist layer forms the gate.
  • the method for manufacturing the thin film transistor further includes: forming a third photoresist layer on a side of the gate away from the gate insulating layer, and the third photoresist layer is in contact with the A plurality of micro-holes are provided in the area overlapping with the lightly doped region in the direction perpendicular to the substrate; and the gate insulating layer is etched to prevent the gate insulating layer in the direction perpendicular to the substrate.
  • a plurality of through holes penetrating the thickness of the gate insulating layer are formed in a region overlapping with the gate electrode.
  • the method for manufacturing the thin film transistor further includes: forming an interlayer insulating layer on a side of the gate away from the active layer, and A first via hole and a second via hole are formed in the insulating layer, the first via hole and the second via hole exposing the heavily doped region; and the interlayer insulating layer away from the gate A source electrode and a drain electrode are formed on one side of, the source electrode is connected to the heavily doped region through the first via hole, and the drain electrode is connected to the heavily doped region through the second via hole.
  • the present disclosure provides a thin film transistor including: a substrate; an active layer on the substrate, the active layer including a heavily doped region, a lightly doped region, and an active region; A gate insulating layer on the side of the source layer away from the substrate; and a gate located on the side of the gate insulating layer away from the active layer.
  • the orthographic projection of the heavily doped region on the substrate does not overlap with the orthographic projection of the gate insulating layer on the substrate and the orthographic projection of the gate on the substrate.
  • the orthographic projection of the region on the substrate overlaps with the orthographic projection of the gate insulating layer on the substrate, but does not overlap with the orthographic projection of the gate on the substrate.
  • the active region is on the substrate.
  • the orthographic projection on the substrate overlaps the orthographic projection of the gate insulating layer on the substrate and the orthographic projection of the grid on the substrate.
  • the boundary between the lightly doped region and the active region is aligned with a boundary of the gate, and the boundary between the heavily doped region and the lightly doped region is aligned with the boundary of the gate insulating layer. One boundary is aligned.
  • the doping concentration of the lightly doped region is in the range of 1 ⁇ 10 12 -1 ⁇ 10 14 atom/cm 2
  • the doping concentration of the heavily doped region is in the range of 1 ⁇ 10 14 -1 ⁇ 10 16 atom/cm 2 .
  • the thin film transistor further includes: an interlayer insulating layer on a side of the gate away from the active layer, and a first via hole and a second layer are provided in the interlayer insulating layer. Two via holes, the first via hole and the second via hole exposing the heavily doped region; and the source and drain on the side of the interlayer insulating layer away from the gate, The source electrode is connected to the heavily doped region through the first via hole, and the drain electrode is connected to the heavily doped region through the second via hole.
  • the present disclosure provides a method for manufacturing an array substrate, including: forming a thin film transistor in the array substrate by using the method for manufacturing a thin film transistor according to the present disclosure.
  • the present disclosure provides an array substrate including the thin film transistor according to the present disclosure.
  • the present disclosure provides a display panel including the array substrate according to the present disclosure.
  • FIG. 1 is a top view of the structure of a transistor according to an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of the structure of the transistor shown in FIG. 1 along a section line AA;
  • step S01 is a cross-sectional view of the transistor structure after the completion of step S01 in the method for manufacturing a transistor according to an embodiment of the present disclosure
  • step S02 is a cross-sectional view of the transistor structure after the completion of step S02 in the method for manufacturing a transistor according to an embodiment of the present disclosure
  • step S03 is a cross-sectional view of the transistor structure after the completion of step S03 in the method for manufacturing a transistor according to an embodiment of the present disclosure
  • FIG. 6 is a cross-sectional view of the transistor structure after the completion of step S04 in the method for manufacturing a transistor according to an embodiment of the present disclosure
  • step S05 is a cross-sectional view of the transistor structure after the completion of step S05 in the method for manufacturing a transistor according to an embodiment of the present disclosure
  • step S06 is a cross-sectional view of the transistor structure after the completion of step S06 in the method for manufacturing a transistor according to an embodiment of the present disclosure
  • step S07 is a cross-sectional view of the transistor structure after the completion of step S07 in the method for manufacturing a transistor according to an embodiment of the present disclosure
  • step S08 is a cross-sectional view of the transistor structure after the completion of step S08 in the method for manufacturing a transistor according to an embodiment of the present disclosure
  • FIG. 11 is a cross-sectional view of the transistor structure after step S09 in the method for manufacturing a transistor according to an embodiment of the present disclosure is completed.
  • the thin film transistor of the present disclosure and its manufacturing method, the array substrate and its manufacturing method, and the display panel will be described in further detail below with reference to the accompanying drawings and specific embodiments.
  • LTPS TFT low-temperature polysilicon thin-film transistors
  • the preparation of low-temperature polysilicon thin film transistors requires the formation of heavily doped regions and lightly doped regions in its active layer.
  • the heavily doped region and the lightly doped region need to be formed by different doping processes respectively, and the preparation process is complicated, which greatly limits the manufacturing efficiency of low-temperature polysilicon thin film transistors.
  • the embodiment of the present disclosure provides a method for manufacturing a thin film transistor, as shown in FIGS. 1 and 2, including: forming an active layer 2 on a substrate 1.
  • the active layer 2 includes a first region 21, a second region 22, and a second region. Three regions 23; a gate insulating layer 3 is formed on the side of the active layer 2 away from the substrate 1; a gate 4 is formed on the side of the gate insulating layer 3 away from the active layer 2, wherein the first of the active layer 2
  • the orthographic projection of the region 21 on the substrate 1 and the orthographic projection of the gate insulating layer 3 on the substrate 1 and the orthographic projection of the gate 4 on the substrate 1 do not overlap.
  • the second region 22 of the active layer 2 is on the substrate 1
  • the orthographic projection overlaps with the orthographic projection of the gate insulating layer 3 on the substrate 1, but does not overlap with the orthographic projection of the gate 4 on the substrate 1.
  • the orthographic projection of the third region 23 of the active layer 2 on the substrate 1 is insulated from the grid
  • the orthographic projection of the layer 3 on the substrate 1 and the orthographic projection of the gate 4 on the substrate 1 overlap; the active layer 2 is ion implanted from the side of the gate 4 away from the active layer 2 to make the active layer 2
  • the first region 21 of the active layer is formed as a heavily doped region
  • the second region 22 of the active layer is formed as a lightly doped region
  • the third region 23 of the active layer is formed as an active region.
  • the method for manufacturing the thin film transistor further includes: forming an interlayer insulating layer 5 on the side of the gate 4 away from the active layer 2, and forming a first layer in the interlayer insulating layer 5.
  • the via hole 11 and the second via hole 12, the first via hole 11 and the second via hole 12 expose the heavily doped region 21; the source electrode 6 and the drain electrode are formed on the side of the interlayer insulating layer 5 away from the gate electrode 4 7.
  • the source 6 is connected to the heavily doped region 21 through the first via hole 11, and the drain 7 is connected to the heavily doped region 21 through the second via hole 12.
  • the active region 23 of the active layer 2 is formed; in the part of the active layer 2 that is shielded by the gate insulating layer 3 but not shielded by the gate 4, ions are partially implanted, thereby forming the lightly doped region 22 of the active layer 2 ; In the fully exposed part of the active layer 2 that is not blocked by the gate insulating layer 3 and the gate 4, ions are fully implanted to form a heavily doped region 21 of the active layer 2.
  • the preparation method of the embodiment of the present disclosure greatly simplifies the preparation process of the thin film transistor and improves the preparation efficiency of the thin film transistor.
  • the active layer 2 is made of low temperature polysilicon material.
  • the energy of ion implantation is 10-100 KeV, and the dose of ion implantation is less than 2 ⁇ 10 18 atom/cm 3 .
  • the process of forming the heavily doped region 21, the lightly doped region 22 and the active region 23 of the active layer 2 by ion implantation can be achieved by using the gate 4 and the gate insulating layer. 3 is used as a mask to simultaneously prepare the heavily doped region 21, the lightly doped region 22, and the active region 23 to form the active layer 2, thereby simplifying the thin film transistor manufacturing process and improving the thin film transistor manufacturing efficiency.
  • the doping concentration range of the lightly doped region 22 is 1 ⁇ 10 12 -1 ⁇ 10 14 atom/cm 2
  • the doping concentration range of the heavily doped region 21 is 1 ⁇ 10 14 -1 ⁇ 10 16 atom/cm 2
  • the width between the boundary of the lightly doped region 22 close to the active region 23 and the boundary of the lightly doped region 22 close to the heavily doped region 21 is in the range of 1.5-6 ⁇ m.
  • the heavily doped region 21 in this doping concentration range has good electrical conductivity, and can well realize the electrical conductivity between the source 6 and the drain 7 and the heavily doped region 21.
  • the lightly doped region 22 of the doping concentration range and width range can well solve the poor reliability and stability of thin film transistors caused by the effects of hot carriers caused by the strong electric field at the source 6 and the drain 7 The problem to ensure the reliability and stability of thin film transistors.
  • the boundary between the lightly doped region 22 and the active region 23 is formed to be aligned with a boundary of the gate 4, and/or the boundary between the heavily doped region 21 and the lightly doped region 22 It is formed to be aligned with one boundary of the gate insulating layer 3.
  • forming the gate insulating layer 3 further includes forming a plurality of regions of the gate insulating layer 3 corresponding to the lightly doped region 22 (that is, the region that does not overlap the gate electrode 4 in the direction perpendicular to the substrate 1).
  • the through hole 30 penetrates its thickness, and the pore diameter of the through hole 30 ranges from 1 to 4 ⁇ m.
  • a plurality of through holes 30 are evenly distributed, and the total open area of all through holes 30 is less than 30% of the area of the lightly doped region 22.
  • the through hole 30 By forming the through hole 30 in the region of the gate insulating layer 3 corresponding to the lightly doped region 22, it is helpful to better adjust the ion concentration of the lightly doped region 22 during the process of ion implantation to form the lightly doped region 22, so that the ion Partially injected into the active layer 2 through the gate insulating layer 3, thereby forming the lightly doped region 22 in the above-mentioned specific doping concentration range, which is beneficial to the lightly doped region 22 to better meet its performance requirements; Reduce the energy of ion implantation to reduce the effect of ion implantation on the structure of the active layer 2.
  • the gate 4 is made of one or more alloy materials among copper, aluminum, molybdenum, titanium, chromium, and tungsten; the gate insulating layer 3 is made of silicon nitride or silicon oxide.
  • the gate 4 has a single-layer or multi-layer structure.
  • the gate 4 may adopt a three-layer structure of molybdenum ⁇ aluminum ⁇ molybdenum, titanium ⁇ copper ⁇ titanium, or molybdenum ⁇ titanium ⁇ copper.
  • the gate insulating layer 3 has a single-layer or multi-layer structure.
  • the gate insulating layer 3 may adopt a two-layer structure of silicon oxide ⁇ silicon nitride.
  • the material and structure of the source 6 and the drain 7 may be the same as the gate 4, and the material and structure of the interlayer insulating layer 5 may be the same as the gate insulating layer 3.
  • FIGS. 3 to 11 show a manufacturing process of a thin film transistor using a method of manufacturing a thin film transistor according to a disclosed embodiment.
  • step S01 as shown in FIG. 3, a pattern of an active layer film of amorphous silicon is formed on the substrate 1, and the active layer film of amorphous silicon is crystallized by a laser to form an active layer of low-temperature polysilicon 2.
  • step S02 on the substrate 1 after step S01, a gate insulating layer film 31 is formed on the side of the active layer 2 away from the substrate 1, and the gate insulating layer film 31 is away from the active layer.
  • a gate layer film 41 is formed on the side of 2 and a photoresist layer film is formed on the side of the gate layer film 41 away from the gate insulating layer film 31.
  • the first photoresist layer 8 is formed by exposing and developing the photoresist layer film. The boundary of the first photoresist layer 8 is aligned with the boundary between the heavily doped region and the lightly doped region of the active layer 2 to be formed.
  • step S03 as shown in FIG. 5, the gate layer film 41 and the gate insulating layer film 31 are etched to remove the portions of the gate layer film 41 and the gate insulating layer film 31 that are not blocked by the first photoresist layer 8. , The pattern of the gate insulating layer 3 is formed. After the step S03 is completed, the first photoresist layer 8 can be peeled off.
  • step S04 a photoresist layer film is formed on the side of the gate layer film 41 away from the gate insulating layer 3, and the second photoresist layer 9 is formed by exposing and developing the photoresist layer film.
  • the boundary of the second photoresist layer 9 is aligned with the boundary between the lightly doped region to be formed of the active layer 2 and the active region.
  • the second photoresist layer 9 may be formed of the first photoresist layer 8.
  • the first photoresist layer 8 may have a stepped shape.
  • the first photoresist layer 8 may be ashed to obtain the second photoresist layer 9.
  • step S05 as shown in FIG. 7, the gate layer film 41 is etched to remove the portion of the gate layer film 41 that is not blocked by the second photoresist layer 9 to form a pattern of the gate electrode 4.
  • step S05 the second photoresist layer 9 can be peeled off.
  • step S06 a photoresist layer film is formed on the side of the gate electrode 4 away from the gate insulating layer 3, and a pattern of the third photoresist layer 10 is formed by exposing and developing the photoresist layer film.
  • a plurality of micro holes are opened in the region of the third photoresist layer 10 corresponding to the lightly doped region, and the gate insulating layer 3 is etched to form a plurality of through holes 30 in the region of the gate insulating layer 3 corresponding to the lightly doped region.
  • the third photoresist layer 10 may be peeled off.
  • step S07 ion implantation is performed on the active layer 2 from the side of the gate 4 away from the active layer 2 to form a heavily doped region 21 and a lightly doped region in the active layer 2. 22. Active area 23.
  • ions are not implanted to form the active region 23; in the active layer that is shielded by the gate insulating layer 3 but not shielded by the gate 4 In part, ions are partially implanted to form a lightly doped region 22; in the fully exposed active layer part that is not blocked by the gate 4 and the gate insulating layer 3, ions are fully implanted to form a heavily doped region 21.
  • step S08 as shown in FIG. 10, an interlayer insulating layer 5 is formed on the side of the gate 4 away from the active layer 2, and a first via hole 11 and a second via hole are formed in the interlayer insulating layer 5. 12. The heavily doped region 21 is exposed at the first via hole 11 and the second via hole 12.
  • step S09 as shown in FIG. 11, a source 6 and a drain 7 are formed on the side of the interlayer insulating layer 5 away from the gate 4, and the source 6 is connected to the heavily doped region 21 through the first via 11 , The drain 7 is connected to the heavily doped region 21 through the second via hole 12.
  • the thin film transistor includes: a substrate 1; an active layer 2 located on the substrate 1.
  • the active layer 2 includes a heavily doped region 21, a lightly doped region 22, and an active region 23;
  • the gate insulating layer 3 on the side away from the substrate 1; and the gate 4 on the side away from the active layer 2 of the gate insulating layer 3.
  • the orthographic projection of the heavily doped region 21 on the substrate 1 and the orthographic projection of the gate insulating layer 3 on the substrate 1 and the orthographic projection of the gate 4 on the substrate 1 do not overlap, and the orthographic projection of the lightly doped region 21 on the substrate 1
  • the projection overlaps with the orthographic projection of the gate insulating layer 3 on the substrate 1, but does not overlap with the orthographic projection of the gate 4 on the substrate 1.
  • the orthographic projection of the active region 23 on the substrate 1 is the same as the orthographic projection of the gate insulating layer 3 on the substrate 1.
  • the orthographic projection of the grid 4 and the orthographic projection of the grid 4 on the substrate 1 overlap.
  • the boundary between the lightly doped region 22 and the active region 23 is aligned with a boundary of the gate 4, and the boundary between the heavily doped region 21 and the lightly doped region 22 is aligned with a boundary of the gate insulating layer 3.
  • the active layer 2 includes two lightly doped regions 22, which are respectively disposed at opposite ends of the active region 23, and the active layer 2 includes two heavily doped regions 21, which are respectively disposed far away from the lightly doped regions 22. One side of the source area 23.
  • the thin film transistor further includes: an interlayer insulating layer 5 on the side of the gate 4 away from the active layer 2, and the interlayer insulating layer 5 is provided with a first via 11 and a second Via 12, the first via 11 and the second via 12 expose the heavily doped region 21; and the source 6 and drain 7 on the side of the interlayer insulating layer 5 away from the gate 4, and the source 6
  • the first via hole 11 is connected to the heavily doped region 21, and the drain 6 is connected to the heavily doped region 21 through the second via hole 12.
  • the gate insulating layer 3 is provided with a plurality of through holes 30 in a region corresponding to the lightly doped region 22, and the aperture of the through holes 30 ranges from 1 to 4 ⁇ m.
  • the plurality of through holes 30 are evenly distributed, and the total opening area of all the through holes 30 is less than 30% of the area of the lightly doped region 22.
  • ion implantation of the active layer from the side of the gate away from the active layer can be adopted.
  • the formed gate and gate insulating layer are used as masks to form the heavily doped region, lightly doped region and active region of the active layer at the same time; compared with the thin film transistor, the heavily doped region and lightly doped region need to pass through different.
  • the separate preparation of the doping process greatly simplifies the preparation process of the thin film transistor and improves the preparation efficiency of the thin film transistor.
  • the embodiment of the present disclosure also provides a method for manufacturing an array substrate, including forming the thin film transistor in the array substrate by using the method for manufacturing a thin film transistor according to the embodiment of the present disclosure.
  • the method further includes: sequentially forming a passivation layer and a pixel electrode on the side of the thin film transistor away from the substrate.
  • Forming the passivation layer includes opening a third via hole in the passivation layer, and the pixel electrode is connected to the drain of the thin film transistor through the third via hole.
  • an embodiment of the present disclosure also provides an array substrate including the thin film transistor according to the embodiment of the present disclosure.
  • the array substrate further includes a passivation layer and a pixel electrode.
  • the passivation layer and the pixel electrode are arranged on the side of the thin film transistor away from the substrate, and the passivation layer and the pixel electrode are arranged away from the thin film transistor in turn.
  • a third via hole is opened in the layer, and the pixel electrode is connected to the drain of the thin film transistor through the third via hole.
  • the thin film transistor in the array substrate is formed by using the preparation method of the thin film transistor according to the embodiment of the present disclosure, which greatly simplifies the preparation process of the array substrate and improves the preparation of the array substrate. effectiveness.
  • the embodiment of the present disclosure also provides a display panel including the array substrate according to the embodiment of the present disclosure.
  • the manufacturing process of the display panel is greatly simplified, thereby improving the manufacturing efficiency of the display panel.
  • the display panel provided by the present disclosure can be any product or component with display function such as LCD panel, LCD TV, OLED panel, OLED TV, display, mobile phone, navigator, etc.

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Abstract

一种薄膜晶体管及其制备方法、阵列基板及其制备方法、显示面板。该薄膜晶体管的制备方法包括：在基底（1）上形成包括第一区域（21）、第二区域（22）和第三区域（23）的有源层（2）；在有源层（2）的远离基底（1）一侧形成栅绝缘层（3）；在栅绝缘层（3）的远离有源层（2）一侧形成栅极（4），其中，有源层（2）的第一区域（21）在基底（1）上的正投影与栅绝缘层（3）和栅极（4）在基底（1）上的正投影均不重叠，有源层（2）的第二区域（22）在基底（1）上的正投影与栅绝缘层（3）在基底（1）上的正投影重叠，但与栅极（4）在基底（1）上的正投影不重叠，有源层（2）的第三区域（23）在基底（1）上的正投影与栅绝缘层（3）和栅极（4）在基底（1）上的正投影均重叠；以及从栅极（4）的背离有源层（2）一侧对有源层（2）进行离子注入，使第一区域（21）形成为重掺杂区，第二区域（22）形成为轻掺杂区，第三区域（23）形成为有源区。

Description

薄膜晶体管及其制备方法、阵列基板及其制备方法、显示面板
相关申请的交叉引用
本公开要求于2019年11月6日提交至中国知识产权局的中国专利公开No.201911077318.9的优先权，所述公开的内容通过引用其全部合并于此。
技术领域
本公开属于显示技术领域，具体涉及一种薄膜晶体管及其制备方法、阵列基板及其制备方法、显示面板。
背景技术
诸如液晶显示器(LCD)和有机发光二极管(OLED)的显示装置已被广泛使用。LCD和OLED显示装置使用薄膜晶体管(TFT)来控制显示面板中的像素。TFT的示例包括非晶硅TFT、多晶硅TFT、单晶硅TFT和金属氧化物TFT。
发明内容
一方面，本公开提供一种薄膜晶体管的制备方法，包括：在基底上形成有源层，所述有源层包括第一区域、第二区域和第三区域；在所述有源层的远离基底的一侧形成栅绝缘层；在所述栅绝缘层的远离有源层的一侧形成栅极，其中，所述有源层的第一区域在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影和所述栅极在所述基底上的正投影均不重叠，所述有源层的第二区域在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影重叠，但是与所述栅极在所述基底上的正投影不重叠，所述有源层的第三区域在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影和所述栅极在所述基底上的正投影均重叠；以及从所述栅极的背离所述有源层的一侧对所述有源层进行离子注入，使所述有源层的第一区域形成为重掺杂区，所述有源层的第二区域形成 为轻掺杂区，所述有源层的第三区域形成为有源区。
在一些实施例中，所述离子注入的能量为10-100KeV,所述离子注入的剂量小于2×10 18atom/cm 3。
在一些实施例中，所述轻掺杂区的掺杂浓度范围为1×10 12-1×10 14atom/cm 2，所述重掺杂区的掺杂浓度范围为1×10 14-1×10 16atom/cm 2。
在一些实施例中，所述有源层采用低温多晶硅材质。
在一些实施例中，形成所述栅绝缘层还包括在所述栅绝缘层的在与所述基底垂直的方向上不与所述栅极重叠的区域形成多个贯穿所述栅绝缘层厚度的通孔，所述通孔的孔径范围为1-4μm。
在一些实施例中，所述多个通孔均匀分布，所有通孔的总开孔面积小于所述轻掺杂区面积的30％。
在一些实施例中，所述轻掺杂区的靠近所述有源区的边界与所述轻掺杂区的靠近所述重掺杂区的边界之间的宽度范围为1.5-6μm。
在一些实施例中，所述轻掺杂区与所述有源区之间的边界形成为与所述栅极的一个边界对齐。
在一些实施例中，所述重掺杂区与所述轻掺杂区之间的边界形成为与所述栅绝缘层的一个边界对齐。
在一些实施例中，所述栅极采用铜、铝、钼、钛、铬、钨中的一种或几种的合金材料制成；所述栅绝缘层采用氮化硅或氧化硅材料制成。
在一些实施例中，在基底上形成有源层包括：
在基底上形成非晶硅的有源层膜的图形；以及
利用激光使非晶硅的有源层膜的图形晶化，以形成低温多晶硅的有源层。
在一些实施例中，在所述有源层的远离基底的一侧形成栅绝缘层，以及在所述栅绝缘层的远离有源层的一侧形成栅极包括：在所述有源层的远离基底的一侧形成栅绝缘层膜；在所述栅绝缘层膜的远离所述有源层的一侧形成栅极层膜；在所述栅极层膜的远离所述栅绝缘层膜的一侧形成第一光阻层；刻蚀所述 栅极层膜和所述栅绝缘层膜，以去除述栅极层膜和所述栅绝缘层膜的未被所述第一光阻层遮挡的部分，形成所述栅绝缘层；在所述栅极层膜的远离所述栅绝缘层的一侧形成第二光阻层；以及刻蚀所述栅极层膜，以去除所述栅极层膜的未被所述第二光阻层遮挡的部分，形成所述栅极。
在一些实施例中，所述薄膜晶体管的制备方法还包括：在所述栅极的远离所述栅绝缘层的一侧形成第三光阻层，所述第三光阻层的在与所述基底垂直的方向上与所述轻掺杂区重叠的区域内设有多个微孔；以及刻蚀所述栅绝缘层，以在所述栅绝缘层的在与所述基底垂直的方向上不与所述栅极重叠的区域形成多个贯穿所述栅绝缘层厚度的通孔。
在一些实施例中，在进行所述离子注入之后，所述薄膜晶体管的制备方法还包括：在所述栅极的远离所述有源层的一侧形成层间绝缘层，在所述层间绝缘层中形成第一过孔和第二过孔，所述第一过孔和所述第二过孔暴露出所述重掺杂区；以及在所述层间绝缘层的远离所述栅极的一侧形成源极和漏极，所述源极通过所述第一过孔与所述重掺杂区连接，所述漏极通过所述第二过孔与所述重掺杂区连接。
另一方面，本公开提供一种薄膜晶体管，包括：基底；位于所述基底上的有源层，所述有源层包括重掺杂区、轻掺杂区和有源区；位于所述有源层的远离所述基底一侧的栅绝缘层；以及位于所述栅绝缘层的远离所述有源层的一侧的栅极。所述重掺杂区在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影和所述栅极在所述基底上的正投影均不重叠，所述轻掺杂区在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影重叠，但是与所述栅极在所述基底上的正投影不重叠，所述有源区在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影和所述栅极在所述基底上的正投影均重叠。所述轻掺杂区与所述有源区之间的边界与所述栅极的一个边界对齐，所述重掺杂区与所述轻掺杂区之间的边界与所述栅绝缘层的一个边界对齐。
在一些实施例中，所述轻掺杂区的掺杂浓度范围为1×10 12-1×10 14atom/cm 2， 所述重掺杂区的掺杂浓度范围为1×10 14-1×10 16atom/cm 2。
在一些实施例中，所述薄膜晶体管还包括：在所述栅极的远离所述有源层的一侧的层间绝缘层，在所述层间绝缘层中设有第一过孔和第二过孔，所述第一过孔和所述第二过孔暴露出所述重掺杂区；以及在所述层间绝缘层的远离所述栅极的一侧的源极和漏极，所述源极通过所述第一过孔与所述重掺杂区连接，所述漏极通过所述第二过孔与所述重掺杂区连接。
另一方面，本公开提供一种阵列基板的制备方法，包括：采用根据本公开的薄膜晶体管的制备方法形成所述阵列基板中的薄膜晶体管。
另一方面，本公开提供一种阵列基板，包括根据本公开的薄膜晶体管。
另一方面，本公开提供一种显示面板，包括根据本公开的阵列基板。
附图说明
图1为根据本公开实施例的晶体管的结构俯视图；
图2为图1所示的晶体管沿AA剖切线的结构剖视图；
图3为根据本公开实施例的晶体管的制备方法中的步骤S01完成后的晶体管结构剖视图；
图4为根据本公开实施例的晶体管的制备方法中的步骤S02完成后的晶体管结构剖视图；
图5为根据本公开实施例的晶体管的制备方法中的步骤S03完成后的晶体管结构剖视图；
图6为根据本公开实施例的晶体管的制备方法中的步骤S04完成后的晶体管结构剖视图；
图7为根据本公开实施例的晶体管的制备方法中的步骤S05完成后的晶体管结构剖视图；
图8为根据本公开实施例的晶体管的制备方法中的步骤S06完成后的晶体管结构剖视图；
图9为根据本公开实施例的晶体管的制备方法中的步骤S07完成后的晶体管结构剖视图；
图10为根据本公开实施例的晶体管的制备方法中的步骤S08完成后的晶体管结构剖视图；
图11为根据本公开实施例的晶体管的制备方法中的步骤S09完成后的晶体管结构剖视图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开薄膜晶体管及其制备方法、阵列基板及其制备方法、显示面板作进一步详细描述。
随着低温多晶硅薄膜晶体管(LTPS TFT)器件尺寸的不断减小，LTPS TFT会出现明显的短沟道效应，主要是由于漏极端处强大的电场造成的，由此引起的诸如热载流子等效应会影响器件的可靠性和稳定性。
因此，低温多晶硅薄膜晶体管的制备需要在其有源层中形成重掺杂区和轻掺杂区。在传统制备工艺中，重掺杂区和轻掺杂区需要分别通过不同的掺杂工艺形成，制备起来工艺复杂，大大限制了低温多晶硅薄膜晶体管的制备效率。
本公开实施例提供一种薄膜晶体管的制备方法，如图1和图2所示，包括：在基底1上形成有源层2，有源层2包括第一区域21、第二区域22和第三区域23；在有源层2的远离基底1的一侧形成栅绝缘层3；在栅绝缘层3的远离有源层2的一侧形成栅极4，其中，有源层2的第一区域21在基底1上的正投影与栅绝缘层3在基底1上的正投影和栅极4在基底1上的正投影均不重叠，有源层2的第二区域22在基底1上的正投影与栅绝缘层3在基底1上的正投影重叠，但是与栅极4在基底1上的正投影不重叠，有源层2的第三区域23在基底1上的正投影与栅绝缘层3在基底1上的正投影和栅极4在基底1上的正投影均重叠；从栅极4的背离有源层2的一侧对有源层2进行离子注入，使有源层2的 第一区域21形成为重掺杂区，有源层的第二区域22形成为轻掺杂区，有源层的第三区域23形成为有源区。在一些实施例中，在进行离子注入后，薄膜晶体管的制备方法还包括：在栅极4的远离有源层2的一侧形成层间绝缘层5，在层间绝缘层5中形成第一过孔11和第二过孔12，第一过孔11和第二过孔12暴露出重掺杂区21；在层间绝缘层5的远离栅极4的一侧形成源极6和漏极7，源极6通过第一过孔11与重掺杂区21连接，漏极7通过第二过孔12与重掺杂区21连接。
在从栅极4的背离有源层2的一侧对有源层2进行离子注入时，在有源层2的既被栅绝缘层3遮挡又被栅极4遮挡的部分，没有离子注入，从而形成有源层2的有源区23；在有源层2的被栅绝缘层3遮挡但未被栅极4遮挡的部分，离子部分注入，从而形成有源层2的轻掺杂区22；在有源层2的未被栅绝缘层3和栅极4遮挡的完全暴露的部分，离子充分注入，从而形成有源层2的重掺杂区21。
该薄膜晶体管的制备方法中，通过在形成栅极4之后且在形成层间绝缘层5之前，从栅极4的背离有源层2的一侧对有源层2进行离子注入，能采用已经形成的栅极4和栅绝缘层3作为掩膜，同时形成有源层2的重掺杂区21、轻掺杂区22和有源区23。相对于薄膜晶体管重掺杂区和轻掺杂区需要通过不同掺杂工艺分别制备的情况，本公开实施例的制备方法大大简化了薄膜晶体管的制备工艺，提高了薄膜晶体管的制备效率。
本公开实施例中，有源层2采用低温多晶硅材质。在一些实施例中，离子注入的能量为10-100KeV,离子注入的剂量小于2×10 18atom/cm 3。利用该离子注入能量和离子注入剂量，能在离子注入形成有源层2的重掺杂区21、轻掺杂区22和有源区23的工艺过程中，通过采用栅极4和栅绝缘层3作为掩膜，同时制备形成有源层2的重掺杂区21、轻掺杂区22和有源区23，从而简化了薄膜晶体管制备工艺，提高了薄膜晶体管制备效率。
本公开实施例中，轻掺杂区22的掺杂浓度范围为1×10 12-1×10 14atom/cm 2，重掺杂区21的掺杂浓度范围为1×10 14-1×10 16atom/cm 2。轻掺杂区22的靠近有 源区23的边界与轻掺杂区22的靠近重掺杂区21的边界之间的宽度范围为1.5-6μm。该掺杂浓度范围的重掺杂区21具有良好的导电性能，能够很好地实现源极6和漏极7与重掺杂区21之间的电导通性能。该掺杂浓度范围和宽度范围的轻掺杂区22能够很好地解决由源极6和漏极7处强大电场引起的热载流子等效应所导致的薄膜晶体管可靠性和稳定性不好的问题，确保薄膜晶体管的可靠性和稳定性。
在一些实施例中，轻掺杂区22与有源区23之间的边界形成为与栅极4的一个边界对齐，和/或，重掺杂区21与轻掺杂区22之间的边界形成为与栅绝缘层3的一个边界对齐。
本公开实施例中，形成栅绝缘层3还包括在栅绝缘层3的对应轻掺杂区22的区域(即，在与基底1垂直的方向上不与栅极4重叠的区域)形成多个贯穿其厚度的通孔30，通孔30的孔径范围为1-4μm。在一些实施例中，多个通孔30均匀分布，所有通孔30的总开孔面积小于轻掺杂区22面积的30％。通过在栅绝缘层3对应轻掺杂区22的区域内形成通孔30，有助于在离子注入形成轻掺杂区22的过程中更好地调节轻掺杂区22的离子浓度，使离子通过栅绝缘层3后部分注入至有源层2中，从而形成上述特定掺杂浓度范围的轻掺杂区22，进而有利于轻掺杂区22更好地满足其性能要求；同时能起到降低离子注入的能量，以减少离子注入对有源层2结构的破坏的作用。
在一些实施例中，栅极4采用铜、铝、钼、钛、铬、钨中的一种或几种的合金材料制成；栅绝缘层3采用氮化硅或氧化硅材料制成。栅极4为单层或多层结构。例如，栅极4可以采用钼\铝\钼、钛\铜\钛、或者钼\钛\铜的三层结构。栅绝缘层3为单层或多层结构。例如，栅绝缘层3可以采用氧化硅\氮化硅的两层结构。
另外，源极6和漏极7的材质和结构可以与栅极4相同，层间绝缘层5的材质和结构可以与栅绝缘层3相同。
图3至图11示出了利用根据公开实施例的薄膜晶体管的制备方法来制备薄膜晶体管的制备过程。
在步骤S01中，如图3所示，在基底1上形成非晶硅的有源层膜的图形,利用激光对非晶硅的有源层膜进行晶化，以形成低温多晶硅的有源层2。
在步骤S02中，如图4所示，在完成步骤S01的基底1上，在有源层2的远离基底1的一侧形成栅绝缘层膜31，在栅绝缘层膜31的远离有源层2的一侧形成栅极层膜41，在栅极层膜41的远离栅绝缘层膜31的一侧形成光阻层膜，通过对光阻层膜进行曝光、显影形成第一光阻层8的图形，第一光阻层8的边界与有源层2的待形成的重掺杂区和轻掺杂区的交界对齐。
在步骤S03中，如图5所示，刻蚀栅极层膜41和栅绝缘层膜31，以去除未被第一光阻层8遮挡的栅极层膜41部分和栅绝缘层膜31部分，形成栅绝缘层3的图形。在完成步骤S03后，可以剥离第一光阻层8。
在步骤S04中，如图6所示，在栅极层膜41的远离栅绝缘层3的一侧形成光阻层膜，通过对光阻层膜进行曝光、显影形成第二光阻层9的图形，第二光阻层9的边界与有源层2的待形成的轻掺杂区和有源区的交界对齐。在一些实施例中，第二光阻层9可以由第一光阻层8形成。例如，第一光阻层8可以具有台阶形状，在完成步骤S03后，可以对第一光阻层8进行灰化处理，得到第二光阻层9。
在步骤S05中，如图7所示，刻蚀栅极层膜41，以去除栅极层膜41的未被第二光阻层9遮挡的部分，形成栅极4的图形。在完成步骤S05后，可以剥离第二光阻层9。
在步骤S06中，如图8所示，在栅极4的远离栅绝缘层3的一侧形成光阻层膜，通过对光阻层膜进行曝光、显影形成第三光阻层10的图形，在第三光阻层10对应轻掺杂区的区域内开设多个微孔，刻蚀栅绝缘层3，以在栅绝缘层3的对应轻掺杂区的区域内形成多个通孔30。在完成步骤S06后，可以剥离第三光阻层10。
在步骤S07中，如图9所示，从栅极4的背离有源层2的一侧对有源层2进行离子注入，在有源层2中形成重掺杂区21、轻掺杂区22、有源区23。
该步骤中，在被栅极4和栅绝缘层3共同遮挡的有源层部分，离子没有注入，形成有源区23；在被栅绝缘层3遮挡但未被栅极4遮挡的有源层部分，离子部分注入，形成轻掺杂区22；在未被栅极4和栅绝缘层3遮挡的完全暴露的有源层部分，离子充分注入，形成重掺杂区21。
在步骤S08中，如图10所示，在栅极4的远离有源层2的一侧形成层间绝缘层5，并在层间绝缘层5中形成第一过孔11和第二过孔12，第一过孔11和第二过孔12处暴露出重掺杂区21。
在步骤S09中，如图11所示，在层间绝缘层5的远离栅极4的一侧形成源极6和漏极7,源极6通过第一过孔11与重掺杂区21连接，漏极7通过第二过孔12与重掺杂区21连接。
上述步骤S01-S09中各膜层的具体制备可采用现有工艺，这里不再赘述。
基于薄膜晶体管的上述制备方法，本实施例还提供一种采用上述制备方法制备的薄膜晶体管。如图2所示，薄膜晶体管包括：基底1；位于基底1上的有源层2，有源层2包括重掺杂区21、轻掺杂区22和有源区23；位于有源层2的远离基底1一侧的栅绝缘层3；以及位于栅绝缘层3的远离有源层2的一侧的栅极4。重掺杂区21在基底1上的正投影与栅绝缘层3在基底1上的正投影和栅极4在基底1上的正投影均不重叠，轻掺杂区21在基底1上的正投影与栅绝缘层3在基底1上的正投影重叠，但是与栅极4在基底1上的正投影不重叠，有源区23在基底1上的正投影与栅绝缘层3在基底1上的正投影和栅极4在基底1上的正投影均重叠。轻掺杂区22与有源区23之间的边界与栅极4的一个边界对齐，重掺杂区21与轻掺杂区22之间的边界与栅绝缘层3的一个边界对齐。有源层2包括两个轻掺杂区22，分别设于有源区23的相对两端，有源层2包括两个重掺杂区21，分别设于各轻掺杂区22的远离有源区23的一侧。在一些实施例中，所述薄膜晶体管还包括：在栅极4的远离有源层2的一侧的层间绝缘层5，在层间绝缘层5中设有第一过孔11和第二过孔12，第一过孔11和第二过孔12暴露出重掺杂区21；以及在层间绝缘层5的远离栅极4的一侧的源极6 和漏极7，源极6通过第一过孔11与重掺杂区21连接，漏极6通过第二过孔12与重掺杂区21连接。
在一些实施例中，栅绝缘层3在对应轻掺杂区22的区域开设有多个通孔30，通孔30的孔径范围为1-4μm。多个通孔30均匀分布，所有通孔30的总开孔面积小于轻掺杂区22面积的30％。
在根据本公开实施例的薄膜晶体管的制备方法中，通过在形成栅极之后且在形成层间绝缘层之前，从栅极的背离有源层的一侧对有源层进行离子注入，能采用已经形成的栅极和栅绝缘层作为掩膜，同时形成有源层的重掺杂区、轻掺杂区和有源区；相对于薄膜晶体管的重掺杂区和轻掺杂区需要通过不同掺杂工艺分别制备的情况，大大简化了薄膜晶体管的制备工艺，提高了薄膜晶体管的制备效率。
本公开实施例还提供一种阵列基板的制备方法，包括采用根据本公开实施例的薄膜晶体管的制备方法形成阵列基板中的薄膜晶体管。
本实施例中，在形成薄膜晶体管之后还包括：在所述薄膜晶体管的背离基底的一侧依次形成钝化层和像素电极。形成钝化层包括在钝化层中开设第三过孔，像素电极通过第三过孔与薄膜晶体管的漏极连接。
基于阵列基板的上述制备方法，本公开实施例还提供一种阵列基板，包括根据本公开实施例的薄膜晶体管。
另外，本实施例中，阵列基板还包括钝化层和像素电极，钝化层和像素电极设置于薄膜晶体管的背离基底的一侧，且钝化层和像素电极依次远离薄膜晶体管设置，钝化层中开设第三过孔，像素电极通过第三过孔与薄膜晶体管的漏极连接。
在根据本公开实施例的阵列基板的制备方法中，通过采用根据本公开实施例的薄膜晶体管的制备方法形成阵列基板中的薄膜晶体管，大大简化了阵列基板的制备工艺，提高了阵列基板的制备效率。
本公开实施例还提供一种显示面板，包括根据本公开实施例的阵列基板。
通过采用根据本公开实施例的阵列基板，使该显示面板的制备工艺大大简化，从而提高了该显示面板的制备效率。
本公开所提供的显示面板可以为LCD面板、LCD电视、OLED面板、OLED电视、显示器、手机、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (20)

  1. 一种薄膜晶体管的制备方法，包括：
    在基底上形成有源层，所述有源层包括第一区域、第二区域和第三区域，
    在所述有源层的远离基底的一侧形成栅绝缘层，
    在所述栅绝缘层的远离有源层的一侧形成栅极，其中，所述有源层的第一区域在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影和所述栅极在所述基底上的正投影均不重叠，所述有源层的第二区域在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影重叠，但是与所述栅极在所述基底上的正投影不重叠，所述有源层的第三区域在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影和所述栅极在所述基底上的正投影均重叠，
    从所述栅极的背离所述有源层的一侧对所述有源层进行离子注入，使所述有源层的第一区域形成为重掺杂区，所述有源层的第二区域形成为轻掺杂区，所述有源层的第三区域形成为有源区。
  2. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述离子注入的能量为10-100KeV,所述离子注入的剂量小于2×10 18atom/cm 3。
  3. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述轻掺杂区的掺杂浓度范围为1×10 12-1×10 14atom/cm 2，所述重掺杂区的掺杂浓度范围为1×10 14-1×10 16atom/cm 2。
  4. 根据权利要求1-3中任意一项所述的薄膜晶体管的制备方法，其中，所述有源层采用低温多晶硅材质。
  5. 根据权利要求1所述的薄膜晶体管的制备方法，其中，形成所述栅绝缘 层还包括在所述栅绝缘层的在与所述基底垂直的方向上不与所述栅极重叠的区域形成多个贯穿所述栅绝缘层厚度的通孔，所述通孔的孔径范围为1-4μm。
  6. 根据权利要求5所述的薄膜晶体管的制备方法，其中，所述多个通孔均匀分布，所有通孔的总开孔面积小于所述轻掺杂区面积的30％。
  7. 根据权利要求1所述的晶体管的制备方法，其中，所述轻掺杂区的靠近所述有源区的边界与所述轻掺杂区的靠近所述重掺杂区的边界之间的宽度范围为1.5-6μm。
  8. 根据权利要求1所述的晶体管的制备方法，其中，所述轻掺杂区与所述有源区之间的边界形成为与所述栅极的一个边界对齐。
  9. 根据权利要求1所述的晶体管的制备方法，其中，所述重掺杂区与所述轻掺杂区之间的边界形成为与所述栅绝缘层的一个边界对齐。
  10. 根据权利要求1所述的薄膜晶体管的制备方法，其中，所述栅极采用铜、铝、钼、钛、铬、钨中的一种或几种的合金材料制成；所述栅绝缘层采用氮化硅或氧化硅材料制成。
  11. 根据权利要求4所述的薄膜晶体管的制备方法，其中，在基底上形成有源层包括：
    在基底上形成非晶硅的有源层膜的图形；以及
    利用激光使非晶硅的有源层膜的图形晶化，以形成低温多晶硅的有源层。
  12. 根据权利要求1所述的薄膜晶体管的制备方法，其中，在所述有源层 的远离基底的一侧形成栅绝缘层，以及在所述栅绝缘层的远离有源层的一侧形成栅极包括：
    在所述有源层的远离基底的一侧形成栅绝缘层膜，
    在所述栅绝缘层膜的远离所述有源层的一侧形成栅极层膜，
    在所述栅极层膜的远离所述栅绝缘层膜的一侧形成第一光阻层，
    刻蚀所述栅极层膜和所述栅绝缘层膜，以去除述栅极层膜和所述栅绝缘层膜的未被所述第一光阻层遮挡的部分，形成所述栅绝缘层，
    在所述栅极层膜的远离所述栅绝缘层的一侧形成第二光阻层，
    刻蚀所述栅极层膜，以去除所述栅极层膜的未被所述第二光阻层遮挡的部分，形成所述栅极。
  13. 根据权利要求12所述的薄膜晶体管的制备方法，还包括：
    在所述栅极的远离所述栅绝缘层的一侧形成第三光阻层，所述第三光阻层的在与所述基底垂直的方向上与所述轻掺杂区重叠的区域内设有多个微孔，以及
    刻蚀所述栅绝缘层，以在所述栅绝缘层的在与所述基底垂直的方向上不与所述栅极重叠的区域形成多个贯穿所述栅绝缘层厚度的通孔。
  14. 根据权利要求13所示的薄膜晶体管的制备方法，在进行所述离子注入之后，还包括：
    在所述栅极的远离所述有源层的一侧形成层间绝缘层，在所述层间绝缘层中形成第一过孔和第二过孔，所述第一过孔和所述第二过孔暴露出所述重掺杂区，以及
    在所述层间绝缘层的远离所述栅极的一侧形成源极和漏极，所述源极通过所述第一过孔与所述重掺杂区连接，所述漏极通过所述第二过孔与所述重掺杂区连接。
  15. 一种薄膜晶体管，包括：
    基底，
    位于所述基底上的有源层，所述有源层包括重掺杂区、轻掺杂区和有源区，
    位于所述有源层的远离所述基底一侧的栅绝缘层，以及
    位于所述栅绝缘层的远离所述有源层的一侧的栅极，
    其中，所述重掺杂区在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影和所述栅极在所述基底上的正投影均不重叠，所述轻掺杂区在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影重叠，但是与所述栅极在所述基底上的正投影不重叠，所述有源区在所述基底上的正投影与所述栅绝缘层在所述基底上的正投影和所述栅极在所述基底上的正投影均重叠，
    所述轻掺杂区与所述有源区之间的边界与所述栅极的一个边界对齐，所述重掺杂区与所述轻掺杂区之间的边界与所述栅绝缘层的一个边界对齐。
  16. 根据权利要求15所述的薄膜晶体管，其中，所述轻掺杂区的掺杂浓度范围为1×10 12-1×10 14atom/cm 2，所述重掺杂区的掺杂浓度范围为1×10 14-1×10 16atom/cm 2。
  17. 根据权利要求15所述的薄膜晶体管，还包括：
    在所述栅极的远离所述有源层的一侧的层间绝缘层，在所述层间绝缘层中设有第一过孔和第二过孔，所述第一过孔和所述第二过孔暴露出所述重掺杂区，
    在所述层间绝缘层的远离所述栅极的一侧的源极和漏极，所述源极通过所述第一过孔与所述重掺杂区连接，所述漏极通过所述第二过孔与所述重掺杂区 连接。
  18. 一种阵列基板的制备方法，包括：采用权利要求1-14中任意一项所述的薄膜晶体管的制备方法形成所述阵列基板中的薄膜晶体管。
  19. 一种阵列基板，包括根据权利要求15-17中任一项所述的薄膜晶体管。
  20. 一种显示面板，包括根据权利要求19所述的阵列基板。
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