WO2017054260A1 - 一种显示装置、tft基板及goa驱动电路 - Google Patents

一种显示装置、tft基板及goa驱动电路 Download PDF

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Publication number
WO2017054260A1
WO2017054260A1 PCT/CN2015/092354 CN2015092354W WO2017054260A1 WO 2017054260 A1 WO2017054260 A1 WO 2017054260A1 CN 2015092354 W CN2015092354 W CN 2015092354W WO 2017054260 A1 WO2017054260 A1 WO 2017054260A1
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Prior art keywords
switch tube
signal
output
control
pull
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Ceased
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PCT/CN2015/092354
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English (en)
French (fr)
Inventor
曹尚操
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd, Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to JP2018515439A priority Critical patent/JP6587329B2/ja
Priority to KR1020187011341A priority patent/KR102057822B1/ko
Priority to DE112015006977.1T priority patent/DE112015006977B4/de
Priority to GB1804765.4A priority patent/GB2556837B/en
Priority to US14/894,357 priority patent/US9886927B2/en
Publication of WO2017054260A1 publication Critical patent/WO2017054260A1/zh
Priority to US15/853,729 priority patent/US9972270B1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2354/00—Aspects of interface with display user

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display device, a TFT substrate, and a GOA driving circuit.
  • the in-cell touch panel can achieve a thinner body and better user experience, and is being pursued by more and more users.
  • the in-cell panel touch driving frequency is related to the sensitivity and accuracy of the touch, such as high generation.
  • the 120HZ touch drive frequency is favored by panel manufacturers, but this drive method requires scanning multiple times within one frame, when TP (touch When the panel or the touch panel is driven, the GOA (Gate On Array) is driven to be interrupted, which improves the difficulty of designing the GOA driving circuit.
  • the technical problem to be solved by the present invention is to provide a display device, a TFT substrate and a GOA circuit, which realizes pause and level transmission of the GOA circuit, realizes high-frequency TP driving, and can save IC cost to the utmost.
  • a technical solution adopted by the present invention is to provide a GOA driving circuit, wherein the GOA driving circuit includes a multi-level driving unit, and each driving unit includes: an input module, configured to receive a touch control signal, a low level signal, a high level signal and an output signal of the upper stage, and outputting a first control signal according to the received signal, wherein the input module of the first stage driving unit receives the touch control signal and the low level a signal, a high level signal, and a preset initial signal; an output module, configured to receive the first control signal and the first clock signal, and output a first output control signal according to the first control signal and the first clock signal; And receiving a first control signal, a second clock signal, and a low level signal, and outputting a pull-down signal according to the first control signal, the second clock signal, and the low level signal, wherein the second clock signal and the first clock signal are opposite a pull-down maintenance module for receiving a pull-down signal, a high-level
  • the input module includes a first switch tube, a second switch tube and a first capacitor, wherein: the control end of the first switch tube receives the output signal of the upper stage, and the input end of the first open switch tube receives the low level signal, The output end of the first switch tube is connected to the input end of the second switch tube, wherein the control end of the first switch tube of the first stage drive unit receives a preset initial signal; the control end of the second switch tube receives the touch control signal The input end of the second switch tube is connected to the output end of the first switch tube, and the output end of the second switch tube outputs a first control signal; one end of the first capacitor receives a high level signal, and the other end is connected to the input of the second switch tube; end.
  • the output module includes a third switch tube and a second capacitor, wherein: the control end of the third switch tube is connected to the output end of the second switch tube to receive the first control signal, and the input end of the third switch tube receives the first clock
  • the output end of the third switch tube outputs a first output control signal; the two ends of the second capacitor are respectively connected to the control end and the output end of the third switch tube.
  • the pull-down signal includes a first pull-down signal and a second pull-down signal
  • the pull-down module includes a fourth switch tube and a fifth switch tube, wherein: the control end of the fourth switch tube is connected to the output end of the second switch tube to receive the first a control signal, the input end of the fourth switch tube receives the second clock signal, the output end of the fourth switch tube outputs a first pull-down signal; the control end of the fifth switch tube receives the second clock signal, and the input of the fifth switch tube
  • the terminal receives the low level signal, and the output end of the fifth switch tube outputs the second pull down signal.
  • the pull-down maintenance module includes a sixth switch tube, a seventh switch tube, an eighth switch tube, and a third capacitor, wherein: the control end of the sixth switch tube receives the first clock signal, and the input end of the sixth switch tube is connected to the seventh An output end of the switch tube, the output end of the sixth switch tube is connected to the control end of the third switch tube; the control end of the seventh switch tube is respectively connected to the output ends of the fourth switch tube and the fifth switch tube to receive the pull-down signal, The input end of the seventh switch tube receives a high level signal, and the output end of the seventh switch tube is connected to the input end of the sixth switch tube; the control end of the eighth switch tube is respectively connected to the output end of the fourth switch tube and the fifth switch tube, Receiving the pull-down signal, the input end of the eighth switch tube receives the high level signal, and the output end of the eighth switch tube outputs the second output control signal; the third end of the third capacitor is connected to the control end of the seventh switch tube and the eighth switch tube The other end receives
  • the circuit further includes a ninth switch tube, the control end of the ninth switch tube receives a low level signal, the input end of the ninth switch tube is connected to the output end of the second switch tube, and the output end of the ninth switch tube is connected to the third switch The control end of the tube.
  • the ninth switch tube is a P-type switch tube, the control end is a gate of a P-type switch tube, the input end is a source of a P-type switch tube, and the output end is a drain of a P-type switch tube.
  • the first switch tube to the eighth switch tube are all P-type switch tubes, the control end is the gate of the P-type switch tube, the input end is the source of the P-type switch tube, and the output end is the drain of the P-type switch tube. .
  • a TFT substrate including a GOA driving circuit
  • the GOA driving circuit includes a multi-level driving unit
  • each driving unit includes: an input module. And receiving the touch control signal, the low level signal, the high level signal, and the output signal of the previous stage, and outputting the first control signal according to the received signal
  • the input module of the first stage driving unit receives a touch control signal, a low level signal, a high level signal, and a preset initial signal
  • an output module configured to receive the first control signal and the first clock signal, and output the first according to the first control signal and the first clock signal
  • a pull-down module configured to receive the first control signal, the second clock signal, and the low level signal, and output a pull-down signal according to the first control signal, the second clock signal, and the low level signal, wherein the second The clock signal and the first clock signal are reversed
  • the pull-down maintaining module is configured to receive the pull-
  • the input module includes a first switch tube, a second switch tube and a first capacitor, wherein: the control end of the first switch tube receives the output signal of the upper stage, and the input end of the first open switch tube receives the low level signal, The output end of the first switch tube is connected to the input end of the second switch tube, wherein the control end of the first switch tube of the first stage drive unit receives a preset initial signal; the control end of the second switch tube receives the touch control signal The input end of the second switch tube is connected to the output end of the first switch tube, and the output end of the second switch tube outputs a first control signal; one end of the first capacitor receives a high level signal, and the other end is connected to the input of the second switch tube; end.
  • the output module includes a third switch tube and a second capacitor, wherein: the control end of the third switch tube is connected to the output end of the second switch tube to receive the first control signal, and the input end of the third switch tube receives the first clock
  • the output end of the third switch tube outputs a first output control signal; the two ends of the second capacitor are respectively connected to the control end and the output end of the third switch tube.
  • the pull-down signal includes a first pull-down signal and a second pull-down signal
  • the pull-down module includes a fourth switch tube and a fifth switch tube, wherein: the control end of the fourth switch tube is connected to the output end of the second switch tube to receive the first a control signal, the input end of the fourth switch tube receives the second clock signal, the output end of the fourth switch tube outputs a first pull-down signal; the control end of the fifth switch tube receives the second clock signal, and the input of the fifth switch tube
  • the terminal receives the low level signal, and the output end of the fifth switch tube outputs the second pull down signal.
  • the pull-down maintenance module includes a sixth switch tube, a seventh switch tube, an eighth switch tube, and a third capacitor, wherein: the control end of the sixth switch tube receives the first clock signal, and the input end of the sixth switch tube is connected to the seventh An output end of the switch tube, the output end of the sixth switch tube is connected to the control end of the third switch tube; the control end of the seventh switch tube is respectively connected to the output ends of the fourth switch tube and the fifth switch tube to receive the pull-down signal, The input end of the seventh switch tube receives a high level signal, and the output end of the seventh switch tube is connected to the input end of the sixth switch tube; the control end of the eighth switch tube is respectively connected to the output end of the fourth switch tube and the fifth switch tube, Receiving the pull-down signal, the input end of the eighth switch tube receives the high level signal, and the output end of the eighth switch tube outputs the second output control signal; the third end of the third capacitor is connected to the control end of the seventh switch tube and the eighth switch tube The other end receives
  • the circuit further includes a ninth switch tube, the control end of the ninth switch tube receives a low level signal, the input end of the ninth switch tube is connected to the output end of the second switch tube, and the output end of the ninth switch tube is connected to the third switch The control end of the tube.
  • a display device including a TFT substrate, the TFT substrate including a GOA driving circuit, wherein the GOA driving circuit includes a multi-level driving unit, and each driving The unit includes: an input module, configured to receive a touch control signal, a low level signal, a high level signal, and an output signal of a previous stage, and output a first control signal according to the received signal, wherein the first stage driving unit
  • the input module receives a touch control signal, a low level signal, a high level signal, and a preset initial signal; and an output module, configured to receive the first control signal and the first clock signal, and according to the first control signal and The first clock signal outputs a first output control signal;
  • the pull-down module is configured to receive the first control signal, the second clock signal, and the low level signal, and output pull-down according to the first control signal, the second clock signal, and the low level signal a signal, wherein the second clock signal and the first clock signal are in
  • the input module includes a first switch tube, a second switch tube and a first capacitor, wherein: the control end of the first switch tube receives the output signal of the upper stage, and the input end of the first open switch tube receives the low level signal, The output end of the first switch tube is connected to the input end of the second switch tube, wherein the control end of the first switch tube of the first stage drive unit receives a preset initial signal; the control end of the second switch tube receives the touch control signal The input end of the second switch tube is connected to the output end of the first switch tube, and the output end of the second switch tube outputs a first control signal; one end of the first capacitor receives a high level signal, and the other end is connected to the input of the second switch tube; end.
  • the output module includes a third switch tube and a second capacitor, wherein: the control end of the third switch tube is connected to the output end of the second switch tube to receive the first control signal, and the input end of the third switch tube receives the first clock
  • the output end of the third switch tube outputs a first output control signal; the two ends of the second capacitor are respectively connected to the control end and the output end of the third switch tube.
  • the pull-down signal includes a first pull-down signal and a second pull-down signal
  • the pull-down module includes a fourth switch tube and a fifth switch tube, wherein: the control end of the fourth switch tube is connected to the output end of the second switch tube to receive the first a control signal, the input end of the fourth switch tube receives the second clock signal, the output end of the fourth switch tube outputs a first pull-down signal; the control end of the fifth switch tube receives the second clock signal, and the input of the fifth switch tube
  • the terminal receives the low level signal, and the output end of the fifth switch tube outputs the second pull down signal.
  • the pull-down maintenance module includes a sixth switch tube, a seventh switch tube, an eighth switch tube, and a third capacitor, wherein: the control end of the sixth switch tube receives the first clock signal, and the input end of the sixth switch tube is connected to the seventh An output end of the switch tube, the output end of the sixth switch tube is connected to the control end of the third switch tube; the control end of the seventh switch tube is respectively connected to the output ends of the fourth switch tube and the fifth switch tube to receive the pull-down signal, The input end of the seventh switch tube receives a high level signal, and the output end of the seventh switch tube is connected to the input end of the sixth switch tube; the control end of the eighth switch tube is respectively connected to the output end of the fourth switch tube and the fifth switch tube, Receiving the pull-down signal, the input end of the eighth switch tube receives the high level signal, and the output end of the eighth switch tube outputs the second output control signal; the third end of the third capacitor is connected to the control end of the seventh switch tube and the eighth switch tube The other end receives
  • the circuit further includes a ninth switch tube, the control end of the ninth switch tube receives a low level signal, the input end of the ninth switch tube is connected to the output end of the second switch tube, and the output end of the ninth switch tube is connected to the third switch The control end of the tube.
  • the invention has the beneficial effects that the present invention provides a GOA driving circuit, wherein the GOA driving circuit comprises a multi-level driving unit, and each driving unit comprises an input module, an output module, a pull-down module and a pull-down. Maintain the module.
  • the input module is configured to receive a touch control signal, a low level signal, a high level signal, and an output signal of a previous stage, and output a first control signal according to the received signal, wherein the input of the first stage driving unit
  • the module receives the touch control signal, the low level signal, the high level signal, and the preset initial signal.
  • the output module is configured to receive the first control signal and the first clock signal, and output the first output control signal according to the first control signal and the first clock signal.
  • the pull-down module is configured to receive the first control signal, the second clock signal, and the low level signal, and output a pull-down signal according to the first control signal, the second clock signal, and the low level signal, wherein the second clock signal and the first clock The signal is reversed.
  • the pull-down maintaining module is configured to receive the pull-down signal, the high-level signal, and the first clock signal, and output a second output control signal according to the pull-down signal, the high-level signal, and the first clock signal, where the first output control signal and the second output The control signals work together to obtain an output signal. Therefore, the GOA driving circuit of the present invention can perform pause and level transmission according to the touch control signal, thereby implementing high frequency TP driving. Further, the present invention implements the GOA driving circuit by using the above simple modules, which can maximize Saving IC costs.
  • FIG. 1 is a schematic structural diagram of a GOA driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram of an nth stage driving unit of a GOA driving circuit according to an embodiment of the present invention
  • Figure 3 is a timing diagram of signals when the GOA driving circuit is operating
  • FIG. 4 is a schematic structural diagram of another GOA driving circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a display device according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a GOA driving circuit according to an embodiment of the present invention.
  • the GOA driving circuit 10 of the embodiment of the present invention includes a multi-stage driving unit 11.
  • Each of the driving units 11 receives the touch control signal TC, the low level signal VGL, the high level signal VGH, the output signal Gn-1 of the previous stage, the first clock signal CK, and the second clock signal XCK.
  • the output signal of the upper stage received by the first stage driving unit 11 is replaced with a preset initial signal STV. Therefore, the GOA driving circuit 10 of the present embodiment can perform pause and level transmission according to the touch control signal TC, thereby implementing high-frequency TP driving, and further, can save the IC cost to the utmost.
  • FIG. 2 is a schematic circuit diagram of an nth stage driving unit of a GOA driving circuit according to an embodiment of the present invention.
  • the driving unit 10 includes an input module 110, an output module 111, a pull-down module 112, and a pull-down maintaining module 113.
  • the input module 110 is configured to receive the touch control signal TC, the low level signal VGL, the high level signal VGH, and the output signal Gn-1 of the previous stage, and output the first control signal K1 according to the received signal.
  • the first control signal K1 is output to the first node Qn, and the first node Qn is a point for controlling the output of the driving signal.
  • the input module 110 of the first-stage driving unit 11 receives the touch control signal TC, the low-level signal VGL, the high-level signal VGH, and the preset initial signal STV.
  • the output module 111 is configured to receive the first control signal K1 and the first clock signal CK, and output the first output control signal O1 according to the first control signal K1 and the first clock signal CK.
  • the pull-down module 112 is configured to receive the first control signal K1, the second clock signal XCK, and the low-level signal VGL, and output the pull-down signal L1 according to the first control signal K1, the second clock signal XCK, and the low-level signal VGL.
  • the pull-down signal L1 is output to the second node Pn, and the second node Pn is a point for controlling the stable output of the circuit during the inactive period of the circuit.
  • the second clock signal XCK is opposite to the first clock signal CK.
  • the pull-down maintaining module 113 is configured to receive the pull-down signal L1, the high-level signal VGH, and the first clock signal CK, and output a second output control signal O2 according to the pull-down signal L1, the high-level signal VGH, and the first clock signal CK, where An output control signal O1 and a second output control signal O2 cooperate to obtain an output signal Gn.
  • the input module 110 includes a first switch tube T1, a second switch tube T2, and a first capacitor C1.
  • the control end of the first switch tube T1 receives the output signal Gn-1 of the previous stage, the input end of the first open switch tube T1 receives the low level signal VGL, and the output end of the first switch tube T1 is connected to the second switch tube.
  • the control end of the second switch tube T2 receives the touch control signal TC, the input end of the second switch tube T2 is connected to the output end of the first switch tube T1, and the output end of the second switch tube T2 outputs the first control signal K1, the specific The output of the second switching transistor T2 is connected to the first node Qn to output the first control signal K1 to the first node Qn.
  • One end of the first capacitor C1 receives the high level signal VGH, and the other end is connected to the input end of the second switching tube T2, that is, the other end is connected between the input end of the second switching tube T2 and the output end of the first switching tube T1.
  • the first capacitor C1 is used to stabilize the voltage on the input terminal of the second switching transistor T2.
  • the output module 111 includes a third switching transistor T3 and a second capacitor C2.
  • the control end of the third switch tube T3 is connected to the output end of the second switch tube T2 to receive the first control signal K1.
  • the control end of the third switch tube T3 is connected to the first node Qn to pass the first node.
  • Qn receives the first control signal K1 output by the second switching transistor T2.
  • the input end of the third switch T3 receives the first clock signal CK, and the output end of the third switch T3 outputs the first output control signal O1.
  • the two ends of the second capacitor C2 are respectively connected to the control end and the output end of the third switch tube T3, that is, one end of the second capacitor C2 and the control end of the third switch tube T3 are connected to the first node Qn.
  • the pull-down signal L1 includes a first pull-down signal L11 and a second pull-down signal L12
  • the pull-down module 112 includes a fourth switch tube T4 and a fifth switch tube T5.
  • the control end of the fourth switch tube T4 is connected to the output end of the second switch tube T2 to receive the first control signal K1.
  • the control end of the fourth switch tube T4 and the output end of the second switch tube T2 are connected.
  • the first node Qn, the input end of the fourth switch tube T4 receives the second clock signal XCK, and the output end of the fourth switch tube T4 outputs the first pull-down signal L11.
  • the output end of the fourth switch tube T4 is connected to the first The two nodes Pn output a first pull-down signal L11 to the second node Pn.
  • the control end of the fifth switch T5 receives the second clock signal XCK, the input end of the fifth switch T5 receives the low level signal VGL, and the output end of the fifth switch T5 outputs the second pull down signal L12, specifically, the fifth The output of the switching transistor T5 is connected to the second node Pn to output a second pull-down signal L12 to the second node Pn.
  • the pull-down maintaining module 113 includes a sixth switching transistor T6, a seventh switching transistor T7, an eighth switching transistor T8, and a third capacitor C3.
  • the control end of the sixth switch tube T6 receives the first clock signal CK, the input end of the sixth switch tube T6 is connected to the output end of the seventh switch tube T7, and the output end of the sixth switch tube T6 is connected to the first node Qn.
  • the control terminal of the third switching transistor T3 is connected through the first node Qn.
  • the control end of the seventh switch tube T7 is connected to the output ends of the fourth switch tube T4 and the fifth switch tube T5 through the second node Pn to receive the pull-down signal L1, and the input end of the seventh switch tube T7 receives the high level signal VGH.
  • the output end of the seventh switch tube T7 is connected to the input end of the sixth switch tube T6.
  • the control end of the eighth switch tube T8 is connected to the output ends of the fourth switch tube T4 and the fifth switch tube T5 through the second node Pn to receive the pull-down signal L1, and the input end of the eighth switch tube T8 receives the high level signal VGH.
  • the output end of the eighth switch tube T8 outputs a second output control signal O2.
  • One end of the third capacitor C3 is connected to the control ends of the seventh switch tube T7 and the eighth switch tube T8, and the other end receives the high level signal VGH.
  • the first switch tube T1 to the eighth switch tube T8 are all P-type switch tubes, the control end thereof is the gate of the P-type switch tube, the input end is the source of the P-type switch tube, and the output end is the P-type switch tube.
  • the drain is the P-type switch tube
  • FIG. 3 is a timing diagram of signals when the GOA driving circuit of the present invention operates.
  • the GOA driving circuit of the present invention includes a display driving time and a TP action time, wherein the display driving time includes four stages, as follows:
  • the first stage the first switching transistor T1 and the second switching transistor T2 are turned on, and the low level signal VGL is used as the first control signal K1 to pull the first node Qn low to a low potential.
  • the control ends of the third switching transistor T3 and the fourth switching transistor T4 are at a low potential, and therefore, the third switching transistor T3 and the fourth switching transistor T4 are both turned on.
  • the second clock signal XCK is low, and the fifth switch T5 is turned on, so that the first pull-down signal L11 and the second pull-down signal L12 are both low, and the output pull-down signal L1 is low, pulling down the first
  • the two nodes Pn are at a low potential, so that the seventh switch tube T7 and the eighth switch tube T8 are both turned on.
  • the first clock signal CK which is opposite to the second clock signal XCK, is now at a high potential, so that the sixth switching transistor T6 is turned off.
  • the third switch T3 outputs a high-potential first output control signal O1
  • the eighth switch T8 also outputs a high-potential first output control signal O2 such that the output signal Gn is at a high potential.
  • the second stage the second capacitor C2 is charged in the first stage, and the end connected to the first node Qn is low, so the first node Qn is still at a low potential, that is, the second capacitor C2 makes the first control Signal K1 remains low, causing third switch T3 to open.
  • the first clock signal CK is at a low potential, so the output signal Gn is at a low potential, which can drive the TFT (Thin The Film Transistor is a pixel unit of the display area (AA area) of the substrate of the thin film transistor, and can be transmitted as a level signal to the next stage driving unit.
  • the fourth switching transistor T4 is turned on.
  • the second clock signal XCK is at a high potential, so that the first pull-down signal L11 is at a high potential, and the fifth switch T5 is turned off, so that the pull-down signal L1 is at a high potential, that is, the second node Pn becomes a high potential, so that the seventh The switch tube T7 and the eighth switch tube T8 are turned off, the second output control signal O2 disappears, and the second node Q point is coupled to the lower potential through the second capacitor C2, so that the first control signal K1 becomes lower potential to ensure The output signal Gn is output normally.
  • the third stage due to the action of the second capacitor C2, the first node Qn is still at a low potential, that is, the second capacitor C2 keeps the first control signal K1 low, and the third switch tube T3 and the fourth switch tube T4 turn on.
  • the first clock signal CK is at a high potential
  • the second clock signal XCK is at a low potential, so that the first output control signal O1 outputted by the third switching transistor T3 is at a high potential, and the first pull-down signal L11 is at a low potential.
  • the fifth switch tube T5 is turned on, and the second pull-down signal L12 is also low, so the pull-down signal L1 is low, that is, the second node Pn becomes low, and the seventh switch tube T7 and the eighth switch tube T8 are turned on, and the output is
  • the two output control signal O2 is at a high potential, and acts on the first output control signal O1 which is also at a high potential such that the output signal Gn is at a high potential.
  • the fourth stage the first clock signal CK is low, and the sixth switch tube T6 is turned on. Due to the action of the third capacitor C3, the seventh switch tube T7 is ensured to be opened at this time, so the first control signal K1 of the first node Qn is The moment is pulled high, so that the third switch tube T3 and the fourth switch tube T4 are turned off, and the first control signal K1 of the first node Qn and the pull-down signal L1 of the second node Pn are kept in the process of one frame thereafter. High potential and low potential.
  • the touch control signal TC becomes high, so that the second switching transistor T2 is turned off, the level signal is temporarily stored on the first capacitor C1, and when the TP action time is over, the touch is The control signal TC becomes low, the second switch T2 is turned on, and the low potential temporarily stored on the first capacitor C1 is charged as the first control signal K1 to the first node Qn, so that the first node Qn goes low, and the third switch tube T3 is turned on, and then the process continues as described above.
  • FIG. 4 is a schematic structural diagram of another GOA driving circuit according to an embodiment of the present invention.
  • the GOA driving circuit of the present embodiment is different from the GOA driving circuit described above in that the GOA driving circuit of the embodiment further includes a ninth switching transistor T9 and a control terminal of the ninth switching transistor T9.
  • the input end of the ninth switch tube T9 is connected to the output end of the second switch tube T2, and the output end of the ninth switch tube T9 is connected to the control end of the third switch tube T3.
  • the function of the ninth switch T9 is that when the first control signal K1 of the first node Qn is coupled to the lower potential, the ninth switch T9 is turned off, and the potential of the first control signal K1 of the first node Qn is reduced by the outside. influences.
  • FIG. 5 is a schematic diagram of the display device of the present invention.
  • the display device 40 includes a TFT substrate 1 and a GOA driving circuit 2 on the side of the TFT substrate 1, wherein the GOA driving circuit 2 is the GOA driving circuit 10 described above.
  • the GOA driving circuit of the present invention can implement pause and level transmission through the touch control signal TC, and is suitable for high frequency TP driving.
  • the GOA driving circuit of the present invention can be formed by only 9 switching tubes and three capacitors, and the IC cost can be saved to the utmost.

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Abstract

一种显示装置（40）、TFT基板（1）及GOA驱动电路（2）。该GOA驱动电路（2）的驱动单元（11）包括输入模块（110），用于根据接收到的信号（TC）输出第一控制信号（K1）；输出模块（111），用于根据第一控制信号（K1）和第一时钟信号（CK）输出第一输出控制信号（O1）；下拉模块（112），用于根据第一控制信号（K1）、第二时钟信号（XCK）和低电平信号（VGL）输出下拉信号（L1）；下拉维持模块（113），用于根据下拉信号（L1）、高电平信号（VGH）和第一时钟信号（CK）输出第二输出控制信号（O2），以和第一输出控制信号（O1）共同作用来获得输出信号（Gn）。通过上述方式，能够实现GOA驱动电路（2）的暂停和级传。

Description

一种显示装置、TFT基板及GOA驱动电路
【技术领域】
本发明涉及显示技术领域，尤其是涉及一种显示装置、TFT基板及GOA驱动电路。
【背景技术】
内嵌式触控面板可以实现更薄的机身和较佳的用户体验，受到越来越多的用户追求，内嵌式面板触控驱动频率关乎到触控的灵敏度和精确度，如高代120HZ的触控驱动频率受到面板厂商的青睐，但此种驱动方式要求在一帧之内扫描多次，当TP（touch panel，触控面板）驱动时，GOA（Gate On Array，栅极驱动设置在阵列基板上）驱动要中断，提高了GOA驱动电路设计的难度。
【发明内容】
本发明主要解决的技术问题是提供一种显示装置、TFT基板及GOA电路，实现GOA电路的暂停和级传，实现高频TP驱动，并能够在最大限度的节约IC成本。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种GOA驱动电路，其中，GOA驱动电路包括多级驱动单元，每一驱动单元包括：输入模块，用于接收触控控制信号、低电平信号、高电平信号和上一级的输出信号，并根据接收到的信号输出第一控制信号，其中，第一级驱动单元的输入模块接收的是触控控制信号、低电平信号、高电平信号和预设的初始信号；输出模块，用于接收第一控制信号和第一时钟信号，并根据第一控制信号和第一时钟信号输出第一输出控制信号；下拉模块，用于接收第一控制信号、第二时钟信号和低电平信号，并根据第一控制信号、第二时钟信号和低电平信号输出下拉信号，其中，第二时钟信号和第一时钟信号反向；下拉维持模块，用于接收下拉信号、高电平信号和第一时钟信号，并根据下拉信号、高电平信号和第一时钟信号输出第二输出控制信号，其中第一输出控制信号和第二输出控制信号共同作用来获得输出信号。
其中，输入模块包括第一开关管、第二开关管和第一电容，其中：第一开关管的控制端接收上一级的输出信号，第一开开关管的输入端接收低电平信号，第一开关管的输出端连接第二开关管的输入端，其中，第一级驱动单元的第一开关管的控制端接收预设的初始信号；第二开关管的控制端接收触控控制信号，第二开关管的输入端连接第一开关管的输出端，第二开关管的输出端输出第一控制信号；第一电容的一端接收高电平信号，另一端连接第二开关管的输入端。
其中，输出模块包括第三开关管和第二电容，其中：第三开关管的控制端连接第二开关管的输出端，以接收第一控制信号，第三开关管的输入端接收第一时钟信号，第三开关管的输出端输出第一输出控制信号；第二电容的两端分别连接第三开关管的控制端和输出端。
其中，下拉信号包括第一下拉信号和第二下拉信号，下拉模块包括第四开关管和第五开关管，其中：第四开关管的控制端连接第二开关管的输出端，以接收第一控制信号，第四开关管的输入端接收第二时钟信号，第四开关管的输出端输出第一下拉信号；第五开关管的控制端接收第二时钟信号，第五开关管的输入端接收低电平信号，第五开关管的输出端输出第二下拉信号。
其中，下拉维持模块包括第六开关管、第七开关管、第八开关管和第三电容，其中：第六开关管的控制端接收第一时钟信号，第六开关管的输入端连接第七开关管的输出端，第六开关管的输出端连接第三开关管的控制端；第七开关管的控制端分别连接第四开关管和第五开关管的输出端，以接收下拉信号，第七开关管的输入端接收高电平信号，第七开关管的输出端连接第六开关管的输入端；第八开关管的控制端分别连接第四开关管和第五开关管的输出端，以接收下拉信号，第八开关管的输入端接收高电平信号，第八开关管的输出端输出第二输出控制信号；第三电容一端与第七开关管和第八开关管的控制端连接，另一端接收高电平信号。
其中，电路进一步包括第九开关管，第九开关管的控制端接收低电平信号，第九开关管的输入端连接第二开关管的输出端，第九开关管的输出端连接第三开关管的控制端。
其中，第九开关管为P型开关管，控制端为P型开关管的栅极，输入端为P型开关管的源极，输出端为P型开关管的漏极。
其中，第一开关管至第八开关管均为P型开关管，控制端为P型开关管的栅极，输入端为P型开关管的源极，输出端为P型开关管的漏极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种TFT基板，该TFT基板包括GOA驱动电路，其中，GOA驱动电路包括多级驱动单元，每一驱动单元包括：输入模块，用于接收触控控制信号、低电平信号、高电平信号和上一级的输出信号，并根据接收到的信号输出第一控制信号，其中，第一级驱动单元的输入模块接收的是触控控制信号、低电平信号、高电平信号和预设的初始信号；输出模块，用于接收第一控制信号和第一时钟信号，并根据第一控制信号和第一时钟信号输出第一输出控制信号；下拉模块，用于接收第一控制信号、第二时钟信号和低电平信号，并根据第一控制信号、第二时钟信号和低电平信号输出下拉信号，其中，第二时钟信号和第一时钟信号反向；下拉维持模块，用于接收下拉信号、高电平信号和第一时钟信号，并根据下拉信号、高电平信号和第一时钟信号输出第二输出控制信号，其中第一输出控制信号和第二输出控制信号共同作用来获得输出信号。
其中，输入模块包括第一开关管、第二开关管和第一电容，其中：第一开关管的控制端接收上一级的输出信号，第一开开关管的输入端接收低电平信号，第一开关管的输出端连接第二开关管的输入端，其中，第一级驱动单元的第一开关管的控制端接收预设的初始信号；第二开关管的控制端接收触控控制信号，第二开关管的输入端连接第一开关管的输出端，第二开关管的输出端输出第一控制信号；第一电容的一端接收高电平信号，另一端连接第二开关管的输入端。
其中，输出模块包括第三开关管和第二电容，其中：第三开关管的控制端连接第二开关管的输出端，以接收第一控制信号，第三开关管的输入端接收第一时钟信号，第三开关管的输出端输出第一输出控制信号；第二电容的两端分别连接第三开关管的控制端和输出端。
其中，下拉信号包括第一下拉信号和第二下拉信号，下拉模块包括第四开关管和第五开关管，其中：第四开关管的控制端连接第二开关管的输出端，以接收第一控制信号，第四开关管的输入端接收第二时钟信号，第四开关管的输出端输出第一下拉信号；第五开关管的控制端接收第二时钟信号，第五开关管的输入端接收低电平信号，第五开关管的输出端输出第二下拉信号。
其中，下拉维持模块包括第六开关管、第七开关管、第八开关管和第三电容，其中：第六开关管的控制端接收第一时钟信号，第六开关管的输入端连接第七开关管的输出端，第六开关管的输出端连接第三开关管的控制端；第七开关管的控制端分别连接第四开关管和第五开关管的输出端，以接收下拉信号，第七开关管的输入端接收高电平信号，第七开关管的输出端连接第六开关管的输入端；第八开关管的控制端分别连接第四开关管和第五开关管的输出端，以接收下拉信号，第八开关管的输入端接收高电平信号，第八开关管的输出端输出第二输出控制信号；第三电容一端与第七开关管和第八开关管的控制端连接，另一端接收高电平信号。
其中，电路进一步包括第九开关管，第九开关管的控制端接收低电平信号，第九开关管的输入端连接第二开关管的输出端，第九开关管的输出端连接第三开关管的控制端。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种显示装置，该显示装置包括TFT基板，TFT基板包括GOA驱动电路，其中，GOA驱动电路包括多级驱动单元，每一驱动单元包括：输入模块，用于接收触控控制信号、低电平信号、高电平信号和上一级的输出信号，并根据接收到的信号输出第一控制信号，其中，第一级驱动单元的输入模块接收的是触控控制信号、低电平信号、高电平信号和预设的初始信号；输出模块，用于接收第一控制信号和第一时钟信号，并根据第一控制信号和第一时钟信号输出第一输出控制信号；下拉模块，用于接收第一控制信号、第二时钟信号和低电平信号，并根据第一控制信号、第二时钟信号和低电平信号输出下拉信号，其中，第二时钟信号和第一时钟信号反向；下拉维持模块，用于接收下拉信号、高电平信号和第一时钟信号，并根据下拉信号、高电平信号和第一时钟信号输出第二输出控制信号，其中第一输出控制信号和第二输出控制信号共同作用来获得输出信号。
其中，输入模块包括第一开关管、第二开关管和第一电容，其中：第一开关管的控制端接收上一级的输出信号，第一开开关管的输入端接收低电平信号，第一开关管的输出端连接第二开关管的输入端，其中，第一级驱动单元的第一开关管的控制端接收预设的初始信号；第二开关管的控制端接收触控控制信号，第二开关管的输入端连接第一开关管的输出端，第二开关管的输出端输出第一控制信号；第一电容的一端接收高电平信号，另一端连接第二开关管的输入端。
其中，输出模块包括第三开关管和第二电容，其中：第三开关管的控制端连接第二开关管的输出端，以接收第一控制信号，第三开关管的输入端接收第一时钟信号，第三开关管的输出端输出第一输出控制信号；第二电容的两端分别连接第三开关管的控制端和输出端。
其中，下拉信号包括第一下拉信号和第二下拉信号，下拉模块包括第四开关管和第五开关管，其中：第四开关管的控制端连接第二开关管的输出端，以接收第一控制信号，第四开关管的输入端接收第二时钟信号，第四开关管的输出端输出第一下拉信号；第五开关管的控制端接收第二时钟信号，第五开关管的输入端接收低电平信号，第五开关管的输出端输出第二下拉信号。
其中，下拉维持模块包括第六开关管、第七开关管、第八开关管和第三电容，其中：第六开关管的控制端接收第一时钟信号，第六开关管的输入端连接第七开关管的输出端，第六开关管的输出端连接第三开关管的控制端；第七开关管的控制端分别连接第四开关管和第五开关管的输出端，以接收下拉信号，第七开关管的输入端接收高电平信号，第七开关管的输出端连接第六开关管的输入端；第八开关管的控制端分别连接第四开关管和第五开关管的输出端，以接收下拉信号，第八开关管的输入端接收高电平信号，第八开关管的输出端输出第二输出控制信号；第三电容一端与第七开关管和第八开关管的控制端连接，另一端接收高电平信号。
其中，电路进一步包括第九开关管，第九开关管的控制端接收低电平信号，第九开关管的输入端连接第二开关管的输出端，第九开关管的输出端连接第三开关管的控制端。
本发明的有益效果是：区别于现有技术的情况，本发明提供一种GOA驱动电路，其中，GOA驱动电路包括多级驱动单元，每一驱动单元包括输入模块、输出模块、下拉模块以及下拉维持模块。其中，输入模块用于接收触控控制信号、低电平信号、高电平信号和上一级的输出信号，并根据接收到的信号输出第一控制信号，其中，第一级驱动单元的输入模块接收的是触控控制信号、低电平信号、高电平信号和预设的初始信号。输出模块用于接收第一控制信号和第一时钟信号，并根据第一控制信号和第一时钟信号输出第一输出控制信号。下拉模块用于接收第一控制信号、第二时钟信号和低电平信号，并根据第一控制信号、第二时钟信号和低电平信号输出下拉信号，其中，第二时钟信号和第一时钟信号反向。下拉维持模块用于接收下拉信号、高电平信号和第一时钟信号，并根据下拉信号、高电平信号和第一时钟信号输出第二输出控制信号，其中第一输出控制信号和第二输出控制信号共同作用来获得输出信号。因此，本发明的GOA驱动电路能够根据触控控制信号来进行暂停和级传，进而实现高频TP驱动，进一步的，本发明通过上述的几个简单的模块来实现GOA驱动电路，可以最大限度的节约IC成本。
【附图说明】
图1是本发明实施例提供的一种GOA驱动电路的结构示意图；
图2是本发明实施例提供的一种GOA驱动电路的第n级驱动单元的电路示意图；
图3是GOA驱动电路工作时各信号的时序图；
图4是本发明实施例提供的另一种GOA驱动电路的结构示意图；
图5是本发明实施例提供的一种显示装置的结构示意图。
【具体实施方式】
请参阅图1，图1是本发明实施例提供的一种GOA驱动电路的结构示意图。如图1所示，本发明实施例的GOA驱动电路10包括多级驱动单元11。其中，每一级驱动单元11都接收触控控制信号TC、低电平信号VGL、高电平信号VGH、上一级的输出信号Gn-1、第一时钟信号CK以及第二时钟信号XCK。其中，如图1所示，第一级驱动单元11接收的上一级的输出信号替换为预设的初始信号STV。因此，本实施例的GOA驱动电路10可以根据触控控制信号TC来进行暂停和级传，进而实现高频TP驱动，进一步的，还能够在最大限度的节约IC成本。
由于每一级的GOA驱动单元11的结构都相同，因此以下将以其中一级GOA驱动单元为例进行介绍。
请参阅图2，图2是本发明实施例提供的一种GOA驱动电路的第n级驱动单元的电路示意图。如图2所示，驱动单元10包括输入模块110、输出模块111、下拉模块112以及下拉维持模块113。
其中，输入模块110用于接收触控控制信号TC、低电平信号VGL、高电平信号VGH和上一级的输出信号Gn-1，并根据接收到的信号输出第一控制信号K1。其中，第一控制信号K1输出到第一节点Qn，第一节点Qn为用于控制驱动信号输出的点。其中，第一级驱动单元11的输入模块110接收的是触控控制信号TC、低电平信号VGL、高电平信号VGH和预设的初始信号STV。
输出模块111用于接收第一控制信号K1和第一时钟信号CK，并根据第一控制信号K1和第一时钟信号CK输出第一输出控制信号O1。
下拉模块112用于接收第一控制信号K1、第二时钟信号XCK和低电平信号VGL，并根据第一控制信号K1、第二时钟信号XCK和低电平信号VGL输出下拉信号L1。其中，下拉信号L1输出到第二节点Pn，第二节点Pn为用于控制在电路非作用期间保持电路稳定输出的点。其中，第二时钟信号XCK和第一时钟信号CK反向。
下拉维持模块113用于接收下拉信号L1、高电平信号VGH和第一时钟信号CK，并根据下拉信号L1、高电平信号VGH和第一时钟信号CK输出第二输出控制信号O2，其中第一输出控制信号O1和第二输出控制信号O2共同作用来获得输出信号Gn。
可选的，输入模块110包括第一开关管T1、第二开关管T2和第一电容C1。其中，第一开关管T1的控制端接收上一级的输出信号Gn-1，第一开开关管T1的输入端接收低电平信号VGL，第一开关管T1的输出端连接第二开关管T2的输入端，其中，第一级驱动单元的第一开关管T1的控制端接收预设的初始信号STV。第二开关管T2的控制端接收触控控制信号TC，第二开关管T2的输入端连接第一开关管T1的输出端，第二开关管T2的输出端输出第一控制信号K1，具体的，第二开关管T2的输出端连接在第一节点Qn，以向第一节点Qn输出第一控制信号K1。第一电容C1的一端接收高电平信号VGH，另一端连接第二开关管T2的输入端，即另一端连接在第二开关管T2的输入端和第一开关管T1的输出端之间。第一电容C1用于稳定第二开关管T2的输入端上的电压。
输出模块111包括第三开关管T3和第二电容C2。其中，第三开关管T3的控制端连接第二开关管T2的输出端，以接收第一控制信号K1，具体的，第三开关管T3的控制端连接第一节点Qn，以通过第一节点Qn接收第二开关管T2输出的第一控制信号K1。第三开关管T3的输入端接收第一时钟信号CK，第三开关管T3的输出端输出第一输出控制信号O1。第二电容C2的两端分别连接第三开关管T3的控制端和输出端，也就是说，第二电容C2的一端和第三开关管T3的控制端均连接第一节点Qn。
本实施例中，下拉信号L1包括第一下拉信号L11和第二下拉信号L12，下拉模块112包括第四开关管T4和第五开关管T5。其中，第四开关管T4的控制端连接第二开关管T2的输出端，以接收第一控制信号K1，具体的，第四开关管T4的控制端和第二开关管T2的输出端均连接第一节点Qn，第四开关管T4的输入端接收第二时钟信号XCK，第四开关管T4的输出端输出第一下拉信号L11，具体的，第四开关管T4的输出端连接到第二节点Pn，以向第二节点Pn输出第一下拉信号L11。第五开关管T5的控制端接收第二时钟信号XCK，第五开关管T5的输入端接收低电平信号VGL，第五开关管T5的输出端输出第二下拉信号L12，具体的，第五开关管T5的输出端连接到第二节点Pn，以向第二节点Pn输出第二下拉信号L12。
下拉维持模块113包括第六开关管T6、第七开关管T7、第八开关管T8和第三电容C3。其中，第六开关管T6的控制端接收第一时钟信号CK，第六开关管T6的输入端连接第七开关管T7的输出端，第六开关管T6的输出端连接到第一节点Qn，以通过第一节点Qn连接第三开关管T3的控制端。第七开关管T7的控制端通过第二节点Pn分别连接第四开关管T4和第五开关管T5的输出端，以接收下拉信号L1，第七开关管T7的输入端接收高电平信号VGH，第七开关管T7的输出端连接第六开关管T6的输入端。第八开关管T8的控制端通过第二节点Pn分别连接第四开关管T4和第五开关管T5的输出端，以接收下拉信号L1，第八开关管T8的输入端接收高电平信号VGH，第八开关管T8的输出端输出第二输出控制信号O2。第三电容C3一端与第七开关管T7和第八开关管T8的控制端连接，另一端接收高电平信号VGH。
其中，第一开关管T1至第八开关管T8均为P型开关管，其控制端为P型开关管的栅极，输入端为P型开关管的源极，输出端为P型开关管的漏极。
请一并参阅图3，图3是本发明的GOA驱动电路工作时各信号的时序图。结合图2和图3所示，本发明的GOA驱动电路包括显示驱动时间和TP作用时间，其中，显示驱动时间包括四个阶段，具体如下文所述：
第一阶段：第一开关管T1和第二开关管T2打开，低电平信号VGL作为第一控制信号K1拉低第一节点Qn到低电位。第三开关管T3和第四开关管T4的控制端为低电位，因此，第三开关管T3和第四开关管T4均打开。此时，第二时钟信号XCK为低电位，第五开关管T5打开，使得第一下拉信号L11和第二下拉信号L12都为低电位，进而输出的下拉信号L1为低电位，拉低第二节点Pn为低电位，使得第七开关管T7和第八开关管T8均打开。此外，与第二时钟信号XCK反向的第一时钟信号CK此时为高电位，使得第六开关管T6关闭。第三开关管T3输出高电位的第一输出控制信号O1，第八开关管T8同样输出高电位的第一输出控制信号O2，使得输出信号Gn为高电位。
第二阶段：第一阶段时第二电容C2进行了充电，并且与第一节点Qn连接的一端为低电位，因此此时第一节点Qn仍然为低电位，即第二电容C2使得第一控制信号K1保持低电位，使得第三开关管T3打开。此时，第一时钟信号CK为低电位，因此输出信号Gn为低电位，这一方面可以驱动TFT（Thin Film Transistor，是薄膜晶体管）基板的显示区（AA区）的像素单元，另一方面可以作为级传讯号传递到下一级驱动单元中。
此外，由于第一控制信号K1为低电位，则第四开关管T4打开。此时第二时钟信号XCK为高电位，使得第一下拉信号L11为高电位，第五开关管T5关闭，因此下拉信号L1为高电位，即第二节点Pn变为高电位，使得第七开关管T7和第八开关管T8关闭，第二输出控制信号O2消失了，第二节点Q点通过第二电容C2耦合到更低电位，使得第一控制信号K1变为更低电位，以保证输出信号Gn正常输出。
第三阶段：由于第二电容C2的作用，此时第一节点Qn仍然为低电位，即第二电容C2使得第一控制信号K1保持低电位，则第三开关管T3和第四开关管T4打开。此阶段第一时钟信号CK为高电位，第二时钟信号XCK变为低电位，使得第三开关管T3输出的第一输出控制信号O1为高电位，第一下拉信号L11为低电位，第五开关管T5打开，第二下拉信号L12也为低电位，因此下拉信号L1为低电位，即第二节点Pn变为低电位，第七开关管T7和第八开关管T8打开，输出的第二输出控制信号O2为高电位，与同为高电位的第一输出控制信号O1作用使得输出信号Gn为高电位。
第四阶段：第一时钟信号CK为低电位，第六开关管T6打开，由于第三电容C3的作用，保证了第七开关管T7此时打开，因此第一节点Qn的第一控制信号K1瞬间被拉高，使得第三开关管T3和第四开关管T4关闭，在一帧其后的过程中第一节点Qn的第一控制信号K1和第二节点Pn的下拉信号L1一直分别保持在高电位和低电位。
当GOA驱动电路10在TP作用时间时，触控控制信号TC变为高电位，使得第二开关管T2关闭，级传讯号暂存在第一电容C1上，而当TP作用时间结束后，触控控制信号TC变为低电位，第二开关管T2打开，暂存在第一电容C1上的低电位作为第一控制信号K1向第一节点Qn充电，使得第一节点Qn变低，第三开关管T3打开，随后按前文所述的过程继续级传。
请参阅图4，图4是本发明实施例提供的另一种GOA驱动电路的结构示意图。如图4所示，本实施例的GOA驱动电路与前文所述的GOA驱动电路不同之处在于：本实施例的GOA驱动电路还进一步包括第九开关管T9，第九开关管T9的控制端接收低电平信号VGL，第九开关管T9的输入端连接第二开关管T2的输出端，第九开关管T9的输出端连接第三开关管T3的控制端。第九开关管T9的作用是在第一节点Qn的第一控制信号K1被耦合到更低电位时，第九开关管T9关闭，减小第一节点Qn的第一控制信号K1的电位受外界影响。
请进一步参阅图5，图5是本发明显示装置的示意图。在本实施例中，显示装置40包括TFT基板1和位于TFT基板1一侧的GOA驱动电路2，其中该GOA驱动电路2为前文所述的GOA驱动电路10。
综上所述，本发明的GOA驱动电路可以通过触控控制信号TC实现暂停和级传，适用于高频TP驱动。另外，本发明的GOA驱动电路只需通过9个开关管和三个电容即可形成，能够在最大限度的节约IC成本。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA驱动电路，其中，所述GOA驱动电路包括多级驱动单元，其中，所述每一驱动单元包括：
    输入模块，用于接收触控控制信号、低电平信号、高电平信号和上一级的输出信号，并根据接收到的信号输出第一控制信号，其中，第一级驱动单元的输入模块接收的是触控控制信号、低电平信号、高电平信号和预设的初始信号；
    输出模块，用于接收所述第一控制信号和第一时钟信号，并根据所述第一控制信号和所述第一时钟信号输出第一输出控制信号；
    下拉模块，用于接收所述第一控制信号、第二时钟信号和低电平信号，并根据所述第一控制信号、第二时钟信号和低电平信号输出下拉信号，其中，所述第二时钟信号和所述第一时钟信号反向；
    下拉维持模块，用于接收所述下拉信号、高电平信号和第一时钟信号，并根据所述下拉信号、高电平信号和第一时钟信号输出所述第二输出控制信号，其中所述第一输出控制信号和所述第二输出控制信号共同作用来获得输出信号。
  2. 根据权利要求1所述的电路，其中，所述输入模块包括第一开关管、第二开关管和第一电容，其中：
    所述第一开关管的控制端接收所述上一级的输出信号，所述第一开开关管的输入端接收所述低电平信号，所述第一开关管的输出端连接所述第二开关管的输入端，其中，所述第一级驱动单元的第一开关管的控制端接收所述预设的初始信号；
    所述第二开关管的控制端接收所述触控控制信号，所述第二开关管的输入端连接所述第一开关管的输出端，所述第二开关管的输出端输出所述第一控制信号；
    所述第一电容的一端接收所述高电平信号，另一端连接所述第二开关管的输入端。
  3. 根据权利要求2所述的电路，其中，所述输出模块包括第三开关管和第二电容，其中：
    所述第三开关管的控制端连接所述第二开关管的输出端，以接收所述第一控制信号，所述第三开关管的输入端接收所述第一时钟信号，所述第三开关管的输出端输出所述第一输出控制信号；
    所述第二电容的两端分别连接所述第三开关管的控制端和输出端。
  4. 根据权利要求3所述的电路，其中，所述下拉信号包括第一下拉信号和第二下拉信号，所述下拉模块包括第四开关管和第五开关管，其中：
    所述第四开关管的控制端连接所述第二开关管的输出端，以接收所述第一控制信号，所述第四开关管的输入端接收所述第二时钟信号，所述第四开关管的输出端输出所述第一下拉信号；
    所述第五开关管的控制端接收所述第二时钟信号，所述第五开关管的输入端接收所述低电平信号，所述第五开关管的输出端输出所述第二下拉信号。
  5. 根据权利要求4所述的电路，其中，所述下拉维持模块包括第六开关管、第七开关管、第八开关管和第三电容，其中：
    所述第六开关管的控制端接收所述第一时钟信号，所述第六开关管的输入端连接所述第七开关管的输出端，所述第六开关管的输出端连接所述第三开关管的控制端；
    所述第七开关管的控制端分别连接所述第四开关管和所述第五开关管的输出端，以接收所述下拉信号，所述第七开关管的输入端接收所述高电平信号，第七开关管的输出端连接所述第六开关管的输入端；
    所述第八开关管的控制端分别连接所述第四开关管和所述第五开关管的输出端，以接收所述下拉信号，所述第八开关管的输入端接收所述高电平信号，所述第八开关管的输出端输出所述第二输出控制信号；
    所述第三电容一端与所述第七开关管和第八开关管的控制端连接，另一端接收所述高电平信号。
  6. 根据权利要求1所述的电路，其中，所述电路进一步包括第九开关管，所述第九开关管的控制端接收所述低电平信号，所述第九开关管的输入端连接所述第二开关管的输出端，所述第九开关管的输出端连接所述第三开关管的控制端。
  7. 根据权利要求6所述的电路，其中，所述第九开关管为P型开关管，所述控制端为P型开关管的栅极，输入端为P型开关管的源极，输出端为P型开关管的漏极。
  8. 根据权利要求5所述的电路，其中，所述第一开关管至所述第八开关管均为P型开关管，所述控制端为P型开关管的栅极，输入端为P型开关管的源极，输出端为P型开关管的漏极。
  9. 一种TFT基板，其中，所述TFT基板包括GOA驱动电路，其中，所述GOA驱动电路包括多级驱动单元，所述每一驱动单元包括：
    输入模块，用于接收触控控制信号、低电平信号、高电平信号和上一级的输出信号，并根据接收到的信号输出第一控制信号，其中，第一级驱动单元的输入模块接收的是触控控制信号、低电平信号、高电平信号和预设的初始信号；
    输出模块，用于接收所述第一控制信号和第一时钟信号，并根据所述第一控制信号和所述第一时钟信号输出第一输出控制信号；
    下拉模块，用于接收所述第一控制信号、第二时钟信号和低电平信号，并根据所述第一控制信号、第二时钟信号和低电平信号输出下拉信号，其中，所述第二时钟信号和所述第一时钟信号反向；
    下拉维持模块，用于接收所述下拉信号、高电平信号和第一时钟信号，并根据所述下拉信号、高电平信号和第一时钟信号输出所述第二输出控制信号，其中所述第一输出控制信号和所述第二输出控制信号共同作用来获得输出信号。
  10. 根据权利要求9所述的TFT基板，其中，所述输入模块包括第一开关管、第二开关管和第一电容，其中：
    所述第一开关管的控制端接收所述上一级的输出信号，所述第一开开关管的输入端接收所述低电平信号，所述第一开关管的输出端连接所述第二开关管的输入端，其中，所述第一级驱动单元的第一开关管的控制端接收所述预设的初始信号；
    所述第二开关管的控制端接收所述触控控制信号，所述第二开关管的输入端连接所述第一开关管的输出端，所述第二开关管的输出端输出所述第一控制信号；
    所述第一电容的一端接收所述高电平信号，另一端连接所述第二开关管的输入端。
  11. 根据权利要求10所述的TFT基板，其中，所述输出模块包括第三开关管和第二电容，其中：
    所述第三开关管的控制端连接所述第二开关管的输出端，以接收所述第一控制信号，所述第三开关管的输入端接收所述第一时钟信号，所述第三开关管的输出端输出所述第一输出控制信号；
    所述第二电容的两端分别连接所述第三开关管的控制端和输出端。
  12. 根据权利要求11所述的TFT基板，其中，所述下拉信号包括第一下拉信号和第二下拉信号，所述下拉模块包括第四开关管和第五开关管，其中：
    所述第四开关管的控制端连接所述第二开关管的输出端，以接收所述第一控制信号，所述第四开关管的输入端接收所述第二时钟信号，所述第四开关管的输出端输出所述第一下拉信号；
    所述第五开关管的控制端接收所述第二时钟信号，所述第五开关管的输入端接收所述低电平信号，所述第五开关管的输出端输出所述第二下拉信号。
  13. 根据权利要求12所述的TFT基板，其中，所述下拉维持模块包括第六开关管、第七开关管、第八开关管和第三电容，其中：
    所述第六开关管的控制端接收所述第一时钟信号，所述第六开关管的输入端连接所述第七开关管的输出端，所述第六开关管的输出端连接所述第三开关管的控制端；
    所述第七开关管的控制端分别连接所述第四开关管和所述第五开关管的输出端，以接收所述下拉信号，所述第七开关管的输入端接收所述高电平信号，第七开关管的输出端连接所述第六开关管的输入端；
    所述第八开关管的控制端分别连接所述第四开关管和所述第五开关管的输出端，以接收所述下拉信号，所述第八开关管的输入端接收所述高电平信号，所述第八开关管的输出端输出所述第二输出控制信号；
    所述第三电容一端与所述第七开关管和第八开关管的控制端连接，另一端接收所述高电平信号。
  14. 根据权利要求9所述的TFT基板，其中，所述电路进一步包括第九开关管，所述第九开关管的控制端接收所述低电平信号，所述第九开关管的输入端连接所述第二开关管的输出端，所述第九开关管的输出端连接所述第三开关管的控制端。
  15. 一种显示装置，其中，所述显示装置包括TFT基板，所述TFT基板包括GOA驱动电路，其中，所述GOA驱动电路包括多级驱动单元，所述每一驱动单元包括：
    输入模块，用于接收触控控制信号、低电平信号、高电平信号和上一级的输出信号，并根据接收到的信号输出第一控制信号，其中，第一级驱动单元的输入模块接收的是触控控制信号、低电平信号、高电平信号和预设的初始信号；
    输出模块，用于接收所述第一控制信号和第一时钟信号，并根据所述第一控制信号和所述第一时钟信号输出第一输出控制信号；
    下拉模块，用于接收所述第一控制信号、第二时钟信号和低电平信号，并根据所述第一控制信号、第二时钟信号和低电平信号输出下拉信号，其中，所述第二时钟信号和所述第一时钟信号反向；
    下拉维持模块，用于接收所述下拉信号、高电平信号和第一时钟信号，并根据所述下拉信号、高电平信号和第一时钟信号输出所述第二输出控制信号，其中所述第一输出控制信号和所述第二输出控制信号共同作用来获得输出信号。
  16. 根据权利要求15所述的显示装置，其中，所述输入模块包括第一开关管、第二开关管和第一电容，其中：
    所述第一开关管的控制端接收所述上一级的输出信号，所述第一开开关管的输入端接收所述低电平信号，所述第一开关管的输出端连接所述第二开关管的输入端，其中，所述第一级驱动单元的第一开关管的控制端接收所述预设的初始信号；
    所述第二开关管的控制端接收所述触控控制信号，所述第二开关管的输入端连接所述第一开关管的输出端，所述第二开关管的输出端输出所述第一控制信号；
    所述第一电容的一端接收所述高电平信号，另一端连接所述第二开关管的输入端。
  17. 根据权利要求16所述的显示装置，其中，所述输出模块包括第三开关管和第二电容，其中：
    所述第三开关管的控制端连接所述第二开关管的输出端，以接收所述第一控制信号，所述第三开关管的输入端接收所述第一时钟信号，所述第三开关管的输出端输出所述第一输出控制信号；
    所述第二电容的两端分别连接所述第三开关管的控制端和输出端。
  18. 根据权利要求17所述的显示装置，其中，所述下拉信号包括第一下拉信号和第二下拉信号，所述下拉模块包括第四开关管和第五开关管，其中：
    所述第四开关管的控制端连接所述第二开关管的输出端，以接收所述第一控制信号，所述第四开关管的输入端接收所述第二时钟信号，所述第四开关管的输出端输出所述第一下拉信号；
    所述第五开关管的控制端接收所述第二时钟信号，所述第五开关管的输入端接收所述低电平信号，所述第五开关管的输出端输出所述第二下拉信号。
  19. 根据权利要求18所述的显示装置，其中，所述下拉维持模块包括第六开关管、第七开关管、第八开关管和第三电容，其中：
    所述第六开关管的控制端接收所述第一时钟信号，所述第六开关管的输入端连接所述第七开关管的输出端，所述第六开关管的输出端连接所述第三开关管的控制端；
    所述第七开关管的控制端分别连接所述第四开关管和所述第五开关管的输出端，以接收所述下拉信号，所述第七开关管的输入端接收所述高电平信号，第七开关管的输出端连接所述第六开关管的输入端；
    所述第八开关管的控制端分别连接所述第四开关管和所述第五开关管的输出端，以接收所述下拉信号，所述第八开关管的输入端接收所述高电平信号，所述第八开关管的输出端输出所述第二输出控制信号；
    所述第三电容一端与所述第七开关管和第八开关管的控制端连接，另一端接收所述高电平信号。
  20. 根据权利要求15所述的显示装置，其中，所述电路进一步包括第九开关管，所述第九开关管的控制端接收所述低电平信号，所述第九开关管的输入端连接所述第二开关管的输出端，所述第九开关管的输出端连接所述第三开关管的控制端。
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