WO2017024892A1 - 埋入硅基板扇出型封装结构及其制造方法 - Google Patents

埋入硅基板扇出型封装结构及其制造方法 Download PDF

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WO2017024892A1
WO2017024892A1 PCT/CN2016/085925 CN2016085925W WO2017024892A1 WO 2017024892 A1 WO2017024892 A1 WO 2017024892A1 CN 2016085925 W CN2016085925 W CN 2016085925W WO 2017024892 A1 WO2017024892 A1 WO 2017024892A1
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silicon substrate
chip
groove
package structure
fan
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PCT/CN2016/085925
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English (en)
French (fr)
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于大全
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华天科技（昆山）电子有限公司
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Priority to EP16834516.3A priority Critical patent/EP3336893A4/en
Priority to JP2018507534A priority patent/JP2018523315A/ja
Priority to KR1020187005298A priority patent/KR20180037988A/ko
Publication of WO2017024892A1 publication Critical patent/WO2017024892A1/zh
Priority to US15/893,691 priority patent/US20180182727A1/en

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Definitions

  • the present invention relates to the field of semiconductor packaging technologies, and in particular, to a buried silicon substrate fan-out type package structure and a method of fabricating the same.
  • Fan-out wafer-level packaging technology complements the wafer-level chip-scale packaging technology by re-staging the chip I/O ports to form solder balls on the reconstructed encapsulant or
  • the bump terminal array can replace the traditional wire bond solder ball array (WBBGA) package or flip chip solder ball array (FCBGA) package ( ⁇ 500I/Os) package structure in a certain range, especially suitable for booming portable The field of consumer electronics.
  • the FOWLP process began to be applied in 2008, mainly in the Infineon Wireless (later Intel's wireless division) eWLB (Embedded Wafer Level BGA) technology, package foundry mainly in STATS Chip PAC, NANIUM, the main application is Intel Wireless The baseband chip package of the department.
  • eWLB embedded Wafer Level BGA
  • STATS Chip PAC STATS Chip PAC
  • NANIUM the main application is Intel Wireless The baseband chip package of the department.
  • FOWLP process technology matures, costs continue to decrease, and chip technology continues to increase (baseband chips and mobile terminal application processor chips have entered 28nm mass production), FOWLP may explode. In order to achieve cost reduction, it will be facing the big side.
  • the Panel Size Fan-out WLP (PWLP) is developed and may be implemented by using a package substrate process.
  • the standard eWLB process is as follows: first film the film on a carrier, then place the chip pad face down on the film; use the wafer-level injection molding process to embed the chip into the molding compound; cure the molding compound, remove the carrier . The wafer-level process of the die-molded plastic wafer is then performed. Passivation on the exposed side of the die pad, metal rewiring, preparation of the bottom metal layer of the bump, ball implantation, and final slicing to complete the package.
  • Patent US20080308917 and US2015003000 use a plastic sealing material such as a polymer to coat a plurality of chips, embedding the chip therein, and then performing a wafer level process.
  • the main problems of the method are as follows. First, the warpage of polymer gel discs, using silicon or glass slides can help reduce warpage, but introduces a complex process of temporary bonding and debonding. The development of new low warping mold plastics, high material costs. Secondly, for 10 ⁇ 10mm to 12 ⁇ 12mm fan-out packages, board-level reliability is very challenging, especially for temperature-cycle-related tests. For eWLB products, underfill is required after board-level connections to improve reliability. Again, the use of polymer gel discs has a large effect on the yield. Chip offset is a major process obstacle during injection molding and molding compound curing. Another important point is the choice of rewiring dielectric materials, as reconstituted wafers need to accommodate rewiring processes, and standard wafer level media cannot be directly applied.
  • Patent CN 104037133 A discloses a fan-out package structure, which is slotted on a silicon carrier board, the chip is placed on the bottom of the slot, and the chip pad is electrically routed to the surface of the silicon carrier board; the slot is filled with a molding material. , made on the surface of plastic packaging materials Redistribute the metal to electrically route the line. The structure and process are very complicated and costly.
  • the present invention provides a buried silicon substrate fan-out type package structure and a manufacturing method thereof, which use a silicon matrix instead of a molding compound as a fan-out substrate, and fully utilizes the advantages of the silicon substrate to enable fine wiring and utilization.
  • the mature silicon etching process can precisely etch holes, trenches and the like; and the heat dissipation performance is good.
  • the wafer can be removed, the bonding process can be removed, and the process difficulty can be reduced, thereby significantly reducing the cost and improving the yield.
  • a buried silicon substrate fan-out type package structure comprising a silicon substrate having a first surface and a second surface opposite thereto, the first surface being formed with at least one extending toward the second surface a groove, the side of the groove being perpendicular or nearly perpendicular to the bottom surface, wherein at least one chip is placed in the groove, a pad surface of the chip is opposite to a bottom surface of the groove, and a pad surface of the chip Adjacent to the first surface; an adhesive layer is disposed between the bottom of the chip and the bottom of the groove, and a gap is formed between a side surface of the chip and a sidewall of the groove, and the gap is filled with a first a dielectric layer; a second dielectric layer formed on the chip and the first surface; at least one metal wiring connected to a pad of the chip, and an outermost metal wiring formed on the second dielectric layer Covered with a passivation layer, and the An under bump metal layer for the solder ball is formed on the metal wiring, and the passivation layer is provided
  • the distance between the sidewall of the recess and the chip is greater than 1 micron.
  • the distance between the groove bottom of the groove and the second surface of the silicon substrate is greater than 1 micron.
  • the difference in height between the land surface of the chip and the first surface of the silicon substrate is less than 50 microns.
  • the material of the first dielectric layer is a polymer glue.
  • the materials of the first dielectric layer and the second dielectric layer are all the same polymer glue.
  • the adhesion layer has a thickness of less than 50 microns and greater than 1 micron.
  • the adhesion layer is a non-conductive polymer glue or film.
  • the metal wiring is made of copper or aluminum.
  • solder balls are copper pillar solder bumps or solder balls.
  • the under bump metal layer is Ni/Au, One of Cr/W/Cu, Ti/W/Cu/Ni/Au, Ti/Cu.
  • a method for fabricating a fan-out package structure of a buried silicon substrate comprises the following steps:
  • the second surface of the silicon substrate wafer is thinned before and after the bump preparation or soldering of the ball, and after the thinning, the bottom of the groove is to the silicon substrate.
  • the thickness between the second surfaces is greater than 1 micron.
  • the chip wafer to be packaged is thinned to a set thickness, and then the adhesive is applied to the non-pad surface of the chip wafer, and a single chip is formed after dicing, which is adhered by the pick-up tool. A glued chip is placed in the recess in the silicon substrate.
  • filling the gap between the side wall of the groove and the chip is carried out in a vacuum environment.
  • the second dielectric layer is a photolithographic material.
  • the invention has the beneficial effects that the present invention provides a buried silicon substrate fan-out type package structure and a manufacturing method thereof.
  • the silicon substrate is used as a fan-out substrate instead of the molding compound, and the advantage of the silicon substrate is utilized to make fine wiring. With the mature silicon etching process, holes, grooves, and the like can be precisely etched. By embedding the chip in a recess in the silicon substrate and fanning out part of the solder ball to the surface of the silicon substrate, the package reliability can be improved, the process is simple, and the cost is low. Due to the good heat dissipation of the silicon substrate, it is advantageous to improve the heat dissipation of the package.
  • the invention can eliminate the plastic sealing of the wafer, the debonding process, and reduce the process difficulty, thereby significantly reducing the cost and improving the yield.
  • the gap between the chip and the sidewall of the recess is filled by the polymer glue to prevent chip offset; preferably, the chip is bonded to the bottom of the groove through the adhesive layer, so that the chip can be better fixed and the chip offset can be prevented.
  • the reliability of the package can be improved by forming the first dielectric layer and the second dielectric layer by the same polymer glue.
  • 1 is a fan-out type package structure in which a chip is embedded in a recess
  • 2 is a fan-out type package structure in which two chips are embedded in one recess of the present invention
  • FIG. 3 is a fan-out type package structure in which two different chips are embedded in two recesses respectively.
  • a buried silicon substrate fan-out type package structure includes a silicon substrate 1 having a first surface 101 and a second surface 102 opposite thereto, and the first surface is formed with a groove extending toward the second surface,
  • the groove is a straight groove or a chute having a side wall and a bottom surface angle of 80 to 120 degrees, and is not limited herein.
  • the schematic view of this embodiment is a straight groove shape.
  • a chip 2 is placed in the recess, the pad side of the chip faces upward, and the pad surface of the chip is close to the first surface; the chip has adhesion to the groove bottom of the groove Layer 8, the chip is bonded to the bottom of the groove through the adhesive layer, which can better fix the chip and prevent chip offset.
  • the gap is filled with a first dielectric layer 3; the chip and the first surface are covered with an insulating second dielectric layer 4;
  • the dielectric layer is formed with at least one metal wiring 5 connected to the pad 201 of the chip, and the outermost metal wiring is covered with a passivation layer 6, and the metal wiring is formed with a solder ball.
  • a metal layer under the bump the passivation layer is provided with an opening corresponding to the underlying metal layer, wherein the opening is implanted with solder balls or bumps 7; and at least one solder ball or bump and its corresponding A sub-bump metal layer is on the first surface.
  • the distance between the sidewall of the groove and the chip is greater than 1 micrometer to facilitate the placement of the chip into the groove bottom.
  • the distance between the groove bottom of the groove and the second surface of the silicon substrate is greater than 1 micron to facilitate the support of the silicon substrate to the chip.
  • the difference in height between the pad surface of the chip and the first surface of the silicon substrate is less than 50 microns to ensure uniformity of the material of the surface of the package.
  • the material of the first dielectric layer is a polymer glue, and additional vacuum coating is applied to fill the gap of the groove with the polymer glue to fix the chip while ensuring insulation performance.
  • the materials of the first dielectric layer and the second dielectric layer are all the same polymer glue to improve the reliability of the package.
  • the adhesive layer is a non-conductive polymer glue or film, which bonds the chip and the bottom surface of the groove to ensure that the chip position does not shift in the following process, so as to obtain better alignment precision. Get finer rewiring lines.
  • the polymer glue can be prepared by coating on the back side of the chip wafer, and the film can be prepared by laminating the film on the back side of the chip wafer.
  • the metal wiring is made of copper or aluminum.
  • the solder balls are copper pillar solder bumps or solder balls.
  • the under bump metal layer is one of Ni/Au, Cr/W/Cu, Ti/W/Cu/Ni/Au, Ti/Cu, and is not shown in the figure, wherein Ni/Au means In order to form a layer of metallic nickel, a layer of metallic gold is formed on the metallic nickel.
  • Cr/W/Cu means to form three layers of metallic chromium, metallic tungsten and metallic copper, Ti/W/Cu/Ni.
  • /Au means to form a metal layer of metal titanium, metal tungsten, metal copper, metal nickel, metal gold in sequence
  • Ti/Cu means to form two metal layers of metal titanium and metal copper in sequence.
  • the method for manufacturing the buried silicon substrate fan-out package structure is implemented as follows:
  • the gap between the sidewall of the groove and the chip is filled with a colloid, and after curing, an insulating first dielectric layer is formed;
  • the coating process in step C uses polymer glue
  • the second dielectric layer and the first dielectric layer in step D are the same polymer glue to improve the reliability of the package.
  • the second surface of the silicon substrate wafer is thinned to a desired thickness before or after the bump preparation or soldering of the ball.
  • the thickness between the bottom of the groove and the second surface of the silicon substrate is greater than 1 micron.
  • the chip wafer to be packaged is thinned to a set thickness, and then the adhesive is applied to the non-pad surface of the chip wafer, and a single chip is formed after dicing, and the chip with the adhesive glue is taken by the pick-up tool. Placed in the groove on the silicon substrate.
  • the gap between the sidewall of the recess and the chip is filled
  • the colloid is implemented in a vacuum environment to reduce air bubbles and ensure a gap filling effect.
  • the second dielectric layer is a photolithographic material
  • the passivation layer is a photolithographic material.
  • the pad of the chip is exposed, and the metal wiring is connected to the pad.
  • the second embodiment includes all the technical features of the first embodiment, and the difference is that two chips 2 are embedded in one groove of the first surface of the silicon substrate, and the two chips have the same size and function. Or different. This embodiment expands the functionality of the package.
  • this embodiment 3 includes all the technical features of Embodiment 1, except that the first surface of the silicon substrate is formed with two grooves, and each of the grooves is embedded with a chip 2, which is embedded in FIG.
  • the two chips can be the same size or function. This embodiment expands the functionality of the package while reducing signal interference between the two chips.
  • the invention provides a fan-out package structure and a manufacturing method thereof for embedding a silicon substrate, and adopting a silicon substrate instead of a molding compound as a fan-out substrate, and fully utilizing the advantages of the silicon substrate, can make fine wiring.
  • a silicon substrate instead of a molding compound as a fan-out substrate, and fully utilizing the advantages of the silicon substrate, can make fine wiring.
  • holes, grooves, and the like can be precisely etched.
  • the chip is bonded and fixed to the bottom of the groove through the adhesive layer to prevent chip offset, and the I/O of the chip is fanned out to the surface of the chip and the silicon substrate by rewiring.
  • the invention can eliminate the plastic sealing of the wafer, the debonding process, and reduce the process difficulty, thereby significantly reducing the cost and improving the yield.
  • the gap between the chip and the sidewall of the recess is filled by the polymer glue to prevent chip offset; preferably, the first dielectric layer and the second dielectric layer are formed by the same polymer glue, thereby improving the reliability of the package. .

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Abstract

一种埋入硅基板扇出型封装结构及其制造方法，采用硅基体（1）取代模塑料作为扇出的基体，充分利用硅基体（1）的优势，能够制作精细布线。利用成熟的硅刻蚀工艺，可以精确刻蚀孔、槽结构。通过将芯片（2）埋入硅基体（1）上的凹槽内，将聚合物胶填充芯片（2）与凹槽侧壁之间的间隙，并把部分焊球（7）扇出到硅基体（1）表面，能够提高封装可靠性，工艺简单，降低成本。由于硅基体（1）的散热性好及具有更小的翘曲度，有利于提高封装的散热性，克服不良翘曲，获得更小的布线线宽，适于高密度封装。该封装结构可以取消圆片塑封，降低工艺难度，从而降低成本，提高成品率。

Description

埋入硅基板扇出型封装结构及其制造方法 技术领域
本发明涉及半导体封装技术领域，具体是涉及一种埋入硅基板扇出型封装结构及其制造方法。
背景技术
随着芯片变得越来越小，I/O数越来越多，芯片级封装已不能满足I/O扇出的要求。扇出型圆片级封装技术(FOWLP)是对圆片级芯片尺寸封装技术的补充，通过再构圆片的方式将芯片I/O端口引出，在重构的包封体上形成焊球或凸点终端阵列，在一定范围内可代替传统的引线键合焊球阵列(WBBGA)封装或倒装芯片焊球阵列(FCBGA)封装(<500I/Os)封装结构，特别适用于蓬勃发展的便携式消费电子领域。
FOWLP工艺在2008年就开始应用，主要是英飞凌无线(后来的英特尔的无线部门)的eWLB(Embedded Wafer Level BGA)技术，封装代工主要在STATS Chip PAC、NANIUM进行，主要应用是英特尔无线部门的基带芯片封装。随着FOWLP工艺技术逐渐成熟，成本不断降低，同时加上芯片工艺的不断提升(基带芯片和移动终端应用处理器芯片已经进入28nm量产)，FOWLP可能出现爆发性增长。为了实现成本降低将会朝着大面 板尺寸的封装工艺(Panel Size Fan-out WLP，PWLP)发展，并可能通过使用封装基板工艺实现。
标准的eWLB工艺流程如下：首先在一个载片上贴膜，然后把芯片焊盘面朝下放置于膜上；使用圆片级注塑工艺，将芯片埋入到模塑料中；固化模塑料，移除载片。之后对埋有芯片的模塑料圆片进行晶圆级工艺。在芯片焊盘暴露的一侧进行钝化、金属再布线、制备凸点底部金属层，植球，最后切片完成封装。
专利US20080308917与专利US2015003000使用聚合物等塑封材料包覆若干芯片，使芯片嵌入其中，再进行晶圆级工艺，该方法主要问题有以下几点。首先，聚合物胶圆片的翘曲问题，使用硅或者玻璃载片可以帮助减少翘曲，但带来临时键合和拆键合复杂工艺。研发新型低翘曲模塑料，材料成本高。其次，对于10×10mm到12×12mm扇出封装体，板级可靠性具有很大挑战，特别是与温度循环相关的测试，对于eWLB产品，板级连接后需要底部填充胶来提高可靠性。再次，对于使用聚合物胶圆片对产率具有很大影响。在注塑以及模塑料固化过程中芯片偏移是一个主要的工艺障碍。另一个要点是选择再布线介质材料，因为重构圆片需要适应再布线工艺制程，标准的晶圆级介质不能直接应用。
专利CN 104037133 A公开了一种扇出封装结构，该结构是在硅载板上开槽，芯片倒置于槽底，芯片焊盘电性通过线路引到硅载板表面；槽内用塑封材料填充，在塑封材料表面制作 重布线金属，将线路电性导出。该结构及制程十分复杂，成本较高。
为解决上述问题，需要开发新的扇出型方案，具有很好的工艺加工性，更好的可靠性，降低成本。
发明内容
为了解决上述技术问题，本发明提出一种埋入硅基板扇出型封装结构及其制造方法，采用硅基体取代模塑料作为扇出的基体，充分利用硅基体的优势，能够制作精细布线，利用成熟的硅刻蚀工艺，可以精确刻蚀孔、槽等结构；且散热性能好。工艺上，还可以取消圆片塑封，拆键合工艺，降低工艺难度，从而显著降低成本，提高成品率。
本发明的技术方案是这样实现的：
一种埋入硅基板扇出型封装结构，包括一硅基体，所述硅基体具有第一表面和与其相对的第二表面，所述第一表面上形成有至少一个向所述第二表面延伸的凹槽，所述凹槽侧面与底面垂直或接近垂直，所述凹槽内放置有至少一颗芯片，所述芯片的焊盘面与所述凹槽底面反向，且所述芯片的焊盘面接近所述第一表面；所述芯片底部与所述凹槽底部之间设有一层粘附层，所述芯片侧面与所述凹槽的侧壁之间具有间隙，该间隙内填充有第一介质层；所述芯片及所述第一表面上形成有第二介质层；所述第二介质层上形成有至少一层与所述芯片的焊盘连接的金属布线，最外一层金属布线上覆盖有一层钝化层，且该 金属布线上形成有用于植焊球的凸点下金属层，所述钝化层上开设有对应该凸点下金属层的开口，所述凸点下金属层上植有焊球或凸点；且至少有一个焊球或凸点及其对应的凸点下金属层位于所述硅基体的第一表面上。
作为本发明的进一步改进，所述凹槽的侧壁与所述芯片之间的距离大于1微米。
作为本发明的进一步改进，所述凹槽的槽底与所述硅基体的第二表面之间的距离大于1微米。
作为本发明的进一步改进，所述芯片的焊盘面和所述硅基体的第一表面之间的高度差小于50微米。
作为本发明的进一步改进，所述第一介质层的材料为聚合物胶。
作为本发明的进一步改进，所述第一介质层及所述第二介质层的材料均为同一种聚合物胶。
作为本发明的进一步改进，所述粘附层的厚度小于50微米，大于1微米。
作为本发明的进一步改进，所述粘附层为非导电聚合物胶或薄膜。
作为本发明的进一步改进，所述金属布线的材质为铜或铝。
作为本发明的进一步改进，所述焊球为铜柱焊料凸点或焊料球。
作为本发明的进一步改进，所述凸点下金属层为Ni/Au、 Cr/W/Cu、Ti/W/Cu/Ni/Au、Ti/Cu中的一种。
一种埋入硅基板扇出型封装结构的制作方法，包括如下步骤：
A.提供一硅基体圆片，所述硅基体圆片具有第一表面和与其相对的第二表面，在所述硅基体圆片的第一表面刻蚀形成至少一个具有设定形状和深度的凹槽；
B.在所述凹槽内放置至少一个待封装的芯片，使所述芯片的焊盘面朝上，芯片背面涂布有一定厚度的粘附胶，芯片与凹槽底部粘接并固化，形成粘附层，所述芯片的焊盘面接近所述硅基体的第一表面，且所述芯片与所述凹槽的侧壁之间具有间隙；
C.通过涂布工艺，在所述凹槽的侧壁与所述芯片之间的间隙内填充聚合物胶，固化后形成一层绝缘的第一介质层；
D.在所述芯片的焊盘面上以及所述硅基体的第一表面上，形成一层绝缘的第二介质层；
E.打开所述芯片的焊盘上面的第二介质层，并在第二介质层上面制作连接芯片的焊盘的金属布线；
F.在所述金属布线上面制作一层钝化层，在该金属布线上需要植焊球的位置打开钝化层，在露出的金属布线上制备所需的凸点下金属层，然后进行凸点制备或植焊球，最后切片，形成一埋入硅基板扇出型封装结构。
作为本发明的进一步改进，在凸点制备或植焊球前后，将所述硅基体圆片的第二表面减薄，减薄后，凹槽底部到硅基体 的第二表面之间的厚度大于1微米。
作为本发明的进一步改进，将待封装的芯片圆片减薄至设定厚度，然后在芯片圆片的非焊盘面刷粘附胶，划片后形成单颗芯片，通过拾取工具将带有粘附胶的芯片放置于所述硅基体上凹槽内。
作为本发明的进一步改进，在所述凹槽的侧壁与所述芯片之间的空隙内填充聚合物胶在真空环境下实施。
作为本发明的进一步改进，所述第二介质层为可光刻材料。
本发明的有益效果是：本发明提供一种埋入硅基板扇出型封装结构及其制造方法，采用硅基体取代模塑料作为扇出的基体，充分利用硅基体的优势，能够制作精细布线。利用成熟的硅刻蚀工艺，可以精确刻蚀孔、槽等结构。通过将芯片埋入硅基体上的凹槽内，并把部分焊球扇出到硅基体表面，能够提高封装可靠性，工艺简单，成本低。由于硅基体的散热性好，有利于提高封装的散热性。由于硅基体圆片具有更小的翘曲，可以获得更小的布线线宽，适于高密度封装。工艺上，本发明可以取消圆片塑封，拆键合工艺，降低工艺难度，从而显著降低成本，提高成品率。通过聚合物胶填充芯片与凹槽侧壁之间的间隙，防止芯片偏移；较佳的，芯片通过粘附层与凹槽底部黏结，可以更好的固定芯片，防止芯片偏移。较佳的，通过同一种聚合物胶形成第一介质层及第二介质层，可以提高封装体的可靠性。
附图说明
图1为本发明一个芯片埋入一个凹槽的扇出型封装结构；
图2为本发明两个芯片埋入一个凹槽的扇出型封装结构；
图3为本发明两个不同芯片分别埋入两个凹槽的扇出型封装结构。
结合附图，作以下说明：
1——硅基体            101——第一表面
102——第二表面        2——芯片
201——焊盘            3——第一介质层
4——第二介质层        5——金属布线
6——钝化层            7——焊球或凸点
8——粘附层
具体实施方式
为了能够更清楚地理解本发明的技术内容，特举以下实施例详细说明，其目的仅在于更好理解本发明的内容而非限制本发明的保护范围。实施例附图的结构中各组成部分未按正常比例缩放，故不代表实施例中各结构的实际相对大小。
实施例1
如图1所示，一种埋入硅基板扇出型封装结构，包括一硅基体1，所述硅基体具有第一表面101和与其相对的第二表面102，所述第一表面上形成有一个向所述第二表面延伸的凹槽， 该凹槽最好为直槽或侧壁与底面角度在80度～120度的斜槽，这里不做限制。本实施例示意图为直槽形状。所述凹槽内放置有一颗芯片2，所述芯片的焊盘面朝上，且所述芯片的焊盘面接近所述第一表面；所述芯片与所述凹槽的槽底之间具有粘附层8，芯片通过粘附层与凹槽底部黏结，可以更好的固定芯片，防止芯片偏移。
所述芯片与所述凹槽的侧壁之间具有间隙，该间隙内填充有第一介质层3；所述芯片及所述第一表面上铺设有绝缘的第二介质层4；所述第二介质层上形成有至少一层与所述芯片的焊盘201连接的金属布线5，最外一层金属布线上覆盖有一层钝化层6，且该金属布线上形成有用于植焊球的凸点下金属层，所述钝化层上开设有对应该凸点下金属层的开口，所述开口内植有焊球或凸点7；且至少有一个焊球或凸点及其对应的凸点下金属层位于所述第一表面上。
优选的，所述凹槽的侧壁与所述芯片之间的距离大于1微米，以方便芯片放入凹槽槽底。
优选的，所述凹槽的槽底与所述硅基体的第二表面之间的距离大于1微米，以利于硅基体对芯片的支撑。
优选的，所述芯片的焊盘面和所述硅基体的第一表面之间的高度差小于50微米，以保证封装体表面材料的均一性。
优选的，所述第一介质层的材料为聚合物胶，附加真空涂布，使凹槽间隙内填充满该聚合物胶，以固定芯片，同时保证绝缘性能。
优选的，所述第一介质层及所述第二介质层的材料均为同一种聚合物胶，以提高封装体的可靠性。
优选的，所述粘附层为非导电聚合物胶或薄膜，粘接芯片与凹槽底面，保证在接下来的工艺中，芯片位置不发生偏移，以便于获得较好的对准精度，获得更细的再布线线条。聚合物胶可以通过在芯片晶圆背面涂布方式制备，薄膜可以通过在芯片晶圆背面压膜方式制备。
优选的，所述金属布线的材质为铜或铝。
优选的，所述焊球为铜柱焊料凸点或焊料球。
优选的，所述凸点下金属层为Ni/Au、Cr/W/Cu、Ti/W/Cu/Ni/Au、Ti/Cu中的一种，图示未画出，其中Ni/Au意为先形成一层金属镍，再在金属镍上形成一层金属金，同理Cr/W/Cu意为依次形成金属铬、金属钨、金属铜三层金属层，Ti/W/Cu/Ni/Au意为依次形成金属钛、金属钨、金属铜、金属镍、金属金五层金属层，Ti/Cu意为依次形成金属钛、金属铜两层金属层。
作为一种优选实施例，该埋入硅基板扇出型封装结构的制造方法按如下步骤实施：
A.提供一硅基体圆片，所述硅基体圆片具有第一表面和与其相对的第二表面，在所述硅基体圆片的第一表面刻蚀形成至少一个具有设定形状和深度的凹槽；
B.在所述凹槽内放置至少一个待封装的芯片，使所述芯片的焊盘面朝上，芯片背面涂布有一定厚度的粘附胶，芯片与 凹槽底部粘接并固化，形成粘附层，所述芯片的焊盘面接近所述硅基体的第一表面，且所述芯片与所述凹槽的侧壁之间具有间隙；
C.通过涂布工艺，在所述凹槽的侧壁与所述芯片之间的间隙内填充胶体，固化后形成一层绝缘的第一介质层；
D.在所述芯片的焊盘面上以及所述硅基体的第一表面上，形成一层绝缘的第二介质层；
E.打开所述芯片的焊盘上面的第二介质层，并在第二介质层上面制作连接芯片的焊盘的金属布线；
F.在所述金属布线上面制作一层钝化层，在该金属布线上需要植焊球的位置打开钝化层，在露出的金属布线上制备所需的凸点下金属层，然后进行凸点制备或植焊球，最后切片，形成一埋入硅基板扇出型封装结构。
较佳的，步骤C中涂布工艺采用聚合物胶，步骤D中第二介质层与第一介质层为同一种聚合物胶，以提高封装体的可靠性。
优选的，在凸点制备或植焊球前后，将硅基体圆片的第二表面减薄到所需厚度。较佳的，减薄后，凹槽底部到硅基体的第二表面之间的厚度大于1微米。
优选的，将待封装的芯片圆片减薄至设定厚度，然后在芯片圆片的非焊盘面刷粘附胶，划片后形成单颗芯片，通过拾取工具将带有粘附胶的芯片放置于所述硅基体上凹槽内。
优选的，在所述凹槽的侧壁与所述芯片之间的空隙内填充 胶体在真空环境下实施，可以减少气泡，确保间隙填充效果。
优选的，所述第二介质层为可光刻材料，钝化层为可光刻材料。以便使用光刻制程形成开口，暴露出芯片的焊盘，使金属布线连接焊盘。
实施例2
如图2所示，本实施例2包含实施例1的所有技术特征，其区别在于，硅基体的第一表面的一个凹槽内埋入有两颗芯片2，两颗芯片大小、功能可以相同或相异。该实施例可扩展封装体的功能。
实施例3
如图3所示，本实施例3包含实施例1的所有技术特征，其区别在于，硅基体的第一表面形成有两个凹槽，每个凹槽内分别埋入一颗芯片2，这两颗芯片大小、功能可以相同或相异。该实施例可扩展封装体的功能，同时降低两芯片之间的信号干扰。
本发明提供一种埋入硅基板扇出型封装结构及其制造方法，采用硅基体取代模塑料作为扇出的基体，充分利用硅基体的优势，能够制作精细布线。利用成熟的硅刻蚀工艺，可以精确刻蚀孔、槽等结构。通过将芯片埋入硅基体上的凹槽内，芯片通过粘附层与凹槽底部黏结固定，防止芯片偏移，通过再布线把芯片的I/O扇出到芯片和硅基体的表面，能够提高封装可 靠性，工艺简单，成本低。由于硅基体的散热性好，有利于提高封装的散热性。由于硅基体圆片具有更小的翘曲，可以获得更小的布线线宽，适于高密度封装。工艺上，本发明可以取消圆片塑封，拆键合工艺，降低工艺难度，从而显著降低成本，提高成品率。通过聚合物胶填充芯片与凹槽侧壁之间的间隙，可防止芯片偏移；较佳的，通过同一种聚合物胶形成第一介质层及第二介质层，可以提高封装体的可靠性。
以上实施例是参照附图，对本发明的优选实施例进行详细说明。本领域的技术人员通过对上述实施例进行各种形式上的修改或变更，但不背离本发明的实质的情况下，都落在本发明的保护范围之内。

Claims (16)

  1. 一种埋入硅基板扇出型封装结构，其特征在于：包括一硅基体(1)，所述硅基体具有第一表面(101)和与其相对的第二表面(102)，所述第一表面上形成有至少一个向所述第二表面延伸的凹槽，所述凹槽侧面与底面垂直或接近垂直，所述凹槽内放置有至少一颗芯片(2)，所述芯片的焊盘面与所述凹槽底面反向，且所述芯片的焊盘面接近所述第一表面；所述芯片底部与所述凹槽底部之间设有一层粘附层(8)，所述芯片侧面与所述凹槽的侧壁之间具有间隙，该间隙内填充有第一介质层(3)；所述芯片及所述第一表面上形成有第二介质层(4)；所述第二介质层上形成有至少一层与所述芯片的焊盘(201)连接的金属布线(5)，最外一层金属布线上覆盖有一层钝化层(6)，且该金属布线上形成有用于植焊球的凸点下金属层，所述钝化层上开设有对应该凸点下金属层的开口，所述凸点下金属层上植有焊球或凸点(7)；且至少有一个焊球或凸点及其对应的凸点下金属层位于所述硅基体的第一表面上。
  2. 根据权利要求1所述的埋入硅基板扇出型封装结构，其特征在于：所述凹槽的侧壁与所述芯片之间的距离大于1微米。
  3. 根据权利要求1所述的埋入硅基板扇出型封装结构，其特征在于：所述凹槽的槽底与所述硅基体的第二表面之间的距离大于1微米。
  4. 根据权利要求1所述的埋入硅基板扇出型封装结构，其特征在于：所述芯片的焊盘面和所述硅基体的第一表面之间的高度差小于50微米。
  5. 根据权利要求1所述的埋入硅基板扇出型封装结构，其特征在于：所述第一介质层的材料为聚合物胶。
  6. 根据权利要求1所述的埋入硅基板扇出型封装结构，其特征在于：所述第一介质层及所述第二介质层的材料均为同一种聚合物胶。
  7. 根据权利要求1所述的埋入硅基板扇出型封装结构，其特征在于：所述粘附层(8)的厚度小于50微米，大于1微米。
  8. 根据权利要求1所述的埋入硅基板扇出型封装结构，其特征在于：所述粘附层为非导电聚合物胶或薄膜。
  9. 根据权利要求1所述的一种埋入硅基板扇出型封装结构，其特征在于：所述金属布线的材质为铜或铝。
  10. 根据权利要求1所述的一种埋入硅基板扇出型封装结构，其特征在于：所述焊球为铜柱焊料凸点或焊料球。
  11. 根据权利要求1所述的一种埋入硅基板扇出型封装结构，其特征在于：所述凸点下金属层为Ni/Au、Cr/W/Cu、Ti/W/Cu/Ni/Au、Ti/Cu中的一种。
  12. 一种埋入硅基板扇出型封装结构的制作方法，其特征在于，包括如下步骤：
    A.提供一硅基体圆片，所述硅基体圆片具有第一表面和 与其相对的第二表面，在所述硅基体圆片的第一表面刻蚀形成至少一个具有设定形状和深度的凹槽；
    B.在所述凹槽内放置至少一个待封装的芯片，使所述芯片的焊盘面朝上，芯片背面涂布有一定厚度的粘附胶，芯片与凹槽底部粘接并固化，形成粘附层，所述芯片的焊盘面接近所述硅基体的第一表面，且所述芯片与所述凹槽的侧壁之间具有间隙；
    C.通过涂布工艺，在所述凹槽的侧壁与所述芯片之间的间隙内填充聚合物胶，固化后形成一层绝缘的第一介质层；
    D.在所述芯片的焊盘面上以及所述硅基体的第一表面上，形成一层绝缘的第二介质层；
    E.打开所述芯片的焊盘上面的第二介质层，并在第二介质层上面制作连接芯片的焊盘的金属布线；
    F.在所述金属布线上面制作一层钝化层，在该金属布线上需要植焊球的位置打开钝化层，在露出的金属布线上制备所需的凸点下金属层，然后进行凸点制备或植焊球，最后切片，形成一埋入硅基板扇出型封装结构。
  13. 根据权利要求12所述的埋入硅基板扇出型封装结构的制作方法，其特征在于，在凸点制备或植焊球前后，将所述硅基体圆片的第二表面减薄，减薄后，凹槽底部到硅基体的第二表面之间的厚度大于1微米。
  14. 根据权利要求12所述的埋入硅基板扇出型封装结构的制作方法，其特征在于，将待封装的芯片圆片减薄至设定厚 度，然后在芯片圆片的非焊盘面刷粘附胶，划片后形成单颗芯片，通过拾取工具将带有粘附胶的芯片放置于所述硅基体上凹槽内。
  15. 根据权利要求12所述的埋入硅基板扇出型封装结构的制作方法，其特征在于，在所述凹槽的侧壁与所述芯片之间的空隙内填充聚合物胶在真空环境下实施。
  16. 根据权利要求12所述的埋入硅基板扇出型封装结构的制作方法，其特征在于，所述第二介质层为可光刻材料。
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