WO2016208081A1 - 電子装置 - Google Patents
電子装置 Download PDFInfo
- Publication number
- WO2016208081A1 WO2016208081A1 PCT/JP2015/068574 JP2015068574W WO2016208081A1 WO 2016208081 A1 WO2016208081 A1 WO 2016208081A1 JP 2015068574 W JP2015068574 W JP 2015068574W WO 2016208081 A1 WO2016208081 A1 WO 2016208081A1
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- WIPO (PCT)
- Prior art keywords
- power supply
- supply line
- chip
- wiring
- wiring board
- Prior art date
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Definitions
- the present invention relates to, for example, a semiconductor device in which a plurality of semiconductor chips are mounted side by side on a wiring board, and an electronic device in which the semiconductor device is mounted.
- Patent Document 1 JP-A-2006-237385 (Patent Document 1) and JP-A-2007-213375 (Patent Document 2), a plurality of memory chips and a data processing chip for controlling the plurality of memory chips are wired A semiconductor device mounted side by side on a substrate is described.
- Patent Document 3 discloses a semiconductor in which ground pins and power pins among a plurality of pins (terminals) of a wiring board are continuously arranged from the inside to the outside. An apparatus is described.
- a semiconductor device in which a plurality of semiconductor chips are arranged side by side on a wiring board, and the plurality of semiconductor chips are electrically connected via the wiring board.
- a technique for increasing the amount of data that can be processed by the semiconductor device is required.
- An electronic device includes a first wiring board and a semiconductor device mounted on the first wiring board.
- the semiconductor device includes a second wiring board having a plurality of terminals, a plurality of first semiconductor chips mounted on the second wiring board, and a second semiconductor chip mounted on the second wiring board.
- the first wiring board includes a first power supply line and a second power supply line for supplying a plurality of different power supply potentials to the second semiconductor chip.
- the second power supply line is disposed so as to straddle the first substrate side of the second wiring substrate and the first chip side of the second semiconductor chip.
- the first power supply line extends between the second power supply line and a part of the plurality of first semiconductor chips toward a region overlapping with the second semiconductor chip. Placed in.
- the area of the first power supply line that overlaps with the second power supply line in the thickness direction is smaller than the area of the first power supply line that does not overlap with the second power supply line. is there.
- the performance of an electronic device equipped with a semiconductor device in which a plurality of semiconductor chips are electrically connected to each other via a wiring board can be improved.
- FIG. 1 is an enlarged plan view illustrating a configuration example of an electronic device including a semiconductor device according to an embodiment.
- FIG. 2 is an explanatory diagram illustrating an electrical connection relationship of components included in the electronic device in a cross section taken along line AA in FIG. 1.
- FIG. 2 is an enlarged plan view showing an example of a wiring layout in a plan view of the motherboard shown in FIG. 1.
- FIG. 2 is an enlarged plan view showing an example of a terminal layout in a plan view of the motherboard shown in FIG. 1. It is an expanded sectional view which expands and shows the periphery of the some terminal shown in FIG. FIG.
- FIG. 2 is an explanatory diagram illustrating an outline of a configuration of a plurality of transmission paths that are electrically connected to a plurality of semiconductor chips included in the semiconductor device illustrated in FIG. 1.
- FIG. 2 is a cross-sectional view taken along line BB of the semiconductor device shown in FIG.
- FIG. 2 is a plan view showing a structure on the lower surface side of the semiconductor device shown in FIG. 1. It is a top view of the surface side of the logic chip shown in FIG.
- FIG. 2 is a plan view of the surface side of the memory chip shown in FIG. 1.
- FIG. 5 is an enlarged plan view showing a part of a wiring layer in which a power supply line is formed in the wiring board shown in FIG. 4.
- FIG. 9 is an enlarged plan view showing the terminal array on the lower surface side of the wiring board shown in FIG. 8 and the power supply line shown in FIG. It is an enlarged plan view which shows the modification with respect to FIG.
- FIG. 14 is an enlarged plan view showing an example of a terminal layout in a plan view of the motherboard shown in FIG. 13.
- FIG. 12 is an enlarged plan view showing a positional relationship between an extending direction of a power supply line and a through-hole wiring in a wiring board included in an electronic device according to a modified example with respect to FIG.
- FIG. 8 is a plan view showing a layout example of conductor planes provided in one wiring layer included in the wiring board shown in FIG. 7.
- FIG. 7 is an enlarged cross-sectional view schematically showing a configuration of a path for supplying a power supply potential to an analog circuit included in the semiconductor device shown in FIG. 6. It is an expanded sectional view which shows the example of examination with respect to FIG.
- FIG. 19 is an explanatory diagram showing an outline of a manufacturing process of the semiconductor device described with reference to FIGS. 1 to 18; It is a top view which shows the chip mounting surface side of the wiring board prepared by the wiring board preparation process shown in FIG.
- FIG. 21 is a plan view showing a state in which a plurality of semiconductor chips are mounted on the wiring board shown in FIG. 20. It is a top view which shows the electronic device by which the semiconductor device which is a modification with respect to FIG. 1 is mounted.
- FIG. 19 is an explanatory diagram showing an outline of a manufacturing process of the semiconductor device described with reference to FIGS. 1 to 18; It is a top view which shows the chip mounting surface side of the wiring board prepared by the wiring board preparation process shown in FIG.
- FIG. 23 is an enlarged plan view showing an example of a wiring layout in a plan view of the motherboard shown in FIG. 22. It is an expanded sectional view which shows the structural example of the electronic device which is a modification with respect to FIG. It is explanatory drawing which shows the modification of the manufacturing process shown in FIG.
- X consisting of A is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain.
- the component it means “X containing A as a main component”.
- silicon member is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included.
- gold plating, Cu layer, nickel / plating, etc. unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.
- hatching or the like may be omitted even in a cross section when it becomes complicated or when it is clearly distinguished from a gap.
- the contour line of the background may be omitted even if the hole is planarly closed.
- hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.
- the car navigation device taken as an example in this embodiment is an electronic device mounted on a car. 2. Description of the Related Art
- a car navigation device has various functions (systems) such as a music playback system and a video playback system in addition to a car navigation system that displays the current position of a car and provides route guidance to a destination.
- functions such as a music playback system and a video playback system
- a car navigation device has various functions (systems) such as a music playback system and a video playback system in addition to a car navigation system that displays the current position of a car and provides route guidance to a destination.
- functions such as a music playback system and a video playback system in addition to a car navigation system that displays the current position of a car and provides route guidance to a destination.
- An electronic device including a plurality of systems as described above includes a plurality of semiconductor devices having different functions (for example, a control semiconductor device and a storage semiconductor device) mounted on a motherboard, and the mother board is connected between the plurality of semiconductor devices.
- a method of electrical connection by wiring is conceivable.
- electrical characteristics can be improved in the case of a system in which a plurality of semiconductor devices are connected through wiring on a motherboard. difficult.
- a semiconductor device PKG1 (see FIG. 1) described below is a multi-chip module (MCM: Multi-Chip Module) having a plurality of semiconductor chips.
- MCM Multi-Chip Module
- the semiconductor device PKG1 is a SiP (System in Package) in which a system is formed in one semiconductor package.
- the wiring board IP1 (see FIG. 2) provided in the semiconductor device PKG1 has a smaller plane area than the wiring board MB1 that is a mother board, and can form wiring with high processing accuracy. For this reason, when a plurality of semiconductor chips are electrically connected, high electrical characteristics can be obtained.
- a large current exceeding 5 A may be required.
- the impedance increases as the cross-sectional area of the power supply path decreases.
- the margin of the power supply potential for operating the circuit is small, there is a concern that the circuit may not operate due to a voltage drop. Therefore, it is preferable to widen the wiring width in the path for supplying the driving power supply potential.
- the resistance value of the drive voltage supply path is large, there is a concern that the temperature of the semiconductor device PKG1 rises and the circuit operation becomes unstable.
- a power supply path through which a large current flows as described above and a high-speed signal transmission path of 1.6 Gbps (Giga bit per bit second) or more coexist it is necessary to consider noise countermeasures for the high-speed signal transmission path.
- noise countermeasures for the high-speed signal transmission path.
- signals are transmitted using a differential pair, or when the amount of signal transmission per unit time is increased by increasing the bus width, the number of signal transmission paths increases. For this reason, a technique for efficiently forming a wiring path on the wiring board of the interposer having a smaller plane area than the mother board is required.
- FIG. 1 is an enlarged plan view illustrating a configuration example of the electronic device according to the present embodiment.
- FIG. 2 is an explanatory diagram showing an electrical connection relationship of components of the electronic device in a cross section taken along the line AA in FIG.
- FIG. 3 is an enlarged plan view showing an example of a wiring layout in plan view of the motherboard shown in FIG.
- FIG. 4 is an enlarged plan view showing an example of a terminal layout in plan view of the motherboard shown in FIG.
- FIG. 5 is an enlarged cross-sectional view showing the periphery of the plurality of terminals shown in FIG.
- FIG. 2 is a cross-sectional view, hatching is omitted and a plurality of wirings WM are represented by a solid line, a two-dot chain line, and a dotted line in order to make it easy to see an example of the electrical connection relationship of the components of the electronic device EDV1. Shown in one of them.
- the power supply line WVH1 and the power supply line WVH2 that supply the power supply potential to the logic chip LC do not overlap in the thickness direction.
- FIG. 1 In the cross section along the line AA shown in FIG. 1, in the vicinity of the power supply device RGL1, the power supply line WVH1 and the power supply line WVH2 that supply the power supply potential to the logic chip LC do not overlap in the thickness direction.
- FIG. 1 In the cross section along the line AA shown in FIG. 1, in the vicinity of the power supply device RGL1, the power supply line WVH1 and the power supply line WVH2 that supply the power supply potential to the logic chip LC do not overlap in the
- the power supply line WVH ⁇ b> 1 and the power supply line WVH ⁇ b> 2 are explicitly connected to the logic chip LC and the power supply device RGL ⁇ b> 1.
- a part in the vicinity of the device RGL1 (a part not overlapping with the power supply line WVH1) is indicated by a two-dot chain line.
- the signal line WSG for transmitting an electrical signal is indicated by a dotted line.
- the memory chip MC is not mounted on the cross section along the line AA shown in FIG. However, in FIG. 2, in order to explicitly indicate that the logic chip LC and the memory chip MC are electrically connected, the memory chip MC is schematically shown by a one-dot chain line.
- the power supply line WVH1, the power supply line WVH2, the power supply line WVQ1, and the power supply line WVQ2 shown in FIG. 3 are formed in the wiring layer of the wiring board MB1 which is a multilayer wiring board.
- the power supply line WVH1, the power supply line WVH2, the power supply line WVQ1, and the power supply line WVQ2 are indicated by solid lines for easy understanding of the wiring layout.
- the power supply line WVH1 is provided with a pattern. Further, on the upper surface MBt of the wiring board MB1 shown in FIG.
- a plurality of terminals CN shown in FIG. 4 are exposed at positions where the semiconductor device PKG1 is mounted.
- the wiring board MB1 has a large number of signal lines WSG, but a part of the large number of signal lines WSG is indicated by dotted lines for the sake of clarity.
- FIG. 4 is a plan view, a plurality of terminals CN are shown with different patterns depending on the type of current flowing, and the meanings of the patterns are indicated by symbols next to the legend. Yes.
- An electronic device (electronic device) EDV1 shown in FIG. 1 includes a wiring board (motherboard, mounting board) MB1, a semiconductor device PKG1 mounted on the wiring board MB1, and a power supply device (regulator) RGL1 mounted on the wiring board MB1. And having.
- a plurality of electronic components such as a capacitor CC1 (see FIG. 2) are mounted on the wiring board MB1.
- the power supply device RGL1 mounted on the wiring board MB1 is a power supply component that supplies power to each of a plurality of electronic components included in the electronic device EDV1.
- the power supply device RGL1 has, for example, a power conversion circuit, and uses power input from an external power source (not shown) provided outside the electronic device EDV1 corresponding to operating voltages and operating currents of various circuits included in the electronic device EDV1. Converted to voltage and current values.
- the power converted by the power supply device RGL1 is supplied to each of a plurality of circuits (circuits included in electronic components not shown) included in the electronic device EDV1 via the wiring WM included in the wiring board MB1.
- the wiring board MB1 included in the electronic device EDV1 includes an upper surface (surface, semiconductor device mounting surface) MBt that is a mounting surface of the semiconductor device PKG1, and a lower surface (surface, back surface) MBb opposite to the upper surface MBt (see FIG. 2).
- the wiring board MB1 is a board that mounts and electrically connects a plurality of electronic components including the semiconductor device PKG1 and constitutes a module, and is required to have strength to support the plurality of electronic components. For this reason, the thickness of the wiring board MB1 is larger (thicker) than the thickness of the wiring board IP1 of the semiconductor device PKG1.
- the thickness of the wiring board MB1 is 1.4 mm.
- the thickness of the wiring board IP1 is 1.2 mm, which is smaller than the thickness of the wiring board MB1.
- the thickness of each substrate is not limited to the above values, and the thickness of the wiring substrate MB1 is, for example, about 1.0 mm to 2.0 mm, and the thickness of the wiring substrate IP1 is, for example, about 0.2 mm to 1.5 mm. May be used.
- the thickness of the wiring board MB1 is a distance from one surface to the other surface of the upper surface MBt and the lower surface MBb.
- the thickness of the wiring board IP1 is a distance from one surface to the other surface of the upper surface IPt and the lower surface IPb.
- the wiring board MB1 has a base material made of an insulating material such as a prepreg material in which, for example, a glass cloth is impregnated with an epoxy resin.
- the wiring board MB1 is formed by alternately laminating a plurality of insulating layers made of prepreg and a plurality of wiring layers made of a conductor film such as a copper foil. Laminated substrate).
- the wiring board IP1 may also have a base material (core material) made of prepreg, but the wiring board MB1 requires a base material that is relatively thicker than the base material that the wiring board IP1 has.
- the insulating layer may be formed of an insulating material made of not only a prepreg but also an epoxy resin.
- the wiring board MB1 has a plurality of wirings (mounting board wiring, motherboard wiring) WM.
- the wiring board MB1 is a multilayer wiring board having a plurality of wiring layers, and a wiring WM is formed in each of the plurality of wiring layers.
- the wiring board MB1 has a wiring layer MBL1, a wiring layer MBL2, a wiring layer MBL3, a wiring layer MBL4, along the thickness direction (Z direction) from the upper surface MBt side to the lower surface MBb side. It has six wiring layers including a wiring layer MBL5 and a wiring layer MBL6.
- the plurality of wirings WM include a power supply line WVH1 and a power supply line WVH2 for supplying a power supply potential to the logic chip (semiconductor chip) LC among the plurality of semiconductor chips included in the semiconductor device PKG1.
- the plurality of wirings WM include a power supply line WVQ1 (see FIG. 3) and a power supply line WVQ2 (see FIG. 3) for supplying a power supply potential to the memory chip (semiconductor chip) MC. It is.
- the plurality of wirings WM include signal lines WSG that transmit or receive electrical signals to the logic chip LC. Although many signal lines WSG are formed on the wiring board MB1, two of the many signal lines WSG are shown as an example in FIG.
- the signal line WSG for transmitting an electric signal is mainly provided in the first wiring layer MBL1 provided on the uppermost surface MBt side among the plurality of wiring layers of the wiring board MB1. It has been.
- a reference potential line WVS to which a reference potential (for example, a ground potential) is supplied is mainly provided in the second wiring layer MBL2 next to the upper surface MBt next to the first layer.
- the third wiring layer MBL3 next to the upper surface MBt next to the second layer is mainly provided with a power supply line WVH2 to which a power supply potential is supplied.
- the fourth wiring layer MBL4 next to the upper surface MBt next to the third layer is mainly provided with a power supply line WVH1 to which a power supply potential is supplied.
- a reference potential line WVS to which a reference potential is supplied is mainly provided in the fifth wiring layer MBL5 next to the upper surface MBt next to the fourth layer.
- the wiring layer MBL6 of the sixth layer next to the upper surface MBt next to the fifth layer is mainly provided with wirings for supplying potentials and electric signals to other components not shown.
- the power supply lines WVQ1 and WVQ2 shown in FIG. 3 are provided in the third wiring layer MBL3 or the fourth wiring layer MBL4 shown in FIG.
- the reference potential line WVS of the wiring layer MBL2 and the reference potential line WVS of the wiring layer MBL5 are electrically connected via a through-hole wiring WTH that penetrates the wiring board MB1 in the thickness direction. Supplied.
- the layout of power supply line WVH1, power supply line WVH2, power supply line WVQ1, and power supply line WVQ2 will be described in detail later.
- the wiring board MB1 has a plurality of terminals CN formed on the upper surface MBt side.
- the plurality of terminals CN are mounting terminals for electrically connecting the semiconductor device PKG1 and the wiring board MB1.
- the plurality of terminals CN are supplied with a power supply potential to a terminal CNVH1, a terminal CNVH2, and a memory chip (semiconductor chip) MC that supply a power supply potential to the logic chip (semiconductor chip) LC.
- a terminal CNVQ1 and a terminal CNVQ2 to be supplied are included.
- the plurality of terminals CN include terminals CNSG that transmit or receive electrical signals to the logic chip LC.
- the plurality of terminals CN include a terminal CNVS that supplies a reference potential to the logic chip LC and the memory chip MC. Note that the plurality of terminals CN include terminals that are used for purposes other than those described above, but in FIG. 4, the terminals CN other than those described above are shown without a pattern in the same manner as the terminal CNVS.
- the plurality of terminals CN are conductor patterns formed in the uppermost layer (first layer) among the plurality of wiring layers of the wiring board MB1. Specifically, as shown in FIG. 5, the conductor pattern formed in the uppermost layer of the plurality of wiring layers of the wiring board MB1 is covered with the insulating film SR1 formed so as to cover the upper surface MBt of the wiring board MB1. . In addition, a plurality of openings SRk1 are formed in the insulating film SR1, and a part of the conductor pattern formed in the uppermost layer is exposed in each of the plurality of openings SRk1.
- the conductor pattern constituting the terminal CN includes individual conductor patterns that are electrically separated from other terminals CN and formed independently for each terminal CN, like the terminal CN1 shown in FIG. .
- the number per unit area (specifically, the number of signal transmission paths) Number) can be increased.
- each of the terminal CNVH1, the terminal CNVH2, the terminal CNVQ1, the terminal CNVQ2, and the terminal CNVS illustrated in FIG. 4 can be formed independently.
- the conductor pattern constituting the terminal CN may include a conductor pattern in which adjacent terminals CN are integrally formed and have a larger area than the terminal CN1, like the terminal CN2 shown in FIG.
- a conductor pattern having a large area is used as a part of the terminal CN, a plurality of openings SRk1 are provided on one conductor pattern. For example, if the area of the conductor pattern constituting the supply path for the power supply potential and the reference potential is increased, the resistance in the supply path can be reduced. As a result of reducing the resistance of the supply path of the power supply potential and the reference potential, the circuit operation can be stabilized.
- some of the plurality of terminals CN are connected to a through-hole wiring WTH that penetrates the wiring board MB1 in the thickness direction.
- a through-hole wiring WTH that penetrates the wiring board MB1 in the thickness direction.
- the conductor pattern constituting the terminal CN may include a terminal CN that is not connected to the through-hole wiring WTH, like the terminal CN3 shown in FIG.
- the wiring is routed using the uppermost wiring layer among the plurality of wiring layers of the wiring board MB1.
- a signal line for example, an analog signal path, etc.
- it is preferable not to be connected to the hall wiring WTH.
- the electronic device EDV1 of the present embodiment has a semiconductor device PKG1 mounted on the upper surface MBt of the wiring board MB1.
- a detailed configuration of the semiconductor device PKG1 will be described.
- FIG. 6 is an explanatory diagram illustrating an outline of a configuration of a plurality of transmission paths that are electrically connected to a plurality of semiconductor chips included in the semiconductor device illustrated in FIG. 1.
- FIG. 6 a control circuit CTL that controls the memory chip MC among a plurality of circuits included in the logic chip LC and an arithmetic processing circuit PRC that performs arithmetic processing such as an image display system are illustrated as representative examples. .
- FIG. 6 representatively shows an input / output circuit CAC that performs an input / output operation of a data signal and a memory circuit RAM that stores the data signal among a plurality of circuits included in the memory chip MC.
- the semiconductor device PKG1 of the present embodiment includes a wiring board IP1 and a plurality of semiconductor chips mounted on the upper surface IPt of the wiring board IP1.
- the plurality of semiconductor chips include two memory chips MC (memory chips M ⁇ b> 1 and M ⁇ b> 2) each having a memory circuit (memory circuit) and two memory chips MC.
- a logic chip LC provided with a control circuit for controlling the operation.
- the number of the plurality of semiconductor chips is not limited to the above, and various modifications can be applied.
- the number of memory chips MC differs in required storage capacity depending on the system provided in the semiconductor device PKG1.
- the number of memory chips MC may be two or more, or one.
- a plurality of logic chips LC may be mounted on the upper surface IPt.
- a semiconductor chip having functions other than the logic chip LC and the memory chip MC may be mounted.
- Each of the plurality of memory chips MC shown in FIG. 6 performs an input / output operation of a data circuit for a memory circuit (hereinafter referred to as a memory circuit RAM) called a DRAM (Dynamic Random Access Memory) and a memory circuit RAM.
- An output circuit CAC is provided.
- the logic chip LC electrically connected to each of the plurality of memory chips MC includes a control circuit CTL that controls the operation of the memory circuit RAM of the memory chip MC, and an arithmetic process that performs an arithmetic process on the data signal.
- a circuit PRC is provided.
- Each of the plurality of memory chips MC includes a power supply potential supply path VDQ1P (or a power supply potential supply path VDQ2P that supplies the power supply potential VDDQ2) for supplying the power supply potential VDDQ1 for driving the input / output circuit CAC, and a reference potential.
- a reference potential supply path VSSP for supplying VSS is provided.
- the power supply potential VDDQ1 for the memory chip M1 and the power supply potential VDDQ2 for the memory chip M2 are shown separately, but the power supply potential VDDQ1 and the power supply potential VDDQ2 are the same potential.
- the power supply potential VDDQ1 and the power supply potential VDDQ2 are about 1.1 V, respectively, and a current of about 4 A flows.
- the reference potential VSS is a potential having a value different from the power supply potential, such as a ground potential (GND potential).
- the power supply potential supply paths VDQ1P and VDQ2P and the reference potential supply path VSSSP are connected to a terminal (land) LD which is an external terminal provided in the wiring board IP1.
- the power supply potential supply paths VDQ1P and VDQ2P and the reference potential supply path VSSP branch off on the wiring board IP1 and are connected to the electrode PDL of the logic chip LC.
- each of the plurality of memory chips MC has a plurality of signal transmission paths SGP1 (see FIG. 2) for transmitting an electrical signal.
- the plurality of signal transmission paths SGP1 include a data signal transmission path DTP1 for transmitting the data signal SGDAT1, a clock signal transmission path CKP1 for transmitting the clock signal SGCLK1 for synchronizing operation timing, and a control signal SGCTL1 for controlling the input / output operation. Is included in the control signal transmission path CTP1.
- Each of the data signal transmission path DTP1, the clock signal transmission path CKP1, and the control signal transmission path CTP1 connects the electrode PDL of the logic chip LC and the electrode PDM of the memory chip MC.
- a power supply potential supply path VDQ1P for supplying a power supply potential VDDQ1 for driving the input / output circuit CAC a power supply potential supply path VDQ2P for supplying a power supply potential VDDQ2
- the reference potential supply path VSSSP for supplying the reference potential VSS is also shown.
- a power supply potential supply path for a core circuit for driving a main circuit (core circuit) such as a power supply control circuit and a clock oscillation circuit (not shown) may be included, or another reference potential supply path may be included. good.
- FIG. 6 shows an example in which the data signal transmission path DTP1, the clock signal transmission path CKP1, and the control signal transmission path CTP1 are connected to each of the plurality of memory chips MC. However, a plurality of data signal transmission paths DTP1, a plurality of clock signal transmission paths CKP1, and a plurality of control signal transmission paths CTP1 are connected to the memory chip MC.
- the memory chip MC is connected with a number of data signal transmission paths corresponding to the number of channels of the memory circuit RAM and the width of the data bus of each channel. For example, when each of the memory chips MC has four channels with a bus width of 8 bits, a data signal transmission path DTP1 for 64 bits is connected. In addition to the data signal SGDAT1, the number of data signal transmission paths DTP1 further increases in consideration of data strobe signals and data mask signals (not shown).
- the signal current transmitted through the clock signal transmission path CKP1 shown in FIG. 6 includes a clock signal SGCLK1 that is a timing signal and a clock enable signal that controls the activation of the clock signal SGCLK1.
- the control signal SGCTL1 shown in FIG. 6 includes command signals such as a chip select signal, a row address strobe signal, a column address strobe signal, and a write enable signal, and address designation signals such as an address signal and a bank address signal. It is. Therefore, a number of control signal transmission paths CTP1 corresponding to the number of types of control signals SGCTL1 are connected to each of the plurality of memory chips MC.
- the logic chip LC also includes a power supply potential supply path VDH1P that supplies a power supply potential VDDH1 for driving the arithmetic processing circuit PRC, a power supply potential supply path VDH2P that supplies a power supply potential VDDH2 for driving the control circuit CTL, A reference potential supply path VSSSP for supplying the reference potential VSS.
- VDH1P that supplies a power supply potential VDDH1 for driving the arithmetic processing circuit PRC
- VDH2P that supplies a power supply potential VDDH2 for driving the control circuit CTL
- a reference potential supply path VSSSP for supplying the reference potential VSS.
- the amount of power consumed varies depending on the type of system. For example, a relatively large amount of power is consumed to drive the arithmetic processing circuit PRC that performs arithmetic processing for forming graphics, moving images, and the like.
- the power consumption of the control circuit CTL that controls the input / output operation is smaller than the power consumption of the arithmetic processing circuit PRC, and the value of the current flowing through the power supply potential supply path VDH2P for the control circuit CTL is relatively small.
- the function of the semiconductor device PKG1 is increased, a large number of control circuits CTL may be operated at the same time.
- the value of the current flowing through the power supply potential supply path VDH2P is also large when evaluated by the maximum value.
- a current of about 10 A at the maximum flows through the power supply potential supply path VDH2P for the control circuit CTL that supplies the power supply potential VDDH2 of 0.80 V (volts).
- the current value flowing through the power supply potential supply path VDH1P for the arithmetic processing circuit PRC is larger than the current value flowing through the power supply potential supply path VDH2P for the control circuit CTL.
- the power supply potential VDDH1 supplied for driving the arithmetic processing circuit PRC may be the same as the power supply potential VDDH2 supplied for driving the control circuit CTL.
- the current value flowing through the power supply potential supply path VDH1P is larger than the current value flowing through the power supply potential supply path VDH2P.
- the value of the current described above varies depending on the operation of the load-side circuit, that is, the circuit that consumes power. Therefore, in designing, the maximum value of the current is evaluated assuming that the power consumption of the circuit on the load side is the largest.
- power consumption can be reduced when the power supply potential VDDH1 and the power supply potential VDDH2 are smaller. Further, if the power consumption is reduced, the heat generation in the conductive path is suppressed, so that the operation can be stabilized. Therefore, in this embodiment, the values of power supply potential VDDH1 and power supply potential VDDH2 are smaller than the values of power supply potential VDDQ1 and power supply potential VDDQ2.
- each of the power supply potential supply path VDH1P, the power supply potential supply path VDH2P, and the reference potential supply path VSSP is connected to a terminal LD that is an external terminal provided in the wiring board IP1.
- the logic chip LC has a plurality of signal transmission paths SGP1 (see FIG. 2) for transmitting electrical signals.
- the plurality of signal transmission paths SGP1 include a data signal transmission path DTP1 that transmits a data signal SGDAT1 to and from the memory chip MC, a clock signal transmission path CKP1 that transmits a clock signal SGCLK1 for synchronizing operation timing, and an input
- a control signal transmission path CTP1 for transmitting a control signal SGCTL1 for controlling the output operation is included.
- a plurality of signal transmission paths include a data signal transmission path DTP2 for transmitting the data signal SGDAT2 and a clock signal transmission path for transmitting a clock signal SGCLK2 for synchronizing operation timings with an external device of the semiconductor device PKG1.
- CKP2 and control signal transmission path CTP2 for transmitting control signal SGCTL2 for controlling the input / output operation are included.
- the plurality of signal transmission paths SGP2 include an analog signal transmission path ANLP for inputting the analog signal SGANL to the logic chip LC.
- the electrode PDL that is a signal transmission path transmits an internal interface electrode (the clock signal SGCLK1, the control signal SGCTL1, and the data signal SGDAT1) to and from the memory chip MC. Interface terminal) IIF.
- the electrode PDL serving as a signal transmission path includes an external interface electrode (interface terminal) OIF that transmits a clock signal SGCLK2, a control signal SGCTL2, and a data signal SGDAT2 to and from an external device of the semiconductor device PKG1.
- the data signal SGDAT2 transmitted between the terminal LD of the wiring board IP1 and the logic chip LC and the data signal SGDAT1 transmitted between the logic chip LC and the memory chip MC are different data signals. Also good.
- the arithmetic processing circuit PRC of the logic chip LC performs arithmetic processing, the input signal and the output signal may be different before and after the processing.
- control signal SGCTL2 transmitted between the terminal LD of the wiring board IP1 and the logic chip LC includes a signal for controlling the control circuit CTL and the arithmetic processing circuit PRC. Therefore, the control signal SGCTL2 transmitted between the terminal LD of the wiring board IP1 and the logic chip LC and the control signal SGCTL1 transmitted between the logic chip LC and the memory chip MC are different from each other.
- the clock signal SGCLK2 transmitted between the terminal LD of the wiring board IP1 and the logic chip LC may include a timing signal for the arithmetic processing circuit PRC in addition to a timing signal for the control circuit CTL circuit. Therefore, the clock signal SGCLK2 transmitted between the terminal LD of the wiring board IP1 and the logic chip LC and the clock signal SGCLK1 transmitted between the logic chip LC and the memory chip MC may be different from each other. .
- the input of the data signal SGDAT1 to the memory circuit RAM and the output of the data signal SGDAT1 from the memory circuit RAM are performed via the logic chip LC. Therefore, most of the signal transmission path (see FIG. 2) connected to the memory chip MC is electrically connected to the terminal LD of the wiring board IP1 via the logic chip LC, and the wiring board is not connected via the logic chip LC. There are almost no signal transmission paths electrically connected to the terminal LD of IP1.
- the electrode PDL constituting the signal transmission path of the logic chip LC includes a plurality of external interface electrodes OIF and a plurality of internal interface electrodes IIF.
- most of the electrodes PDM constituting the signal transmission path of the memory chip MC are internal interface electrodes IIF that transmit signals to and from the logic chip LC, and there are no or few external interface electrodes OIF.
- all signal transmission paths connected to the memory chip MC are electrically connected to the logic chip LC.
- the external interface electrode OIF of the memory chip MC does not exist.
- a signal transmission path other than the signal transmission path shown in FIG. 6 may be electrically connected to the terminal LD of the wiring board IP1 without going through the logic chip LC.
- a signal transmission path for testing for individually testing the memory chip MC after the assembly of the semiconductor device PKG1 does not go through the logic chip LC but the terminal LD of the wiring board IP1. And may be electrically connected.
- a plurality of signal terminals electrically connected to the MC may be included.
- the above-mentioned “number of signal terminals electrically connected to the memory chip MC without going through the logic chip LC” means the memory chip MC without going through the logic chip LC as in the example shown in FIG. This also includes the case where the number of signal terminals electrically connected to each other is zero.
- FIG. 7 is a cross-sectional view taken along the line BB of the semiconductor device shown in FIG.
- FIG. 8 is a plan view showing the structure of the lower surface side of the semiconductor device shown in FIG.
- FIG. 9 is a plan view of the surface side of the logic chip shown in FIG.
- FIG. 10 is a plan view of the surface side of the memory chip shown in FIG.
- FIG. 7 is a cross-sectional view, hatching of the insulating layers IL, SR2, SR3 and the underfill resin UF is omitted for easy viewing.
- the wiring board IP1 includes an upper surface (surface, main surface, chip mounting surface) IPt on which the logic chip LC and the memory chip MC are mounted, and a lower surface (surface, main surface, Mounting surface) IPb and a plurality of side surfaces IPs arranged between the upper surface IPt and the lower surface IPb, and form a rectangular outer shape in plan view as shown in FIG.
- the planar size of the wiring substrate IP1 is, for example, a quadrangle whose side is about 30 mm to 100 mm.
- the peripheral portion of the wiring board IP1 includes a substrate side Sip1, a substrate side Sip2 located on the opposite side of the substrate side Sip1, a substrate side Sip1, and a substrate side Sip3 that intersects the substrate side Sip2. And a substrate side Sip4 located on the opposite side of the substrate side Sip3.
- the substrate side Sip1 and the substrate side Sip2 each extend along the Y direction.
- the substrate side Sip3 and the substrate side Sip4 extend along the X direction orthogonal to the Y direction.
- the semiconductor device PKG1 is mounted on the wiring board MB1 so that a part of the board side Sip3 of the four sides of the wiring board IP1 and the power supply device RGL1 face each other.
- the wiring board IP1 is an interposer (relay) for electrically connecting a plurality of semiconductor chips including the logic chip LC mounted on the upper surface IPt side and the wiring board MB1 which is the mother board (mounting board) shown in FIG. Substrate).
- the wiring board IP1 is an interposer for electrically connecting the logic chip LC mounted on the upper surface IPt side and the plurality of memory chips MC.
- the wiring board IP1 has a plurality of wiring layers (10 layers in the example shown in FIG. 7) that electrically connect the upper surface IPt side that is the chip mounting surface and the lower surface IPb side that is the mounting surface.
- Each wiring layer is formed with a conductor pattern such as a wiring that is a path for supplying an electric signal or electric power, and is covered with an insulating layer IL.
- most of the wiring layer WL1 disposed on the uppermost surface IPt side is covered with the insulating film SR3 which is a solder resist film.
- most of the wiring layer WL10 disposed on the lowermost surface IPb side among the plurality of wiring layers is covered with the insulating film SR2 which is a solder resist film.
- the wiring board IP1 is formed by, for example, laminating a plurality of wiring layers on the upper and lower surfaces of a core layer (core material, core insulating layer) CR made of a prepreg obtained by impregnating glass fiber with a resin by a build-up method. And formed.
- the core layer CR has a structure in which three insulating layers IL are stacked, and the insulating layer between the wiring layer WL4 and the wiring layer WL7 is the core layer CR.
- the uppermost wiring layer WL4 and the lowermost wiring layer WL7 of the core layer CR have a plurality of through holes provided so as to penetrate from one to the other of the upper and lower surfaces of the core layer CR. They are electrically connected via a plurality of through-hole wirings TW embedded in (through-holes).
- a plurality of bonding pads (bonding leads, semiconductor chip connection terminals) TCS electrically connected to the logic chip LC or the memory chip MC are formed on the upper surface IPt of the wiring board IP1.
- a plurality of terminals (lands, external connection terminals) LD which are external input / output terminals of the semiconductor device PKG1 are formed on the lower surface IPb of the wiring board IP1.
- the plurality of bonding pads TCS and the plurality of terminals LD are electrically connected to each other via a wiring WR, a via VA, and a through-hole wiring TW formed on the wiring board IP1.
- the wiring board IP1 is a wiring board in which a plurality of wiring layers are laminated on the upper surface side and the lower surface side of the core layer CR that is a core material.
- a so-called coreless substrate is used that does not have a core layer CR made of a hard material such as a prepreg material, and is formed by sequentially laminating a conductor pattern such as an insulating layer IL and a wiring WR. May be.
- the through-hole wiring TW is not formed, and each wiring layer is electrically connected via the via VA.
- the wiring board IP1 having 10 wiring layers is exemplarily shown.
- a wiring board having 11 or more wiring layers or 9 or less wiring layers is used. Also good.
- the plurality of terminals LD shown in FIG. 7 are conductor patterns formed in the lowest layer (the tenth wiring layer WL10 in the example shown in FIG. 7) among the plurality of wiring layers of the wiring board IP1. .
- the conductor pattern formed in the lowermost layer is covered with an insulating film SR2 formed so as to cover the lower surface IPb of the wiring board IP1.
- a plurality of openings SRk2 are formed in the insulating film SR2, and a part of the conductor pattern formed in the lowermost wiring layer WL10 is exposed in each of the plurality of openings SRk2.
- the plurality of conductor patterns constituting the terminal LD shown in FIG. 7 are electrically separated from the other terminals LD as the terminal LD1 shown in FIG. Includes individual conductor patterns.
- the adjacent terminals LD may be formed integrally and may include a conductor pattern having a larger area than the other terminals LD1.
- a conductor pattern with a large area is used as part of the terminal LD, a plurality of openings SRk2 are provided on one conductor pattern. For example, if the area of the conductor pattern constituting the supply path for the power supply potential and the reference potential is increased, the resistance in the supply path can be reduced. As a result of reducing the resistance of the supply path of the power supply potential and the reference potential, the circuit operation can be stabilized.
- solder ball SBp solder material, external terminal, electrode, external electrode
- the solder ball SBp electrically connects the plurality of terminals CN (see FIG. 4) on the wiring board MB1 side and the plurality of terminals LD. It is a member.
- the solder ball SBp is, for example, a Sn—Pb solder material containing lead (Pb), or a solder material made of so-called lead-free solder that does not substantially contain Pb.
- lead-free solder examples include tin (Sn) only, tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), and the like.
- the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHS (Restriction of az Hazardous Substances) directive.
- the plurality of terminals LD are arranged in a plurality of rows (regularly) along the outer periphery of the lower surface IPb of the wiring board IP1.
- a plurality of solder balls SBp (see FIG. 7) joined to the plurality of terminals LD are also arranged in a plurality of rows (regularly) along the outer periphery of the lower surface IPb of the wiring board IP1.
- the plurality of terminals LD provided on the lower surface IPb side of the wiring board IP1 and the plurality of solder balls SBb connected to the plurality of terminals LD are arranged in a matrix.
- a semiconductor device in which a plurality of external terminals (solder balls SBp, terminals LD) are arranged in a plurality of rows on the mounting surface side of the wiring board IP1 is referred to as an area array type semiconductor device.
- the mounting surface (lower surface IPb) side of the wiring board IP1 can be effectively used as an arrangement space for the external terminals. Therefore, even if the number of external terminals increases, the mounting area of the semiconductor device increases. It is preferable at the point which can suppress. That is, a semiconductor device in which the number of external terminals increases with higher functionality and higher integration can be mounted in a space-saving manner.
- the semiconductor device PKG1 has a logic chip LC and a plurality of memory chips MC mounted on the wiring board IP1.
- the logic chip LC and the plurality of memory chips MC are mounted side by side on the wiring board IP1.
- the logic chip LC and the plurality of memory chips MC are not stacked and do not overlap each other in plan view.
- the logic chip LC has a quadrangular outer shape having a smaller plane area than the wiring board IP1 in plan view.
- the peripheral portion of the logic chip LC includes a chip side Scp1, a chip side Scp2 located on the opposite side of the chip side Scp1, a chip side Scp1, a chip side Scp3 intersecting with the chip side Scp2, and a chip side Scp3.
- Chip side Scp4 located on the opposite side.
- the logic chip LC is mounted on the wiring board IP1 so that the chip side Scp1 and the substrate side Sip1 extend side by side.
- the logic chip LC includes a wiring substrate such that the chip side Scp1 and the substrate side Sip1, the chip side Scp2 and the substrate side Sip2, the chip side Scp3 and the substrate side Sip3, and the chip side Scp4 and the substrate side Sip4 are aligned with each other. Mounted on IP1.
- each of the plurality of memory chips MC has a rectangular outer shape having a smaller plane area than the wiring board IP1 in plan view.
- each of the plurality of memory chips MC has a rectangular shape.
- the peripheral edge of the memory chip MC intersects the chip side Smc1, the chip side Smc2, the chip side Smc1, and the chip side Smc2 located on the opposite side of the chip side Smc1. It has a side Smc3 and a chip side Smc4 located on the opposite side of the chip side Smc3.
- the chip side Smc1 and the chip side Smc2 are long sides
- the chip side Smc3 and the chip side Smc4 are short sides.
- the area of each of the plurality of memory chips MC is larger than the area of the logic chip LC.
- the storage capacity of the memory chip MC increases in proportion to the area of the formation region of the memory circuit RAM (see FIG. 6). For this reason, the storage capacity of the memory chip MC can be increased by making the area of each of the plurality of memory chips MC larger than the area of the logic chip LC.
- the memory chip M1 is mounted between the chip side Scp2 of the logic chip LC and the substrate side Sip2 of the wiring board IP1.
- the memory chip M2 is mounted between the chip side Scp3 of the logic chip LC and the substrate side Sip3 of the wiring board IP1.
- the memory chip M1 and the memory chip M2 are mounted so as to face the chip side Scp2 and the chip side Scp3, thereby electrically connecting the memory chip MC and the logic chip LC. Therefore, it is possible to secure a wide arrangement space for the wiring to be connected.
- the logic chip LC includes a front surface (main surface, upper surface) LCt, a back surface (main surface, lower surface) LCb opposite to the surface LCt, and between the front surface LCt and the back surface LCb. Has side LCs located.
- a plurality of electrodes (chip terminals, bonding pads) PDL are formed on the surface LCt side of the logic chip LC.
- the plurality of electrodes PDL are exposed from the protective film protecting the surface LCt of the logic chip LC on the surface LCt of the logic chip LC.
- the plurality of electrodes PDL are arranged in a plurality of rows (in an array) on the surface LCt of the logic chip LC along the outer periphery of the surface LCt.
- the present invention can be applied to a semiconductor chip of a type in which a plurality of electrodes PDL are formed on the peripheral portion of the surface LCt.
- the logic chip LC is mounted on the wiring board IP1 in a state where the surface LCt is disposed opposite to the upper surface IPt of the wiring board IP1.
- a mounting method is called a face-down mounting method or a flip-chip connection method.
- the main surface of the logic chip LC (specifically, the semiconductor element formation region provided on the element formation surface of the semiconductor substrate that is the base material of the logic chip LC) includes a plurality of semiconductor elements (circuits). Element) is formed.
- the plurality of electrodes PDL are connected to the plurality of electrodes via wiring (not shown) formed in a wiring layer disposed inside the logic chip LC (specifically, between the surface LCt and a semiconductor element formation region (not shown)). Each is electrically connected to the semiconductor element.
- the logic chip LC (specifically, the base material of the logic chip LC) is made of, for example, silicon (Si).
- an insulating film that covers the base material and wiring of the logic chip LC is formed on the surface LCt, and a part of each of the plurality of electrodes PDL is formed from the insulating film in the opening formed in the insulating film. Exposed.
- each of the plurality of electrodes PDL is made of metal, and in this embodiment, is made of, for example, aluminum (Al).
- the material constituting the electrode PDL is not limited to aluminum (Al), but may be copper (Cu).
- the plurality of electrodes PDL are connected to the protruding electrodes SBc, and the plurality of electrodes PDL of the logic chip LC and the plurality of bonding pads TCS of the wiring board IP1 are connected to the plurality of protruding electrodes SBc.
- the protruding electrode (bump electrode) SBc is a metal member (conductive member) formed so as to protrude on the surface LCt of the logic chip LC.
- the protruding electrode SBc is a so-called solder bump in which a solder material is laminated on the electrode PDL via a base metal film (under bump metal).
- the base metal film is, for example, a laminated film in which titanium (Ti), copper (Cu), and nickel (Ni) are laminated from the connection surface side with the electrode PDL (when a gold (Au) film is further formed on the nickel film) Can also be exemplified.
- solder material constituting the solder bump a lead-containing solder material or lead-free solder can be used in the same manner as the solder ball SBp described above.
- solder bumps are formed in advance on both the plurality of electrodes PDL and the plurality of bonding pads TCS, and the heat treatment (reflow) is performed with the solder bumps in contact with each other. By applying the processing, the solder bumps are integrated with each other to form the protruding electrode SBc.
- a pillar bump in which a solder film is formed on the tip surface of a conductor column made of copper (Cu) or nickel (Ni) may be used as the protruding electrode SBc.
- each of the memory chips MC includes a front surface (main surface, upper surface) MCt, a back surface (main surface, lower surface) MCb opposite to the surface MCt, and a front surface MCt and a back surface MCb. It has side surfaces MCs located between them.
- a plurality of electrodes (chip terminals, bonding pads) PDM are formed on the surface MCt side of the memory chip MC.
- the plurality of electrodes PDM are exposed from the protective film that protects the surface MCt of the memory chip MC at the surface MCt of the memory chip MC.
- the plurality of electrodes PDM are arranged in a plurality of rows (in an array) on the surface MCt of the memory chip MC along the outer periphery of the surface MCt.
- the memory chip MC is divided into four channel regions of channels ChA0, ChA1, ChB0, and ChB1, and a plurality of electrodes PDM are arranged in a matrix in each channel region.
- Each channel region of the memory chip MC has a region in which a memory circuit RAM (see FIG. 6) is formed, and each of the memory circuit RAMs in each channel region has a logic chip LC shown in FIG. And electrically connected.
- the surface MCt of the memory chip MC can be used effectively as an electrode arrangement space, so that the number of electrodes of the memory chip MC increases.
- the memory chip MC is mounted on the wiring board IP1 in a state where the surface MCt is disposed opposite to the upper surface IPt of the wiring board IP1. That is, like the logic chip LC, it is mounted on the wiring board IP1 by the face-down mounting method.
- a plurality of semiconductor elements are formed on the main surface of the memory chip MC (specifically, a semiconductor element formation region provided on an element formation surface of a semiconductor substrate that is a base material of the memory chip MC).
- the plurality of electrodes PDM are connected to the plurality of electrodes via wiring (not shown) formed in a wiring layer disposed inside the memory chip MC (specifically, between the surface MCt and a semiconductor element formation region not shown). Each is electrically connected to the semiconductor element.
- the memory chip MC (specifically, the base material of the memory chip MC) is made of, for example, silicon (Si).
- an insulating film is formed on the surface MCt so as to cover the base material and the wiring of the memory chip MC.
- a part of each of the plurality of electrodes PDM is formed from the insulating film in the opening formed in the insulating film. Exposed.
- Each of the plurality of electrodes PDM is made of metal, and in the present embodiment, is made of, for example, aluminum (Al).
- the plurality of electrodes PDM are connected to the protruding electrodes SBc, respectively, and the plurality of electrodes PDM of the memory chip MC and the plurality of bonding pads TCS of the wiring board IP1 are connected to the plurality of protruding electrodes SBc.
- the protruding metal (bump electrode) SBc and the base metal film disposed between the protruding electrode SBc and the electrode PDM are as described above, the overlapping description is omitted.
- underfill resin (insulating resin) UF is disposed between the logic chip LC and the wiring board IP1 and between the memory chip MC and the wiring board IP1.
- the underfill resin UF is disposed so as to block the space between the surface LCt of the logic chip LC and the upper surface IPt of the wiring board IP1 and the space between the surface MCt of the memory chip MC and the upper surface IPt of the wiring board IP1.
- the underfill resin UF is made of an insulating (non-conductive) material (for example, a resin material), and an electrical connection portion (a plurality of protruding electrodes) between the semiconductor chip (logic chip LC and memory chip MC) and the wiring board IP1. SBc bonding portion) is arranged to be sealed.
- the stress generated in the electrical connection portion between the semiconductor chip and the wiring board IP1 can be relaxed.
- the stress generated at the joints between the plurality of electrodes PDL and the plurality of protruding electrodes SBc of the logic chip LC can be relaxed.
- the main surface on which the semiconductor element (circuit element) of the logic chip LC is formed can be protected.
- the supply path of the power supply potential through which a large current exceeding 5 A (ampere) flows is formed with a wider wiring width than the signal line in order to stably supply the current.
- the wiring width Wh1 of the power supply line WVH1 and the wiring width Wh2 of the power supply line WVH2 are each thicker (larger) than the wiring width Wsg of the signal line WSG.
- the wiring width Wq1 of the power supply line WVQ1 and the wiring width Wq2 of the power supply line WVQ2 are the wiring width of the signal line WSG. Thicker (larger) than Wsg.
- the wiring width Wh1 of the power supply line WVH1 is thicker (larger) than the wiring width Wh2, the wiring width Wq1, and the wiring width Wq2.
- the wiring width Wh2 of the power supply line WVH2 is thicker (larger) than the wiring width Wq1 and the wiring width Wq2.
- the power supply potential VDDH1 (see FIG. 6) supplied to the power supply line WVH1 and the power supply potential VDDH2 (see FIG. 6) supplied to the power supply line WVH2 are the power supply potential supplied to the power supply line WVQ1. It is lower than the power supply potential VDDQ2 (see FIG. 6) supplied to VDDQ1 (see FIG. 6) and the power supply line WVQ2. Further, the power supply potential VDDH1 supplied to the power supply line WVH1 is lower than the power supply potential VDDH2 supplied to the power supply power WVH2.
- FIG. 6 exemplarily shows a typical drive power supply, and another power supply potential may be supplied in addition to the power supply potential described above.
- one supply path affects the electrical characteristics of the other supply path. For example, when supply paths that supply different power supply potentials overlap each other in the thickness direction, a supply path that supplies a relatively high potential affects a supply path that supplies a relatively low potential. In addition, for example, in two supply paths that overlap in the thickness direction, when the value of the current flowing through one of the supply paths changes suddenly, the impedance of the other supply path may change.
- the noise effect between the supply paths described above is caused by the electrical coupling of two supply paths that overlap in the thickness direction. Therefore, in order to reduce the influence of noise, it is preferable to reduce the area of the portion where the supply path overlaps in the thickness direction.
- the electronic device EDV1 when viewing the electronic device EDV1 of the present embodiment shown in FIG. 3, the electronic device EDV1 has the following configuration. That is, the memory chip MC is mounted along each of the chip side Scp2 and the chip side Scp3 among the four sides of the logic chip LC. Since the power supply line WVQ1 is drawn into the memory chip M1 and the power supply line WVQ2 is drawn into the memory chip M2, it is difficult to provide the power supply lines WVH1 and WVH2 across the memory chips M1 and M2.
- a plurality of signal lines WSG are provided along the chip side Scp4.
- terminals CNSG that transmit or receive electrical signals to the logic chip LC are concentrated in the region between the chip side Scp4 and the substrate side Sip4. It has been.
- the terminal CNSG is provided in a region other than the region between the chip side Scp4 and the substrate side Sip4.
- the plurality of terminals CNSG have the highest density. Is arranged. For this reason, in the region between the chip side Scp4 and the substrate side Sip4, the signal lines WSG connected to the plurality of terminals CNSG are arranged with the highest density.
- the power lines WVH1 and WVH2 through which a large current flows do not overlap the signal line WSG.
- the analog signal transmission path ANLP for inputting the analog signal SGANL (see FIG. 6) to the plurality of signal lines WSG provided between the chip side Scp4 and the substrate side Sip4.
- a plurality of signal lines WSG are included.
- power supply line WVH1 and power supply line WVH2 through which a large current flows are not provided in the region between chip side Scp4 and substrate side Sip4.
- the memory chip MC and a large number of signal lines WSG are provided outside the chip side Scp2, the chip side Scp3, and the chip side Scp4.
- a plurality of memory chips MC are not mounted between the chip side Scp1 and the substrate side Sip1. Therefore, in the present embodiment, power supply line WVH1 and power supply line WVH2 are drawn from the chip side Scp1 side of logic chip LC.
- the power supply line WVH2 is arranged to straddle the substrate side Sip1 of the wiring board IP1 and the chip side Scp1 of the logic chip LC in a plan view. Further, in plan view, the power supply line WVH2 is disposed so as to extend toward the region overlapping with the logic chip through between the power supply line WVH1 and the plurality of memory chips M2. Further, the power supply line WVH1 and the power supply line WVH2 are provided so as not to overlap as much as possible except in a region overlapping with the logic chip LC. Therefore, the area of the power supply line WVH2 that overlaps with the power supply line WVH1 in the thickness direction is smaller than the area of the power supply line WVH2 that does not overlap with the power supply line WVH1.
- each of the power supply line WVQ1 and the power supply line WVQ2 is disposed so as to straddle the substrate side Sip3 of the wiring board IP1, and each of the power supply line WVQ1 and the power supply line WVQ2 is a logic chip. Does not overlap with LC in the thickness direction.
- the power supply potential VDDQ1 and the power supply potential VDDQ2 are power supply potentials for driving the input / output circuit CAC. Therefore, the power supply potential VDDQ1 and the power supply potential VDDQ2 are supplied to the logic chip LC in addition to the memory chip MC.
- the power supply line WVQ1 when attention is paid to the stability of power supply to the power supply potential VDDQ1, the power supply line WVQ1 preferably passes through the region overlapping the memory chip M1 to the region overlapping the logic chip LC. . Focusing on the stability of power supply to the power supply potential VDDQ2, the power supply line WVQ2 preferably passes through a region overlapping the memory chip M2 to a region overlapping the logic chip LC.
- the power supply line WVQ1 and the power supply line WVQ2 are drawn to a region overlapping the logic chip LC, a part of the power supply line WVQ1 and the power supply line WVQ2 overlaps with a part of the power supply line WVH1 or the power supply line WVH2. Therefore, if the power supply line WVQ1 and the power supply line WVQ2 are arranged so as not to overlap the logic chip LC in the thickness direction as in the present embodiment, the power supply lines WVQ1 and WVQ2 are partially powered. Even if it overlaps with part of the line WVH1 or the power supply line WVH2, the area of the overlapping part can be reduced.
- the power supply line WVQ1 and the power supply line WVQ2 may be configured not to overlap the power supply line WVH1 and the power supply line WVH2. As a result, the influence of noise on the power supply line WVH1 or the power supply line WVH2 by the power supply line WVQ1 and the power supply line WVQ2 can be reduced.
- the power supply line WVQ1 does not overlap the power supply line WVH1 and the power supply line WVH2. Thereby, it is possible to reduce the influence of noise from power supply line WVQ1 to power supply line WVH1 and power supply line WVH2.
- the power supply line WVQ2 does not overlap with the power supply line WVH1 and the power supply line WVH2. Thereby, it is possible to reduce noise influence from the power supply line WVQ2 to the power supply line WVH1 and the power supply line WVH2.
- power supply line WVQ1, power supply line WVQ2, and power supply line WVH1 are formed in the same wiring layer (for example, wiring layer MBL4 shown in FIG. 2).
- the power supply line WVH2 is formed in a wiring layer (for example, the wiring layer MBL3 shown in FIG. 2) different from the power supply line WVQ1, the power supply line WVQ2, and the power supply line WVH1.
- the power supply line WVH1 does not overlap with the power supply line WVQ1 and the power supply line WVQ2, but may overlap with the power supply line WVQ1 or the power supply line WVQ2 depending on the wiring layout of the power supply line WVH2.
- the power supply line WVH2 is provided so as to pass between the power supply line WVH1 and the power supply line WVQ2, depending on the respective wiring widths of the power supply line WVH2 and the power supply line WVQ2, a part of the power supply line WVH2 overlaps the power supply line WVQ2.
- a part of the power supply line WVH2 overlaps with a part of the power supply line WVQ2 (or power supply line WVQ1)
- the area of the overlapping part does not overlap with the power supply line WVQ2 (or power supply line WVQ1).
- the area is preferably smaller than the area of the portion.
- the separation distance PT2 between the memory chip M2 and the logic chip LC is larger than the separation distance PT1 between the memory chip M1 and the logic chip LC.
- the memory chip M2 has a wide gap (separation distance PT2) between the logic chip LC.
- the chip side Scp3 of the logic chip LC and the chip side Smc4 of the memory chip M2 are arranged.
- the space can be used as a space for the power line WVH2.
- the power supply line WVH2 is provided so as to straddle the chip side Scp3 of the logic chip LC. Thereby, the area of the region where power supply line WVH1 and power supply line WVH2 overlap can be further reduced.
- each of the power supply line WVH1 and the power supply line WVH2 through which a large current exceeding 5 amperes flows is the top surface of the plurality of wiring layers provided in the wiring board MB1. It is provided in a wiring layer other than the wiring layer MBL1 provided on the MBt side. In other words, each of the power supply line WVH1 and the power supply line WVH2 is provided in a wiring layer other than the wiring layer MBL1 closest to the semiconductor device PKG1. Thereby, the influence of electromagnetic noise (EMI: Electro-Magnetic Interference) on the semiconductor device PKG1 can be reduced.
- EMI Electro-Magnetic Interference
- Each of power supply line WVH1 and power supply line WVH2 through which a large current exceeding 5 amperes flows is formed in the inner layer (wiring layer other than wiring layer MBL1 and wiring layer MBL6 shown in FIG. 2) of wiring board MB1. Therefore, electromagnetic noise generated by the electronic device EDV1 can be reduced.
- FIG. 11 is an enlarged plan view showing a part of the wiring layer in which the power supply line is formed in the wiring board shown in FIG.
- FIG. 12 is an enlarged plan view showing the terminal array on the lower surface side of the wiring board shown in FIG.
- the opening WVh in the conductor pattern constituting the power supply line. Further, if the number of intersections between the power supply lines and the through-hole wirings WTH increases, the number of openings WVh formed in the conductor pattern constituting the power supply lines increases. If the opening WVh is increased, the plane area of the power supply line is reduced. Therefore, it is preferable to reduce the number of intersections between the power supply line and the through-hole wiring WTH as much as possible.
- the arrangement of the signal terminals CN is reduced as compared with other regions. ing.
- the plurality of terminals LD are arranged in a plurality of rows on the lower surface IPb of the wiring board IP1 along the outer periphery of the lower surface IPb.
- the plurality of terminals LD include a terminal LDVH1 and a terminal LDVH2 that supply a power supply potential to the logic chip LC, and a terminal LDVQ1 and a terminal LDVQ2 that supply a power supply potential to the memory chip MC.
- the plurality of terminals LD include terminals LDSG that transmit or receive electrical signals to the logic chip LC.
- the plurality of terminals LD include a terminal LDVS that supplies a reference potential to the logic chip LC and the memory chip MC.
- the lower surface IPb of the wiring board IP is mainly arranged with terminals LD for power supply potentials or terminals LDVS for reference potentials (the terminals LD for power supply potentials or the terminals LDVS for reference potentials are used for signals).
- a first terminal arrangement portion (arranged more than terminals LDSG).
- the lower surface IPb of the wiring board IP is mainly arranged with signal terminals LDSG (the LDVS signal terminals LDSG are arranged more than the number of power supply potential terminals LD and reference potential terminals LDVS.
- a second terminal array portion Since the signal terminals LD are mainly provided on the outer peripheral side of the lower surface IPb, the second terminal arrangement portion is provided on the outer peripheral side rather than the first terminal arrangement portion described above.
- the lower surface IPb that overlaps the region sandwiched between the power supply line WVQ1 and the power supply line WVQ2 Compared with the second region, the number of columns of the second terminal array portion is small.
- the number of columns of the second terminal array portion is one.
- the number of columns of the second terminal array portion is three.
- the number of columns of the second terminal array portion is one in a region overlapping any one of the power supply line WVH1 (see FIG. 4) and the power supply line WVH2 (see FIG. 4). ing.
- the first region of the lower surface IPb that overlaps any one of the power supply line WVH1, the power supply line WVH2, the power supply line WVQ1, and the power supply line WVQ2 is sandwiched between the power supply line WVQ1 and the power supply line WVQ2.
- the number of columns of the second terminal array portion is small.
- the signal terminal CN is reduced by reducing the arrangement of the signal terminals CN compared to other regions. While reducing the number of CNSGs, it is possible to suppress a reduction in the planar area of the power supply line. Thereby, for example, it becomes possible to supply power stably in response to a sudden change in the required power amount.
- the signal terminal CNSG is provided in a region overlapping with the power supply line WVH1, the power supply line WVH2, the power supply line WVQ1, or the power supply line WVQ2 shown in FIG. If not connected to the wiring WTH, the plane area of the power supply line is not affected.
- the signal terminal CNSG provided in the region overlapping with the power supply line WVH1, the power supply line WVH2, the power supply line WVQ1, or the power supply line WVQ2 is the wiring layer MBL shown in FIG. There is a case where it is routed and not connected to another wiring layer.
- FIG. 13 is an enlarged plan view showing a modification to FIG.
- FIG. 14 is an enlarged plan view showing an example of a terminal layout in a plan view of the motherboard shown in FIG.
- the semiconductor device PKG2 included in the electronic device EDV2 of the modification shown in FIG. 13 is that the semiconductor chip FMC is mounted between the chip side Scp1 and the substrate side Sip1 on the upper surface IPt of the wiring board IP1.
- the semiconductor chip FMC is a so-called nonvolatile memory chip including a nonvolatile memory circuit, and the nonvolatile memory circuit is electrically connected to the logic chip LC.
- a plurality of signal terminals CNSG are provided at positions overlapping with the semiconductor chip FMC, but most of the signal terminals CNSG are provided in the uppermost layer of the wiring board MB2.
- the wiring layers other than the wiring layer MBL1 are not connected and are routed by the wiring layer MBL1.
- the number of first terminals connected to a wiring layer other than the wiring layer MBL1 is larger than the number of second terminals not connected to a wiring layer other than the wiring layer MBL1. Few.
- the modified examples shown in FIGS. 13 and 14 can be considered from the following viewpoints. That is, when the number of semiconductor chips connected to the logic chip LC increases, it is necessary to mount the semiconductor chips so as to face each of the four sides of the logic chip LC. In this case, it becomes difficult to secure a lead-in path for the power supply line WVH1 and the power supply line WVH2 that supply the power supply potential to the logic chip LC.
- the semiconductor chip FMC connected mainly to the uppermost wiring layer MBL1 (see FIG. 2) among the plurality of wiring layers of the wiring board MB2, like the semiconductor chip FMC, the power supply line WVH1 and the power supply line There is little influence on the wiring width of WVH2. Therefore, the electronic device EDV2 can be downsized by allowing the space for mounting the semiconductor chip FMC and the power supply line WVH1 and the lead-in path of the power supply line WVH2 to the logic chip LC to overlap in the thickness direction. .
- FIG. 15 is an enlarged plan view showing the positional relationship between the extending direction of the power supply line and the through-hole wiring in the wiring board included in the electronic device of the modification example with respect to FIG.
- a wiring board MB3 included in the electronic device EDV shown in FIG. 15 is different from the wiring board MB1 shown in FIG. 11 in that the power supply line WVH1 or the power supply line WVH2 and the through-hole wiring WTH intersect at many places.
- the wiring board MB1 has a plurality of through-hole wirings WTH penetrating at least one of the power supply line WVH1 and the power supply line WVH2 in the thickness direction.
- the power supply line WVH1 or the power supply line WVH2 has a plurality of openings WVh provided at intersections with the plurality of through-hole wirings WTH.
- the plurality of through-hole wirings WTH and the plurality of openings WVh are arranged along the X direction that is the extending direction of the power supply line WVH1 or the power supply line WVH2. Further, among the plurality of openings WVh, the separation distance PTh1 between the openings WVh adjacent along the X direction is smaller than the separation distance PTh2 between the openings WVh adjacent along the Y direction orthogonal to the X direction. . In other words, the separation distance PTh2 is larger than the separation distance PTh1.
- the wiring width of the power supply line WVH1 or the power supply line WVH2 is reduced.
- the plurality of openings WVh so that the separation distance PTh2 is greater than the separation distance PTh1, it is possible to suppress a reduction in the cross-sectional area of the power supply path formed by the power supply line WVH1 or the power supply line WVH2. .
- the power supply line WVQ1 included in the wiring board MB1 does not overlap with the power supply line WVH1 and the power supply line WVH2. Thereby, it is possible to reduce the influence of noise from power supply line WVQ1 to power supply line WVH1 and power supply line WVH2.
- the power supply line WVQ2 does not overlap with the power supply line WVH1 and the power supply line WVH2. Thereby, it is possible to reduce noise influence from the power supply line WVQ2 to the power supply line WVH1 and the power supply line WVH2.
- the region overlapping the logic chip LC in the thickness direction is covered with the power supply line WVH2, so that each of the power supply line WVQ1 and the power supply line WVQ1 overlaps the logic chip LC in the thickness direction. Don't be.
- the power supply potential VDDQ1 and the power supply potential VDDQ2 are power supplies that drive the input / output circuit CAC between the logic chip LC and the memory chip MC.
- a part of the power supply potential VDDQ2 is also supplied to the logic chip LC.
- the semiconductor device PKG1 has a conductor pattern having a larger area than a normal wiring in one of the plurality of wiring layers (in the example of FIG. 16) of the wiring board IP1. Then, the power supply potential VDDQ1 and the power supply potential VDDQ2 shown in FIG. 6 are supplied through this conductor pattern.
- FIG. 16 is a plan view showing a layout example of conductor planes provided in one wiring layer of the wiring board shown in FIG.
- a conductor pattern (conductor film) having a relatively large area is referred to as a conductor plane among conductor patterns constituting an electric signal or power transmission path.
- a conductor plane that constitutes a supply path for the power supply potential is referred to as a power supply plane.
- a conductor plane constituting a reference potential supply path is referred to as a ground plane.
- the wiring board IP1 includes a power plane (conductor pattern) VQ1P that supplies a power supply potential VDDQ1 (see FIG. 6) to the logic chip LC and the memory chip M1. Further, the wiring board IP1 has a power plane (conductor pattern) VQ2P that supplies the power supply potential VDDQ2 (see FIG. 6) to the logic chip LC and the memory chip M2. The wiring board IP1 has a ground plane (conductor pattern) VSP that supplies the reference potential VSS (see FIG. 6) to the logic chip LC and the plurality of memory chips MC.
- the areas of the power plane VQ1P and the power plane VQ2P are larger than the plane areas of the plurality of memory chips MC.
- the resistance in the supply path of the power supply potential can be reduced.
- the power supply can be stabilized.
- the temperature rise of the semiconductor device PKG1 during driving can be suppressed, so that the circuit operation can be stabilized.
- each of the power plane VQ1P and the power plane VQ2P is formed so as to partially overlap the logic chip LC in the thickness direction. For this reason, the transmission distance from the logic chip LC to the power supply planes VQ1P and VQ2P can be reduced.
- the plurality of signal transmission paths included in the electronic device EDV1 of the present embodiment include the analog signal transmission path ANLP for inputting the analog signal SGANL to the logic chip LC as shown in FIG. .
- the semiconductor device PKG1 of the present embodiment has an analog circuit.
- FIG. 17 is an enlarged cross-sectional view schematically showing a configuration of a path for supplying a power supply potential to an analog circuit included in the semiconductor device shown in FIG.
- FIG. 18 is an enlarged cross-sectional view showing a study example for FIG.
- the plurality of terminals LD of the wiring board IP1 include terminals (analog power supply terminals) LDVA for supplying a power supply potential to the analog circuit described above.
- the terminal LDVA is electrically connected to the through-hole wiring WTH2 that penetrates the wiring board MB1 in the thickness direction via the solder ball SBp and the terminal CN.
- the terminal LD of the wiring board IP1 includes a terminal (power supply terminal) LDVH2 electrically connected to the power supply line WVH2 through the through-hole wiring WTH1.
- the terminal LDVA is electrically connected to the terminal LDVH2 through the through-hole wiring WTH1, the through-hole wiring WTH2, and the connection wiring WBY.
- the terminal LDVA is electrically connected to the power supply line WVH2 through the through-hole wiring WTH1, the through-hole wiring WTH2, and the connection wiring WBY.
- the analog power supply potential is supplied from the power supply line WVH2.
- FIG. 17 shows an embodiment in which the analog power supply potential is supplied from the power supply line WVH2 of the power supply line WVH1 and the power supply line WVH2 shown in FIG. It can also be supplied from the power supply line WVH1.
- the power supply line WVH2 is extended to the position of the through-hole wiring WTH2 as in the wiring board MBh shown in FIG. A method of directly connecting the wiring WTH2 is conceivable.
- connection wiring WBY that electrically connects the through-hole wiring WTH1 and the through-hole wiring WTH2 is lower than the wiring layer MBL3 and the wiring layer MBL4 (on the lower surface MBb side). ). Further, the connection wiring WBY is not provided in the wiring layer MBL3 and the wiring layer MBL4. Further, the connection wiring WBY is not provided in an upper layer (on the lower surface MBb side) than the wiring layer MBL3 and the wiring layer MBL4.
- FIG. 19 is an explanatory diagram showing an outline of the manufacturing process of the semiconductor device described with reference to FIGS. Note that FIG. 19 shows a process from manufacturing a semiconductor device to mounting it on a motherboard and manufacturing the electronic device shown in FIG.
- the manufacturing method a method of manufacturing the semiconductor device PKG1 for one layer by preparing the wiring board IP1 formed in advance in the product size will be described.
- a modification after preparing a so-called multi-chip substrate divided into a plurality of product formation regions and assembling each of the plurality of product formation regions, it is divided into product formation regions.
- the present invention can also be applied to a multi-cavity method that acquires a plurality of semiconductor devices. In this case, after the ball mounting process shown in FIG. 19 (flow diagram) or after the electrical test process, a singulation process for cutting the multi-piece substrate and dividing it into product formation regions is added.
- the wiring board IP1 shown in FIG. 20 is prepared.
- 20 is a plan view showing the chip mounting surface side of the wiring board prepared in the wiring board preparation step shown in FIG. 20 is the same as that obtained by removing the logic chip LC, the memory chip MC, the underfill resin UF, and the plurality of solder balls SBc and SBp shown in FIG. 7, and will be described with reference to FIG.
- the upper surface IPt of the wiring board IP1 includes a plurality of chip mounting areas DBA that are areas where a plurality of semiconductor chips are mounted in the semiconductor chip mounting step shown in FIG. 19 (flow diagram).
- the chip mounting area DBA is a planned area where the logic chip LC and the plurality of memory chips MC shown in FIG. 1 are mounted, and there may be no visible boundary line.
- a two-dot chain line is added to indicate the boundary of the chip mounting area DBA.
- a plurality of bonding pads TCS are formed in each of the plurality of chip mounting areas DBA.
- the plurality of bonding pads TCS are electrode terminals that are electrically connected to the logic chip LC and the memory chip MC via the protruding electrodes SBc shown in FIG. 7 in the die bonding mounting step shown in FIG. 19 (flow diagram).
- FIG. 20 shows an example in which the bonding pads TCS are arranged in rows and columns along the contour of the chip mounting area as an example of the arrangement of the bonding pads TCS. is there.
- the bonding pads TCS may be arranged along the periphery of the chip mounting area DBA, and the bonding pads TCS may not be formed in the center of the chip mounting area DBA.
- the method of manufacturing the wiring board IP1 having the core layer CR that is a core material is, for example, the upper surface side of the core layer CR with the core layer CR having a plurality of through-hole wirings TW formed as a base material. It can be manufactured by laminating a wiring layer on the bottom surface side by a build-up method. When the core material is not used, a wiring board can be manufactured by laminating a plurality of wiring layers on a base material (not shown) and then peeling the base material.
- FIG. 21 is a plan view showing a state in which a plurality of semiconductor chips are mounted on the wiring board shown in FIG. 20 is the same as that obtained by removing the plurality of solder balls SBc and the plurality of solder balls SBp shown in FIG. 7, and will be described with reference to FIG.
- the logic chip LC shown in FIG. 9 and the memory chip MC shown in FIG. 10 are prepared (semiconductor chip preparation step) and mounted on the chip mounting area DBA (see FIG. 20) of the wiring board IP1.
- mounting is performed by a so-called face-down mounting method in a state where the surface LCt (see FIG. 7) of the logic chip LC and the upper surface IPt of the wiring board IP1 face each other.
- mounting is performed by the face-down mounting method with the surface MCt (see FIG. 7) of the memory chip MC and the upper surface IPt of the wiring board IP1 facing each other.
- the plurality of electrodes PDL formed on the surface LCt side of the logic chip LC and the plurality of bonding pads TCS of the wiring board IP1 are respectively connected via the plurality of protruding electrodes SBc. Electrically connected. Further, as shown in FIG. 7, the plurality of electrodes PDM formed on the surface MCt side of the memory chip MC and the plurality of bonding pads TCS of the wiring board IP1 are electrically connected through the plurality of protruding electrodes SBc, respectively. Is done.
- a solder bump in which a solder material is formed into a spherical shape is often used as the plurality of protruding electrodes SBc.
- the protruding electrode SBc is not limited to a solder bump, and for example, a pillar bump formed of a metal material such as copper in a columnar shape may be used.
- underfill resin (insulating resin) UF is disposed between the logic chip LC and the wiring board IP1 and between the plurality of memory chips MC and the wiring board IP1.
- the underfill resin UF is disposed so as to seal an electrical connection portion between the semiconductor chip and the wiring board IP1 (joint portion between the plurality of protruding electrodes SBc).
- the underfill resin UF is disposed on the chip mounting area DBA (see FIG. 20) before mounting the semiconductor chip.
- the logic chip LC is pressed from above the underfill resin UF to electrically connect the wiring board IP1 and the logic chip LC.
- the underfill resin UF is cured.
- the resin material is arranged before mounting the semiconductor chip, not only the paste-like resin material as described above but also a film-like resin material can be used.
- the logic chip LC and the wiring board IP1 are electrically connected before the underfill resin UF is disposed. Thereafter, a liquid resin is injected into the gap between the logic chip LC and the wiring board IP1 and cured. In this step, either the above-described pre-bonding method or post-injection method may be used.
- the thickness of the memory chip MC (the separation distance between the front surface MCt and the back surface MCb) is larger than the thickness of the logic chip LC (the separation distance between the front surface LCt and the back surface LCb).
- the semiconductor chips it is preferable to mount the memory chip MC after mounting the relatively thin logic chip LC.
- a mounting jig (not shown) from coming into contact with the already mounted semiconductor chip.
- the logic chip LC is mounted first.
- the logic chip LC is mounted on the wiring board IP1 so that the chip side Scp1 is along the board side Sip1 of the wiring board IP1.
- the plurality of memory chips MC are respectively provided between the substrate side Sip2 of the wiring board IP1 and the chip side Scp2 of the logic chip LC, and between the substrate side Sip3 of the wiring board IP1 and the chip side Scp3 of the logic chip LC. Installed.
- solder balls SBp are attached to the lower surface IPb side of the wiring board IP1.
- the solder balls SBp are arranged on the terminals LD exposed from the insulating film SR2 shown in FIG. 7 and subjected to a reflow process (a process of heating and melting the solder components and then cooling them) to perform soldering.
- Ball SBp is joined to terminal LD.
- this step may be omitted when the solder ball SBp is not used as the conductive material for electrically connecting the wiring board MB1 and the semiconductor device PKG1 shown in FIG.
- a metal film such as a thin solder film may be formed on the exposed surface of the terminal LD instead of the solder ball SBp.
- the semiconductor device PKG1 that has passed the inspection is transported to the semiconductor device mounting process shown in FIG. 19 (flow diagram).
- a packing process for packing the semiconductor device PKG1 and a shipping process for shipping to another establishment are performed after the inspection process. Also good.
- the semiconductor device PKG1 is mounted on the wiring board MB1 as shown in FIG.
- the wiring board MB1 shown in FIG. 3 is prepared (mounting board preparation step), and the semiconductor device PKG1 shown in FIG. 1 is mounted on the upper surface MBt of the wiring board MB1.
- a plurality of terminals CN for connecting the semiconductor device PKG1 are formed on the upper surface (mounting surface) MBt of the wiring board MB1.
- the semiconductor device PKG1 includes a plurality of solder balls SBp that are external terminals.
- the power supply device (regulator) RGL1 may be mounted on the wiring board MB1 in advance at the stage of the mounting board preparation process. Alternatively, the power supply device RGL1 may be mounted immediately before mounting the semiconductor device PKG. Although the power supply device RGL1 can be mounted after mounting the semiconductor device PKG, as shown in FIG. 2, when the thickness of the power supply device RGL1 is thinner than the thickness of the semiconductor device PKG1, The supply device RGL1 is preferably mounted before the semiconductor device PKG1.
- the semiconductor device PKG1 is mounted on the side of the power supply device RGL1 mounted on the wiring board MB1, with the substrate side Sip1 of the wiring board IP1 included in the semiconductor device PKG1 facing.
- the plurality of solder balls SBp of the semiconductor device PKG1 are respectively joined to the plurality of terminals CN of the wiring board MB1, thereby electrically connecting the semiconductor device PKG1 and the wiring board MB1.
- a plurality of solder materials for example, cream solder
- the plurality of solder materials are brought into contact with the plurality of solder balls SBp of the semiconductor device PKG1.
- solder material and the solder ball SBp are integrated with each other by performing a heat treatment (reflow treatment) in a state where the solder material and the solder ball SBp are in contact with each other.
- a heat treatment reflow treatment
- the plurality of terminals LD of the semiconductor device PKG1 and the plurality of terminals CN of the wiring board MB1 are electrically connected through the plurality of solder balls SBp, respectively.
- an electronic component other than the semiconductor device PKG1 when mounted like the capacitor CC1 shown in FIG. 2, it can be mounted before the semiconductor device PKG is mounted or after the semiconductor device PKG1 is mounted.
- ⁇ Modification 1> For example, in the above-described embodiment, an example in which the logic chip LC and the two memory chips MC are mounted on the wiring board IP1 and no electronic component other than the semiconductor chip is mounted has been described. However, as a modification to the above embodiment, electronic components (including other semiconductor chips) other than the logic chip LC and the memory chip MC may be mounted.
- a capacitor (not shown) may be mounted.
- electronic components such as a capacitor (not shown) may be mounted.
- a bypass capacitor or a decoupling capacitor may be mounted on the wiring board IP1 as the termination power supply.
- the number of semiconductor chips mounted on the wiring board IP1 has various modifications other than the above embodiment.
- the number of memory chips MC differs in required storage capacity depending on the system provided in the semiconductor device PKG1. Since the value of the storage capacity increases in proportion to the number of memory chips MC, for example, the number of memory chips MC may be two or more, or one.
- a plurality of logic chips LC may be mounted on the upper surface IPt.
- a semiconductor chip having functions other than the logic chip LC and the memory chip MC may be mounted.
- FIG. 22 is a plan view showing an electronic device on which a semiconductor device which is a modified example of FIG. 1 is mounted.
- FIG. 23 is an enlarged plan view showing an example of a wiring layout in plan view of the motherboard shown in FIG.
- the semiconductor device PKG3 shown in FIG. 22 is different from the semiconductor device PKG1 shown in FIG. 1 in that four memory chips MC are mounted on the wiring board IP1.
- the memory chip M3 and the memory chip M4 newly added as compared with FIG. 1 are mounted between the memory chip M1 and the logic chip LC and the substrate side Sip3, respectively.
- the memory chip M3 is mounted between the chip side Smc3 of the memory chip M1 and the substrate side Sip3.
- the memory chip M4 is mounted between the chip side Scp3 of the logic chip LC and the substrate side Sip3.
- the memory chips M2, M3, and M4 are mounted side by side between the extension line of the chip side Scp3 of the logic chip LC and the substrate side Sip3.
- the memory chip M1 and the memory chip M3 are mounted so as to be aligned along the Y direction.
- the semiconductor device PKG3 includes a plurality of memory chips M1, M2, M3, and M4, and each of the plurality of memory chips M1, M2, M3, and M4 is connected to the chip side Scp2 of the logic chip LC in a plan view. It is mounted in a concentrated manner between the substrate side Sip2 of the substrate IP1 and between the chip side Scp3 of the logic chip LC and the substrate side Sip3 of the wiring substrate IP1.
- the above embodiment is applied even if the number of memory chips MC is three or more. The technique described in the above can be similarly applied.
- the power supply potential VDDQ1 (see FIG. 5) is supplied to the memory chip M1 and the memory chip M3 via the power supply line WVQ1. Further, the power supply potential VDDQ2 (see FIG. 5) is supplied to the memory chip M2 and the memory chip M4 through the power supply line WVQ2.
- a part of the power supply line WVQ2 and a part of the power supply line WVH2 may overlap each other due to the layout restriction of the memory chips M2 and M4.
- the power supply line WVH2 is provided so as to pass between the power supply line WVH1 and the power supply line WVQ2, the area where the power supply line WVH2 and the power supply line WVQ2 overlap can be reduced. it can.
- the separation distance PT2 between the memory chip M2 and the logic chip LC is larger than the separation distance PT1 between the memory chip M1 and the logic chip LC.
- the separation distance PT3 between the memory chip M4 and the logic chip LC is larger than the separation distance PT1 between the memory chip M1 and the logic chip LC.
- each of the memory chip M2 and the memory chip M4 has a wide gap (separation distance PT2) between the logic chip LC.
- the area of the power supply line WVH2 that overlaps with the power supply line WVQ2 in the thickness direction is the area of the power supply line WVH2 that does not overlap with the power supply line WVQ2. Is smaller than the area.
- FIG. 24 is an enlarged cross-sectional view illustrating a configuration example of an electronic device that is a modification example of FIG. 2.
- the logic chip LC included in the electronic device EDV5 shown in FIG. 24 is mounted on the upper surface IPt of the wiring board IP1 via the wiring board IP2, which is an interposer different from the wiring board IP1.
- the logic package LCP in which the logic chip LC is mounted on the wiring board IP2 is mounted on the upper surface IPt of the wiring board IP1.
- the description relating to the logic chip LC described in the above embodiment may be replaced with a logic package LCP incorporating the logic chip LC as shown in FIG.
- the plurality of electrodes PDL shown in FIG. 7 are made of, for example, a material mainly composed of copper (Cu).
- FIG. 24 as an example of a semiconductor package mounted on the wiring board IP1, a logic package LPC that typically includes a logic chip LC has been described.
- a memory package (semiconductor package) incorporating the memory chip MC shown in FIG. 7 may be mounted. That is, the memory chip MC shown in FIG. 7 may be replaced with a memory package.
- the plurality of electrodes PDM shown in FIG. 7 are made of a material mainly composed of copper (Cu).
- either one or both of the logic package LCP and the memory package may be mounted.
- FIG. 25 is an explanatory view showing a modified example of the manufacturing process shown in FIG. 19 (flow diagram).
- PoP Package on Package
- the lower side semiconductor device and the upper side semiconductor device may be manufactured by different manufacturers, and the business operator who purchased the semiconductor device from each manufacturer may perform final assembly.
- the assembly flow is as shown in FIG. That is, in the semiconductor device manufacturing process, the logic chip LC is mounted on the wiring board IP1 shown in FIG. 2, and the memory chip MC is inspected and shipped without being mounted. Further, for example, another manufacturer manufactures a memory package in which the memory chip MC is mounted on the wiring board (memory chip preparation step). Next, a semiconductor device on which the logic chip LC is mounted and an operator who has purchased the memory package each mount the memory package on the wiring board IP1. Thereafter, the semiconductor device on which the memory package is mounted is mounted on the wiring board MB shown in FIG. Through the above process, a semiconductor device manufactured by the PoP method and an electronic device on which the semiconductor device is mounted are obtained.
- ANLP Analog signal transmission path CAC I / O circuit CC1 Capacitor ChA0, ChA1, ChB0, ChB1 Channel CKP1, CKP2 Clock signal transmission path CN, CN1, CN2, CN3, CNSG, CNVH1, CNVH2, CNVQ1, CNVQ2, CNVS terminal (CNVSQ terminal) ) CR core layer (core material, core insulation layer) CTL control circuit CTP1, CTP2 Control signal transmission path DBA Chip mounting area DTP1, DTP2 Data signal transmission path EDV1, EDV2, EDV3, EDV4, EDV5 Electronic device (electronic equipment) FMC semiconductor chip (nonvolatile memory chip) IIF Internal interface electrode (interface terminal) IL Insulation layer IP1, IP2 Wiring board (interposer) IPb bottom surface (surface, main surface, mounting surface) IPs Side surface IPt Upper surface (surface, main surface, chip mounting surface) LC logic chip (semiconductor chip) LCb, MCb Back (Main
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Abstract
Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
本実施の形態では、複数の半導体チップが配線基板を介して電気的に接続された半導体装置、および上記半導体装置が搭載された電子装置、の一例として、カーナビゲーション装置の内部に搭載される半導体装置、および上記半導体装置を有するモジュール(電子装置)を取り上げて説明する。
まず、本実施の形態の電子装置の構成例について説明する。図1は、本実施の形態の電子装置の構成例を示す拡大平面図である。また、図2は、図1のA-A線に沿った断面において、電子装置が有する構成部品の電気的な接続関係を示す説明図である。また、図3は、図1に示すマザーボードの平面視における配線レイアウトの例を示す拡大平面図である。また、図4は、図1に示すマザーボードの平面視における端子レイアウトの例を示す拡大平面図である。また、図5は、図4に示す複数の端子の周辺を拡大して示す拡大断面図である。
図1および図2に示すように、本実施の形態の電子装置EDV1は、配線基板MB1の上面MBt上に搭載される、半導体装置PKG1を有する。以下、半導体装置PKG1の詳細な構成について説明する。本セクションでは、まず、半導体装置PKG1の回路構成例を説明した後、半導体装置PKG1の構造について説明する。図6は、図1に示す半導体装置が有する複数の半導体チップと電気的に接続される複数の伝送経路の構成の概要を示す説明図である。
次に、半導体装置PKG1の構造について説明する。図7は、図1に示す半導体装置のB-B線に沿った断面図である。また、図8は、図1に示す半導体装置の下面側の構造を示す平面図である。また、図9は、図1に示すロジックチップの表面側の平面図である。また、図10は、図1に示すメモリチップの表面側の平面図である。
次に、上記した電子装置EDV1(図1参照)が有する半導体装置PKG1の電源電位供給経路と、信号伝送経路とのレイアウトについて詳細に説明する。まず、本実施の形態のように、一つの半導体パッケージ内に複数のシステムを作りこみ、かつ、電気的な特性を向上させるためには、複数のシステムの電力需要に応じて、安定的に電力を供給する必要がある。
次に、図1~図18を用いて説明した半導体装置PKG1の製造工程について説明する。半導体装置PKG1は、図19(フロー図)に示すフローに沿って製造される。図19(フロー図)は、図1~図18を用いて説明した半導体装置の製造工程の概要を示す説明図である。なお、図19では、半導体装置を製造した後、マザーボードに搭載し、図1に示す電子装置を製造する工程までを記載している。
まず、図19に示す配線基板準備工程では、図20に示す配線基板IP1を準備する。図20は、図19に示す配線基板準備工程で準備する配線基板のチップ搭載面側を示す平面図である。なお、図20の断面は、図7に示すロジックチップLC、メモリチップMC、アンダフィル樹脂UF、および複数の半田ボールSBc、SBpを取り除いたものと同様なので、図7を参照して説明する。
次に、図19(フロー図)に示すダイボンド工程では、図21に示すように、配線基板IP1の上面IPtにロジックチップLCおよび複数のメモリチップMCを搭載する。図21は、図20に示す配線基板に複数の半導体チップを搭載した状態を示す平面図である。なお、図20の断面は、図7に示す複数の半田ボールSBcおよび複数の半田ボールSBpを取り除いたものと同様なので、図7を参照して説明する。
次に、図19(フロー図)に示すボールマウント工程では、図7に示すように、配線基板IP1の下面IPb側に、複数の半田ボールSBpを取り付ける。本工程では、図7に示す絶縁膜SR2から露出する端子LD上に半田ボールSBpを配置して、リフロー処理(加熱して半田成分を溶融接合させた後、冷却する処理)を施すことにより半田ボールSBpが端子LDに接合される。なお、図1に示す配線基板MB1と半導体装置PKG1を電気的に接続する導電性材料として半田ボールSBpを用いない場合、本工程は省略することもできる。あるいは、本工程において、半田ボールSBpに代えて、端子LDの露出面に、薄い半田膜などの金属膜を形成しても良い。
次に、図19(フロー図)に示す検査工程では、図19(フロー図)に示すボールマウント工程で、複数の半田ボールSBpが接合された検査体の検査を行う。本工程では、外観検査や、検査体に形成された回路の電気的な試験を行う。また、本工程では、予め準備された検査項目毎の評価基準に基づいて検査体の合否を判定する。そして、合格と判定された検査体が図7に示す半導体装置PKG1として取得される。
次に、図19(フロー図)に示す半導体装置実装工程では、図1に示すように配線基板MB1上に、半導体装置PKG1を搭載する。本工程では、図3に示す配線基板MB1を準備して(実装基板準備工程)、配線基板MB1の上面MBt上に図1に示す半導体装置PKG1を搭載する。
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。なお、上記実施の形態中でも複数の変形例について説明したが、以下では、上記以外の変形例について説明する。
例えば、上記実施の形態では、配線基板IP1上に、ロジックチップLCおよび2個のメモリチップMCが搭載され、半導体チップ以外の電子部品が搭載されていない例を取り上げて説明した。しかし、上記実施の形態に対する変形例としては、ロジックチップLCおよびメモリチップMC以外の電子部品(他の半導体チップも含む)を搭載しても良い。
また上記実施の形態では、配線基板IP1上に、ロジックチップLCおよび2個のメモリチップMCが搭載され、半導体チップ以外の電子部品が搭載されていない例を取り上げて説明した。しかし、配線基板IP1上に搭載される半導体チップの数は、上記実施の形態以外にも種々の変形例がある。特に、メモリチップMCの数は、半導体装置PKG1に設けられたシステムに応じて必要な記憶容量が異なる。記憶容量の値は、メモリチップMCの数に比例して大きくなるので、例えば、メモリチップMCの数は、2個以上、あるいは1個でも良い。また、上面IPt上に複数のロジックチップLCを搭載しても良い。また、ロジックチップLCおよびメモリチップMC以外の機能を備える半導体チップを搭載しても良い。
また上記実施の形態では、半導体装置PKG1の例として、配線基板IP1上に、半導体チップをフェイスダウン実装方式により実装する実施態様を説明した。しかし、図7に示すロジックチップLCや、図7に示すメモリチップMCは、パッケージ基板である配線基板IP1上に直接搭載する場合の他、インタポーザを介して配線基板IP1上に搭載されていても良い。一例として、図2に対する変形例として、図2に示すロジックチップLCを配線基板IP1とは別のインタポーザ用の配線基板を介して配線基板IP1上に搭載した実施態様を説明する。図24は、図2に対する変形例である電子装置の構成例を示す拡大断面図である。
また、例えば、上記の通り種々の変形例について説明したが、上記で説明した各変形例同士を組み合わせて適用することができる。
CAC 入出力回路
CC1 コンデンサ
ChA0、ChA1、ChB0、ChB1 チャネル
CKP1、CKP2 クロック信号伝送経路
CN、CN1、CN2、CN3、CNSG、CNVH1、CNVH2、CNVQ1、CNVQ2、CNVS 端子(実装基板端子)
CR コア層(コア材、コア絶縁層)
CTL 制御回路
CTP1、CTP2 制御信号伝送経路
DBA チップ搭載領域
DTP1、DTP2 データ信号伝送経路
EDV1、EDV2、EDV3、EDV4、EDV5 電子装置(電子機器)
FMC 半導体チップ(不揮発性メモリチップ)
IIF 内部インタフェース電極(インタフェース端子)
IL 絶縁層
IP1、IP2 配線基板(インタポーザ)
IPb 下面(面、主面、実装面)
IPs 側面
IPt 上面(面、主面、チップ搭載面)
LC ロジックチップ(半導体チップ)
LCb、MCb 裏面(主面、下面)
LCP ロジックパッケージ
LCs、MCs 側面
LCt、MCt 表面(主面、上面)
LD、LD1、LD2、LDSG、LDVA、LDVH1、LDVH2、LDVQ1、LDVQ2、LDVS 端子(ランド、外部接続端子)
M1、M2、M3、M4、MC メモリチップ(半導体チップ)
MB1、MB2、MB3、MBh 配線基板(マザーボード、実装基板)
MBb 下面(面、裏面)
MBL1、MBL2、MBL3、MBL4、MBL5、MBL6、WL1、WL2、WL3、WL4、WL5、WL6、WL7、WL8、WL9、WL10 配線層
MBt 上面(面、半導体装置搭載面)
OIF 外部インタフェース電極(インタフェース端子)
PDL、PDM 電極(チップ端子、ボンディングパッド)
PKG1、PKG2、PKG3 半導体装置
PRC 演算処理回路
PT1、PT2、PT3、PTh1、PTh2 離間距離
RAM メモリ回路(記憶回路)
RGL1 電力供給装置(レギュレータ)
SBc 突起電極(バンプ電極)
SBp 半田ボール(半田材、外部端子、電極、外部電極)
Scp1、Scp2、Scp3、Scp4、Smc1、Smc2、Smc3、Smc4 チップ辺
SGANL アナログ信号
SGCLK1、SGCLK2 クロック信号
SGCTL1、SGCTL2 制御信号
SGDAT1、SGDAT2 データ信号
SGP1、SGP2 信号伝送経路
Sip1、Sip2、Sip3、Sip4 基板辺
SR1、SR2、SR3 絶縁膜
SRk1、SRk2 開口部
TCS ボンディングパッド(ボンディングリード、半導体チップ接続用端子)
THW、TW スルーホール配線
UF アンダフィル樹脂(絶縁性樹脂)
VA ビア
VDDH1、VDDH2、VDDQ1、VDDQ2 電源電位
VDH1P、VDH2P、VDQ1P、VDQ2P 電源電位供給経路
VQ1P、VQ2P 電源プレーン(電源用導体パターン)
VSP グランドプレーン(導体パターン)
VSS 基準電位
VSSP 基準電位供給経路
WBY 連結配線
Wh1、Wh2、Wq1、Wq2、Wsg 配線幅
WM 配線(実装基板配線、マザーボード配線)
WR 配線
WSG 信号線
WTH WTH1、WTH2 スルーホール配線
WVh 開口部
WVH1、WVH2、WVQ1、WVQ2 電源線(配線)
WVS 基準電位線 (配線)
Claims (19)
- 第1面および前記第1面の反対側に位置する第2面を有する第1配線基板と、
第3面、前記第3面の反対側に位置する第4面、および前記第4面に形成された複数の端子を有する第2配線基板と、前記第2配線基板の前記第3面上に搭載された複数の第1半導体チップと、前記第2配線基板の前記第3面上において前記複数の第1半導体チップと並べて搭載され、かつ、前記複数の第1半導体チップのそれぞれを制御する回路を備える第2半導体チップと、を備え、前記第1配線基板の前記第1面上に搭載された半導体装置と、
を含み、
平面視において、前記第2配線基板の周縁部は、第1基板辺、前記第1基板辺の反対側に位置する第2基板辺、前記第1基板辺および前記第2基板辺と交差する第3基板辺、および前記第3基板辺の反対側に位置する第4基板辺を有し、
平面視において、前記第2半導体チップの周縁部は、第1チップ辺、前記第1チップ辺の反対側に位置する第2チップ辺、前記第1チップ辺および前記第2チップ辺と交差する第3チップ辺、および前記第3チップ辺の反対側に位置する第4チップ辺を有し、
前記第2半導体チップは、前記第2半導体チップの前記第1チップ辺が、前記第2配線基板の第1基板辺と並び、かつ、前記第2半導体チップの前記第3チップ辺が、前記第2配線基板の第3基板辺と並ぶように前記第2配線基板上に搭載され、
前記複数の第1半導体チップのうちの一部は、前記第2半導体チップの前記第2チップ辺と前記第2配線基板の前記第2基板辺との間に搭載され、
前記複数の第1半導体チップのうちの他の一部は、前記第2半導体チップの前記第3チップ辺と前記第2配線基板の前記第3基板辺との間に搭載され、
前記第2半導体チップの前記第4チップ辺と前記第2配線基板の前記第4基板辺との間には、複数の信号配線が形成され、
前記第1配線基板は、前記第2半導体チップに第1電源電位を供給する第1電源線と、前記第2半導体チップに前記第1電源電位よりも大きい第2電源電位を供給する第2電源線と、を有し、
平面視において、前記第2電源線は、前記第2配線基板の前記第1基板辺および前記第2半導体チップの前記第1チップ辺を跨ぐように配置され、
平面視において、前記第1電源線は、前記第2電源線と前記複数の第1半導体チップのうちの一部との間を通って前記第2半導体チップと重なる領域に向かって延びるように配置され、
前記第1電源線のうち、前記第2電源線と厚さ方向に重なる領域の面積は、前記第1電源線のうち、前記第2電源線と重ならない領域の面積よりも小さい、電子装置。 - 請求項1において、
前記第1配線基板は、前記複数の第1半導体チップのうちの一部に第3電源電位を供給する第3電源線と、前記複数の第1半導体チップのうちの他の一部に第4電源電位を供給する第4電源線と、を有し、
平面視において、前記第3電源線および前記第4電源線のそれぞれは、前記第2配線基板の前記第3基板辺を跨ぐように配置され、
前記第3電源線および前記第4電源線のそれぞれは、前記第2半導体チップと厚さ方向に重ならない、電子装置。 - 請求項2において、
前記第3電源線は、前記第1電源線および前記第2電源線と厚さ方向に重ならない、電子装置。 - 請求項3において、
前記第4電源線は、前記第1電源線および前記第2電源線と厚さ方向に重ならない、電子装置。 - 請求項3において、
前記第4電源線は、前記第1電源線の一部と厚さ方向に重なり、かつ、前記第2電源線とは厚さ方向に重ならず、
前記第2電源線のうち、前記第4電源線と厚さ方向に重なる領域の面積は、前記第2電源線のうち、前記第4電源線と重ならない領域の面積よりも小さい、電子装置。 - 請求項3において、
前記第3電源電位は、前記第1電源電位および前記第2電源電位のそれぞれよりも大きい、電子装置。 - 請求項1において、
前記第2電源線の配線幅は、前記第1電源線の配線幅よりも大きい、電子装置。 - 請求項1において、
前記第2半導体チップの前記第4チップ辺と前記第2配線基板の前記第4基板辺との間に形成された前記複数の信号配線には、アナログ信号が供給される複数のアナログ信号配線が含まれる、電子装置。 - 請求項1において、
前記複数の第1半導体チップのうち、前記第2半導体チップの前記第2チップ辺と前記第2配線基板の前記第2基板辺との間に搭載された第1半導体チップは、前記第2半導体チップとの間に第1離間距離を有し、
前記複数の第1半導体チップのうち、前記第2半導体チップの前記第3チップ辺と前記第2配線基板の前記第3基板辺との間に搭載された第1半導体チップは、前記第2半導体チップとの間に第2離間距離を有し、
前記第2離間距離は、前記第1離間距離よりも大きく、
前記第1電源線は、前記第2半導体チップの前記第3チップ辺を跨ぐように配置されている、電子装置。 - 請求項1において、
前記第1配線基板は、複数の配線層を有し、
前記第1電源線および前記第2電源線のそれぞれは、前記複数の配線層のうち、最も前記第1面側に設けられた第1配線層以外の配線層に形成されている、電子装置。 - 請求項2において、
前記第2配線基板の前記第4面に、前記第4面の外周に沿って複数列で配列される前記複数の端子は、
前記第1電源電位、前記第2電源電位、前記第3電源電位、および前記第4電源電位を含む電源電位が供給される電源電位用端子と、
基準電位が供給される基準電位用端子と、
電気信号が伝送される信号用端子と、
を有し、
前記複数の端子の前記第4面は、
前記複数の端子のうち、前記電源電位用端子または前記基準電位用端子の方が、前記信号用端子よりも多く配列される第1端子配列部と、
前記第1端子配列部よりも前記第4面の外周側に設けられ、複数の前記信号用端子が前記電源電位用端子および前記基準電位用端子の数以上に配列される第2端子配列部と、
を有し、
前記第3電源線および前記第4電源線のうちのいずれかと重なる前記第4面の第1領域では、前記第3電源線と前記第4電源線との間に挟まれた領域と重なる前記第4面の第2領域と比較して、第2端子配列部の列数が少ない、電子装置。 - 請求項1において、
前記第1配線基板は、前記複数の第1半導体チップのうちの一部に第3電源電位を供給する第3電源線と、前記複数の第1半導体チップのうちの他の一部に第4電源電位を供給する第4電源線と、を有し、
前記第2配線基板の前記第4面に、前記第4面の外周に沿って複数列で配列される前記複数の端子は、
前記第1電源電位、前記第2電源電位、前記第3電源電位、および前記第4電源電位を含む電源電位が供給される電源電位用端子と、
基準電位が供給される基準電位用端子と、
電気信号が伝送される信号用端子と、
を有し、
前記複数の端子の前記第4面は、
前記複数の端子のうち、前記電源電位用端子または前記基準電位用端子の方が、前記信号用端子よりも多く配列される第1端子配列部と、
前記第1端子配列部よりも前記第4面の外周側に設けられ、複数の前記信号用端子が前記電源電位用端子および前記基準電位用端子の数以上に配列される第2端子配列部と、
を有し、
前記第1電源線、前記第2電源線、前記第3電源線、前記第4電源線のうちのいずれかと重なる前記第4面の第1領域では、前記第3電源線と前記第4電源線との間に挟まれた領域と重なる前記第4面の第2領域と比較して、第2端子配列部の列数が少ない、電子装置。 - 請求項1において、
前記半導体装置は、
前記第2配線基板の前記第3面において、前記第2半導体チップの前記第1チップ辺と前記第2配線基板の前記第1基板辺との間には、前記第1電源線または前記第2電源線と厚さ方向に重なる位置に搭載され、前記第1半導体チップと電気的に接続される第3半導体チップを有し、
前記第3半導体チップは、前記第2配線基板の前記第4面に形成された前記複数の端子のうちの複数の第3半導体チップ用端子と電気的に接続され、
前記第1配線基板は、前記第1電源線が設けられた第1配線層、および前記第2電源線が設けられた第2配線層、および前記第1面の最も近くに設けられた第1面側配線層を含む複数の配線層を有し、
前記複数の第3半導体チップ用端子のうち、前記第1面側配線層以外の配線層に接続される第1端子の数は、前記第1面側配線層以外の配線層に接続されない第2端子の数よりも少ない、電子装置。 - 請求項1において、
前記第1配線基板は、前記第1電源線または前記第2電源線を厚さ方向に貫通する複数のスルーホール配線を有し、
前記第1電源線または前記第2電源線には、前記複数のスルーホール配線との交差部分に、前記第1電源線または前記第2電源線が延在する第1方向に沿って配列された複数の開口部が設けられ、
前記複数の開口部のうち、前記第1方向に沿って隣り合う開口部間の第1離間距離は、前記第1方向に直交する第2方向に沿って隣り合う開口部間の第2離間距離よりも小さい、電子装置。 - 請求項2において、
前記第2配線基板は、
前記第2半導体チップに前記第3電源電位を供給する第3電源電位供給経路と、
前記第2半導体チップに前記第4電源電位を供給する第4電源電位供給経路と、
を備え、
前記第3電源電位供給経路および前記第4電源電位供給経路のそれぞれには、前記複数の第1半導体チップのそれぞれの平面積よりも大きい面積を有する導体パターンが含まれる、電子装置。 - 請求項15において、
前記第3電源電位供給経路を構成する第1導体パターンおよび前記第3電源電位供給経路を構成する第2導体パターンのそれぞれは、前記第2半導体チップと厚さ方向に重なっている、電子装置。 - 請求項1において、
前記第2配線基板の前記複数の端子は、
前記第1配線基板を厚さ方向に貫通する第1スルーホール配線を介して前記第1電源線または前記第2電源線に接続される第1電源端子と、
前記第2半導体チップが備えるアナログ回路に電源電位を供給するアナログ用電源端子と、
を含み、
前記第1配線基板は、前記第1電源線が設けられた第1配線層、および前記第2電源線が設けられた第2配線層を含む複数の配線層を有し、
前記アナログ用電源端子は、前記第1配線基板を厚さ方向に貫通する第2スルーホール配線、および前記第1スルーホール配線と前記第2スルーホール配線とを連結する連結配線を介して前記第1電源端子と電気的に接続され、
前記連結配線は、前記第1配線層の前記複数の配線層のうち、前記第1配線層および前記第2配線層よりも前記第2面側の配線層に設けられ、かつ、前記第1配線層と、前記第2配線層と、前記第1配線層および前記第2配線層よりも前記第1面側の配線層と、には設けられていない、電子装置。 - 第1面および前記第1面の反対側に位置する第2面を有する第1配線基板と、
第3面、前記第3面の反対側に位置する第4面、および前記第4面に形成された複数の端子を有する第2配線基板と、前記第2配線基板の前記第3面上に搭載された複数の第1半導体チップと、前記第2配線基板の前記第3面上において前記複数の第1半導体チップと並べて搭載され、かつ、前記複数の第1半導体チップのそれぞれを制御する回路を備える第2半導体チップと、を備え、前記第1配線基板の前記第1面上に搭載された半導体装置と、
を含み、
平面視において、前記第2配線基板の周縁部は、第1基板辺、前記第1基板辺の反対側に位置する第2基板辺、前記第1基板辺および前記第2基板辺と交差する第3基板辺、および前記第3基板辺の反対側に位置する第4基板辺を有し、
平面視において、前記第2半導体チップの周縁部は、第1チップ辺、前記第1チップ辺の反対側に位置する第2チップ辺、前記第1チップ辺および前記第2チップ辺と交差する第3チップ辺、および前記第3チップ辺の反対側に位置する第4チップ辺を有し、
前記第2半導体チップは、前記第2半導体チップの前記第1チップ辺が、前記第2配線基板の第1基板辺と並び、かつ、前記第2半導体チップの前記第3チップ辺が、前記第2配線基板の第3基板辺と並ぶように前記第2配線基板上に搭載され、
前記複数の第1半導体チップのうちの一部は、前記第2半導体チップの前記第2チップ辺と前記第2配線基板の前記第2基板辺との間に搭載され、
前記複数の第1半導体チップのうちの他の一部は、前記第2半導体チップの前記第3チップ辺と前記第2配線基板の前記第3基板辺との間に搭載され、
前記第2半導体チップの前記第4チップ辺と前記第2配線基板の前記第4基板辺との間には、複数の信号配線が形成され、
前記第1配線基板は、前記第2半導体チップに第1電源電位を供給する第1電源線と、前記第1電源線よりも広い配線幅を備え、前記第2半導体チップに第2電源電位を供給する第2電源線と、を有し、
平面視において、前記第2電源線は、前記第2配線基板の前記第1基板辺および前記第2半導体チップの前記第1チップ辺を跨ぐように配置され、
平面視において、前記第1電源線は、前記第2電源線と前記複数の第1半導体チップのうちの一部との間を通って前記第2半導体チップと重なる領域に向かって延びるように配置され、
前記第1電源線のうち、前記第2電源線と厚さ方向に重なる領域の面積は、前記第1電源線のうち、前記第2電源線と重ならない領域の面積よりも小さい、電子装置。 - 第1面および前記第1面の反対側に位置する第2面を有する第1配線基板と、
第3面、前記第3面の反対側に位置する第4面、および前記第4面に形成された複数の端子を有する第2配線基板と、前記第2配線基板の前記第3面上に搭載された複数の第1半導体チップと、前記第2配線基板の前記第3面上において前記複数の第1半導体チップと並べて搭載され、かつ、前記複数の第1半導体チップのそれぞれを制御する回路を備える第2半導体チップと、を備え、前記第1配線基板の前記第1面上に搭載された半導体装置と、
を含み、
平面視において、前記第2配線基板の周縁部は、第1基板辺、前記第1基板辺の反対側に位置する第2基板辺、前記第1基板辺および前記第2基板辺と交差する第3基板辺、および前記第3基板辺の反対側に位置する第4基板辺を有し、
平面視において、前記第2半導体チップの周縁部は、第1チップ辺、前記第1チップ辺の反対側に位置する第2チップ辺、前記第1チップ辺および前記第2チップ辺と交差する第3チップ辺、および前記第3チップ辺の反対側に位置する第4チップ辺を有し、
前記第2半導体チップは、前記第2半導体チップの前記第1チップ辺が、前記第2配線基板の第1基板辺と並び、かつ、前記第2半導体チップの前記第3チップ辺が、前記第2配線基板の第3基板辺と並ぶように前記第2配線基板上に搭載され、
前記複数の第1半導体チップのうちの一部は、前記第2半導体チップの前記第2チップ辺と前記第2配線基板の前記第2基板辺との間に搭載され、
前記複数の第1半導体チップのうちの他の一部は、前記第2半導体チップの前記第3チップ辺と前記第2配線基板の前記第3基板辺との間に搭載され、
前記第2半導体チップの前記第4チップ辺と前記第2配線基板の前記第4基板辺との間には、複数の信号配線が形成され、
前記第1配線基板は、前記第2半導体チップに第1電流を供給する第1電源線と、前記第2半導体チップに前記第1電流よりも大きい第2電流を供給する第2電源線と、を有し、
平面視において、前記第2電源線は、前記第2配線基板の前記第1基板辺および前記第2半導体チップの前記第1チップ辺を跨ぐように配置され、
平面視において、前記第1電源線は、前記第2電源線と前記複数の第1半導体チップのうちの一部との間を通って前記第2半導体チップと重なる領域に向かって延びるように配置され、
前記第1電源線のうち、前記第2電源線と厚さ方向に重なる第1領域の面積は、前記第1電源線のうち、前記第2電源線と重ならない第2領域の面積よりも小さい、電子装置。
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JP2017524561A JP6317855B2 (ja) | 2015-06-26 | 2015-06-26 | 電子装置 |
TW105112492A TW201712845A (en) | 2015-06-26 | 2016-04-21 | Electronic device |
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