WO2016199634A1 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- WO2016199634A1 WO2016199634A1 PCT/JP2016/066155 JP2016066155W WO2016199634A1 WO 2016199634 A1 WO2016199634 A1 WO 2016199634A1 JP 2016066155 W JP2016066155 W JP 2016066155W WO 2016199634 A1 WO2016199634 A1 WO 2016199634A1
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- WIPO (PCT)
- Prior art keywords
- conductive cap
- conductive
- semiconductor device
- ground pad
- outer peripheral
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 134
- 238000000034 method Methods 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 16
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- 229910000881 Cu alloy Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
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- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
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- 239000011889 copper foil Substances 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000005242 forging Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- ZBTDWLVGWJNPQM-UHFFFAOYSA-N [Ni].[Cu].[Au] Chemical compound [Ni].[Cu].[Au] ZBTDWLVGWJNPQM-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000010946 fine silver Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
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- 239000002245 particle Substances 0.000 description 1
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- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/1631—Structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a conductive cap that covers a semiconductor element and a manufacturing method thereof.
- Some semiconductor devices include a semiconductor element mounted on the main surface of a substrate covered with a conductive cap.
- the conductive cap is bonded to a ground pad provided on the main surface so as to surround the semiconductor element by a conductive bonding member. With such a structure, an electric field outside the conductive cap can be shielded, and an internal semiconductor element can be protected.
- the conductive bonding member flows out to the inside of the conductive cap to short-circuit the semiconductor element and the signal pad, or the conductive bonding member is scattered to the inside of the conductive cap to break the bonding wire. There are things to do.
- Patent Document 1 Japanese Patent No. 5277755 discloses a semiconductor device having a structure for suppressing the conductive bonding member from flowing into the conductive cap.
- the inner peripheral side of the bonding pad (ground electrode) is covered with a solder resist (covering member).
- a pressing portion for the conductive cap is disposed on the upper surface of the solder resist. For this reason, it is suppressed that a conductive joining member flows out inside a conductive cap by blocking a conductive joining member with a soldering resist.
- the conductive bonding member may flow out to the inside of the conductive cap through the space between the upper surface of the solder resist and the pressing portion of the conductive cap. Therefore, in the semiconductor device described in the above publication, the conductive bonding member cannot be sufficiently prevented from flowing out inside the conductive cap.
- the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can sufficiently prevent the conductive bonding member from flowing into the conductive cap.
- the semiconductor device of the present invention includes a substrate, a semiconductor element, a ground pad, an insulating coating member, a conductive bonding member, and a conductive cap.
- the substrate has a main surface.
- the semiconductor element is mounted on the main surface.
- the ground pad is provided on the main surface so as to surround the semiconductor element.
- the insulating covering member is provided such that the outer peripheral side of the ground pad is exposed, the inner peripheral side of the ground pad is covered, and a step is formed on the substrate from the ground pad.
- the conductive bonding member is disposed on the outer peripheral side of the ground pad.
- the conductive cap is bonded to the ground pad by a conductive bonding member so as to cover the semiconductor element.
- the inner peripheral end of the bottom portion of the conductive cap is disposed on the inner peripheral side with respect to the outer peripheral end of the insulating coating member.
- the bottom has a shape in which the distance from the main surface continuously decreases from the outer peripheral end toward the inner peripheral end.
- the conductive bonding member can be blocked by the insulating coating member.
- the bottom portion has a shape in which the distance from the main surface continuously decreases from the outer peripheral end toward the inner peripheral end, the conductive joining member can be pushed out to the outer peripheral end side of the conductive cap by the shape of the bottom portion. it can. Therefore, it is possible to sufficiently suppress the conductive bonding member from flowing into the conductive cap.
- FIG. 1 is a perspective view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along the line II-II in FIG.
- FIG. 2 is a top view of the semiconductor device of FIG. 1. It is a top view which shows roughly the structure of the semiconductor device of the modification of Embodiment 1 of this invention.
- It is a schematic sectional drawing which shows 1 process of the manufacturing method of the semiconductor device of Embodiment 1 of this invention.
- It is a schematic sectional drawing which shows the next process of the process shown in FIG.
- FIG. is a schematic sectional drawing which shows the next process of the process shown in FIG.
- FIG. 1 is a perspective view schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along the line II-II in FIG.
- FIG. 2 is a top view of the semiconductor device of FIG. 1. It is
- FIG. 7 is a cross-sectional view schematically showing a configuration of a semiconductor device of Comparative Example 1.
- FIG. 6 is a cross-sectional view schematically showing a configuration of a semiconductor device of Comparative Example 2.
- FIG. It is sectional drawing which shows schematically the structure of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device of Embodiment 3 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device of Embodiment 4 of this invention.
- semiconductor device 1 of the present embodiment includes printed wiring board 2, semiconductor element 3, conductive cap 4, bonding wire 6, and conductive bonding member 12. Insulating coating member 13 is mainly included.
- the semiconductor device 1 has a conductive cap 4 covering the upper side of a semiconductor element 3 mounted on a main surface S1 of a substrate 2a described later.
- the printed wiring board 2 is composed of, for example, a glass epoxy resin double-sided printed wiring board.
- the printed wiring board 2 mainly includes a substrate 2a, a die attach pad 5, a signal pad 7, a via 8, a signal electrode 9, a ground pad 10, and a ground electrode 11.
- the substrate 2a in the present embodiment is an insulating plate.
- the substrate 2a has a main surface (upper surface) S1 and an other surface (lower surface) S2 facing the main surface S1.
- the main surface S1 and the other surface S2 face each other in the thickness direction of the substrate 2a.
- a die attach pad 5, a signal pad 7, and a ground pad 10 are provided on the main surface S1.
- a signal electrode 9 and a ground electrode 11 are provided on the other surface S2.
- the die attach pad 5, the signal pad 7, the via 8, the signal electrode 9, the ground pad 10, and the ground electrode 11 have conductivity.
- the die attach pad 5, the signal pad 7, the signal electrode 9, the ground pad 10 and the ground electrode 11 are formed by etching the copper foil attached to both surfaces of the substrate 2a.
- Via 8 is formed so as to penetrate main surface S1 and other surface S2 of substrate 2a.
- the signal pad 7 is electrically connected to the signal electrode 9 by a via 8.
- the die attach pad 5 is electrically connected to the ground electrode 11 by a via 8.
- the ground pad 10 is electrically connected to the ground electrode 11 by a via (not shown).
- the ground pad 10 is disposed on the outer peripheral side of the substrate 2a.
- the conductive cap 4 is shown by a broken line for easy viewing.
- the ground pad 10 is arranged over the entire outer periphery of the substrate 2a.
- the ground pad 10 is provided on the main surface S ⁇ b> 1 so as to surround the semiconductor element 3.
- the ground pad 10 is formed so as to surround the die attach pad 5 and the signal pad 7.
- the signal pad 7 is disposed on the outer peripheral side of the substrate 2 a with respect to the die attach pad 5.
- the signal pad 7 is disposed in the vicinity of the die attach pad 5.
- the insulating coating member 13 is formed so as to surround the die attach pad 5 and the signal pad 7.
- the insulating covering member 13 has an insulating property.
- the insulating covering member 13 is formed along the entire circumference of the ground pad 10.
- the insulating covering member 13 is formed so that the outer peripheral side of the ground pad 10 is exposed.
- the insulating covering member 13 is formed so as to cover the inner peripheral side of the ground pad 10.
- the insulating covering member 13 is provided so that a step is formed on the ground pad 10 to the substrate 2a.
- the substrate 2a is exposed in a region where the die attach pad 5 and the signal pad 7 are not formed inside the ground pad 10, but the ground pad 10 is also an insulating coating member. 13 may be formed to the inside.
- the insulation coating member 13 is, for example, a solder resist.
- the insulating covering member 13 is cured by being applied to the surface of the substrate 2a with a uniform thickness by a screen printing method or a spraying method, and then heated.
- the semiconductor element 3 is a high-frequency element that amplifies an input signal.
- the semiconductor element 3 is mounted on the main surface S1 of the substrate 2a. Specifically, the semiconductor element 3 is mounted on a die attach pad 5 provided on the main surface S1 by a die bond adhesive (not shown).
- a die bond adhesive a conductive silver paste in which fine silver particles are dispersed in a liquid epoxy resin and a silicone adhesive that maintains flexibility even when cured are used.
- the semiconductor element 3 is connected to the signal pad 7 by a bonding wire 6. Thereby, the semiconductor element 3 is electrically connected to the signal electrode 9 provided on the other surface S2 of the substrate 2a via the bonding wire 6, the signal pad 7, and the via 8.
- a plurality of semiconductor elements 3 may be mounted on the main surface S1 of the substrate 2a, and other electric and electronic components may be mounted.
- the copper foil pad may be freely designed as appropriate according to the form of the semiconductor element and electrical / electronic component to be mounted.
- the conductive cap 4 is bonded to the ground pad 10 by the conductive bonding member 12 so as to cover the semiconductor element 3.
- the conductive cap 4 has conductivity.
- the conductive cap 4 is formed in a cap shape by processing a copper alloy whose linear expansion coefficient is close to the plane direction of the printed wiring board 2, for example.
- the surface of the conductive cap 4 is plated.
- the conductive cap 4 has a space IS for accommodating the semiconductor element 3, the bonding wire 6 and the like on the lower surface US of the conductive cap 4.
- the space IS is hermetically sealed with the conductive cap 4 joined to the ground pad 10. Therefore, the semiconductor element 3 is accommodated in the conductive cap 4 in an airtight manner.
- a bottom BP is provided on the outer peripheral side of the lower surface US of the conductive cap 4.
- the inner peripheral end of the bottom portion BP of the conductive cap 4 is disposed closer to the inner peripheral side of the insulating coating member 13 than the outer peripheral end of the insulating coating member 13.
- the bottom BP has a shape in which the distance from the main surface S1 continuously decreases from the outer peripheral end toward the inner peripheral end.
- the bottom portion BP has a bottom surface portion 4a and a tapered portion 4b.
- the bottom surface portion 4 a and the taper portion 4 b are provided over the entire outer periphery of the lower surface US of the conductive cap 4.
- a bottom surface portion 4a which is a horizontal surface is provided on the inner peripheral side of the bottom portion BP.
- a tapered portion 4b is provided on the outer peripheral side of the bottom surface portion 4a.
- the tapered portion 4b forms a shape in which the distance from the main surface S1 continuously decreases from the outer peripheral end to the inner peripheral end of the bottom portion BP.
- the angle formed by the tapered portion 4b and the horizontal plane is, for example, 45 degrees.
- the conductive cap 4 of the present embodiment is created by cutting. For this reason, the variation in dimensions is small compared to press working.
- the plating on the surface of the conductive cap 4 may be a plurality of layers.
- the multi-layer plating may be, for example, copper-nickel-gold three-layer plating from the base side or copper-nickel-palladium-gold four-layer plating.
- the surface of the copper single layer plating may be subjected to an organic rust preventive, for example, OSP (Organic Solderability Preservative) treatment for forming an imidazole film.
- OSP Organic Solderability Preservative
- the conductive cap 4 is disposed on the substrate 2a so as to cover the semiconductor element 3 and the like. A part of each of the bottom surface portion 4a and the taper portion 4b is mechanically fixed to the ground pad 10 by the conductive bonding member 12 and is electrically connected thereto. As a result, the conductive cap 4 has the same potential (ground potential) as the ground electrode 11 on the other surface S2.
- a part of the bottom surface portion 4 a of the conductive cap 4 is located above a part of the insulating coating member 13.
- the conductive cap 4 is lifted by the surface tension of the conductive bonding member 12.
- the bottom surface portion 4 a of the conductive cap 4 is in light contact with the insulating coating member 13, or has a slight gap with the insulating coating member 13.
- the conductive bonding member 12 is disposed on the outer peripheral side of the ground pad 10.
- the conductive bonding member 12 is disposed over the entire outer periphery of the ground pad 10.
- the conductive bonding member 12 has conductivity.
- tin-silver-copper solder is used as the conductive bonding member 12.
- the end on the inner peripheral side of the tapered portion 4b of the conductive cap 4 coincides with the end on the outer peripheral side of the bottom surface portion 4a.
- An end on the inner peripheral side of the taper portion 4 b of the conductive cap 4 is disposed directly above the center CP of the region (joining region) exposed from the insulating coating member 13 on the outer peripheral side of the ground pad 10.
- the end on the inner peripheral side of the taper portion 4 b is either on the inner peripheral side of the ground pad 10 above or just above the center CP of the outer peripheral side region (bonding region) of the ground pad 10 exposed from the insulating coating member 13. It suffices if they are arranged in a crab.
- the center CP is a position that equally divides the distance between the outer peripheral end of the insulating coating member 13 and the outer peripheral end of the ground pad 10.
- the end on the outer peripheral side of the taper portion 4 b is disposed directly above the end on the outer peripheral side of the ground pad 10.
- the outer peripheral end of the conductive cap 4 is illustrated outside the outer peripheral end of the ground pad 10 for easy viewing.
- the outer peripheral end of the ground pad 10 may be disposed either on the inner peripheral side of the conductive cap 4 just below or directly below the outer peripheral end of the conductive cap 4.
- the semiconductor device 1 may have a sealed structure or a structure that is not sealed. That is, the semiconductor element 3 may be accommodated in the conductive cap 4 in a non-airtight manner.
- a notch NP is provided in a part of the ground pad 10. For this reason, the outside and the inside of the conductive cap 4 communicate with each other through the notch NP. Therefore, the semiconductor element 3 is accommodated in the conductive cap 4 in a non-airtight manner.
- 5 to 9 are cross-sectional views at the same cross-sectional position as FIG.
- printed wiring board 2 is prepared.
- the paste 20 is supplied to the printed wiring board 2.
- the paste 20 is a mixture of the conductive bonding member 12 powder and a flux capable of reducing the oxide film on the surface thereof.
- the paste 20 is applied to a region (bonding region) exposed from the insulating coating member 13 on the outer peripheral side of the ground pad 10 provided on the main surface S1 of the substrate 2a by screen printing. At this time, it is desirable to apply the paste 20 so as not to protrude from the region exposed from the insulating coating member 13 on the outer peripheral side of the ground pad 10. In this way, the conductive bonding member 12 is supplied to the outer peripheral side region (bonding region) of the ground pad 10 exposed from the insulating coating member 13.
- conductive bonding member 12 is melted and integrated with ground pad 10 by a reflow method. Thereafter, the flux contained in the paste 20 is dissolved and removed by the immersion cleaning method. In this way, the conductive bonding member 12 is melted in a region (bonding region) on the outer peripheral side of the ground pad 10 exposed from the insulating coating member 13.
- the conductive bonding member 12 wets and spreads in a region (bonding region) exposed from the insulating coating member 13 on the outer peripheral side of the ground pad 10, and has a shape that rises round above the center CP of the bonding region due to its surface tension. . That is, the vertex of the conductive bonding member 12 is located at the center CP.
- the semiconductor element 3 is mounted on the substrate 2a. Specifically, the semiconductor element 3 is mounted on the die attach pad 5 to which a conductive adhesive (die bond adhesive) is supplied by a transfer method. The die bond adhesive is cured by heating in this state. Further, a bonding wire is connected to the semiconductor element 3 and the signal pad 7 by a ball bonding method.
- a conductive adhesive die bond adhesive
- the conductive cap 4 is mounted above the substrate 2a.
- An end on the inner peripheral side of the taper portion 4 b of the conductive cap 4 is disposed either directly above the center CP of the bonding region of the ground pad 10 or on the inner peripheral side from directly above.
- the top part of the conductive bonding member 12 having a shape that rises roundly due to the surface tension comes into contact with the inner peripheral end of the tapered part 4b.
- the conductive cap in which the inner peripheral end of the bottom portion BP having the tapered portion 4b is disposed on the inner peripheral side with respect to the outer peripheral end of the insulating coating member 13 is mounted on the molten conductive bonding member 12. .
- the conductive cap 4 may be mounted while being pressurized after the substrate 2a and the conductive cap 4 are heated to a temperature at which the conductive bonding member 12 does not melt.
- a high pressure is generated due to contact in a narrow region of the top portion of the conductive bonding member 12, and the subsequent handling is easy. The position will not shift.
- the conductive cap 4 may be mounted after the substrate 2a and the conductive cap 4 are heated to a temperature at which the conductive bonding member 12 melts. In this case, since the speed at which the conductive cap 4 is pressed against the molten conductive bonding member 12 can be freely selected, the conductive bonding member 12 can be uniformly pushed to the outer peripheral side of the substrate 2a.
- the semiconductor device 1 in which the upper part of the semiconductor element 3 mounted on the main surface S1 of the substrate 2a is covered with the conductive cap 4 is obtained.
- the semiconductor device 1 of Comparative Example 1 is mainly different from the semiconductor device 1 of the present embodiment in that the insulating coating member 13 is not provided.
- the conductive bonding member 12 cannot be blocked by the insulating coating member 13. Therefore, the conductive bonding member 12 flows out to the inside of the conductive cap 4 to short-circuit the semiconductor element 3 and the signal pad 7, or the conductive bonding member 12 scatters to the inside of the conductive cap 4 to bond the bonding wire 6. It may be disconnected.
- the semiconductor device 1 of Comparative Example 2 does not have a shape in which the distance between the bottom portion of the conductive cap 4 and the main surface S ⁇ b> 1 continuously decreases from the outer peripheral end toward the inner peripheral end.
- the semiconductor device 1 is mainly different from the semiconductor device 1 of the present embodiment.
- the conductive bonding member 12 may flow inside the conductive cap 4 through between the upper surface of the insulating coating member 13 and the conductive cap 4. Therefore, the conductive bonding member 12 cannot be sufficiently prevented from flowing out to the inside of the conductive cap 4.
- the semiconductor device 1 of Comparative Example 2 since the conductive bonding member 12 is blocked by the insulating coating member 13, the conductive bonding member 12 easily flows out of the conductive cap 4. For this reason, the outer peripheral end of the ground pad 10 is formed to be located outside the outer peripheral end of the conductive cap 4. Thereby, the board
- the insulating coating member 13 performs conductivity.
- the joining member 12 can be stopped. Since the bottom portion BP has a shape (tapered portion 4b) in which the distance from the main surface S1 continuously decreases from the outer peripheral end toward the inner peripheral end, the conductive bonding member 12 is electrically conductive by the tapered portion 4b of the bottom BP. Can be pushed out to the outer peripheral end side of the cap 4. Accordingly, it is possible to sufficiently suppress the conductive bonding member 12 from flowing into the conductive cap 4.
- the conductive cap 4 is bonded to the ground pad 10 by the conductive bonding member 12 so as to cover the semiconductor element 3. For this reason, the external electric field can be blocked by the conductive cap 4 to protect the internal semiconductor element 3. Further, the periphery of the semiconductor element 3 is surrounded by the conductive cap 4 and the ground electrode 11, and the conductive cap 4 is electrically connected to the ground pad 10 by the conductive bonding member 12. For this reason, an external electric field can be shut off by forming a space surrounded by a conductor having a ground potential around the semiconductor element 3. Thereby, the semiconductor element 3 can be more effectively protected from external electromagnetic noise.
- the conductive bonding member 12 having a sufficient thickness can be disposed below the tapered portion 4b by the tapered portion 4b. For this reason, the board
- the end on the inner peripheral side of the shape (tapered portion 4b) in which the distance from the main surface S1 continuously decreases from the outer peripheral end of the bottom BP toward the inner peripheral end is
- the ground pad 10 exposed from the insulating coating member 13 is disposed either directly above the center CP of the region on the outer peripheral side (bonding region) or on the inner peripheral side from directly above.
- the vertex of the conductive bonding member 12 is positioned at the center CP of the bonding region.
- the end on the inner peripheral side of the tapered portion 4 b can be in contact with either the apex of the conductive bonding member 12 or the inner peripheral side of the apex. For this reason, the conductive bonding member 12 can be effectively pushed out to the outer peripheral end side by the tapered portion 4b of the bottom portion BP.
- the outer peripheral end of the ground pad 10 is arranged either directly below or directly below the outer peripheral end of the conductive cap 4. For this reason, the end on the outer peripheral side of the ground pad 10 can be arranged on the inner peripheral side of the end on the outer peripheral side of the conductive cap 4. Therefore, the outer shape of the substrate 2a can be reduced. Thereby, the semiconductor device 1 can be reduced in size.
- the manufacturing method of the semiconductor device 1 is a manufacturing method of the semiconductor device 1 including the semiconductor element 3 mounted on the main surface S1 of the substrate 2a.
- the manufacturing method of the semiconductor device 1 includes the following steps. It is exposed from an insulating covering member 13 provided so as to cover the inner peripheral side of the ground pad 10 provided at a position surrounding the semiconductor element 3 on the main surface S1 and to form a step from the ground pad 10 to the substrate 2a.
- the conductive bonding member 12 is supplied to the outer peripheral side region of the ground pad 10.
- the conductive bonding member 12 is melted in a region on the outer peripheral side of the ground pad 10 exposed from the insulating coating member 13.
- the conductive bonding member 12 can be damped. Since the bottom BP has a shape (tapered portion 4b) in which the distance from the main surface S1 continuously decreases from the outer peripheral end toward the inner peripheral end, the conductive bonding member 12 is surrounded by the tapered portion 4b of the bottom BP. Can be pushed to the end side. Accordingly, it is possible to sufficiently suppress the conductive bonding member 12 from flowing into the conductive cap 4.
- the substrate 2a and the conductive cap 4 are heated to a temperature at which the conductive bonding member 12 does not melt.
- the conductive cap 4 is mounted while applying pressure. For this reason, since the conductive cap 4 contacts in the narrow area
- the substrate 2a and the conductive cap 4 are heated to a temperature at which the conductive bonding member 12 is melted. A cap 4 is mounted. For this reason, the speed at which the conductive cap 4 is pressed against the molten conductive bonding member 12 can be freely selected, so that the conductive bonding member 12 can be uniformly pushed out to the outer peripheral side of the substrate 2a.
- the semiconductor device 1 of the present embodiment is mainly different from the semiconductor device 1 of the first embodiment in that the conductive cap 4 is provided with a recess 4c and a protrusion 4d.
- the conductive cap 4 has a concave portion 4c and a convex portion 4d.
- the recessed part 4c is provided in the part on the opposite side to the bottom part BP. That is, the recess 4c is provided at a position facing the bottom BP.
- the recess 4c is recessed toward the bottom BP.
- the recess 4c is formed so that the opening area becomes smaller toward the bottom BP.
- the convex part 4d is provided in the part on the opposite side to the bottom part BP.
- the convex part 4d protrudes on the opposite side to the bottom part BP.
- the convex part 4d protrudes on the opposite side to the direction in which the concave part 4c is recessed.
- the convex portion 4d is provided around the concave portion 4c.
- the convex part 4d is connected to the concave part 4c.
- the convex part 4d is formed so as to be connected to the opening of the concave part 4c.
- the conductive cap 4 is formed into a cap shape by processing a copper alloy having a linear expansion coefficient close to the plane direction of the printed wiring board 2.
- the conductive cap 4 is formed by a forging process that is cheaper than the cutting process.
- the recess 4c is provided in a portion opposite to the bottom BP and is recessed toward the bottom BP. For this reason, the bottom surface portion 4a and the taper portion 4b of the bottom portion BP can be strongly pressed against the lower die by using the pressure applied a plurality of times to form the recess 4c by the upper die of the forging die. Therefore, the shape of the conductive cap 4 processed into the lower mold can be accurately transferred. Thereby, the electroconductive cap 4 with a small dispersion
- the convex portion 4d is provided on a portion opposite to the bottom portion BP, protrudes on the opposite side to the bottom portion BP, and is provided around the concave portion 4c. Therefore, when the shapes of the bottom surface portion 4a and the taper portion 4b are accurately transferred while forming the concave portion 4c, the member constituting the conductive cap 4 causes the convex portion 4d to plastically flow to release excessive pressure. Can do. This can prevent the upper mold from being damaged.
- the point that outermost peripheral convex portion 4 e is provided on the side surface of conductive cap 4 and the depth of ceiling portion 4 f inside conductive cap 4 are the same.
- the semiconductor device 1 is mainly different from the semiconductor device 1 of the first embodiment in that it has a size of 2/3 of the thickness of the conductive cap 4.
- the conductive cap 4 has an outermost peripheral convex portion 4e and a ceiling portion 4f.
- the outermost peripheral convex portion 4 e is provided on the side surface of the conductive cap 4.
- the outermost peripheral convex portion 4 e is provided at the center in the thickness direction of the conductive cap 4.
- the outermost peripheral convex portion 4 e is formed so as to protrude to the side of the conductive cap 4.
- the thickness direction of the conductive cap 4 is a direction in which the main surface S1 and the other surface S2 face each other when the conductive cap 4 is bonded to the ground pad 10 by the conductive bonding member 12.
- the ceiling part 4 f covers the semiconductor element 3.
- the ceiling part 4 f is arranged so as to face the semiconductor element 3.
- the depth D1 from the bottom portion BP to the ceiling portion 4f has a dimension that is 2/3 of the thickness D2 of the conductive cap.
- the thickness direction of the conductive cap 4 is also a direction in which the ceiling portion 4 f and the semiconductor element 3 face each other when the conductive cap 4 is bonded to the ground pad 10 by the conductive bonding member 12.
- the conductive cap 4 is formed into a cap shape by processing a copper alloy having a linear expansion coefficient close to the plane direction of the printed wiring board 2.
- the conductive cap 4 is formed by etching. When etching a copper alloy plate from both sides, the processing conditions are often adjusted to dissolve 2/3 of the plate thickness.
- the depth D1 from the bottom BP to the ceiling portion 4f in the thickness direction of the conductive cap 4 has a dimension that is 2/3 of the thickness D2 of the conductive cap 4. ing. For this reason, the ceiling part 4f and the outermost periphery convex part 4e can be formed simultaneously. Thereby, the labor of processing and the usage-amount of etching liquid can be reduced.
- the semiconductor device 1 of the present embodiment is mainly different from the semiconductor device 1 of the first and third embodiments in the configuration of the conductive cap 4.
- the conductive cap 4 has an outermost peripheral convex portion 4e, a ceiling portion 4f, and an inner tapered portion 4g.
- the outermost peripheral convex portion 4 e is provided on the side surface of the conductive cap 4.
- the ceiling part 4 f covers the semiconductor element 3.
- the conductive cap 4 has a main body portion 41 and a surface portion 42.
- the surface portion 42 covers the surface of the main body portion 41.
- the main body 41 is made of a resin molding material.
- the surface portion 42 is made of a conductive material.
- the conductive cap 4 is made of a resin molded member whose surface is plated. That is, the surface portion 42 is formed by plating.
- the surface part 42 should just have electroconductivity without being limited to plating. It is desirable that this resin molded member has high heat resistance to such an extent that it does not gasify at a temperature at which the conductive bonding member 12 melts and has a glass transition temperature of 125 ° C. or higher.
- the bottom part BP has a shape in which the distance from the main surface S1 continuously increases from the inner peripheral edge toward the ceiling part 4f.
- the inner tapered portion 4g constitutes this shape.
- the distance from the bottom part BP to the outermost peripheral convex part 4e is equal to the distance from the bottom part BP to the ceiling part 4f. That is, in the thickness direction of the conductive cap 4, the position of the outermost peripheral convex portion 4 e is arranged so as to coincide with the position of the ceiling portion 4 f inside the conductive cap 4.
- the inclination angle from the inner peripheral end of the bottom portion BP toward the ceiling portion 4f is equal to the inclination angle from the outer peripheral end of the bottom portion BP toward the outermost peripheral convex portion 4e. That is, the inclination angle of the inner tapered portion 4g of the conductive cap 4 is formed to be the same as the inclination angle of the tapered portion 4b.
- the positions of the outermost peripheral convex portion 4e and the ceiling portion 4f in the thickness direction of the conductive cap 4 are aligned, and the inclination angles of the tapered portion 4b and the inner tapered portion 4g are aligned. Therefore, even when the width of the bottom surface portion 4a is narrow, it is easy to release from the molding die, and the shapes of the bottom surface portion 4a and the tapered portion 4b can be processed accurately.
- SYMBOLS 1 Semiconductor device, 2 printed wiring board, 2a board
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Abstract
Description
(実施の形態1)
最初に、図1~図3を参照して本発明の実施の形態1の半導体装置1の構成について説明する。主に図1および図2を参照して、本実施の形態の半導体装置1は、プリント配線板2と、半導体素子3と、導電性キャップ4と、ボンディングワイヤ6と、導電性接合部材12と、絶縁被覆部材13とを主に有している。半導体装置1は、後述する基板2aの主面S1に実装された半導体素子3の上方を導電性キャップ4で覆ったものである。
比較例の半導体装置として、図10を参照して比較例1の半導体装置について説明し、図11を参照して比較例2の半導体装置について説明する。以下、比較例1および比較例2では、特に説明しない限り、実施の形態1と同一の構成には同一の符号を付し、説明を繰り返さない。
本発明の実施の形態2の半導体装置について説明する。以下、本実施の形態では、特に説明しない限り、実施の形態1と同一の構成には同一の符号を付し、説明を繰り返さない。
本発明の実施の形態3の半導体装置について説明する。以下、本実施の形態では、特に説明しない限り、実施の形態1と同一の構成には同一の符号を付し、説明を繰り返さない。
本発明の実施の形態4の半導体装置について説明する。以下、本実施の形態では、特に説明しない限り、実施の形態1および実施の形態3と同一の構成には同一の符号を付し、説明を繰り返さない。
今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることを意図される。
Claims (10)
- 主面を有する基板と、
前記主面に実装された半導体素子と、
前記半導体素子を囲むように前記主面に設けられた接地パッドと、
前記接地パッドの外周側を露出し、前記接地パッドの内周側を覆い、かつ前記接地パッド上から前記基板上に段差が形成されるように設けられた絶縁被覆部材と、
前記接地パッドの前記外周側に配置された導電性接合部材と、
前記半導体素子を覆うように前記接地パッドに前記導電性接合部材によって接合された導電性キャップとを備え、
前記導電性キャップの底部の内周端が前記絶縁被覆部材の外周端よりも内周側に配置されており、
前記底部は外周端から前記内周端に向かって前記主面との距離が連続的に小さくなる形状を有する、半導体装置。 - 前記底部の前記外周端から前記内周端に向かって前記主面との距離が連続的に小さくなる形状の内周側の端は、前記絶縁被覆部材から露出した前記接地パッドの前記外周側の領域の中央の真上および真上よりも内周側のいずれかに配置されている、請求項1に記載の半導体装置。
- 前記接地パッドの前記外周側の端は、前記導電性キャップの外周側の端の真下および真下よりも内周側のいずれかに配置されている、請求項1または2に記載の半導体装置。
- 前記導電性キャップは、前記底部と反対側の部分に設けられた凹部を含み、
前記凹部は前記底部に向かって凹んでいる、請求項1~3のいずれか1項に記載の半導体装置。 - 前記導電性キャップは、前記底部と反対側の前記部分に設けられた凸部を含み、
前記凸部は、前記底部と反対側に突出しており、かつ前記凹部の周囲に設けられている、請求項4に記載の半導体装置。 - 前記導電性キャップは、前記導電性キャップの側面に設けられた最外周凸部と、前記半導体素子を覆う天井部とを含み、
前記最外周凸部は、前記導電性キャップの厚さ方向の中央に設けられており、
前記導電性キャップの厚さ方向において、前記底部から前記天井部までの深さは、前記導電性キャップの厚みの2/3の寸法を有している、請求項1~5のいずれか1項に記載の半導体装置。 - 前記導電性キャップは、本体部と、本体部の表面を覆う表面部とを含み、
前記本体部は、樹脂成型材料で構成されており、
前記表面部は、導電性材料で構成されており、
前記導電性キャップは、前記導電性キャップの側面に設けられた最外周凸部と、前記半導体素子を覆う天井部とを含み、
前記底部は、前記内周端から前記天井部に向かって前記主面との距離が連続的に大きくなる形状を有し、
前記導電性キャップの厚さ方向において、前記底部から前記最外周凸部まで距離は、前記底部から前記天井部までの距離と等しく、
前記底部の前記内周端から前記天井部に向かう傾斜角度は、前記底部の前記外周端から前記最外周凸部に向かう傾斜角度と等しい、請求項1~5のいずれか1項に記載の半導体装置。 - 基板の主面に実装された半導体素子を備えた半導体装置の製造方法であって、
前記主面の前記半導体素子を囲む位置に設けられた接地パッドの内周側を覆い、かつ前記接地パッド上から前記基板上に段差が形成されるように設けられた絶縁被覆部材から露出した前記接地パッドの外周側の領域に前記導電性接合部材を供給する工程と、
前記絶縁被覆部材から露出した前記接地パッドの前記外周側の領域において前記導電性接合部材を溶融させる工程と、
外周端から内周端に向かって前記主面との距離が連続的に小さくなる形状を有する底部の前記内周端が前記絶縁被覆部材の外周端よりも内周側に配置された導電性キャップが、前記溶融された前記導電性接合部材に搭載される工程とを備えた、半導体装置の製造方法。 - 前記導電性キャップが搭載される工程において、
前記導電性接合部材が溶融しない温度に前記基板と前記導電性キャップとが加熱されてから加圧されながら前記導電性キャップが搭載される、請求項8に記載の半導体装置の製造方法。 - 前記導電性キャップが搭載される工程において、
前記導電性接合部材が溶融する温度に前記基板と前記導電性キャップとが加熱されてから前記導電性キャップが搭載される、請求項8に記載の半導体装置の製造方法。
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Also Published As
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US20180158794A1 (en) | 2018-06-07 |
GB201719387D0 (en) | 2018-01-03 |
GB2555289B (en) | 2020-09-23 |
JP6559236B2 (ja) | 2019-08-14 |
JPWO2016199634A1 (ja) | 2018-02-22 |
GB2555289A (en) | 2018-04-25 |
US10916520B2 (en) | 2021-02-09 |
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