WO2016161842A1 - 横向扩散金属氧化物半导体场效应管及其制造方法 - Google Patents

横向扩散金属氧化物半导体场效应管及其制造方法 Download PDF

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Publication number
WO2016161842A1
WO2016161842A1 PCT/CN2016/072853 CN2016072853W WO2016161842A1 WO 2016161842 A1 WO2016161842 A1 WO 2016161842A1 CN 2016072853 W CN2016072853 W CN 2016072853W WO 2016161842 A1 WO2016161842 A1 WO 2016161842A1
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well
shallow trench
isolation structure
trench isolation
channel region
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English (en)
French (fr)
Inventor
黄枫
韩广涛
孙贵鹏
林峰
赵龙杰
林华堂
赵兵
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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Priority to JP2018503704A priority Critical patent/JP6464313B2/ja
Priority to US15/564,181 priority patent/US10290705B2/en
Publication of WO2016161842A1 publication Critical patent/WO2016161842A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Definitions

  • the present invention relates to semiconductor processes, and more particularly to a laterally diffused metal oxide semiconductor field effect transistor, and to a method of fabricating a laterally diffused metal oxide semiconductor field effect transistor.
  • STI shallow trench isolation structure
  • off-BV breakdown voltage
  • a method of fabricating a laterally diffused metal oxide semiconductor field effect transistor comprising: providing a wafer formed with a first N well, a first P well, and a shallow trench isolation structure of a channel region; depositing on a surface of the wafer a high temperature oxide film; the high temperature oxide film is subjected to photolithography and dry etching, and the thickness of the etching is less than the thickness of the high temperature oxide film, so that a region not covered by the photoresist is retained with a high temperature oxide film As an etch buffer layer; performing wet etching to remove the etch buffer layer, and the remaining high temperature oxide film forms a mini oxide layer under the photoresist; Photolithography and ion implantation of the second N well and the second P well to form a second N well in the first N well, and a second P well in the first P well; the channel a shallow trench isolation structure extends downwardly from the surface of the second N well to an inner portion, the mini oxide layer is located on the second N well, and one
  • a laterally diffused metal oxide semiconductor field effect transistor having a high off-BV STI structure comprising a substrate, a first N well in the substrate, a first P well, and a second N well of the first N well surface, a second P-well of a P-well surface, a shallow trench isolation structure on the substrate, the shallow trench isolation structure comprising a shallow trench isolation structure extending downward from the second N-well surface to the interior, the lateral diffusion
  • the metal oxide semiconductor field effect transistor further includes a source disposed on a surface of the second P well, disposed on the surface of the second N well and located in a shallow trench isolation structure of the channel region away from the end of the second P well a drain, a gate including a polysilicon gate and a gate oxide layer, one end of the gate overlaps the second P well, and the other end extends to the shallow trench isolation structure of the channel region, Including a mini oxide layer, the mini oxide layer is overlapped at one end of the channel region, the shallow trench isolation structure is adjacent to one end of the second
  • the laterally diffused metal oxide semiconductor field effect transistor and the method of fabricating the same by adding a mini oxide layer on the side of the channel region of the STI structure LDMOS near the drift region, the LDMOS can be greatly improved without increasing the LDMOS area. off-BV.
  • FIG. 1 is a schematic cross-sectional view showing a laterally diffused metal oxide semiconductor field effect transistor in an embodiment
  • FIG. 2 is a flow chart showing a method of fabricating a laterally diffused metal oxide semiconductor field effect transistor in an embodiment.
  • FIG. 1 is a cross-sectional view showing a laterally diffused metal oxide semiconductor field effect transistor in an embodiment. Illustrated is an N-channel LDMOS comprising a substrate 10, a first N-well 22 in the substrate 10, a first P-well 24, a second N-well 32 on the surface of the first N-well 22, a first P-well 24 a second P-well 34 of the surface, a shallow trench isolation structure on the substrate 10, wherein the shallow trench isolation structure includes a shallow trench isolation structure 42 extending downward from the surface of the second N-well 32 to the interior; lateral diffusion metal oxide
  • the semiconductor field effect transistor further includes a source 74 disposed on the surface of the second P well 34, disposed on the surface of the second N well 32 and located at a position away from the end of the shallow trench isolation structure 42 of the channel region away from the second P well 34.
  • the laterally diffused metal oxide semiconductor field effect transistor further includes a mini-oxide layer 52 (mini-oxide). One end of the mini-oxide layer 52 overlaps one end of the shallow trench isolation structure 42 near the second P-well 34 (ie, one end away from the drain 72), and the other end extends to the second N-well 32, and the mini-oxide layer 52 Covered by polysilicon gate 52.
  • the laterally diffused metal oxide semiconductor field effect transistor shown in Fig. 1 is a bilaterally symmetrical structure.
  • the laterally diffused metal oxide semiconductor field effect transistor further includes a P-type heavily doped region 76 located in the second P well 34 with the source 74 away from the gate side.
  • the off-line of the LDMOS can be greatly improved without increasing the LDMOS area. BV.
  • a method of manufacturing the aforementioned LDMOSFET is also provided.
  • 2 is a flow chart of a method of fabricating a laterally diffused metal oxide semiconductor field effect transistor in an embodiment, comprising the steps of:
  • a shallow trench isolation structure is formed by a process known to those skilled in the art, and the first N well and the first P well are formed by photolithography and ion implantation.
  • the laterally diffused metal oxide semiconductor field effect transistor is an STI structure LDMOS, and thus the shallow trench isolation structure comprises a shallow trench isolation structure provided in the channel region between the source and the drain.
  • the first N well and the first P well are respectively a high voltage N-well (HV Nwell) and high voltage P-well (HV Pwell).
  • the high temperature oxide is a silicon dioxide formed by a low temperature furnace tube deposited at 750 to 850 degrees Celsius (possibly producing other valence silicon oxides at the same time), using SiH 2 . Cl 2 and N 2 O were used as reaction gases.
  • the step of planarizing the surface of the wafer is further included. Specifically, chemical mechanical polishing (CMP) may be performed. After the CMP is completed, it is ensured that the edge of the shallow trench isolation structure of the channel region is 200-400 angstroms higher than the surrounding substrate (active region).
  • CMP chemical mechanical polishing
  • the dry etching is performed first in step S230, the thickness of the etching is less than the thickness of the high-temperature oxide film, and the high-temperature oxide film remaining in the region not covered by the photoresist is used as an etch buffer layer. Remove it from the second step of etching, ie wet etching. In this embodiment, the thickness of the etch buffer layer left is 70 to 150 angstroms.
  • the edge of the shallow trench isolation structure in the channel region should be 200 to 400 angstroms higher than the surface of the active region around it, which may adversely affect the performance of the low voltage device.
  • the wet etching is performed by a fixed-by-time method to avoid causing over-etching to corrode the STI.
  • the shallow trench isolation structure of the channel region extends downward from the surface of the second N well to the inside, the mini oxide layer is located on the second N well, and one end of the mini oxide layer overlaps the first end of the shallow trench isolation structure of the channel region.
  • the first end is the end of the shallow trench isolation structure of the channel region adjacent to the first P well.
  • the polysilicon gate and the gate oxide layer are overlapped on the second P well at one end, and the other end extends to the first end of the shallow trench isolation structure of the channel region and covers the mini oxide layer.
  • a drain is formed in the second N-well adjacent to the second end of the channel region shallow trench isolation structure opposite the first end while forming a source in the second P-well.
  • the polysilicon gate blocks the formation of ions during implantation, so the source extends only to the lower edge of the polysilicon gate.
  • the implanted drain and source are extremely N+ regions.
  • step S270 photolithography is performed, and P-type ions are implanted, and a P-type heavily doped region is formed in the second P well and the source is away from the gate.
  • the above-mentioned lateral diffusion metal oxide semiconductor field effect transistor manufacturing method adopts a two-step etching scheme, first removing most of the high temperature oxide film by dry etching, and then removing the remaining high temperature oxide film by wet etching.
  • dry etching is anisotropic etching
  • the amount of HTO corrosion can be controlled more stably and accurately than isotropic wet etching.
  • the residual HTO after dry etching is removed by slight wet etching, and the slight wet etching has negligible amount of lateral HTO corrosion.
  • the shallow trench isolation structure of the channel region is not etched away by over-etching, thereby avoiding the negative influence on the low-voltage device.
  • the hot lift well for the first P well and the first N well may be placed after step S220 and before S240, and the high temperature process may make the high temperature oxide film dense, and the wet method capable of lowering the high temperature oxide film
  • the corrosion rate ensures that the amount of corrosion of the mini-oxide remaining after the high-temperature oxide film is etched in the subsequent cleaning process can be stably controlled, ensuring the stability of mass production.
  • the temperature of the hot push trap is 1000 degrees Celsius or more and the time is 60 minutes or more.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

提供一种横向扩散金属氧化物半导体场效应管及其制造方法。该方法包括：提供形成有第一N阱（22）、第一P阱（24）以及沟道区浅槽隔离结构（42）的晶圆；在晶圆表面淀积形成高温氧化膜；对高温氧化膜进行光刻和干法刻蚀，并留下一薄层作为刻蚀缓冲层；进行湿法腐蚀，将未被光刻胶覆盖区域的刻蚀缓冲层去除，形成迷你氧化层（52）；进行光刻和离子注入在第一N阱内形成第二N阱（32），以及在第一P阱内形成第二P阱（34）；在晶圆表面形成多晶硅栅（62）和栅氧层；光刻并注入N型离子，形成漏极（72）和源极（74）。

Description

横向扩散金属氧化物半导体场效应管及其制造方法
【技术领域】
本发明涉及半导体工艺，特别是涉及一种横向扩散金属氧化物半导体场效应管，还涉及一种横向扩散金属氧化物半导体场效应管的制造方法。
【背景技术】
对于横向扩散金属氧化物半导体场效应管（LDMOSFET），其中的一种结构在漏极与源极之间形成有浅槽隔离结构（STI），我们称之为STI结构横向扩散金属氧化物半导体场效应管。由于该器件在部分应用中需要具有较高的击穿耐压（off-BV），因此如何在不增加LDMOS面积的前提下提高器件的off-BV，是亟待解决的一个问题。
【发明内容】
基于此，有必要提供一种具有高off-BV的STI结构横向扩散金属氧化物半导体场效应管。
一种横向扩散金属氧化物半导体场效应管的制造方法，包括：提供形成有第一N阱、第一P阱以及沟道区浅槽隔离结构的晶圆；在所述晶圆的表面淀积高温氧化膜；对所述高温氧化膜进行光刻和干法刻蚀，刻蚀去除的厚度小于所述高温氧化膜的厚度，使未被光刻胶覆盖的区域也得以保留一层高温氧化膜作为刻蚀缓冲层；进行湿法腐蚀，将所述刻蚀缓冲层去除，其余的高温氧化膜在所述光刻胶下方形成迷你氧化层； 进行第二N阱和第二P阱的光刻和离子注入从而在所述第一N阱内形成第二N阱，以及在所述第一P阱内形成第二P阱；所述沟道区浅槽隔离结构从所述第二N阱表面向下延伸至内部，所述迷你氧化层位于所述第二N阱上，且迷你氧化层一端搭接于所述沟道区浅槽隔离结构的第一端上，所述沟道区浅槽隔离结构的第一端为靠近所述第一P阱的一端；在所述晶圆表面形成多晶硅栅和栅氧层；所述多晶硅栅和栅氧层一端搭接于所述第二P阱上，另一端延伸至所述沟道区浅槽隔离结构的第一端且覆盖所述迷你氧化层；光刻并注入N型离子，在所述第二N阱内靠近所述沟道区浅槽隔离结构与第一端相对的第二端旁边的位置形成漏极，同时在所述第二P阱内形成源极。
一种具有高off-BV的STI结构横向扩散金属氧化物半导体场效应管，包括衬底，衬底内的第一N阱、第一P阱，第一N阱表面的第二N阱，第一P阱表面的第二P阱，衬底上的浅槽隔离结构，所述浅槽隔离结构包括从第二N阱表面向下延伸至内部的沟道区浅槽隔离结构，所述横向扩散金属氧化物半导体场效应管还包括设于所述第二P阱表面的源极，设于所述第二N阱表面、且位于沟道区浅槽隔离结构远离所述第二P阱一端旁边的位置的漏极，栅极、包括多晶硅栅和栅氧层，所述栅极的一端搭接于所述第二P阱上，另一端延伸至所述沟道区浅槽隔离结构上，还包括迷你氧化层，所述迷你氧化层一端搭接于所述沟道区浅槽隔离结构靠近所述第二P阱的一端上，另一端延伸至所述第二N阱上，且所述迷你氧化层被所述多晶硅栅极所覆盖。
上述横向扩散金属氧化物半导体场效应管及其制造方法，通过在STI结构LDMOS的沟道区靠近漂移区一侧增加一块迷你氧化层，可以在不增加LDMOS面积的情况下，大幅度地提高LDMOS的off-BV。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例中横向扩散金属氧化物半导体场效应管的剖面示意图；
图2是一实施例中横向扩散金属氧化物半导体场效应管的制造方法的流程图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
图1是一实施例中横向扩散金属氧化物半导体场效应管的剖面示意图。图示的是一个N沟道LDMOS，包括衬底10，衬底10内的第一N阱22、第一P阱24，第一N阱22表面的第二N阱32，第一P阱24表面的第二P阱34，衬底10上的浅槽隔离结构，其中浅槽隔离结构包括从第二N阱32表面向下延伸至内部的沟道区浅槽隔离结构42；横向扩散金属氧化物半导体场效应管还包括设于第二P阱34表面的源极74，设于第二N阱32表面、且位于沟道区浅槽隔离结构42远离第二P阱34一端旁边的位置的漏极72，栅极、包括多晶硅栅62和栅氧层（图1中未示），栅极的一端搭接于第二P阱34上，另一端延伸至沟道区浅槽隔离结构42上。横向扩散金属氧化物半导体场效应管还包括迷你氧化层52（mini-oxide）。迷你氧化层52一端搭接于沟道区浅槽隔离结构42靠近第二P阱34的一端（即远离漏极72的一端），另一端延伸至第二N阱32上，且迷你氧化层52被多晶硅栅极52所覆盖。图1中所示横向扩散金属氧化物半导体场效应管为一个左右对称的结构。横向扩散金属氧化物半导体场效应管还包括位于第二P阱34内、源极74远离栅极一侧的P型重掺杂区76。
上述横向扩散金属氧化物半导体场效应管，通过在STI结构LDMOS的沟道区靠近漂移区一侧增加一块迷你氧化层52，可以在不增加LDMOS面积的情况下，大幅度地提高LDMOS的off-BV。
还提供一种前述LDMOSFET的制造方法。图2是一实施例中横向扩散金属氧化物半导体场效应管的制造方法的流程图，包括下列步骤：
S210，提供形成有第一N阱、第一P阱以及浅槽隔离结构的晶圆。
在本实施例中，是提供硅衬底晶圆后，通过本领域技术人员习知的工艺形成浅槽隔离结构，再通过光刻及离子注入形成第一N阱和第一P阱。其中，横向扩散金属氧化物半导体场效应管为STI结构LDMOS，因此浅槽隔离结构包括设于源极和漏极间的沟道区浅槽隔离结构。第一N阱和第一P阱分别是高压N阱（HV Nwell）和高压P阱（HV Pwell）。
S220，在晶圆表面淀积形成高温氧化膜。
在本实施例中，高温氧化膜（High Temperature Oxide, HTO）是采用低温炉管在750~850摄氏度淀积形成的二氧化硅（可能会同时生产其他价态的硅氧化物），采用SiH2Cl2和N2O作为反应气体。
在本实施例中，执行步骤S220之前，还包括对晶圆表面进行平坦化处理的步骤。具体可以是进行化学机械研磨（CMP），CMP完成后应保证沟道区浅槽隔离结构的边缘比于周围的衬底（有源区）高200-400埃。
S230，对高温氧化膜进行光刻和干法刻蚀，并留下一薄层作为刻蚀缓冲层。
采用两步刻蚀的方案，步骤S230中先进行干法刻蚀，刻蚀掉的厚度小于高温氧化膜的厚度，未被光刻胶覆盖的区域残留的高温氧化膜作为刻蚀缓冲层，留至第二步刻蚀即湿法腐蚀的时候再去除干净。在本实施例中，留下的刻蚀缓冲层的厚度为70~150埃。
S240，进行湿法腐蚀，将未被光刻胶覆盖区域的刻蚀缓冲层去除，形成迷你氧化层。
湿法腐蚀完成后，沟道区浅槽隔离结构的边缘应该比其周围的有源区的表面高出200~400埃，否则容易对低压器件的性能造成负面影响。
在本实施例中，湿法腐蚀采用固定腐蚀时间（by-time）的方法进行腐蚀，避免造成过腐蚀将STI也腐蚀掉。
S250，进行光刻和离子注入在第一N阱内形成第二N阱，以及在第一P阱内形成第二P阱。
沟道区浅槽隔离结构从第二N阱表面向下延伸至内部，迷你氧化层位于第二N阱上，且迷你氧化层一端搭接于沟道区浅槽隔离结构的第一端。该第一端为沟道区浅槽隔离结构靠近第一P阱的那一端。
S260，在晶圆表面形成多晶硅栅和栅氧层。
多晶硅栅和栅氧层一端搭接于第二P阱上，另一端延伸至沟道区浅槽隔离结构的第一端且覆盖迷你氧化层。
S270，光刻并注入N型离子，形成漏极和源极。
在第二N阱内靠近沟道区浅槽隔离结构与第一端相对的第二端旁边的位置形成漏极，同时在第二P阱内形成源极。注入时多晶硅栅对离子形成阻挡，故源极仅延伸至多晶硅栅下方边缘位置。
在本实施例中，注入形成的漏极和源极为N+区域。
步骤S270完后之后再光刻、注入P型离子，在第二P阱内、源极远离栅极的一侧形成P型重掺杂区。
上述横向扩散金属氧化物半导体场效应管的制造方法，采用两步刻蚀的方案，先通过干法刻蚀去除大部分的高温氧化膜，再通过湿法腐蚀去除剩余的高温氧化膜。相对于单独采用湿法腐蚀，由于干法刻蚀是各向异性刻蚀，相对于各向同性的湿法腐蚀，对HTO腐蚀量可以控制得比较稳定、精准。干法刻蚀后残留的HTO经过轻微的湿法腐蚀去除，轻微的湿法腐蚀对横向HTO腐蚀量可以忽略。而相对于单独干法刻蚀，不会由于过刻蚀将沟道区浅槽隔离结构也刻蚀掉一部分，避免了对低压器件的负面影响。
在其中一个实施例中，对第一P阱和第一N阱的热推阱可以放在步骤S220之后、S240之前，高温过程可以使得高温氧化膜变致密，能够地降低高温氧化膜的湿法腐蚀速率，保证了高温氧化膜刻蚀后保留下来的mini-oxide在后续清洗过程中的腐蚀量可以得到稳定的控制，确保了量产的稳定性。在其中一个实施例中，热推阱的温度为1000摄氏度以上，时间为60分钟以上。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (11)

  1. 一种横向扩散金属氧化物半导体场效应管的制造方法，包括：
    提供形成有第一N阱、第一P阱以及沟道区浅槽隔离结构的晶圆；
    在所述晶圆的表面淀积高温氧化膜；
    对所述高温氧化膜进行光刻和干法刻蚀，刻蚀去除的厚度小于所述高温氧化膜的厚度，使未被光刻胶覆盖的区域也得以保留一层高温氧化膜作为刻蚀缓冲层；
    进行湿法腐蚀，将所述刻蚀缓冲层去除，其余的高温氧化膜在所述光刻胶下方形成迷你氧化层；
    进行第二N阱和第二P阱的光刻和离子注入，从而在所述第一N阱内形成第二N阱，以及在所述第一P阱内形成第二P阱；所述沟道区浅槽隔离结构从所述第二N阱表面向下延伸至内部，所述迷你氧化层位于所述第二N阱上，且迷你氧化层一端搭接于所述沟道区浅槽隔离结构的第一端上，所述沟道区浅槽隔离结构的第一端为靠近所述第一P阱的一端；
    在所述晶圆表面形成多晶硅栅和栅氧层；所述多晶硅栅和栅氧层一端搭接于所述第二P阱上，另一端延伸至所述沟道区浅槽隔离结构的第一端且覆盖所述迷你氧化层；及
    光刻并注入N型离子，在所述第二N阱内靠近所述沟道区浅槽隔离结构与第一端相对的第二端旁边的位置形成漏极，同时在所述第二P阱内形成源极。
  2. 根据权利要求1所述的方法，其特征在于，所述对所述高温氧化膜进行光刻和干法刻蚀的步骤中，保留的刻蚀缓冲层的厚度为70~150埃。
  3. 根据权利要求1或2所述的方法，其特征在于，所述进行湿法腐蚀的步骤后，所述沟道区浅槽隔离结构的边缘比所述第一N阱的表面高出200~400埃。
  4. 根据权利要求1所述的方法，其特征在于，所述在晶圆表面淀积形成高温氧化膜的步骤是在750~850摄氏度下淀积形成二氧化硅。
  5. 根据权利要求4所述的方法，其特征在于，所述在所述晶圆表面淀积形成高温氧化膜的步骤的反应气体是N2O和SiH2Cl2。
  6. 根据权利要求1所述的方法，其特征在于，在所述晶圆表面淀积形成高温氧化膜的步骤之后，所述进行湿法腐蚀的步骤之前，还包括对晶圆进行热推阱的步骤。
  7. 根据权利要求1所述的方法，其特征在于，所述进行湿法腐蚀的步骤是采用固定腐蚀时间的方法进行腐蚀。
  8. 根据权利要求1所述的方法，其特征在于，在所述晶圆表面淀积形成高温氧化膜的步骤之前，还包括对晶圆表面进行化学机械研磨的步骤。
  9. 根据权利要求6所述的方法，其特征在于，所述对晶圆进行热推阱的步骤，温度为1000摄氏度以上，时间为60分钟以上。
  10. 一种横向扩散金属氧化物半导体场效应管，包括衬底，位于所述衬底内的第一N阱、第一P阱，位于所述第一N阱表面的第二N阱，位于所述第一P阱表面的第二P阱，及位于所述衬底上的沟道区浅槽隔离结构，所述沟道区浅槽隔离结构从第二N阱的表面向下延伸至其内部，所述横向扩散金属氧化物半导体场效应管还包括设于所述第二P阱表面的源极，设于所述第二N阱表面、且位于沟道区浅槽隔离结构远离所述第二P阱一端旁边的位置的漏极，及栅极、包括多晶硅栅和栅氧层，所述栅极的一端搭接于所述第二P阱上，另一端延伸至所述沟道区浅槽隔离结构上，其特征在于，还包括迷你氧化层，所述迷你氧化层一端搭接于所述沟道区浅槽隔离结构靠近所述第二P阱的一端上，另一端延伸至所述第二N阱上，且所述迷你氧化层被所述多晶硅栅极所覆盖。
  11. 根据权利要求10所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述横向扩散金属氧化物半导体场效应管为N沟道横向扩散金属氧化物半导体场效应管。
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CN106483758B (zh) 2015-09-02 2019-08-20 无锡华润上华科技有限公司 光学邻近效应修正方法和系统
CN106653842B (zh) 2015-10-28 2019-05-17 无锡华润上华科技有限公司 一种具有静电释放保护结构的半导体器件
CN106816468B (zh) 2015-11-30 2020-07-10 无锡华润上华科技有限公司 具有resurf结构的横向扩散金属氧化物半导体场效应管
CN107465983B (zh) 2016-06-03 2021-06-04 无锡华润上华科技有限公司 Mems麦克风及其制备方法
KR102227666B1 (ko) * 2017-05-31 2021-03-12 주식회사 키 파운드리 고전압 반도체 소자
CN112309865B (zh) * 2019-08-01 2022-10-18 无锡华润上华科技有限公司 横向扩散金属氧化物半导体器件及其制造方法
CN114864479A (zh) * 2022-04-27 2022-08-05 绍兴中芯集成电路制造股份有限公司 半导体器件及其制作方法
CN118610266B (zh) * 2024-08-08 2024-11-29 北京智芯微电子科技有限公司 横向双扩散场效应晶体管、制作方法、芯片及电路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262459B1 (en) * 2000-01-18 2001-07-17 United Microelectronics Corp. High-voltage device and method for manufacturing high-voltage device
CN101572271A (zh) * 2008-04-30 2009-11-04 万国半导体股份有限公司 短沟槽横向金属氧化物半导体场效应晶体管及其制造方法
CN102130170A (zh) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 高压隔离n型晶体管及高压隔离p型晶体管
CN102254946A (zh) * 2011-01-11 2011-11-23 苏州英诺迅科技有限公司 一种射频横向扩散n型mos管及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001015741A (ja) * 1999-06-30 2001-01-19 Toshiba Corp 電界効果トランジスタ
JP3831602B2 (ja) * 2000-12-07 2006-10-11 三洋電機株式会社 半導体装置の製造方法
DE102004018153B9 (de) * 2004-04-08 2012-08-23 Austriamicrosystems Ag Hochvolt-Sperrschicht-Feldeffekttransistor mit retrograder Gatewanne und Verfahren zu dessen Herstellung
WO2007072292A1 (en) * 2005-12-19 2007-06-28 Nxp B.V. Asymmetrical field-effect semiconductor device with sti region
US8274114B2 (en) * 2010-01-14 2012-09-25 Broadcom Corporation Semiconductor device having a modified shallow trench isolation (STI) region and a modified well region
TWI478336B (zh) * 2011-05-06 2015-03-21 漢磊科技股份有限公司 減少表面電場的結構及橫向雙擴散金氧半導體元件
JP5994238B2 (ja) * 2011-11-25 2016-09-21 トヨタ自動車株式会社 半導体装置の製造方法
CN102790089A (zh) * 2012-07-24 2012-11-21 华中科技大学 一种漏极下具有埋层的射频ldmos器件
JP2014107302A (ja) * 2012-11-22 2014-06-09 Renesas Electronics Corp 半導体装置
CN103151386A (zh) * 2013-03-27 2013-06-12 上海宏力半导体制造有限公司 横向扩散金属氧化物半导体器件及其制造方法
CN105810583B (zh) * 2014-12-30 2019-03-15 无锡华润上华科技有限公司 横向绝缘栅双极型晶体管的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262459B1 (en) * 2000-01-18 2001-07-17 United Microelectronics Corp. High-voltage device and method for manufacturing high-voltage device
CN101572271A (zh) * 2008-04-30 2009-11-04 万国半导体股份有限公司 短沟槽横向金属氧化物半导体场效应晶体管及其制造方法
CN102130170A (zh) * 2010-01-20 2011-07-20 上海华虹Nec电子有限公司 高压隔离n型晶体管及高压隔离p型晶体管
CN102254946A (zh) * 2011-01-11 2011-11-23 苏州英诺迅科技有限公司 一种射频横向扩散n型mos管及其制造方法

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