WO2016141652A1 - 移位寄存器单元、移位寄存器、显示面板及显示装置 - Google Patents

移位寄存器单元、移位寄存器、显示面板及显示装置 Download PDF

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Publication number
WO2016141652A1
WO2016141652A1 PCT/CN2015/084079 CN2015084079W WO2016141652A1 WO 2016141652 A1 WO2016141652 A1 WO 2016141652A1 CN 2015084079 W CN2015084079 W CN 2015084079W WO 2016141652 A1 WO2016141652 A1 WO 2016141652A1
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WIPO (PCT)
Prior art keywords
pull
signal input
node
input end
thin film
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PCT/CN2015/084079
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English (en)
French (fr)
Inventor
姚星
张元波
韩承佑
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京东方科技集团股份有限公司
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Priority to US14/909,661 priority Critical patent/US10403228B2/en
Publication of WO2016141652A1 publication Critical patent/WO2016141652A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit, a shift register, a display panel, and a display device.
  • the pull-up node is subjected to pull-down discharge processing to avoid erroneously turning on the gate driving signal during the processing of the frame.
  • the output control transistor causes an erroneous output of the gate drive signal.
  • the above pull-up node pull-low discharge processing is realized by using the output signal of the next shift register unit as a reset signal.
  • the output signal of the shift register unit is a short-time pulse signal, the time is very short, the amount of power that can be released is limited, and the discharge of the pull-up node is not complete.
  • the present disclosure provides a shift register unit, a shift register, a display panel, and a display device that ensure that the shift register unit operates as much as possible.
  • Embodiments of the present disclosure provide a shift register unit capable of forming a shift register by cascading, the shift register unit including a bootstrap capacitor connected to a driving output node of the stage and Between the pull nodes, the shift register unit further includes:
  • a first low level signal input end for receiving the first low level signal
  • a source and a drain are respectively connected to the first low level signal input terminal and the discharge thin film transistor of the pull-up node;
  • a first discharge control unit connected to a gate of the discharge thin film transistor for outputting a first control signal to a gate of the discharge thin film transistor between a first time and a second time, such that the discharge film
  • the transistor is in an on state to output the first low level signal to the pull up node, and discharge the pull up node
  • the first time is an end time of the first frame processed by the shift register
  • the second time is a start time of the second frame adjacent to the first frame by the shift register.
  • the discharge thin film transistor is:
  • a gate of the first reset thin film transistor is further connected to a reset signal input end;
  • a thin film transistor is pulled down, and a gate of the pull-down thin film transistor is also connected to the pull-down node.
  • the first discharge control unit includes:
  • a first control signal input terminal for receiving a first control signal between the first time and the second time
  • the gate is connected to the first control signal input end, and the source and the drain are respectively connected to the first control signal input end and the control thin film transistor of the gate of the discharge thin film transistor.
  • the shift register unit further includes:
  • a first pull-down node potential control unit configured to control the pull-down node to be at a low level when the pull-up node is at a high level
  • the second pull-down node potential control unit is configured to control the pull-down node to be at a high level after the level driving output node outputs a high level.
  • the first pull-down node potential control unit includes:
  • a gate connection is input to the pull-up node, and a source and a drain are respectively connected to the thin film transistor of the pull-down node and the first low-level signal input end;
  • the gate is connected to the input signal input end, and the source and the drain are respectively connected to the thin film transistor of the pull-down node and the first low-level signal input end.
  • the second pull-down node potential control unit includes:
  • a pull-down node control signal input end is configured to receive a first pull-down node control signal, and after the first stage driving output node outputs a high level, the first pull-down node control signal is a high level;
  • the gate is connected to the pull-down node control signal input end, and the source and the drain are respectively connected to the pull-down node control signal input end and the thin film transistor of the pull-down node.
  • the pull-down node control signal is a signal formed by alternating a high level signal and a low level signal.
  • the shift register unit further includes:
  • a driving signal input end for receiving a gate driving signal
  • a gate is connected to the pull-up node, and a source and a drain are respectively connected to the driving signal input end and the thin film transistor of the driving output node of the current stage;
  • the first pull-down node potential control unit further includes:
  • the gate is connected to the gate driving signal input end, and the source and the drain are respectively connected to the thin film transistor of the pull-down node and the first low-level signal input end;
  • the gate drive signal is an inverted signal of the pull-down node control signal.
  • the shift register unit further includes:
  • a driving signal input end for receiving a gate driving signal
  • a gate is connected to the pull-up node, and a source and a drain are respectively connected to the driving signal input end and the thin film transistor of the driving output node of the current stage;
  • a gate is connected to the reset signal input end, and a source and a drain are respectively connected to the first low level signal input end and the first reset thin film transistor of the pull-up node;
  • a gate is connected to the reset signal input end, and a source and a drain are respectively connected to the second reset thin film transistor of the current driving output node and the second low level signal input end,
  • the voltage value of the first low level signal outputted by the first low level signal input end is smaller than the voltage value of the second low level signal outputted by the second low level signal input end.
  • the shift register unit further includes:
  • the gate is connected to the pull-down node, and the source and the drain are respectively connected to the driving output node of the current stage and the first a thin film transistor at the input of the low level signal;
  • a gate connection pull-down node control signal input end, a source and a drain are respectively connected to the thin film transistor of the current driving output node and the second low level signal input end;
  • the pull-down node control signal input terminal inputs a high level.
  • the shift register unit further includes:
  • a driving signal input end for receiving a gate driving signal
  • a gate is connected to the pull-up node, and a source and a drain are respectively connected to the driving signal input end and the thin film transistor of the driving output node of the current stage;
  • a gate is connected to the pull-up node, and a source and a drain are respectively connected to the driving signal input end and the thin film transistor of the current control output node;
  • the gate is connected to the pull-down node, and the source and the drain are respectively connected to the thin film transistor of the current control output node and the first low level signal input end,
  • the control output node is connected to a start signal input end of the shift register unit of the next stage and a reset signal input end of the shift register unit of the previous stage.
  • the embodiment of the present disclosure further provides a shift register unit driving method, which is specifically applicable to driving the shift register unit provided by the above embodiments of the present disclosure;
  • the method includes:
  • the first discharge control unit outputs the first control signal to the gate of the discharge thin film transistor such that the discharge thin film transistor is in an on state to connect the source and drain of the discharge thin film transistor a circuit between the first low level signal input end and the pull up node is turned on, so that the first low level signal received by the first low level signal input end is output to the pull up node, Pull the node to discharge.
  • the first control signal input end receives a low level signal
  • the start signal input end receives a high level signal
  • the drive signal input end receives a low level signal
  • the pull down node control signal input end Receiving a high level signal, the reset signal input terminal receiving a low level signal
  • the first control signal input end receives a low level signal
  • the start signal input end receives a low level signal
  • the drive signal input end receives a high level signal
  • the pull down node control signal input end receives a low level a signal
  • the reset signal input terminal receives a low level signal
  • the first control signal input end receives a low level signal
  • the start signal input end receives a low level signal
  • the drive signal input end receives a low level signal
  • the pull down node control signal input end receives a high level signal.
  • the reset signal input receives a high level signal
  • the first control signal input end receives a high level signal
  • the start signal input end, the drive signal input end, the pull-down node control signal input end, and the reset signal input end have no signal reception.
  • the first phase, the second phase, and the third phase are continuous time phases in each frame period
  • the fourth phase is between the first time and the second time.
  • the embodiment of the present disclosure also provides a shift register that can be specifically formed by cascading shift register units provided by a plurality of the above-described embodiments of the present disclosure.
  • the embodiment of the present disclosure further provides a display panel, and the display panel may specifically include the shift register provided by the embodiment of the present disclosure.
  • the embodiment of the present disclosure further provides a display device, which may specifically include the display panel provided by the above embodiments of the present disclosure.
  • the shift register unit, the shift register, the display panel and the display device provided by the present disclosure are provided in the shift register unit by: a first low level signal input terminal for receiving the first a low level signal; a source and a drain respectively connected to the first low level signal input terminal and the discharge thin film transistor of the pull-up node; a first discharge control unit, and a gate of the discharge thin film transistor Connecting, for outputting a first control signal to a gate of the discharge thin film transistor between the first time and the second time, so that the discharge thin film transistor is in an on state to be the first low level signal Outputting to the pull-up node, discharging the pull-up node; the first time is an end time of processing the first frame by the shift register, and the second time is processing by the shift register The start time of the second frame adjacent to the first frame, so that the pull-up node can be pulled down between adjacent two frame processing, so that the pull-up node can be released in time to process the previous frame.
  • the residual electric signal
  • FIG. 1 is a schematic structural diagram 1 of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram 2 of a shift register unit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram 3 of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram 4 of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram 5 of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram 6 of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram 7 of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram 8 of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram 9 of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 11 is a timing diagram of a shift register unit provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a shift register unit capable of forming a shift register in a cascade manner.
  • the shift register unit includes a bootstrap capacitor C connected between the driving output node OUTPUT of the stage and the pull-up node PU.
  • the shift register unit may further include:
  • a first low level signal input terminal LVGL for receiving the first low level signal
  • the source and the drain are respectively connected to the first low level signal input terminal LVGL and the discharge thin film transistor M1 of the pull-up node PU;
  • the first discharge control unit 1 is connected to the gate of the discharge thin film transistor M1 for outputting a first control signal to the gate of the discharge thin film transistor M1 between the first time and the second time such that the discharge thin film transistor M1 is at The on state is to output the first low level signal to the pull-up node PU, and discharge the pull-up node PU.
  • the first time involved in the embodiment of the present disclosure may be that the shift register processes the end time of the first frame
  • the second time involved in the embodiment of the present disclosure may be specifically the shift register processing and the first The start time of the second frame adjacent to the frame.
  • the first time and the second time involved in the embodiments of the present disclosure are not limited thereto.
  • the shift register unit provided by the embodiment of the present disclosure can perform the pull-down processing on the pull-up node PU between the adjacent two frame processing by the setting of the first pull-down control unit 1 described above, so that the pull-up node PU can be released in time
  • the electrical signal remaining after the processing of the previous frame by the pull-up node PU avoids the residual electrical signal accumulated as noise to the next frame processing period after the processing of the previous frame, ensuring as much as possible The normal operation of the shift register unit.
  • the discharge thin film transistor M1 according to the embodiment of the present disclosure may be separately provided to realize the function of discharging thereof.
  • stage I the pull-up node PU should be pulled high
  • the shift register In the second stage, the PU potential of the pull-up node continues to rise, and the shift register outputs a high level
  • the potential of the pull-up node PU is discharged to a low level.
  • the pull-up node PU needs to be pulled low to a low level.
  • the pull-up node PU there are two ways to discharge the pull-up node PU, including:
  • the signal when the next shift register unit outputs a high level signal, the signal is simultaneously used as a reset signal of the shift register unit of the previous stage, and is output to the first connection of the pull-up node PU and the low-level signal input end. Resetting the gate of the thin film transistor M2; and
  • a high level signal is output to the gate of the pull-down thin film transistor M8 that connects the pull-up node PU and the low-level signal input terminal.
  • the first discharge control unit 1 controls the discharge thin film transistor M1 to discharge the pull-up node PU between adjacent frames, and also needs to perform the pull-up node PU during the processing of each frame.
  • the pull-down discharge process (as in the discharge reset phase), and the time of the two discharge processes are staggered from each other and do not affect each other. Therefore, in a specific embodiment of the present disclosure, the first thin film transistor M1 can be implemented by using a pull-down thin film transistor M8 or a first reset transistor M2 during frame processing to reduce the use of the thin film transistor and reduce the circuit design. Complexity and implementation costs.
  • the discharge thin film transistor M1 may further be: a first reset thin film transistor M2 (as shown in FIG. 2), or a pull-down thin film transistor M8 (as shown in FIG. 3). Show).
  • the gate of the first reset thin film transistor M2 is connected to the reset signal input terminal Rst in addition to the first discharge control unit 1, so that the first reset thin film transistor M2 is in the discharge reset phase. And in the time period between two consecutive frames, the pull-up node PU is discharged separately.
  • the gate of the pull-down thin film transistor M8 is connected to the first discharge control unit 1.
  • the pull-down node PD is also connected to cause the pull-down thin film transistor M8 to discharge the pull-up node PU in the discharge reset phase and the period between two consecutive frames.
  • a specific implementation manner of the first discharge control unit 1 according to the embodiment of the present disclosure may be as shown in FIG. 4, including:
  • a first control signal input terminal STV configured to receive the first control signal received between the first time and the second time
  • the gate is connected to the first control signal input terminal STV, and the source and the drain are respectively connected to the first control signal input terminal STV and the control thin film transistor M10 of the gate of the discharge thin film transistor M1.
  • the discharge thin film transistor may be a separately disposed discharge thin film transistor M1, a first reset thin film transistor M2, or a pull-down thin film transistor M8.
  • the first control signal input terminal STV receives the first control signal having a potential (high level or low level) for control
  • the thin film transistor M10 is in an on state.
  • the first control signal can be transmitted to the gate of the discharge thin film transistor M1, and the discharge thin film transistor M1 is placed in an on state to perform discharge processing on the pull-up node PU between the first time and the second time.
  • the pull-down node PD voltage control mode may also be introduced, for example, by introducing a start signal (which is generally a signal outputted by the shift register unit of the upper stage) in the precharge phase to ensure pulldown.
  • the node PD can be pulled low to prevent the residual electrical signal of the pull-down node PD from affecting the pull-down thin film transistor M8, improving the performance of the shift register.
  • the shift register unit may further include:
  • a first pull-down node potential control unit 2 configured to control the pull-down node PD to be at a low level when the pull-up node PU is at a high level
  • the second pull-down node potential control unit 3 is configured to control the pull-down node PD to be at a high level after the current stage drive output node OUTPUT outputs a high level (for example, a discharge reset stage after the charging phase).
  • the first pull-down node potential control unit 2 may specifically include:
  • the gate is connected to the input pull-up node PU, and the source and the drain are respectively connected to the pull-down node PD and the thin film transistor M6 of the first low-level signal input terminal LVGL;
  • the gate connection start signal input terminal INPUT, and the source and the drain are respectively connected to the pull-down node PD and the thin film transistor M7 of the first low-level signal input terminal LVGL.
  • the second pull-down node potential control unit 3 may specifically include:
  • the pull-down node PD control signal input terminal CLKB is configured to receive the first pull-down node PD control signal, and the first pull-down node PD control signal is at a high level after the first stage driving output node OUTPUT outputs a high level;
  • the gate is connected to the pull-down node PD control signal input terminal CLKB, and the source and the drain are respectively connected to the pull-down node PD control signal input terminal CLKB and the thin film transistor M5 of the pull-down node PD.
  • the pull-down thin film transistor M8 is always in an on state until the next pull-up node PU is at a high level. Therefore, in the prior art, the pull-down thin film transistor M8 is in a gate high voltage state for a long time, resulting in a short lifetime.
  • the setting of the signal input terminal CLKB is controlled by the pull-down node PD such that the pull-down node PD is periodically in a high state (ie, discharged) only between the two pull-down processes. In the reset phase), the time during which the pull-down thin film transistor M8 controlled by the pull-down node PD is in the gate high voltage state is greatly reduced, and the lifetime of the device is improved.
  • a thin film transistor M15 may be disposed in the shift register unit provided by the embodiment of the present disclosure to implement control of the enable signal input terminal INPUT.
  • the pull-down node PD control signal may specifically be a signal formed by alternately forming a high level signal and a low level signal.
  • the pull-down node PD When the stage drive output node OUTPUT outputs a high level (ie, the charging phase), the pull-down node PD needs to be at a low level to avoid erroneous conduction of the pull-down thin film transistor M8, resulting in a thin film transistor M3 for controlling the gate drive signal output. Wrong turn off.
  • the thin film transistor M6 and the thin film transistor M7 have been provided.
  • a gate driving signal is further introduced to control the conduction of a newly added thin film transistor M9, and the potential control of the pull-down node PD is realized to ensure shifting.
  • the register unit works normally.
  • the gate drive signal is designed to be a high-low level periodically changing signal, so that the newly added thin film transistor M9 will not be in the gate high voltage state for a long time, thereby improving the device lifetime.
  • the shift register unit provided by the embodiment of the present disclosure may further include:
  • the gate is connected to the pull-up node PU, and the source and the drain are respectively connected to the driving signal input terminal CLK and the thin film transistor M3 of the driving output node OUTPUT of the current stage;
  • the first pull-down node PD potential control unit 2 may further include:
  • the gate is connected to the gate driving signal input terminal CLK, and the source and the drain are respectively connected to the pull-down node PD and the thin film transistor M9 of the first low-level signal input terminal LVGL.
  • the gate driving signal may specifically be an inverted signal of the pull-down node PD control signal.
  • the threshold voltage of the largest thin film transistor M3 is generally positive. However, due to factors such as the manufacturing process and the working environment, the threshold voltage of the thin film transistor M3 may drift and a negative value may occur.
  • two low-level signal input terminals that is, the first low-level signal input terminal LVGL and the second low may be disposed.
  • the level signal input terminal VGL, the pull-down of the driving output node OUTPUT of the current stage is responsible for the signal outputted by the second low-level signal input terminal VGL, and the pull-up node PU is pulled lower by the voltage value of the output low-level signal.
  • the signal input from the low first low level signal input terminal LVGL is responsible, so that the shift register can operate normally even when the threshold voltage of the thin film transistor M3 is negative.
  • the shift register unit provided by the embodiment of the present disclosure may further include:
  • the gate is connected to the pull-up node PU, and the source and the drain are respectively connected to the driving signal input terminal CLK and the thin film transistor M3 of the driving output node OUTPUT of the current stage;
  • the gate is connected to the reset signal input terminal Rst, and the source and the drain are respectively connected to the first low level signal input terminal LVGL and the first reset thin film transistor M2 of the pull-up node PU;
  • the gate is connected to the reset signal input terminal Rst, and the source and the drain are respectively connected to the second reset thin film transistor M4 of the first stage driving output node OUTPUT and the second low level signal input terminal VGL.
  • the voltage value of the first low level signal is smaller than the voltage value of the second low level signal.
  • the embodiment of the present disclosure further provides at least one auxiliary low-lowering thin film transistor for the pull-down of the drive output node OUTPUT of the stage.
  • M13 and/or thin film transistor M14 wherein thin film transistor M13 is controlled by pull-down node PD, and thin film transistor M14 is controlled by a signal output from pull-down node PD control signal input terminal CLKB.
  • the pull-down node PD when the driving output node OUTPUT of the current stage outputs a high level, the pull-down node PD should be at a high level to turn on the pull-down thin film transistor M8 to ensure that the pull-up node PU is at a low level.
  • the pull-down node PD control signal input terminal CLKB outputs a high level.
  • the pull-down node PD is at a high level, and the pull-down node PD control signal input terminal CLKB also outputs a high level, both of which can achieve the function of the reset signal.
  • the shift register unit provided by the embodiment of the present disclosure may further include:
  • the gate is connected to the pull-down node PD, and the source and the drain are respectively connected to the thin film transistor M13 of the driving output node OUTPUT and the second low-level signal input terminal VGL; and/or
  • the gate is connected to the pull-down node PD control signal input terminal CLKB, and the source and the drain are respectively connected to the thin film transistor M14 of the current-stage driving output node OUTPUT and the second low-level signal input terminal VGL.
  • the pull-down node PD control signal input terminal CLKB outputs a high level.
  • each shift register unit has three functions, including:
  • control signal is output to the next stage shift register unit as the start signal of the next stage shift register unit.
  • each shift register unit has only one drive output node OUTPUT, so that its control and output are implemented by a node or interface. It is easy to cause interference between control and output.
  • a mirror node of the driving output node of the present stage is added in the embodiment of the present disclosure, that is, the control output node OUTPUT_C of the current level (the output signals of the two are the same but the connection relationship is different) to realize the separation of the control and the output. , reducing mutual interference between control and output.
  • the driver output node of the stage can be connected to the corresponding gate line, and the control output node of the stage can be connected to the shift register unit of the upper stage and the next stage.
  • a thin film transistor M12 can be additionally controlled by the pull-down node PD to perform continuous discharge, and prevent the output driver node OUTPUT from outputting an erroneous signal.
  • the shift register unit provided by the embodiment of the present disclosure may further include:
  • the gate is connected to the pull-up node PU, and the source and the drain are respectively connected to the driving signal input terminal CLK and the thin film transistor M3 of the driving output node OUTPUT of the current stage;
  • the gate is connected to the pull-up node PU, the source and the drain are respectively connected to the driving signal input terminal CLK and the thin film transistor M11 of the current-level control output node OUTPUT_C;
  • the gate is connected to the pull-down node PD, the source and the drain are respectively connected to the thin film transistor M12 of the local control output node OUTPUT_C and the first low-level signal input terminal LVGL;
  • the control output node is connected to the start signal input terminal INPUT of the next stage shift register unit and the reset signal input terminal Rst of the shift register unit of the previous stage.
  • FIG. 1 A complete structural diagram of the shift register unit provided by the embodiments of the present disclosure may be as shown in FIG.
  • the thin film transistor according to the embodiment of the present disclosure may specifically be an N-type thin film transistor.
  • the above thin film transistor may also be a P-type thin film transistor by a simple timing change.
  • the embodiment of the present disclosure also provides a shift register unit driving method, which may be specifically used to drive the shift register unit passed by the above embodiments of the present disclosure.
  • the method may specifically include:
  • the first discharge control unit 1 outputs the first control signal to the gate of the discharge thin film transistor M1 such that the discharge thin film transistor M1 is in an on state, so that the discharge thin film transistor M1 is sourced,
  • the first low level signal input terminal LVGL and pull-up of the drain connection The circuit between the nodes UP is turned on, so that the first low level signal received by the first low level signal input terminal LVGL is output to the pull-up node PU, and the pull-up node PU is discharged.
  • the first time involved in the embodiment of the present disclosure may be that the shift register processes the end time of the first frame
  • the second time involved in the embodiment of the present disclosure may be specifically the shift register processing and the first The start time of the second frame adjacent to the frame.
  • the shift register unit provided by the embodiment of the present disclosure may specifically include three phases in a frame time period: a first phase, that is, a precharge phase, a second phase, that is, a charging phase, and a third phase, that is, a discharge reset phase. Since the pull-up register PU can also discharge the pull-up node PU between adjacent two frames in the shift register provided by the embodiment of the present disclosure, in the timing diagram shown in FIG. 11, the adjacent two frames are further included. The discharge phase.
  • the first control signal input terminal STV can receive a low-level signal
  • the start signal input terminal INPUT can receive a high-level signal
  • the driving signal input terminal CLK can receive
  • the pull-down node PD control signal input terminal CLKB can receive a high level signal
  • the reset signal input terminal Rst can receive a low level signal.
  • the thin film transistor M15, the thin film transistor M6, and the thin film transistor M7 are in an on state, the pull-up node PU potential is pulled high, the pull-down node PD potential is pulled low, the thin film transistor M14 is in an on state, and the driving output node OUTPUT output is low.
  • the level signal, the thin film transistor M11 is in an on state, and the control output node OUTPUT_C outputs a low level signal.
  • the charging phase (which can also be understood as the output phase)
  • the first control signal input terminal STV can receive a low level signal
  • the enable signal input terminal INPUT can receive a low level signal
  • the driving signal input terminal CLK can receive a high level.
  • the level signal, the pull-down node PD control signal input terminal CLKB can receive a low level signal
  • the reset signal input terminal Rst can receive a low level signal.
  • the thin film transistor M3 is in an on state, and the output output node OUTPUT outputs a high level signal.
  • the potential of the pull-up node PU is pulled high again, and the thin film transistor M11 is in an on state, and the control output is controlled.
  • the node OUTPUT_C outputs a high level signal, and the thin film transistor M9 is turned on. State, the pull-down node PD continues to be discharged causing the potential to be pulled low again.
  • the third stage is the discharge reset stage
  • the first control signal input terminal STV can receive the low level signal
  • the start signal input terminal INPUT can receive the low level signal
  • the drive signal input terminal CLK can receive the low level signal
  • the pulldown node PD controls
  • the signal input terminal CLKB can receive a high level signal
  • the reset signal input terminal Rst can receive a high level signal.
  • the thin film transistor M5 is in an on state
  • the thin film transistor M6, the thin film transistor M7, and the thin film transistor M9 are in an off state, causing the potential of the pull-down node PD to be pulled high, thereby causing the pull-down thin film transistor M8 to be in an on state.
  • the first reset thin film transistor M2 is also in an on state, thereby achieving discharge to the pull-up node PU.
  • the thin film transistor M12, the thin film transistor M13, the thin film transistor M14, and the second reset thin film transistor M4 are in an on state, thereby discharging the driving output node OUTPUT and the control output node OUTPUT_C, thereby implementing the pull-up node PU, the driving output node OUTPUT, and Controls the reset operation of the output node OUTPUT_C.
  • the first control signal input terminal STV can receive a high level signal, and the signal input terminal can be input without a signal.
  • the control thin film transistor M10 and the pull-down thin film transistor M8 are in an on state, so that the pull-up node PU can be discharged between adjacent two frame processing, that is, between the first time and the second time,
  • the electrical signal remaining after the processing of the previous frame by the pull-up node PU can be released in time, thereby avoiding the residual electrical signal accumulated as noise after the processing of the previous frame to the next frame processing cycle, thereby avoiding the false output of the gate signal, etc.
  • the embodiment of the present disclosure may further provide a shift register, which may be specifically implemented by a plurality of shift register unit stages provided by the above embodiments of the present disclosure. Formed together.
  • the shift register according to the embodiment of the present disclosure may specifically be a single gate type or a double gate type shift register. Since the single-gate type shift register is only common, the embodiments of the present disclosure will not be described again.
  • the shift register provided by the embodiment of the present disclosure is a double gate structure, a specific structural diagram thereof may be as shown in FIG.
  • the embodiment of the present disclosure further provides a display panel, which may specifically include the shift register provided by the above embodiments of the present disclosure.
  • the embodiment of the present disclosure further provides a display device, which may specifically include A display panel provided by an embodiment of the present disclosure.
  • the display device may specifically be a display device such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED display, a plasma display, or an electronic paper.
  • a display device such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED display, a plasma display, or an electronic paper.
  • the shift register unit, the shift register, the display panel and the display device described in the present disclosure are particularly suitable for the GOA circuit requirements under the low temperature polysilicon technology (LTPS) process, and are also applicable to the GOA circuit under the amorphous silicon process.
  • LTPS low temperature polysilicon technology
  • the pixel circuit provided by the embodiments of the present disclosure can be applied to a thin film transistor of a process of amorphous silicon, polysilicon, oxide, or the like. At the same time, the above circuit can be easily changed to use a P-type thin film transistor, or a CMOS transistor circuit.
  • the shift register unit, the shift register, the display panel and the display device provided by the present disclosure are provided in the shift register unit by: a first low level signal input terminal for receiving the first low level signal; a source a drain connected to the first low level signal input terminal and the discharge thin film transistor of the pull-up node, respectively; a first discharge control unit connected to a gate of the discharge thin film transistor for use in the first time And outputting a first control signal to the gate of the discharge thin film transistor between the second time, so that the discharge thin film transistor is in an on state to output the first low level signal to the pull-up node, Discharging the pull-up node; the first time is an end time of processing the first frame by the shift register, and the second time is processing by the shift register adjacent to the first frame The start time of the second frame.
  • the pull-up node can be pulled down between adjacent two frames of processing, so that the electrical signal remaining after the processing of the previous frame by the pull-up node can be released in time, thereby avoiding residual electricity after the processing of the previous frame is completed.
  • the signal is accumulated as noise to the next frame processing cycle, ensuring the normal operation of the shift register unit as much as possible.

Abstract

提供了一种移位寄存器单元、移位寄存器、显示面板以及显示装置。所述移位寄存器单元包括一自举电容（C），所述自举电容（C）连接于本级驱动输出节点（OUTPUT）和上拉节点（PU）之间，所述移位寄存器单元还包括：第一低电平信号输入端（LVGL），用于接收第一低电平信号（）；源极、漏极分别连接到所述第一低电平信号输入端（LVGL）和所述上拉节点（PU）的放电薄膜晶体管（M1）；第一放电控制单元（1），与所述放电薄膜晶体管（M1）的栅极连接，用于在第一时间和第二时间之间将第一控制信号输出到所述放电薄膜晶体管（M1）的栅极，使得所述放电薄膜晶体管（M1）处于导通状态，以将所述第一低电平信号输出到所述上拉节点（PU），对所述上拉节点（PU）进行放电。还提供了一种用于驱动的移位寄存器单元的驱动方法。

Description

移位寄存器单元、移位寄存器、显示面板及显示装置
相关申请的交叉参考
本申请主张在2015年3月9日在中国提交的中国专利申请号No.201510102986.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及显示技术领域，具体涉及一种移位寄存器单元、移位寄存器、显示面板及显示装置。
背景技术
现有技术中，在每一帧处理过程中，都会在本级驱动输出节点输出栅极驱动信号之后，对上拉节点进行拉低放电处理，以免在本帧处理过程中误打开栅极驱动信号输出控制晶体管，造成栅极驱动信号的误输出。
然而，现有技术中，上述的上拉节点拉低放电处理都是利用下一个移位寄存器单元的输出信号作为复位信号来实现的。而移位寄存器单元的输出信号是一个短时间的脉冲信号，时间非常短，能够释放的电量有限，导致上拉节点的放电并不完全。
这种帧内处理的放电不完全在短时间来看问题并不大，但一旦连续工作一段时间后，累积的电量越来越多，就会导致上拉节点处于不正确电位。进而，如果在本级输出栅极驱动信号之后还是保持高电平，会致使栅极驱动信号输出控制晶体管仍然处于导通状态，从而造成栅极驱动信号的误输出。
发明内容
(一)要解决的技术问题
本公开文本提供一种移位寄存器单元、移位寄存器、显示面板及显示装置，可尽可能地确保移位寄存器单元正常工作。
(二)技术方案
本公开文本所提供的技术方案如下：
本公开文本实施例提供了一种移位寄存器单元，能够通过级联方式形成移位寄存器，所述移位寄存器单元包括一自举电容，所述自举电容连接于本级驱动输出节点和上拉节点之间，所述移位寄存器单元还包括：
第一低电平信号输入端，用于接收第一低电平信号；
源极、漏极分别连接到所述第一低电平信号输入端和所述上拉节点的放电薄膜晶体管；以及
第一放电控制单元，与所述放电薄膜晶体管的栅极连接，用于在第一时间和第二时间之间将第一控制信号输出到所述放电薄膜晶体管的栅极，使得所述放电薄膜晶体管处于导通状态，以将所述第一低电平信号输出到所述上拉节点，对所述上拉节点进行放电，
所述第一时间为所述移位寄存器处理完第一帧的结束时间，所述第二时间为所述移位寄存器处理与所述第一帧相邻的第二帧的开始时间。
可选的，所述放电薄膜晶体管为：
第一复位薄膜晶体管，所述第一复位薄膜晶体管的栅极还与复位信号输入端连接；或
下拉薄膜晶体管，所述下拉薄膜晶体管的栅极还与下拉节点连接。
可选的，所述第一放电控制单元包括：
第一控制信号输入端，用于在第一时间和第二时间之间接收第一控制信号；以及
栅极连接所述第一控制信号输入端，源、漏极分别连接到所述第一控制信号输入端和所述放电薄膜晶体管的栅极的控制薄膜晶体管。
可选的，所述移位寄存器单元还包括：
第一下拉节点电位控制单元，用于在上拉节点处于高电平时控制所述下拉节点处于低电平；以及
第二下拉节点电位控制单元，用于在本级驱动输出节点输出高电平后控制所述下拉节点处于高电平。
可选的，所述第一下拉节点电位控制单元包括：
栅极连接输入所述上拉节点，源极、漏极分别连接到所述下拉节点和所述第一低电平信号输入端的薄膜晶体管；
栅极连接输入信号输入端，源极、漏极分别连接到所述下拉节点和所述第一低电平信号输入端的薄膜晶体管。
可选的，所述第二下拉节点电位控制单元包括：
下拉节点控制信号输入端，用于接收第一下拉节点控制信号，本级驱动输出节点输出高电平后，所述第一下拉节点控制信号为高电平；
栅极连接所述下拉节点控制信号输入端，源极、漏极分别连接到所述下拉节点控制信号输入端和所述下拉节点的薄膜晶体管。
可选的，所述下拉节点控制信号为高电平信号和低电平信号交替形成的信号。
可选的，所述移位寄存器单元还包括：
驱动信号输入端，用于接收栅极驱动信号；
栅极连接所述上拉节点，源极、漏极分别连接到所述驱动信号输入端和本级驱动输出节点的薄膜晶体管；
所述第一下拉节点电位控制单元还包括：
栅极连接栅极驱动信号输入端，源极、漏极分别连接到所述下拉节点和所述第一低电平信号输入端的薄膜晶体管；
所述栅极驱动信号为所述下拉节点控制信号的反相信号。
可选的，所述移位寄存器单元还包括：
驱动信号输入端，用于接收栅极驱动信号；
栅极连接所述上拉节点，源极、漏极分别连接到所述驱动信号输入端和本级驱动输出节点的薄膜晶体管；
栅极连接所述复位信号输入端，源极、漏极分别连接到所述第一低电平信号输入端和所述上拉节点的第一复位薄膜晶体管；以及
栅极连接所述复位信号输入端，源极、漏极分别连接到所述本级驱动输出节点和第二低电平信号输入端的第二复位薄膜晶体管，
所述第一低电平信号输入端输出的第一低电平信号的电压值小于所述第二低电平信号输入端输出的第二低电平信号的电压值。
可选的，所述移位寄存器单元还包括：
栅极连接下拉节点，源极、漏极分别连接到所述本级驱动输出节点和第 二低电平信号输入端的薄膜晶体管；和/或
栅极连接下拉节点控制信号输入端，源极、漏极分别连接到所述本级驱动输出节点和第二低电平信号输入端的薄膜晶体管；
本级驱动输出节点输出高电平后，所述下拉节点控制信号输入端输入高电平。
可选的，所述移位寄存器单元还包括：
驱动信号输入端，用于接收栅极驱动信号；
栅极连接所述上拉节点，源极、漏极分别连接到所述驱动信号输入端和所述本级驱动输出节点的薄膜晶体管；
栅极连接所述上拉节点，源极、漏极分别连接到所述驱动信号输入端和本级控制输出节点的薄膜晶体管；以及
栅极连接下拉节点，源极、漏极分别连接到所述本级控制输出节点和第一低电平信号输入端的薄膜晶体管，
所述控制输出节点和下一级移位寄存器单元的启动信号输入端以及上一级移位寄存器单元的复位信号输入端连接。
本公开文本实施例还提供了一种移位寄存器单元驱动方法，该方法具体可用于驱动上述本公开文本实施例提供的移位寄存器单元；
所述方法包括：
在第一时间和第二时间之间，第一放电控制单元将第一控制信号输出到放电薄膜晶体管的栅极，使得放电薄膜晶体管处于导通状态，以使放电薄膜晶体管源极、漏极连接的第一低电平信号输入端与上拉节点之间电路导通，使所述第一低电平信号输入端接收的第一低电平信号输出到所述上拉节点，对所述上拉节点进行放电。
可选的，所述方法在第一阶段，第一控制信号输入端接收低电平信号，启动信号输入端接收高电平信号，驱动信号输入端接收低电平信号，下拉节点控制信号输入端接收高电平信号，复位信号输入端接收低电平信号；
所述方法在第二阶段，第一控制信号输入端接收低电平信号，启动信号输入端接收低电平信号，驱动信号输入端接收高电平信号，下拉节点控制信号输入端接收低电平信号，复位信号输入端接收低电平信号；
上述方法在第三阶段，第一控制信号输入端接收低电平信号，启动信号输入端接收低电平信号，驱动信号输入端接收低电平信号，下拉节点控制信号输入端接收高电平信号，复位信号输入端接收高电平信号；以及
所述方法在第四阶段，第一控制信号输入端接收高电平信号，启动信号输入端、驱动信号输入端、下拉节点控制信号输入端、复位信号输入端无信号接收，
所述第一阶段、第二阶段、第三阶段，为所述每一帧周期内连续的时间阶段；
所述第四阶段处于所述第一时间和第二时间之间。
本公开文本实施例还提供了一种移位寄存器，所述移位寄存器具体可由多个上述本公开文本实施例提供的移位寄存器单元级联形成。
本公开文本实施例还提供了一种显示面板，所述显示面板具体可以包括上述本公开文本实施例提供的移位寄存器。
本公开文本实施例还提供了一种显示装置，所述显示装置具体可以包括上述本公开文本实施例提供的显示面板。
(三)有益效果
本公开文本的有益效果如下：
从以上所述可以看出，本公开文本提供的移位寄存器单元、移位寄存器、显示面板以及显示装置，通过在移位寄存器单元中设置：第一低电平信号输入端，用于接收第一低电平信号；源极、漏极分别连接到所述第一低电平信号输入端和所述上拉节点的放电薄膜晶体管；第一放电控制单元，与所述放电薄膜晶体管的栅极连接，用于在第一时间和第二时间之间输出第一控制信号到所述放电薄膜晶体管的栅极，使得所述放电薄膜晶体管处于导通状态，以将所述第一低电平信号输出到所述上拉节点，对所述上拉节点进行放电；所述第一时间为所述移位寄存器处理完第一帧的结束时间，所述第二时间为所述移位寄存器处理与所述第一帧相邻的第二帧的开始时间，从而可在相邻的两帧处理之间，对上拉节点进行拉低处理，从而可及时释放上拉节点在上一帧处理过后残留的电信号，避免了上一帧处理完毕之后残留的电信号作为噪声累积到下一帧处理周期，尽可能地保证了移位寄存器单元的正常工作。
附图说明
为了更清楚地说明本公开文本实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开文本实施例提供的移位寄存器单元结构示意图一；
图2为本公开文本实施例提供的移位寄存器单元结构示意图二；
图3为本公开文本实施例提供的移位寄存器单元结构示意图三；
图4为本公开文本实施例提供的移位寄存器单元结构示意图四；
图5为本公开文本实施例提供的移位寄存器单元结构示意图五；
图6为本公开文本实施例提供的移位寄存器单元结构示意图六；
图7为本公开文本实施例提供的移位寄存器单元结构示意图七；
图8为本公开文本实施例提供的移位寄存器单元结构示意图八；
图9为本公开文本实施例提供的移位寄存器单元结构示意图九；
图10为本公开文本实施例提供的移位寄存器单元结构示意图十；
图11为本公开文本实施例提供的移位寄存器单元所适用的时序示意图；以及
图12为本公开文本实施例提供的移位寄存器结构示意图。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
为使本公开文本实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本实施例的附图，对本公开文本实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所 属领域内具有一般技能的人士所理解的通常意义。本公开文本专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
以下结合附图对本公开文本的原理和特征进行描述，所举实例只用于解释本公开文本，并非用于限定本公开文本的范围。
本公开文本实施例提供了一种移位寄存器单元，能够通过级联方式形成移位寄存器。具体的，该移位寄存器单元包括一自举电容C，该自举电容C连接于本级驱动输出节点OUTPUT和上拉节点PU之间。
如图1所示，该移位寄存器单元具体还可以包括：
第一低电平信号输入端LVGL，用于接收第一低电平信号；
源极、漏极分别连接到第一低电平信号输入端LVGL和上拉节点PU的放电薄膜晶体管M1；
第一放电控制单元1，与放电薄膜晶体管M1的栅极连接，用于在第一时间和第二时间之间将第一控制信号输出到放电薄膜晶体管M1的栅极，使得放电薄膜晶体管M1处于导通状态，以将第一低电平信号输出到上拉节点PU，对上拉节点PU进行放电。
本公开文本实施例中所涉及的第一时间，具体可为移位寄存器处理完第一帧的结束时间，本公开文本实施例所涉及的第二时间，具体可为移位寄存器处理与第一帧相邻的第二帧的开始时间。当然，本公开文本实施例中所涉及的第一时间和第二时间并不局限于此。
本公开文本实施例所提供的移位寄存器单元，通过上述第一下拉控制单元1的设置，可在相邻的两帧处理之间，对上拉节点PU进行拉低处理，从而可及时释放上拉节点PU在上一帧处理过后残留的电信号，避免了上一帧处理完毕之后残留的电信号作为噪声累积到下一帧处理周期，尽可能地保证 了移位寄存器单元的正常工作。
在一具体实施例中，本公开文本实施例所涉及的放电薄膜晶体管M1可以被单独设置，以实现其放电的功能。
另外，移位寄存器的工作可以概括为如下的几个阶段，如下：
第I阶段，上拉节点PU应该被拉高；
第II阶段，上拉节点PU电位继续升高，移位寄存器输出高电平；
第III阶段，放电及复位阶段，此时上拉节点PU的电位放电至低电平。
那么可以发现，在第三阶段，上拉节点PU需要被拉低至低电平并维持低电平。而在第三阶段对上拉节点PU进行放电有两种方式，包括：
如图2所示，当下一个移位寄存器单元输出高电平信号时，该信号同时作为上一级移位寄存器单元的复位信号，输出到连接上拉节点PU和低电平信号输入端的第一复位薄膜晶体管M2的栅极；和
如图3所示，通过控制下拉节点PD处于高电平，并将高电平信号输出到连接上拉节点PU和低电平信号输入端的下拉薄膜晶体管M8的栅极。
通过以上描述可以发现，第一放电控制单元1是在相邻帧之间控制放电薄膜晶体管M1对上拉节点PU进行放电，而在每一帧的处理过程中，也需要对上拉节点PU进行下拉放电处理(如在放电复位阶段)，而两个放电过程的时间相互错开，并不会相互影响。因此，在本公开文本的具体实施例中，上述的第一薄膜晶体管M1可以利用帧处理过程中的下拉薄膜晶体管M8或第一复位晶体管M2来实现，以减少薄膜晶体管的使用，降低电路设计的复杂度和实现成本。
可见，在具体的实施例中，本公开文本实施例所涉及的放电薄膜晶体管M1具体还可为：第一复位薄膜晶体管M2(如图2所示)，或者下拉薄膜晶体管M8(如图3所示)。
那么，从图2中发现，第一复位薄膜晶体管M2的栅极除与第一放电控制单元1连接之外，还与复位信号输入端Rst连接，以使第一复位薄膜晶体管M2在放电复位阶段以及连续两帧之间的时间段内，分别对上拉节点PU进行放电。
而如图3所示，下拉薄膜晶体管M8的栅极除与第一放电控制单元1连 接之外，还与下拉节点PD连接，以使下拉薄膜晶体管M8在放电复位阶段以及连续两帧之间的时间段内，分别对上拉节点PU进行放电。
在一具体实施例中，本公开文本实施例所涉及的第一放电控制单元1的具体实现方式可如图4所示，包括：
第一控制信号输入端STV，用于接收在第一时间和第二时间之间接收第一控制信号；以及
栅极连接第一控制信号输入端STV，源极、漏极分别连接到第一控制信号输入端STV和放电薄膜晶体管M1的栅极的控制薄膜晶体管M10。
在图4所示实施例中，放电薄膜晶体管既可为单独设置的放电薄膜晶体管M1，也可以是第一复位薄膜晶体管M2，或者是下拉薄膜晶体管M8。
那么，在本公开文本实施例所涉及的第一时间与第二时间之间，第一控制信号输入端STV接收具有一电位(高电平或低电平)的第一控制信号，以使控制薄膜晶体管M10处于导通状态。这样，第一控制信号可以传输至放电薄膜晶体管M1的栅极，使放电薄膜晶体管M1处于导通状态，以实现在第一时间与第二时间之间对上拉节点PU进行放电处理。
在本公开文本一具体实施例中，还可通过引入下拉节点PD电压控制方式，例如引入预充电阶段处于高电平的启动信号(一般为上一级移位寄存器单元输出的信号)来确保下拉节点PD的可以被拉低，以防止下拉节点PD的残留电信号对下拉薄膜晶体管M8的影响，提升移位寄存器的性能。
如图5所示，该实施例中，移位寄存器单元具体还可以包括：
第一下拉节点电位控制单元2，用于在上拉节点PU处于高电平时控制下拉节点PD处于低电平；以及
第二下拉节点电位控制单元3，用于在本级驱动输出节点OUTPUT输出高电平后(例如充电阶段之后放电复位阶段)控制下拉节点PD处于高电平。
第一下拉节点电位控制单元2具体可以包括：
栅极连接输入上拉节点PU，源极、漏极分别连接到下拉节点PD和第一低电平信号输入端LVGL的薄膜晶体管M6；
栅极连接启动信号输入端INPUT，源极、漏极分别连接到下拉节点PD和第一低电平信号输入端LVGL的薄膜晶体管M7。
另外，第二下拉节点电位控制单元3具体可以包括：
下拉节点PD控制信号输入端CLKB，用于接收第一下拉节点PD控制信号，本级驱动输出节点OUTPUT输出高电平后，第一下拉节点PD控制信号为高电平；以及
栅极连接下拉节点PD控制信号输入端CLKB，源极、漏极分别连接到下拉节点PD控制信号输入端CLKB和下拉节点PD的薄膜晶体管M5。
在现有技术中，当本级驱动输出节点OUTPUT输出高电平信号之后，下拉薄膜晶体管M8一直处于导通的状态，直至下一次上拉节点PU处于高电平。因此，在现有技术中，下拉薄膜晶体管M8会长时间处于栅极高压状态，导致寿命较短。为了克服上述问题，在本公开文本的具体实施例中，通过下拉节点PD控制信号输入端CLKB的设置，使得下拉节点PD仅在两次拉低过程之间周期性处于高电平状态(即放电复位阶段)，大大缩减了由下拉节点PD控制的下拉薄膜晶体管M8处于栅极高压状态的时间，提高了器件的寿命。
另外，如图5所示，本公开文本实施例所提供的移位寄存器单元内还可以设置薄膜晶体管M15，以实现对启动信号输入端INPUT的控制。
本公开文本实施例中，下拉节点PD控制信号具体可为高电平信号和低电平信号交替形成的信号。
在本级驱动输出节点OUTPUT输出高电平时(即充电阶段)，下拉节点PD需要处于低电平，以避免错误的导通下拉薄膜晶体管M8，造成用于控制栅极驱动信号输出的薄膜晶体管M3错误的关断。在本公开文本的具体实施例中，已经设置了薄膜晶体管M6和薄膜晶体管M7。但为了确保下拉节点PD处于正确的电位，本公开文本具体实施例中，进一步引入栅极驱动信号来控制一个新增加的薄膜晶体管M9的导通，实现对下拉节点PD的电位控制，确保移位寄存器单元的正常工作。
同时，设计栅极驱动信号为高低电平周期性变化的信号，使得新增加的薄膜晶体管M9不会长期处于栅极高压状态，从而提高器件寿命。
那么，在一具体实施例中，如图6所示，本公开文本实施例所提供的所述移位寄存器单元具体还可以包括：
驱动信号输入端CLK，用于接收栅极驱动信号；
栅极连接上拉节点PU，源极、漏极分别连接到驱动信号输入端CLK和本级驱动输出节点OUTPUT的薄膜晶体管M3；
第一下拉节点PD电位控制单元2具体还可以包括：
栅极连接栅极驱动信号输入端CLK，源极、漏极分别连接到下拉节点PD和第一低电平信号输入端LVGL的薄膜晶体管M9。
本公开文本实施例中，栅极驱动信号具体可为下拉节点PD控制信号的反相信号。
在移位寄存器电路中传统的GOA电路，最大的薄膜晶体管M3的阈值电压一般为正值。但由于制作工艺、工作环境等因素的影响，薄膜晶体管M3的阈值电压会产生漂移，出现负值的情形。为了保证薄膜晶体管M3阈值电压为负时还能够正常工作，在本公开文本的具体实施例中，还可设置两个低电平信号输入端即第一低电平信号输入端LVGL和第二低电平信号输入端VGL，本级驱动输出节点OUTPUT的拉低由第二低电平信号输入端VGL输出的信号负责，而上拉节点PU的拉低由输出的低电平信号的电压值更低的第一低电平信号输入端LVGL输入的信号负责，使得即使薄膜晶体管M3阈值电压为负时移位寄存器仍能够正常工作。
另外，如图7所示，本公开文本实施例提供的移位寄存器单元具体还可以包括：
驱动信号输入端CLK，用于接收栅极驱动信号；
栅极连接上拉节点PU，源极、漏极分别连接到驱动信号输入端CLK和本级驱动输出节点OUTPUT的薄膜晶体管M3；
栅极连接复位信号输入端Rst，源极、漏极分别连接到第一低电平信号输入端LVGL和上拉节点PU的第一复位薄膜晶体管M2；以及
栅极连接复位信号输入端Rst，源极、漏极分别连接到本级驱动输出节点OUTPUT和第二低电平信号输入端VGL的第二复位薄膜晶体管M4。
同时，该实施例中，第一低电平信号的电压值小于第二低电平信号的电压值。
为了保证本级驱动输出节点OUTPUT的正常工作，本公开文本实施例还为本级驱动输出节点OUTPUT的拉低提供了至少一个辅助拉低的薄膜晶体管 M13和/或薄膜晶体管M14，其中薄膜晶体管M13由下拉节点PD控制，而薄膜晶体管M14由下拉节点PD控制信号输入端CLKB输出的信号控制。
按照驱动时序的设计，当本级驱动输出节点OUTPUT输出高电平之后，下拉节点PD应该处于高电平，以导通下拉薄膜晶体管M8，保证上拉节点PU处于低电平。而本级驱动输出节点OUTPUT输出高电平后，下拉节点PD控制信号输入端CLKB输出高电平。
因此，当本级驱动输出节点OUTPUT输出高电平之后，下拉节点PD处于高电平，而下拉节点PD控制信号输入端CLKB也输出高电平，二者都可以达到重置信号的作用，实现了对第二复位薄膜晶体管M4的备份。
另外，如图8所示，本公开文本实施例所提供的移位寄存器单元，具体还可以包括：
栅极连接下拉节点PD，源极、漏极分别连接到本级驱动输出节点OUTPUT和第二低电平信号输入端VGL的薄膜晶体管M13；和/或
栅极连接下拉节点PD控制信号输入端CLKB，源极、漏极分别连接到本级驱动输出节点OUTPUT和第二低电平信号输入端VGL的薄膜晶体管M14。
本级驱动输出节点OUTPUT输出高电平后，所述下拉节点PD控制信号输入端CLKB输出高电平。
现有技术中，每一个移位寄存器单元的输出都具有3个作用，包括：
1、将栅极驱动信号输出给显示区域的栅线，以实现显示区域的按行扫描；
2、将控制信号输出给上一级移位寄存器单元，作为上一级移位寄存器单元的复位信号；以及
3、将控制信号输出给下一级移位寄存器单元，作为下一级移位寄存器单元的启动信号。
从以上的描述可以发现，移位寄存器单元的输出有3个作用，在现有技术中，每一个移位寄存器单元都只有一个驱动输出节点OUTPUT，因此其控制和输出由一个节点即接口来实现，容易导致控制和输出之间相互干扰。
为了降低这种干扰，本公开文本实施例中增加一个本级驱动输出节点的镜像节点，即本级控制输出节点OUTPUT_C(二者的输出信号相同但连接关系不同)，以实现控制和输出的分离，降低控制和输出之间的相互干扰。
在一具体实施例中，本级驱动输出节点可与对应的栅线连接，而本级控制输出节点可与上一级和下一级移位寄存器单元连接。
按照驱动时序的设计，当本级驱动输出节点OUTPUT输出高电平之后，下拉节点PD应该处于高电平，以导通下拉薄膜晶体管M8，保证上拉节点PU处于低电平。因此，在本公开文本具体实施例中，可增设一薄膜晶体管M12由下拉节点PD控制进行放电，实现了持续的放电，防止本级驱动输出节点OUTPUT输出错误的信号。
另外，如图9所示，本公开文本实施例提供的移位寄存器单元具体还可以包括：
驱动信号输入端CLK，用于接收栅极驱动信号；
栅极连接上拉节点PU，源极、漏极分别连接到驱动信号输入端CLK和本级驱动输出节点OUTPUT的薄膜晶体管M3；
栅极连接所述上拉节点PU，源极、漏极分别连接到驱动信号输入端CLK和本级控制输出节点OUTPUT_C的薄膜晶体管M11；
栅极连接下拉节点PD，源极、漏极分别连接到所述本级控制输出节点OUTPUT_C和第一低电平信号输入端LVGL的薄膜晶体管M12；
所述控制输出节点和下一级移位寄存器单元的启动信号输入端INPUT以及上一级移位寄存器单元的复位信号输入端Rst连接。
本公开文本实施例所提供的移位寄存器单元的一个完整结构示意图可如图10所示。
上述本公开文本实施例所涉及的薄膜晶体管，具体可为N型薄膜晶体管，但是，可以理解的是，通过简单的时序变化，以上薄膜晶体管还可为P型薄膜晶体管。
本公开文本实施例还提供了一种移位寄存器单元驱动方法，该方法具体可以用于驱动上述本公开文本实施例通过的移位寄存器单元。
该方法具体可以包括：
在第一时间和第二时间之间，第一放电控制单元1将第一控制信号输出到放电薄膜晶体管M1的栅极，使得放电薄膜晶体管M1处于导通状态，以使放电薄膜晶体管M1源、漏极连接的第一低电平信号输入端LVGL与上拉 节点UP之间电路导通，使第一低电平信号输入端LVGL接收的第一低电平信号输出到上拉节点PU，对上拉节点PU进行放电。
本公开文本实施例中所涉及的第一时间，具体可为移位寄存器处理完第一帧的结束时间，本公开文本实施例所涉及的第二时间，具体可为移位寄存器处理与第一帧相邻的第二帧的开始时间。
下面，以附图11所示时序图应用于如图10所示移位寄存器单元为例，对本公开文本实施例提供的移位寄存器单元的一个具体工作周期进行详细的描述。
本公开文本实施例所提供的移位寄存器单元，在一帧时间周期内，具体可以包括三个阶段：第一阶段即预充电阶段、第二阶段即充电阶段以及第三阶段即放电复位阶段。由于本公开文本实施例所提供的移位寄存器中还可在相邻的两帧之间对上拉节点PU进行放电，因此，在图11所示时序图中，还包括相邻两帧之间的放电阶段。
具体的：
在第一阶段即预充电阶段(图11中A所示)，第一控制信号输入端STV可接收低电平信号，启动信号输入端INPUT可接收高电平信号，驱动信号输入端CLK可接收低电平信号，下拉节点PD控制信号输入端CLKB可接收高电平信号，复位信号输入端Rst可接收低电平信号。相应的，薄膜晶体管M15、薄膜晶体管M6、薄膜晶体管M7处于导通状态，上拉节点PU电位被拉高，下拉节点PD电位被拉低，薄膜晶体管M14处于导通状态，驱动输出节点OUTPUT输出低电平信号，薄膜晶体管M11处于导通状态，控制输出节点OUTPUT_C输出低电平信号。
在第二阶段即充电阶段(也可以理解为输出阶段)，第一控制信号输入端STV可接收低电平信号，启动信号输入端INPUT可接收低电平信号，驱动信号输入端CLK可接收高电平信号，下拉节点PD控制信号输入端CLKB可接收低电平信号，复位信号输入端Rst可接收低电平信号。相应的，薄膜晶体管M3处于导通状态，驱动输出节点OUTPUT输出高电平信号，基于电容C的自举效应，上拉节点PU的电位再次被拉高，薄膜晶体管M11处于导通状态，控制输出节点OUTPUT_C输出高电平信号，薄膜晶体管M9处于导通状 态，下拉节点PD继续被放电而导致电位再次被拉低。
第三阶段即放电复位阶段，第一控制信号输入端STV可接收低电平信号，启动信号输入端INPUT可接收低电平信号，驱动信号输入端CLK可接收低电平信号，下拉节点PD控制信号输入端CLKB可接收高电平信号，复位信号输入端Rst可接收高电平信号。相应的，薄膜晶体管M5处于导通状态，薄膜晶体管M6、薄膜晶体管M7、薄膜晶体管M9处于截止状态，致使下拉节点PD的电位被拉高，从而使下拉薄膜晶体管M8处于导通状态。同时，第一复位薄膜晶体管M2也处于导通状态，从而实现对上拉节点PU的放电。薄膜晶体管M12、薄膜晶体管M13、薄膜晶体管M14以及第二复位薄膜晶体管M4处于导通状态，从而实现对驱动输出节点OUTPUT以及控制输出节点OUTPUT_C的放电，从而实现上拉节点PU、驱动输出节点OUTPUT以及控制输出节点OUTPUT_C的复位操作。
第四阶段即放电阶段，第一控制信号输入端STV可接收高电平信号，其信号输入端可无信号输入。相应的，控制薄膜晶体管M10以及下拉薄膜晶体管M8处于导通状态，从而可在相邻的两帧处理之间，即第一时间与第二时间之间，对上拉节点PU进行放电处理，因此可及时释放上拉节点PU在上一帧处理过后残留的电信号，避免了上一帧处理完毕之后残留的电信号作为噪声累积到下一帧处理周期，因此可避免栅极信号的误输出等情况的出现，尽可能地保证了移位寄存器单元的正常工作。
基于本公开文本实施例所提供的移位寄存器单元，本公开文本实施例具体还可以提供一种移位寄存器，该移位寄存器具体可由多个上述本公开文本实施例提供的移位寄存器单元级联形成。
本公开文本实施例所涉及的移位寄存器，具体可为单栅型或双栅型移位寄存器。由于单栅型移位寄存器仅为常见，因此本公开文本实施例不再赘述。而当本公开文本实施例所提供的移位寄存器为双栅型结构时，其具体结构示意图可如图12所示。
本公开文本实施例还提供了一种显示面板，该显示面板具体可以包括上述本公开文本实施例提供的移位寄存器。
本公开文本实施例还提供了一种显示装置，该显示装置具体可以包括上 述本公开文本实施例提供的显示面板。
该显示装置具体可以为液晶面板、液晶电视、液晶显示器、OLED面板、OLED显示器、等离子显示器或电子纸等显示装置。
本公开文本所述的移位寄存器单元、移位寄存器、显示面板与显示装置，特别适合低温多晶硅技术(LTPS)制程下的GOA电路需求，也可适用于非晶硅工艺下的GOA电路。
需指出的是，本公开文本实施例所提供的像素电路可适用于非晶硅、多晶硅、氧化物等工艺的薄膜晶体管。同时，上述电路还可以轻易的改成采用P型薄膜晶体管，或CMOS管电路。
本公开文本提供的移位寄存器单元、移位寄存器、显示面板以及显示装置，通过在移位寄存器单元中设置：第一低电平信号输入端，用于接收第一低电平信号；源极、漏极分别连接到所述第一低电平信号输入端和所述上拉节点的放电薄膜晶体管；第一放电控制单元，与所述放电薄膜晶体管的栅极连接，用于在第一时间和第二时间之间输出第一控制信号到所述放电薄膜晶体管的栅极，使得所述放电薄膜晶体管处于导通状态，以将所述第一低电平信号输出到所述上拉节点，对所述上拉节点进行放电；所述第一时间为所述移位寄存器处理完第一帧的结束时间，所述第二时间为所述移位寄存器处理与所述第一帧相邻的第二帧的开始时间。从而可在相邻的两帧处理之间，对上拉节点进行拉低处理，从而可及时释放上拉节点在上一帧处理过后残留的电信号，避免了上一帧处理完毕之后残留的电信号作为噪声累积到下一帧处理周期，尽可能地保证了移位寄存器单元的正常工作。
以上所述是本公开文本的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开文本所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开文本的保护范围。

Claims (15)

  1. 一种移位寄存器单元，能够通过级联方式形成移位寄存器，所述移位寄存器单元包括一自举电容，所述自举电容连接于本级驱动输出节点和上拉节点之间，所述移位寄存器单元还包括：
    第一低电平信号输入端，用于接收第一低电平信号；
    源极、漏极分别连接到所述第一低电平信号输入端和所述上拉节点的放电薄膜晶体管；
    第一放电控制单元，与所述放电薄膜晶体管的栅极连接，用于在第一时间和第二时间之间将第一控制信号输出到所述放电薄膜晶体管的栅极，使得所述放电薄膜晶体管处于导通状态，以将所述第一低电平信号输出到所述上拉节点，对所述上拉节点进行放电，
    其中，所述第一时间为所述移位寄存器处理完第一帧的结束时间，所述第二时间为所述移位寄存器处理与所述第一帧相邻的第二帧的开始时间。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述放电薄膜晶体管为：
    第一复位薄膜晶体管，所述第一复位薄膜晶体管的栅极还与复位信号输入端连接；或
    下拉薄膜晶体管，所述下拉薄膜晶体管的栅极还与下拉节点连接。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述第一放电控制单元包括：
    第一控制信号输入端，用于在第一时间和第二时间之间接收第一控制信号；以及
    栅极连接所述第一控制信号输入端，源极、漏极分别连接到所述第一控制信号输入端和所述放电薄膜晶体管的栅极的控制薄膜晶体管。
  4. 根据权利要求2或3所述的移位寄存器单元，还包括：
    第一下拉节点电位控制单元，用于在上拉节点处于高电平时控制所述下拉节点处于低电平；以及
    第二下拉节点电位控制单元，用于在本级驱动输出节点输出高电平后控 制所述下拉节点处于高电平。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述第一下拉节点电位控制单元包括：
    栅极连接输入所述上拉节点，源极、漏极分别连接到所述下拉节点和所述第一低电平信号输入端的薄膜晶体管；以及
    栅极连接输入信号输入端，源极、漏极分别连接到所述下拉节点和所述第一低电平信号输入端的薄膜晶体管；并且
    所述第二下拉节点电位控制单元包括：
    下拉节点控制信号输入端，用于接收第一下拉节点控制信号，本级驱动输出节点输出高电平后，所述第一下拉节点控制信号为高电平；以及
    栅极连接所述下拉节点控制信号输入端，源极、漏极分别连接到所述下拉节点控制信号输入端和所述下拉节点的薄膜晶体管。
  6. 根据权利要求5所述的移位寄存器单元，其中，所述下拉节点控制信号为高电平信号和低电平信号交替形成的信号。
  7. 根据权利要求5所述的移位寄存器单元，还包括：
    驱动信号输入端，用于接收栅极驱动信号；
    栅极连接所述上拉节点，源极、漏极分别连接到所述驱动信号输入端和本级驱动输出节点的薄膜晶体管；
    所述第一下拉节点电位控制单元还包括：
    栅极连接栅极驱动信号输入端，源极、漏极分别连接到所述下拉节点和所述第一低电平信号输入端的薄膜晶体管；
    所述栅极驱动信号为所述下拉节点控制信号的反相信号。
  8. 根据权利要求1-6中任意一项所述的移位寄存器单元，还包括：
    驱动信号输入端，用于接收栅极驱动信号；
    栅极连接所述上拉节点，源极、漏极分别连接到所述驱动信号输入端和本级驱动输出节点的薄膜晶体管；
    栅极连接所述复位信号输入端，源极、漏极分别连接到所述第一低电平信号输入端和所述上拉节点的第一复位薄膜晶体管；以及
    栅极连接所述复位信号输入端，源极、漏极分别连接到所述本级驱动输 出节点和第二低电平信号输入端的第二复位薄膜晶体管，
    其中，所述第一低电平信号输入端输出的第一低电平信号的电压值小于所述第二低电平信号输入端输出的第二低电平信号的电压值。
  9. 根据权利要求8所述的移位寄存器单元，还包括：
    栅极连接下拉节点，源极、漏极分别连接到所述本级驱动输出节点和第二低电平信号输入端的薄膜晶体管；和/或
    栅极连接下拉节点控制信号输入端，源极、漏极分别连接到所述本级驱动输出节点和第二低电平信号输入端的薄膜晶体管，
    其中，本级驱动输出节点输出高电平后，所述下拉节点控制信号输入端输入高电平。
  10. 根据权利要求1-6中任意一项所述的移位寄存器单元，还包括：
    驱动信号输入端，用于接收栅极驱动信号；
    栅极连接所述上拉节点，源极、漏极分别连接到所述驱动信号输入端和所述本级驱动输出节点的薄膜晶体管；
    栅极连接所述上拉节点，源极、漏极分别连接到所述驱动信号输入端和本级控制输出节点的薄膜晶体管；以及
    栅极连接下拉节点，源极、漏极分别连接到所述本级控制输出节点和第一低电平信号输入端的薄膜晶体管，
    其中，所述控制输出节点和下一级移位寄存器单元的启动信号输入端以及上一级移位寄存器单元的复位信号输入端连接。
  11. 一种移位寄存器单元驱动方法，所述方法用于驱动如权利要求1所述的移位寄存器单元；
    所述方法包括：
    在第一时间和第二时间之间，第一放电控制单元将第一控制信号输出到放电薄膜晶体管的栅极，使得放电薄膜晶体管处于导通状态，以使放电薄膜晶体管源极、漏极连接的第一低电平信号输入端与上拉节点之间电路导通，使所述第一低电平信号输入端接收的第一低电平信号输出到所述上拉节点，对所述上拉节点进行放电。
  12. 如权利要求11所述的方法，其中，所述方法在第一阶段，第一控制 信号输入端接收低电平信号，启动信号输入端接收高电平信号，驱动信号输入端接收低电平信号，下拉节点控制信号输入端接收高电平信号，复位信号输入端接收低电平信号；
    所述方法在第二阶段，第一控制信号输入端接收低电平信号，启动信号输入端接收低电平信号，驱动信号输入端接收高电平信号，下拉节点控制信号输入端接收低电平信号，复位信号输入端接收低电平信号；
    上述方法在第三阶段，第一控制信号输入端接收低电平信号，启动信号输入端接收低电平信号，驱动信号输入端接收低电平信号，下拉节点控制信号输入端接收高电平信号，复位信号输入端接收高电平信号；以及
    所述方法在第四阶段，第一控制信号输入端接收高电平信号，启动信号输入端、驱动信号输入端、下拉节点控制信号输入端、复位信号输入端无信号接收，
    其中，所述第一阶段、第二阶段、第三阶段，为所述每一帧周期内连续的时间阶段；并且
    所述第四阶段处于所述第一时间和第二时间之间。
  13. 一种移位寄存器，所述移位寄存器由多个如权利要求1-10任一项所述的移位寄存器单元级联形成。
  14. 一种显示面板，包括如权利要求13所述的移位寄存器。
  15. 一种显示装置，包括如权利要求14所述的显示面板。
PCT/CN2015/084079 2015-03-09 2015-07-15 移位寄存器单元、移位寄存器、显示面板及显示装置 WO2016141652A1 (zh)

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