WO2016114377A1 - 半導体素子とその製造方法 - Google Patents
半導体素子とその製造方法 Download PDFInfo
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- WO2016114377A1 WO2016114377A1 PCT/JP2016/051078 JP2016051078W WO2016114377A1 WO 2016114377 A1 WO2016114377 A1 WO 2016114377A1 JP 2016051078 W JP2016051078 W JP 2016051078W WO 2016114377 A1 WO2016114377 A1 WO 2016114377A1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76866—Surface Channel CCD
- H01L29/76891—Four-Phase CCD
Definitions
- the present invention relates to a semiconductor device that can be reduced in size and weight and can be flexibly selected in addition to high integration, high-speed driving, and low power consumption, and a manufacturing method thereof.
- the number of input / output terminals and the area occupied by the input / output buffer circuit increase due to the expansion of the address width and data bit length, and the effective area on the semiconductor element, that is, the relative occupation of internal integrated circuits and memory cells New problems such as the area being pressed by these input / output terminals and input / output buffer circuits are becoming prominent.
- Patent Document 1 discloses a structure of a semiconductor image sensor for imaging an X-ray image, in which X-rays are incident from a side surface portion of a semiconductor substrate, and the X-rays are parallel to the semiconductor substrate surface inside the semiconductor substrate.
- An example of enabling X-ray spectroscopic analysis by performing photoelectric conversion while proceeding to is disclosed.
- this principle is applied to a CT scanner (Patent Document 2).
- it is a semiconductor imaging device whose main purpose is to capture an infrared image, in which visible light or infrared light is incident from a side surface portion of the semiconductor substrate, and the infrared light or the like travels in a direction parallel to the semiconductor substrate surface inside the semiconductor substrate.
- Patent Document 3 An example is disclosed that enables spectral analysis using infrared rays or the like by performing photoelectric conversion between them (Patent Document 3).
- the aim is to increase the photoelectric conversion efficiency in the semiconductor substrate by making light incident in a direction parallel to the surface of the semiconductor substrate.
- visible light such as a digital camera
- the above substrate depth direction is deeper, for example, a depth of several tens of micrometers to several hundreds of micrometers is required, so the drive voltage is set to several tens of volts or more.
- the drive voltage is set to several tens of volts or more.
- This goes against the demands for high integration, high speed driving, and low power consumption.
- a structure in which infrared rays, X-rays, and the like are incident from the side surface portion of the semiconductor substrate has been devised.
- one side surface of the rectangular semiconductor substrate cannot be directly used as the photoelectric conversion unit. This is because the side wall portion of the semiconductor element to be the light receiving surface is mechanically and thermally damaged.
- the side edge of the semiconductor substrate constituting the semiconductor imaging device is first exposed immediately after the semiconductor wafer dicing in the latter half of the manufacturing process (post process). Therefore, the crystal state of the side edge of the semiconductor substrate causes chipping and scratches when using a rotating blade, and there are further problems such as re-adhesion of the melt when using a laser saw. Even in the method, the semiconductor substrate material itself has a large amount of defects, and a precise machining shape cannot be expected. Further, the light receiving surface based on such a manufacturing method is used in a state where the semiconductor substrate is exposed to the outside air as it is, and seriously reduces not only image quality but also reliability and product life as a semiconductor imaging device. Invite a problem.
- the number of input / output terminals for example, contact pads, arranged on the outer periphery of the semiconductor element surface increases. Since the size of the input / output terminals requires an area for wire bonding, it is difficult to miniaturize the transistor elements and the like at the same time. Further, a transistor element or the like cannot be formed in the semiconductor substrate portion located below the input / output terminal. For this reason, the element size (so-called chip size) does not depend on the memory capacity or logic circuit scale that should be integrated on the element, and the element size depends on the number of input / output terminals and their arrangement.
- a typical example is a semiconductor image pickup device for an endoscope that requires a reduction in element size.
- the area occupied by the input / output terminal portion on the semiconductor element can be reduced by adopting electrical connection by micropads and microbumps instead of wire bonding, or through silicon via (TSV) structure.
- TSV through silicon via
- the increase in the area occupied by the input / output terminals and the input / output buffer circuit due to the expansion of the address width and the data bit length tends to exceed this, and a fundamental solution has not been achieved. That is, in addition to reducing the area occupied by the input / output terminal portion, it is necessary to effectively use the peripheral peripheral region of the semiconductor element surface that has not been used as a conventional scribe (or dicing) margin.
- a semiconductor element is obtained by cutting (dicing) a semiconductor wafer and dividing (dividing into pieces) into individual semiconductor elements.
- the peripheral part of the semiconductor element surface or the side wall of the semiconductor element is mechanically and thermally damaged by this dicing process, so that crystal defects are generated and exposed to contamination from heavy metals and reactive chemical substances from the outside. ing.
- a semiconductor element shape other than a rectangle is required in order to efficiently incorporate a semiconductor element inside a casing whose outer shape is nearly circular. Further, if the smoothness and crystal defect level of the semiconductor substrate in the vicinity of the side wall portion can be improved to the extent that the side wall portion of the semiconductor element can be used and impurity contamination from the outside can be prevented, the outer periphery of the semiconductor element can be obtained.
- a logic element and a memory element can be arranged in a part close to the part. Considering the case where a semiconductor imaging element and an image processing semiconductor element are stacked, it is often desirable that the external shapes of different types of semiconductor elements to be stacked are the same. This is because a plurality of stacked semiconductor wafers can be divided into pieces by dicing or the like. In addition, between the semiconductor elements, the input / output terminals, that is, the arrangement of the TSV structure needs to match between adjacent semiconductor elements.
- a new structure capable of further increasing the degree of integration on a semiconductor element, or an element form in which a semiconductor element can be easily used in various application products or use environments, Finding a semiconductor device structure that can improve power consumption driving or environmental performance, semiconductor devices that effectively use the periphery or side of the semiconductor substrate, and noise caused by interface states, lattice defects, etc.
- Semiconductor device structure capable of preventing deterioration of reliability and reliability, and a semiconductor device capable of effectively utilizing a peripheral portion or side surface portion of a semiconductor substrate, and contaminated with heavy metals or reactive chemical substances It is a problem to be solved by the present invention to provide a structure of a semiconductor element or the like that can protect the product and prevent deterioration of the product life.
- a structure of a semiconductor image sensor that is sensitive to infrared light and X-rays and can be driven at low voltage and low power consumption, it improves environmental resistance against temperature, humidity, vibration, etc.
- Realization of a solid-state image pickup device realization of a solid-state image pickup device that can flexibly image various subjects, for example, the size and shape of a human body or an organ, and in particular, close proximity or direct contact with the subject.
- a semiconductor imaging device suitable for application to a large imaging device such as a CT apparatus for image signal processing. It is to realize high speed.
- Another object of the present invention is to realize a high-quality semiconductor imaging device having an imaging surface isotropic with respect to a subject or a light source, or reducing crosstalk between adjacent pixels. Another object of the present invention is to realize a high-sensitivity semiconductor image sensor capable of imaging even weak light. Another object of the present invention is to realize a semiconductor imaging device that prevents deterioration of the device due to radiation damage and improves reliability and product life. Another object of the present invention is to realize a semiconductor imaging device capable of preventing image deterioration such as noise and pixel scratches caused by interface states, lattice defects, and the like in the periphery of a semiconductor substrate used in a semiconductor imaging device.
- Another object of the present invention is to devise a semiconductor image pickup device structure that can improve reliability and product life by protecting the semiconductor image pickup device from contamination of heavy metals or reactive chemical substances.
- Another object of the present invention is to realize a semiconductor imaging device capable of expanding the imageable range by increasing the number of pixels or improving the resolution of a captured image.
- Still another object of the present invention is a semiconductor device that effectively uses a peripheral portion or a side portion of a semiconductor substrate, and prevents performance deterioration such as noise and pixel defects caused by interface states and lattice defects. It is providing the manufacturing method of the semiconductor element which can be performed. It is another object of the present invention to provide a manufacturing method capable of easily processing the shape of the end portion on the semiconductor substrate side into a curved or other arbitrary shape. Furthermore, it is a semiconductor element that effectively uses the peripheral part or the side part of the semiconductor substrate, and protects the semiconductor element, the semiconductor imaging element, etc. from contamination by heavy metals or reactive chemical substances, and prevents deterioration of the product life. It is providing the manufacturing method of a semiconductor element etc. which can be performed. It is another object of the present invention to provide a manufacturing method suitable for manufacturing a laminated semiconductor element in which a plurality of semiconductor elements or the like that effectively use a peripheral part or a side part of a semiconductor substrate are stacked.
- a laminated semiconductor element in which a plurality of semiconductor elements in which an integrated circuit or the like is formed is laminated, and at least one surface of the laminated semiconductor element excluding the semiconductor substrate front surface and the semiconductor substrate back surface is covered with an insulator, and the remaining The other surface has a structure in which the semiconductor substrate is exposed as it is.
- the side surface of the laminated semiconductor element covered with the insulator has a structure that is curved in a plan view with respect to the semiconductor substrate surface on which the integrated circuit or the like is formed.
- the outer peripheral shape of the side surface portion of the laminated semiconductor element is surrounded by a closed figure that is smoothly continuous on the plane view, and the side surface portion of the laminated semiconductor element is covered with an insulator.
- the closed figure is circular.
- the laminated semiconductor element has a structure in which a hollow region is partially removed from the semiconductor element substrate surface on which an integrated circuit or the like is formed in a plan view.
- the side surface of the laminated semiconductor element in the hollow region is covered with an insulator.
- the hollow region is a figure surrounded by the curve on the plane view, and the outer peripheral shape of the laminated semiconductor element is also a figure surrounded by the curve on the plane view with respect to the semiconductor element substrate surface on which the integrated circuit or the like is formed.
- the side surface portion of the laminated semiconductor substrate element covered with the insulator has a structure having a high concentration impurity region in a lower region of the insulator.
- a metal layer 18 is formed between the top and bottom surfaces of the laminated semiconductor element 700, between the semiconductor elements 701 and 702, and between 702 and 703. Further, a sidewall metal layer is formed on the side wall of the hollow portion. Preferably, the metal layer and the sidewall metal layer have a structure in which a part thereof is in contact with each other.
- the semiconductor substrate is a silicon substrate and the insulating film is a silicon oxide film.
- a side surface portion of the semiconductor substrate covered with the insulator or a side surface portion of the hollow area covered with the insulator is used as a light receiving surface, and the photoelectric conversion region is from the light receiving surface (or light receiving window) side to the semiconductor. It extends in the direction parallel to the semiconductor substrate plane toward the inside of the substrate.
- photoelectric conversion regions formed in a radial direction corresponding to the incident light direction are provided in a direction perpendicular to the curved light receiving surface.
- the arrangement pitch of the light receiving windows in the stacking direction of the semiconductor imaging elements is substantially equal to the arrangement pitch of the light receiving windows in each semiconductor imaging element arranged in a direction perpendicular thereto.
- Structure More preferably, a structure is provided in which an annular charge multiplying transfer unit adjacent to the photoelectric conversion region is provided.
- a semiconductor wafer processing step for manufacturing a semiconductor element includes a step of exposing the semiconductor element from the semiconductor substrate surface to the back surface, which is a part of the side surface portion of the semiconductor element on the plane view.
- the semiconductor wafer is cut into pieces by dicing and leaving the exposed portion.
- an insulating film is formed on the side surface of the semiconductor element formed on the semiconductor wafer, and the semiconductor element is separated into individual pieces in the etching process.
- a part of the impurity region is subjected to trench etching, and a silicon oxide film is formed on the inner wall of the trench portion.
- the surface of the buried silicon oxide film is flattened, the back surface of the semiconductor wafer is thinned by grinding, and then a part of the buried silicon oxide film is etched to expose the side surface of the semiconductor element.
- the back surface of the semiconductor wafer is thinned by grinding, and then the high concentration impurity region is removed by reactive ion etching.
- an insulating deposited film for protecting the side wall is formed on the side surface of the semiconductor element.
- the side surface portion of the laminated semiconductor element has a curved shape, it can flexibly cope with the use environment or mounting conditions of the semiconductor element, so that the apparatus can be reduced in size and weight.
- the surface shape of the side surface of the semiconductor substrate is convex, for example, it becomes easy to incorporate a semiconductor element into a small-sized imaging device.
- it is concave for example, it becomes easy to dispose the semiconductor image sensor so as to surround the subject as in a dental or head imaging device.
- a hollow part that penetrates from the upper part to the lower part is provided inside the laminated semiconductor element, and a sidewall metal layer is formed on the sidewall, preferably a structure in which a part of the metal layer formed between the semiconductor elements is in contact with each other. Therefore, it becomes easy to efficiently dissipate the heat generated in the semiconductor element to the outside. As a result, it becomes easy to insert a CPU that easily generates heat and an output buffer circuit having a large driving capability between semiconductor elements, and a heat sink and a cooling fan for cooling can be reduced in size or unnecessary.
- the side surface of the semiconductor substrate covered with the insulating material is a high-concentration impurity region, it is possible to reduce image deterioration such as noise and pixel defects caused by interface states and lattice defects.
- the array pitch of the light receiving windows is equal to or larger than the thickness of the image sensor, the pixel array pitch is isotropically and regularly aligned in both the vertical and horizontal directions even when multiple image sensors are stacked.
- a high-resolution image sensor can be realized. Since the annular charge multiplying transfer unit is provided adjacent to the photoelectric conversion region, a high-sensitivity imaging device capable of imaging a weak incident signal is realized.
- a step of exposing a part of the side part of the semiconductor element and covering it with an insulator is provided, so that the semiconductor element can be easily manufactured. it can.
- the semiconductor element can be singulated while leaving the exposed portion on the semiconductor wafer.
- an insulating film is formed on a side surface portion of a semiconductor element formed on a semiconductor wafer, and the semiconductor element manufacturing method includes a step of separating the semiconductor element in an etching process. The trouble in the peripheral part or side part resulting from the semiconductor element can be solved.
- a trench portion is formed on a side surface of a semiconductor element on a semiconductor wafer, a silicon oxide film is formed on the inner wall thereof, and the trench portion is filled with a silicon oxide film by a CVD method, and then a part of the buried silicon oxide film is formed. Since the step of exposing the side surface of the semiconductor element by etching is provided, the side surface of the semiconductor element with high processing accuracy covered with the insulator can be obtained. According to the present invention, after forming a high concentration impurity region on the side surface of the semiconductor element on the semiconductor wafer, the semiconductor wafer back surface is thinned by grinding, and then the high concentration impurity region is removed by reactive ion etching.
- the silicon wafer can be easily etched at a high speed and applied to the side surface of the semiconductor element. It becomes easy to form an insulator. According to the present invention, there is an effect that damage to the cut surface can be reduced and a highly accurate curved cut surface shape can be easily obtained as compared with the conventional singulation method using blade dicing or laser saw.
- FIG. 3A is a detailed view of a part 102a of FIG. 1C
- a cross-sectional view and an equivalent circuit diagram (b) as seen from a cross-section of the B-B ′ portion shown in FIG. 4A is a side view of the laminated semiconductor element 200a as viewed from the XZ plane and the YZ plane
- FIG. 6B is a side view of the laminated semiconductor element 200b as viewed from the YZ plane.
- FIG. 3A is a perspective view of the laminated semiconductor element 300
- FIG. 2B is a planar circuit block diagram of the semiconductor element 302 constituting the laminated semiconductor element 300
- FIG. 2C is a planar circuit block diagram of the semiconductor element 303.
- FIG. 6C is a plan block diagram (d) of a semiconductor element 403 constituting the laminated semiconductor element 400a.
- FIG. 7C is an enlarged view (d) of a portion 502a surrounded by a broken line in FIG. 6C, and a potential profile (e) in FIG. 6D.
- FIG. 10 is a plan block diagram (d) of a semiconductor element 803 constituting the laminated semiconductor element 800.
- FIG. 2A is an XY plan view of a semiconductor wafer W1 in which semiconductor elements 302 and 402 are formed
- FIG. 2B is an XY plan view of a semiconductor wafer W2 in which a semiconductor element 602 is formed. It is a manufacturing process flowchart for demonstrating an example of the manufacturing method of a semiconductor element.
- FIG. 1A A perspective view of the laminated semiconductor element 100 is shown in FIG.
- the stacked semiconductor element 100 is formed by stacking electrical connection means in the thickness direction of a semiconductor substrate using the semiconductor elements 101, 102, and 103.
- the thickness direction of the semiconductor substrate is defined as the Z axis.
- the semiconductor elements 101, 102, and 103 shown in FIG. 1A have the same shape (quadrangle) in plan view on the XY plane view.
- the side surface of the laminated semiconductor element 100 that is visible in front of this drawing, that is, the side surface portion of each of the semiconductor elements 101, 102, and 103 on the X-Z plane is a silicon oxide film. Etc. are covered with an insulator 3.
- the semiconductor element 102 sandwiched between the semiconductor elements 101 and 103 is, for example, a semiconductor imaging element having a plurality of light receiving windows 6 on the side surface portion.
- the light receiving window 6 has the same concept as pixels and pixels that are conventionally used, and indicates the position of the end portion of the photoelectric conversion region described later.
- the semiconductor element 101 includes, for example, various control circuits for controlling the semiconductor imaging element 102, a digital signal processing circuit, a nonvolatile memory, and the like.
- the semiconductor element 103 includes, for example, a data buffer memory, a digital signal processing circuit, an external communication interface circuit, and the like.
- FIG. 1B shows a cross-sectional view of the YZ plane of the laminated semiconductor element 100 in the Z-axis direction of the broken line AA ′ portion in FIG.
- the side surfaces of the semiconductor elements 101, 102, and 103 in the XZ plane are covered with the insulator 3 such as a silicon oxide film. Therefore, even if this part is exposed to the outside during use, an effect of preventing the reliability of the element from being lowered can be expected.
- the other three side surfaces of each of the semiconductor elements 101, 102, and 103 are surrounded by the side surface 2 where the semiconductor substrate is exposed.
- a microbump 67 and a micropad are formed as electrical connection means, and between the semiconductor elements 101 and 102 and between 102 and 103. It enables electrical connection.
- so-called through silicon vias (TSV) 10 are formed in the semiconductor elements 102 and 103 to facilitate electrical connection between the front and back surfaces of the semiconductor elements 101 and 102.
- TSV through silicon vias
- a laminated semiconductor element 100 is integrally formed between the semiconductor elements 101 and 102 and between 102 and 103 with an insulating adhesive layer 71 interposed therebetween.
- an input / output pad 69 that enables electrical connection with the outside is formed.
- FIG. 1 A circuit block diagram in the XY plane of the semiconductor image sensor 102 is shown in FIG.
- One side of the semiconductor image sensor 102 is covered with an insulator 3 such as a silicon oxide film.
- the other three side surfaces are surrounded by the side surface 2 where the semiconductor substrate is exposed.
- a photoelectric conversion region 7, for example, a pn junction photodiode is formed in a semiconductor substrate below an insulator 3 such as a silicon oxide film.
- Incident light 1 such as infrared light, visible light, or X-ray enters from the Y-axis direction and is converted into an electrical signal in the photoelectric conversion region 7.
- the extension distance of the photoelectric conversion region 7 can be easily extended along the incident direction of the incident light 1 from, for example, about 10 micrometers to about 5 millimeters, and is particularly effective for detecting infrared light and X-rays. is there.
- the converted electrical signal is sent to the signal processing circuit 11 and the like through the signal readout scanning circuit 9.
- Other circuit blocks, for example, circuit blocks 13, 15, and 17 are a drive timing generation circuit, an interface circuit, and an input / output buffer circuit, respectively.
- a plurality of TSVs 10 are arranged on the periphery of the semiconductor imaging device 102 along the three side surfaces where the silicon substrate is exposed.
- the photoelectric conversion region 7 is disposed in the vicinity of the side wall of the semiconductor substrate constituting the semiconductor image sensor 102. be able to.
- the reliability of the semiconductor image pickup element 102 decreases as the design value deviates from the design specification as in the conventional semiconductor element. There is no risk.
- the structure of the region 102a surrounded by the broken line will be described in detail below.
- FIG. 2A is an enlarged view of a part (102a) of FIG. 1C, and its structure will be described by taking the case of a CCD type image pickup device as an example.
- FIG. 2B is a cross-sectional structure of the B-B ′ portion in the optical path direction of the incident light 1 in FIG. 2A and a partial equivalent circuit diagram.
- the photoelectric conversion region 7 is also a charge transfer path. For example, charge transfer is performed by a transfer electrode group 25 driven by four phases. In FIG. 2A, for convenience of explanation, a part of the transfer electrode group 25 is omitted and the photoelectric conversion region 7 is visible.
- the transferred signal charge is sent to the signal readout scanning circuit 9.
- the structure of the signal readout scanning circuit 9 will be described with reference to FIG.
- the transferred signal charge is read by a signal charge detection circuit 19 in the signal readout scanning circuit 9, for example, a floating diffusion amplifier (FDA), and converted into a digital signal by an AD conversion circuit 21.
- the digital data is sequentially read out by the scanning circuit 23.
- the drive signals for these circuits are supplied by the wiring group 27.
- a photoelectric conversion region 7 in which an n-type impurity is introduced is formed in a p-type semiconductor substrate 29 so as to extend along the traveling direction of the incident light 1.
- the photoelectric conversion region 7 is electrically isolated from the peripheral circuit block by an element isolation region, for example, a high concentration p-type impurity region (not shown).
- the p-type and n-type semiconductor regions constitute a photodiode and perform photoelectric conversion.
- the exposure is started in a state where the photodiode is completely depleted by the drive pulse applied to the transfer electrode group.
- the photoelectric conversion region 7 extends in parallel to the semiconductor substrate surface, and the transfer electrode group 25 is laid along the extending direction, so that the photoelectric conversion region 7 is completely depleted.
- the depletion voltage can be set low. Therefore, the drive voltage of the image sensor can be made equal to that of a conventional two-dimensional CCD image sensor.
- the transfer electrode group 25 since the incident light passes through the transfer electrode group and does not enter the photoelectric conversion region, the transfer electrode group 25 does not attenuate the incident light. Furthermore, since the charge readout can be performed while the position information of the charge packet formed along the transfer path is maintained as it is, it is suitable for energy spectroscopy analysis of incident light.
- the charges transferred by the transfer electrode group 25 are transferred to the floating diffusion portion 41 by the output gate terminal 35 and read by the signal charge detection circuit 19. Terminals 37 and 39 are a reset terminal and a reset drain, respectively. Thus, incident light attenuates while traveling through the semiconductor substrate.
- the extension distance of the photoelectric conversion region 7 is several hundred micrometers to several millimeters and the incident X-ray energy is 50 Kev or less
- photoelectric conversion can be efficiently performed by the silicon photodiode.
- X-rays and gamma ( ⁇ ) rays of 50 Kev to 5 Mev Compton scattering becomes dominant, and part of the energy of X-rays and ⁇ -rays is converted to electron energy, and further attenuated X-rays and ⁇ -rays. Interacts with silicon and affects conversion efficiency.
- a signal readout scanning circuit 9 or the like for reading out the photoelectric charge generated in the photoelectric conversion region is formed on the semiconductor substrate opposite to the light receiving window side with the photoelectric conversion region interposed therebetween.
- the side edge of the semiconductor substrate is exposed or formed by a wafer dicing process in which the semiconductor wafer is cleaved into individual semiconductor elements. For this reason, for example, a single crystal silicon portion is exposed at the side end portion of the semiconductor substrate, and a lot of chips and scratches are generated due to dicing.
- a normal semiconductor element has bonding pads, process test patterns, etc. arranged around it, and the actual circuit part is inside the element at a distance of 100 micrometers or more from the dicing part, and is shielded from the outside air by the package. Since the risk of contamination and other element deterioration is extremely low, and it is not premised that the semiconductor side end portion is, for example, a light receiving surface, no problem has occurred.
- the semiconductor substrate side end is used as the light receiving surface as in this embodiment, the above assumption is not applied. That is, there is a photoelectric conversion region from the vicinity of the dicing portion, the light receiving surface usually has to be exposed toward the subject, and it is necessary to introduce incident light into the photoelectric conversion region 7 while suppressing attenuation. Because. Therefore, in this embodiment, the semiconductor substrate side end on the incident light side, that is, the light receiving surface is covered with an insulating film such as a silicon oxide film (SiO 2), and a high-concentration p-type impurity region 43 is provided immediately below the insulating film. did.
- an insulating film such as a silicon oxide film (SiO 2)
- the insulating film 47 such as a silicon oxide film (SiO 2) and the high-concentration p-type impurity region 33 on the bottom surface of the semiconductor substrate, the influence of the interface state on the back surface side of the semiconductor substrate can be minimized. it can.
- This structure makes it possible to prevent image deterioration such as noise and pixel defects caused by interface states and lattice defects, etc., and also protects semiconductor elements from contamination caused by metals or chemical substances. Lifetime deterioration can be prevented.
- a light shielding film 49 is laminated on the back surface of the semiconductor substrate. As the light shielding film, an aluminum thin film is generally used.
- the influence of incident light entering from other than the light receiving window, particularly X-rays, is reduced. be able to.
- the heat dissipation effect can also be expected to suppress the temperature rise of the semiconductor element itself, thereby reducing the dark current of the semiconductor element and reducing the signal-to-noise ( S / N) ratio can be improved.
- the laminated semiconductor element 100 is an example in which three layers of semiconductor elements are laminated, but is not limited thereto. Four or more layers of laminated semiconductor elements may be used. Further, by stacking two or more semiconductor image pickup devices, two-dimensional incident light detection in the XZ plane can be performed.
- FIG. 3A is a side view seen from the XZ plane and a plan view seen from the YZ plane of the laminated semiconductor element 200a in which three layers of the same semiconductor imaging element 201 are laminated.
- a large number of light receiving windows 6 are arranged in an array. What should be noted here is the horizontal arrangement pitch (Dh) and the vertical arrangement pitch (Dv) of the light receiving windows 6.
- the arrangement pitch (Dh) in the horizontal direction can be accurately determined at the photomask design stage of the semiconductor image sensor 201.
- the vertical arrangement pitch (Dv) depends on the thickness (Dt) of the semiconductor imaging element 201 and the thickness of the adhesive layer 71 between the semiconductor imaging elements. That is, as shown in the cross-sectional structure of the YZ plane described on the right side of the figure, the individual semiconductor imaging elements 201 are electrically connected to each other through the silicon through electrode (TSV) 10 and the micro bumps 67.
- TSV silicon through electrode
- the input / output micropad 69 enables connection to the outside of the laminated semiconductor element 200a.
- the horizontal arrangement pitch (Dh) can be determined after estimating the vertical arrangement pitch (Dv) in the design stage.
- the horizontal arrangement pitch (Dh) is set larger than the thickness (Dt) of the individual semiconductor image sensor 201. This is to cope with an increase in the vertical arrangement pitch (Dv) caused by the adhesive layer 71 and the like when a plurality of semiconductor imaging elements 201 are stacked.
- Dv vertical arrangement pitch
- Dv isotropic
- the laminated semiconductor element 200b has, for example, a structure in which a plurality of semiconductor imaging elements 201a, 201b, and 201c manufactured from a silicon semiconductor substrate are laminated.
- a scintillator 73 is stacked on the light receiving surface of the semiconductor imaging element 201a.
- the scintillator material is not limited to an inorganic material such as CsI needle crystal, but may be an organic material-based scintillator such as anthracene or stilbene.
- transmission X-rays and the like that have not contributed to light emission in the scintillator layer are photoelectrically converted in the semiconductor substrate, so that the sensitivity of the image sensor can be increased. Further, spectral sensitivity or wavelength resolution can be further improved by detecting a light emission peak with respect to incident X-rays having a specific wavelength.
- the semiconductor imaging device 201b is used for detection of visible light or near infrared light, for example.
- a color filter 75 is laminated on the light receiving surface of the semiconductor image sensor 201c. Since color light can selectively transmit or block incident light in a specific wavelength range, wavelength resolution is improved.
- a deterioration in image quality can be prevented by stacking a light shielding film that can attenuate or block incident light that may impair image quality.
- a hybrid spectroscopic analysis diagnostic apparatus having a plurality of spectroscopic analysis functions can be realized.
- FIG. 4A A perspective view of the laminated semiconductor element 300 is shown in FIG.
- the stacked semiconductor element 300 is formed by stacking electrical connection means in the thickness direction of a semiconductor substrate using the semiconductor elements 301, 302, and 303.
- the semiconductor elements 301, 302, and 303 shown in FIG. 4A have the same planar shape (one side is convex) on the XY plane view.
- the side surface of the laminated semiconductor element 300 that is visible in front of this drawing, that is, the side surface portion of each of the semiconductor elements 301, 302, and 303 is covered with an insulator 3 such as a silicon oxide film. Has been.
- the semiconductor element 302 sandwiched between the semiconductor elements 301 and 303 is, for example, a semiconductor imaging element having a plurality of light receiving windows 6 on the convex side surface portion.
- the semiconductor element 301 includes, for example, various control circuits for controlling the semiconductor imaging element 302, a digital signal processing circuit, a nonvolatile memory, and the like.
- the semiconductor element 303 includes, for example, a data buffer memory, a digital signal processing circuit, an external communication interface circuit, and the like.
- FIG. 4B is an XY plan view of the semiconductor image sensor 302.
- the peripheral circuit blocks 9, 11, 13, 15, 17, etc. are the same as described in the first embodiment. As shown in the drawing, the surface shape of the light receiving surface of the side surface portion of the semiconductor substrate is convex.
- the remaining three sides are composed of side surfaces 2 from which the semiconductor substrate is exposed, as in the first embodiment.
- Other configurations and advantageous features are the same as in the first embodiment. Since a part of the side surface portion of the laminated semiconductor element 300 in the present embodiment is curved in a convex shape, for example, it is pressed against the human body, inserted into the human body, or used in close contact with the human body.
- This is suitable for a probe type imaging device to be used.
- a small-sized imaging device such as a probe type imaging device or an endoscope for insertion into a patient's body or close contact with a human body.
- the semiconductor element 302 shown in FIG. 4B has an XY plane shape that is not rectangular, and one side wall of the semiconductor element 302 has a convexly curved shape on the XY plane view, and the side wall is formed of a silicon oxide film. It has a curved surface covered with an insulator 3 such as. On the other hand, the remaining three sides are composed of a plane 2 from which the semiconductor substrate is exposed, as in the case of FIG.
- the semiconductor element 303 shown in FIG. 4C has a shape in which the XY plane shape is not rectangular, one side of the side wall is a convexly curved shape on the XY plane view, and the side wall is a silicon oxide film. It has a curved surface covered with an insulator 3 such as.
- integrated circuit blocks 4-1, 4-2, 4-3, and 4-4 are formed. These are, for example, the aforementioned data buffer memory, digital signal processing circuit, external communication interface circuit, or power supply circuit.
- the outer shape of the semiconductor element 303 is partially curved in the same manner as the semiconductor elements 301 and 302, there are restrictions on the space for mounting the semiconductor element, or the outer shape of other semiconductor elements to be stacked. There is a special effect that it becomes easy to match.
- FIG. 5B is an XY plan view of a stacked semiconductor module 400b in which a plurality of stacked semiconductor elements 400a are arranged on the XY plane. With this configuration, for example, it can be used for imaging a fan beam-shaped incident X-ray such as a CT scanner. 5 (c) and 5 (d) and FIGS.
- the photoelectric conversion region 7 in FIG. 5C is characterized in that the photoelectric conversion region 7 is also formed radially to correspond to the incident light 1 that is incident radially. .
- a part of the side surface of the semiconductor element 403 is curved in a concave shape, and the circuit block 4-1 is also formed along the shape.
- the present structure can solve the problem.
- the present structure can solve the problem.
- FIG. 6A A perspective view of the laminated semiconductor element 500 is shown in FIG.
- the stacked semiconductor element 500 is formed by stacking electrical connection means in the thickness direction of a semiconductor substrate using the semiconductor elements 501, 502, and 503.
- the semiconductor elements 501, 502, and 503 shown in FIG. 6A have the same planar shape (circular shape) on the XY plane view.
- the circular side surfaces of the semiconductor elements 501, 502, and 503 are covered with an insulator 3 such as a silicon oxide film.
- the semiconductor element 502 sandwiched between the semiconductor elements 501 and 503 is, for example, a semiconductor imaging element having a plurality of light receiving windows 6 on the side surface portion.
- the semiconductor element 501 includes, for example, various control circuits for controlling the semiconductor imaging element 502, a digital signal processing circuit, a nonvolatile memory, and the like.
- the semiconductor element 503 includes, for example, a data buffer memory, a digital signal processing circuit, an external communication interface circuit, and the like.
- FIG. 6B shows a cross-sectional view of the laminated semiconductor element 500 in the Z-axis direction of the broken line CC ′ portion in FIG. As described above, the outer peripheral surfaces of the semiconductor elements 501, 502, and 503 are all covered with the insulator 3 such as a silicon oxide film.
- a micro bump 67 and a micropad (not shown) are formed as electrical connection means, and between the semiconductor elements 501 and 502 and between 502 and 503. It enables electrical connection.
- TSV10 is formed in the semiconductor elements 502 and 503 to facilitate electrical connection between the front surface and the back surface of the semiconductor elements 502 and 503.
- a laminated semiconductor element 500 is integrally formed between the semiconductor elements 501 and 502 and between 502 and 503 with an insulating adhesive layer 71 interposed therebetween.
- FIG. 1 A circuit block diagram of the semiconductor element 502 in the XY plane is shown in FIG.
- the outer peripheral side surface of the semiconductor element 502 is covered with an insulator 3 such as a silicon oxide film.
- Photoelectric conversion regions 7 are radially formed on the circumference of the semiconductor substrate below the insulator 3 such as a silicon oxide film. Even if incident light 1 such as infrared light, visible light, or X-ray is incident from the 360 ° direction, it is converted into an electrical signal in the photoelectric conversion region 7.
- the extending distance of the photoelectric conversion region 7 can be set, for example, from about 10 micrometers to about 5 millimeters, which is effective for detecting infrared light and X-rays.
- the converted electrical signal is sent to the signal processing circuit 11 and the like through the signal readout scanning circuit 9.
- Other circuit blocks, for example, circuit blocks 13, 15, and 17 are a drive timing generation circuit, an interface circuit, and an input / output buffer circuit, respectively.
- a plurality of TSVs 10 are arranged in the central portion of the silicon substrate.
- the photoelectric conversion region 7 is disposed close to the side wall of the semiconductor substrate constituting the semiconductor element 502. can do.
- the signal readout scanning circuit 9 has a charge transfer path having a charge multiplication function.
- FIG. 6D shows a structure for explaining a part 502a of the scanning circuit 9 surrounded by a broken line in FIG. Four-phase transfer pulses ⁇ 1, ⁇ 2, ⁇ 3, and ⁇ 4 are applied to the charge transfer path having the charge multiplying function, and the signal charges in the semiconductor substrate immediately below the charge transfer electrodes 8 arranged in a strip shape are moved in the direction of the broken line arrow Charge multiplication by impact ionization is performed.
- FIG. 6E is a potential diagram for explaining the potential change in the semiconductor substrate immediately below the charge transfer electrode (for example, JP-A-7-176721).
- the charge transfer path having the charge multiplying function can be formed into a ring shape. Therefore, the sensitivity is increased by changing the charge transfer stage or the transfer rotation speed in the ring transfer path, or an arbitrary sensitivity setting is made.
- the charge transfer path is arranged in an annular shape, so that the shape of the charge transfer path and the transfer electrode can be made substantially the same. As a result, it is possible to suppress variations in transfer efficiency or to improve sensitivity uniformly.
- FIG. 7A A perspective view of the laminated semiconductor element 600 is shown in FIG.
- the stacked semiconductor element 600 is formed by stacking electrical connection means in the thickness direction of a semiconductor substrate using the semiconductor elements 601, 602, and 603.
- the semiconductor elements 601, 602, and 603 shown in FIG. 7A all have the same outer shape (square) on the XY plane view.
- the outer peripheral side surfaces of the semiconductor elements 601, 602, and 603 are surrounded by the surface 2 from which the silicon substrate is exposed.
- a cylindrical hollow portion 20 is formed inside the laminated semiconductor element 600 in a plan view.
- the semiconductor element 602 sandwiched between the semiconductor elements 601 and 603 is, for example, a semiconductor imaging element having a plurality of light receiving windows 6 (not shown) on the side surface of the hollow portion 20.
- the semiconductor element 601 includes, for example, various control circuits for controlling the semiconductor imaging element 602, a digital signal processing circuit, a nonvolatile memory, and the like.
- the semiconductor element 603 includes, for example, a data buffer memory, a digital signal processing circuit, an external communication interface circuit, and the like.
- FIG. 7B shows a cross-sectional view of the laminated semiconductor element 600 in the Z-axis direction of broken line DD ′ in FIG.
- micro bumps 67 and micro pads are formed as electrical connection means, and between the semiconductor elements 601 and 602 and between 602 and 603. It enables electrical connection.
- a TSV 10 is formed in the semiconductor elements 602 and 603 to facilitate electrical connection between the front and back surfaces of the semiconductor elements 602 and 603.
- a laminated semiconductor element 600 is integrally formed between the semiconductor elements 601 and 602 and between the semiconductor elements 602 and 603 with an insulating adhesive layer 71 interposed therebetween.
- an input / output pad 69 On the back surface of the semiconductor element 603, that is, on the bottom of the laminated semiconductor element 600, an input / output pad 69 that enables electrical connection with the outside is formed.
- FIG. 6 A circuit block diagram in the XY plane of the semiconductor element 602 is shown in FIG.
- the side surface of the hollow portion 20 of the laminated semiconductor element 600 is covered with an insulator 3 such as a silicon oxide film.
- Photoelectric conversion regions 7 are radially formed in the semiconductor substrate below the insulator 3 such as a silicon oxide film so as to surround the hollow portion 20. Even if incident light 1 such as infrared light, visible light, or X-rays is incident radially, the photoelectric conversion region 7 efficiently converts it into an electrical signal.
- the extending distance of the photoelectric conversion region 7 can be set, for example, from about 10 micrometers to about 5 millimeters, which is effective for detecting infrared light and X-rays.
- the converted electrical signal is sent to the signal processing circuit 11 and the like through the signal readout scanning circuit 9.
- Other circuit blocks for example, circuit blocks 13, 15, and 17 are a drive timing generation circuit, an interface circuit, and an input / output buffer circuit, respectively.
- a plurality of TSVs 10 are arranged on the outer peripheral portion of the silicon substrate. Therefore, since the TSV 10 is not disposed in the vicinity of the hollow portion 20 of the semiconductor element 602 near the hollow portion 20 covered with the insulator, the photoelectric conversion region 7 can be disposed close to the side wall of the hollow portion.
- FIG. 8A A perspective view of the laminated semiconductor element 700 is shown in FIG.
- the laminated semiconductor element 700 is obtained by laminating semiconductor elements 701, 702, and 703 with an electrical connection means interposed in the thickness direction of a semiconductor substrate to be used.
- the semiconductor elements 701, 702, and 703 shown in FIG. 8A all have the same outer shape (square) on the XY plane view.
- the outer peripheral side surfaces of the semiconductor elements 701, 702, and 703 are surrounded by the surface 2 from which the silicon substrate is exposed.
- a hollow portion 20 having a square shape with rounded corners is formed in the laminated semiconductor element 700 in plan view. As shown in FIG.
- the semiconductor element 701 includes, for example, various control circuits for controlling the semiconductor element 702, a digital signal processing circuit, a nonvolatile memory, and other circuit blocks (4-1, 4-2, 4). -3, 4-4, 4-5, and 4-6).
- the semiconductor element 702 includes, for example, a data buffer memory, a digital signal processing circuit, a central processing element (CPU), and the like.
- the semiconductor element 703 includes, for example, a nonvolatile memory, an external interface circuit, a power supply control circuit, and the like.
- FIG. 8B shows a cross-sectional view of the stacked semiconductor element 700 in the Z-axis direction of the broken line EE ′ portion in FIG. A description will be given of only the portions different from the above embodiment.
- the metal layer 18 is formed between the top and bottom surfaces of the laminated semiconductor element 700, between the semiconductor elements 701 and 702, and between 702 and 703, and further, the hollow portion A sidewall metal layer 16 is formed on the sidewall 20.
- the metal layer 18 and the sidewall metal layer 16 are partially in contact with each other. Accordingly, it becomes easy to efficiently dissipate heat generated in the semiconductor elements 701, 702, and 703 to the outside. Conventionally, particularly in the semiconductor element 702 sandwiched between the upper and lower sides, it has been difficult to dissipate heat. For example, there is a limit in inserting a CPU that easily generates heat or an output buffer circuit having a large driving capability between the semiconductor elements. .
- FIG. 8D shows a cross-sectional structure of the semiconductor element 701 taken along the broken line F-F ′ in FIG.
- the semiconductor element 701 uses, for example, a p-type silicon substrate 29.
- the circuit block 4-5 is a CMOS circuit block formed in the N-well 30-1, the P-well 30-2, and the N-well 30-3, and includes a surface insulating film 12, a high-concentration impurity layer 43, and The back surface is surrounded by the high concentration impurity layer 33.
- the TSV 10 is formed in the vicinity of the outer periphery of the semiconductor element 701, and separates the side surface 2 where the silicon substrate is exposed from the circuit block 4-5.
- FIG. 9A A perspective view of the laminated semiconductor element 800 is shown in FIG.
- the stacked semiconductor element 800 has a structure in which semiconductor elements 801, 802, and 803 are stacked with an electrical connection unit interposed in the thickness direction of the semiconductor substrate.
- the semiconductor elements 801, 802, and 803 shown in FIG. 9A have the same planar shape (circular shape) on the XY plane view.
- the circular outer peripheral side surfaces of the semiconductor elements 801, 802, and 803 are covered with an insulator 3 such as a silicon oxide film.
- the semiconductor element 802 sandwiched between the semiconductor elements 801 and 803 is, for example, a semiconductor imaging element having a plurality of light receiving windows 6 on the side surface portion.
- the semiconductor element 801 includes various control circuits for controlling the semiconductor imaging element 802, a digital signal processing circuit, a nonvolatile memory, and the like.
- the semiconductor element 803 includes, for example, a data buffer memory, a digital signal processing circuit, an external communication interface circuit, and the like.
- a hollow portion 20 having a rectangular shape with rounded corners is formed in the laminated semiconductor element 800 in plan view.
- FIG. 8B shows a cross-sectional view of the stacked semiconductor element 800 in the Z-axis direction of the broken line GG ′ portion in FIG.
- the side walls of the hollow portions 20 of the semiconductor elements 801, 802, and 803 are all covered with an insulator 3 such as a silicon oxide film.
- FIG. 8C and FIG. 8D are no planar blocks of the semiconductor element 802 and the semiconductor element 803, respectively. The details are the same as in the other embodiments described above.
- the outer shape of the laminated semiconductor element 800 is a cylindrical shape, when inserted into a tube and used, for example, it becomes extremely easy to insert it into a test tube or a catheter.
- the laminated semiconductor element 900 has a structure in which semiconductor elements 901, 902, 903, and 904 are laminated with an electrical connection unit interposed in the thickness direction of the semiconductor substrate.
- the semiconductor elements 901, 902, 903, and 904 shown in FIG. 10A have the same shape (doughnut shape) on the XY plane view.
- the circular outer peripheral side surfaces of the semiconductor elements 901, 902, 903, and 904 are covered with an insulator 3 such as a silicon oxide film.
- the semiconductor elements 902 and 903 sandwiched between the semiconductor elements 901 and 904 are, for example, semiconductor imaging elements having a plurality of light receiving windows 6 on the side surface portion.
- the semiconductor element 901 includes various control circuits for controlling the semiconductor imaging element 802, a digital signal processing circuit, a nonvolatile memory, and the like.
- the semiconductor element 904 includes, for example, a data buffer memory, a digital signal processing circuit, an external communication interface circuit, and the like.
- the laminated semiconductor element 900 has a ring shape in which a circular hollow portion 20 is formed in a plan view.
- the side walls of the hollow portions 20 of the semiconductor elements 901, 902, 903, and 904 are all covered with an insulator 3 such as a silicon oxide film. Therefore, even if the outer periphery of the laminated semiconductor element 900 and the side wall of the hollow portion 20 are exposed to the outside during use, the reliability of the element can be prevented from being lowered.
- FIG. 10B and FIG. 10C are plan block diagrams of the semiconductor elements 902 and 903 and the semiconductor element 904, respectively. The details are the same as in the other embodiments described above.
- incident light 1 such as X-rays is emitted from the vicinity of the center of the ring, or when detecting X-rays incident from the direction facing each pixel, that is, the light receiving window. It is suitable for.
- the wafer-sized large-sized laminated semiconductor element 900 in which a single semiconductor substrate is laminated it becomes easy to surround the subject. Therefore, for example, a small CT apparatus targeting a part of the body such as the head or a small animal can be easily realized, and further, high speed and low power consumption driving by on-chip signal processing becomes possible.
- FIG. 10D is an enlarged view of a part 902a in FIG. 10B, and its structure will be described by taking a MOS type image pickup device as an example.
- FIG. 10E is an equivalent circuit diagram of the circuit block 51 in FIG.
- the photoelectric conversion area 7 is divided into, for example, three areas (7-1, 7-2, 7-3) as illustrated.
- the signal charges generated in these three regions are read individually or added by the signal charge detection circuit 19, for example, the FDA, through the adjacent MOS type signal transfer circuit 51, and sent to the AD conversion circuit 21.
- the signal charge detection circuit 19 for example, the FDA
- the MOS type signal transfer circuit 51 sends signal charges from the divided photoelectric conversion regions to the input terminals of the signal charge detection circuit 19, that is, floating diffusion portions (57-1, 57-2, 57-3, 59), the signal transfer electrodes (55-1, 55-2, 55-3) are turned on. After reading the signal charge, the floating diffusion unit turns on the reset terminal 63 and is reset to the potential level of the reset drain 61. As shown in FIG. 10D, the MOS signal transfer circuit 51 is disposed below the opening, that is, the light shielding film 53. By using a material containing heavy metal such as tungsten for the light shielding film, an effect of shielding X-rays or the like is expected, and radiation damage to the MOS element or the like can be reduced.
- the subsequent circuit blocks 21 and 23, the wiring group 27, and the like after the signal charge detection circuit 19 are the same as those in FIG. Since the MOS type image pickup device structure is used, the power consumption particularly in the large-sized stacked semiconductor device 900 can be reduced as compared with the case of the CCD type image pickup device structure.
- An important wafer processing step as a manufacturing method for realizing the structure of the semiconductor element or the laminated semiconductor element described above includes a manufacturing process of a semiconductor element or a laminated semiconductor element having a sidewall insulating film, and a part of the sidewall insulating film. Alternatively, it is a process of dividing into individual semiconductor elements or stacked semiconductor elements with all remaining. As shown in FIG. 11A, for example, a semiconductor element 302 having a convex side wall 3 or a semiconductor element 402 having a concave shape coated with an insulating film is patterned (imposed) on the wafer W1.
- the other side wall may be the surface 2 from which the silicon substrate is exposed, it can be separated into pieces by dicing, that is, along the scribe line 22.
- a semiconductor element 60 having a hollow portion inside the semiconductor element and having a sidewall covered with the insulating film 3 is patterned on the wafer W2. Since the other outer peripheral portion may be the surface 2 from which the silicon substrate is exposed, it can be divided into pieces by dicing, that is, along the scribe line 22. In either case, the post-process such as conventional dicing can be followed as it is. Furthermore, as will be described later, the manufacturing method has an advantageous feature that it can be applied to individualization of a laminated semiconductor element in which a plurality of semiconductor elements and the like are laminated.
- FIG. 12 is a main part flowchart of this manufacturing method.
- a circuit element is formed on a wafer.
- a step of forming the sidewall insulating film 3 may be included in this step.
- it is thinned to, for example, about 10 to 100 micrometers by grinding the back surface of the wafer.
- the sidewall insulating film is completely penetrated and removed by plasma etching.
- a plurality of similar thinned wafers are laminated. These thinned wafers and laminated wafers are cut along the scribe line 22 and separated into pieces by a wafer dicing apparatus. Further, the process proceeds to a packaging process as necessary.
- FIG. 13A for example, a semiconductor element 502 whose outer periphery is covered with an insulating film is patterned on the wafer W3.
- FIG. 13B shows, for example, a semiconductor element 902-1, 902-2, 902-3, which has a hollow portion inside the semiconductor element and whose side walls are covered with the insulating film 3 and have different diameters. And 902-4 are patterned on the wafer W4.
- FIG. 14 is a main part flowchart of the present manufacturing method. First, a circuit element is formed on a wafer. As will be described later, a step of forming the sidewall insulating film 3 may be included in this step.
- FIGS. These 8 methods are related to the details of the sidewall insulating film formation and sidewall insulating film etching steps shown in FIGS. It should be noted that only the characteristic features of the present invention, i.e., the side wall of the semiconductor substrate, particularly the portion having the side wall insulating film or the cross-sectional structure in the vicinity of the region to be singulated, are illustrated, and other internal circuits, input / output circuit portions or through electrodes The structure of parts and the like is omitted.
- FIG. 15A shows a cross-sectional structure in the vicinity of the side wall in the initial stage of the manufacturing process, for example, in the p-well formation process.
- divalent boron ions B ++
- B ++ divalent boron ions
- MeV megaelectron volts
- an impurity introduction region in the vicinity of the element isolation region may be formed by this ion implantation.
- high-temperature thermal diffusion drive-in is performed simultaneously with p-well formation after resist removal.
- a part of the silicon substrate in the vicinity of the sidewall is etched into a trench shape. Dry etching is performed using a gas containing (SF6).
- the depth of the trench portion 85 is, for example, Dt described with reference to FIG. 3A and is set smaller than the pixel pitch Dh in the horizontal direction.
- the sidewall of the trench portion 85 is surrounded by a p-type impurity distribution 79b by the boron ion implantation and subsequent thermal diffusion.
- the side wall of the trench portion 85 is oxidized to form a silicon oxide film (SiO 2) 45. Further, the trench portion 85 is filled back with silicon dioxide (SiO 2) 87 by the CVD method.
- the silicon oxide film 87 formed by the CVD method in the vicinity of the sidewall using the photoresist 89 as a mask is anisotropically formed using, for example, a gas containing carbon tetrafluoride (CF 4) and oxygen (O 2). Removed by reactive plasma etching and separated into individual image sensors 801. In the manufacturing method having the dicing process shown in FIG. 12, only the portion having the sidewall insulating film is etched by the anisotropic plasma etching method.
- CF 4 carbon tetrafluoride
- O 2 oxygen
- a silicon oxide film (SiO 2) can be formed in a portion to be the light receiving surface at the end portion on the semiconductor substrate before the silicon wafer cutting step, and a high-concentration impurity region can be formed immediately therebelow. Therefore, even when a method of manufacturing an image sensor having a light receiving surface on the side surface of a semiconductor substrate simultaneously with the cutting of a silicon wafer, image degradation such as noise and pixel defects due to interface states and lattice defects can be reduced. Can do. Further, without using a rotating blade for wafer dicing, a large number of small image pickup devices can be separated with high throughput by patterning and etching. Further, the light receiving surface at the end portion on the semiconductor substrate side can be precisely processed into a curved or other arbitrary shape.
- the surface of the silicon oxide film 45 is planarized by etching or polishing, or silicon oxide After removing the film 45 once, a new silicon oxide film 45 may be formed.
- FIG. 1 Another method for manufacturing a semiconductor element will be described with reference to FIG.
- This manufacturing method relates to the details of the sidewall insulating film formation and sidewall insulating film etching steps shown in FIGS. It should be noted that only the characteristic features of the present invention, i.e., the side wall portion having an insulating film or the cross-sectional structure in the vicinity of the region to be singulated are shown, and other internal circuits, input / output circuit portions, through electrode portions, etc. are omitted. is doing.
- FIG. 16A shows a cross-sectional structure in the vicinity of the side wall in the initial stage of the manufacturing process, for example, in the p-well formation process.
- divalent boron ions B ++
- B ++ divalent boron ions
- MeV megaelectron volts
- an impurity introduction region in the vicinity of the element isolation region may be formed by this ion implantation.
- the reason why the carbon fluoride (C4F8) and the sulfur hexafluoride (SF6) are alternately used is for the deposition of the sidewall protective film. Thereby, a high aspect ratio is obtained. Note that since the side wall may be uneven, in such a case, the surface can be smoothed by heat treatment in reduced-pressure hydrogen (for example, 10 Torr, 1100 ° C.). Alternatively, the protective film deposition 97 on the side wall of the silicon substrate may be removed by etching or the like to form a new silicon oxide film 45 (not shown).
- this manufacturing method it is possible to form a high concentration impurity region in a portion to be a light receiving surface at the end portion on the semiconductor substrate before the silicon wafer cutting step, and further form a silicon oxide film (SiO 2) on the upper portion.
- image degradation such as noise and pixel defects caused by interface states and lattice defects can be reduced.
- individual image pickup devices can be separated into pieces by patterning and etching, the light receiving surface at the semiconductor substrate side end can be easily processed into a curved or other arbitrary shape at high speed and with precision.
- This manufacturing method is particularly suitable for manufacturing a large image sensor for X-rays or the like when the pixel size or the pixel pitch (Dh) is large, that is, when the thickness (Dv2) of the silicon substrate is large.
- a small-sized semiconductor imaging device or a wafer-sized large-sized semiconductor device that can cope with various object shapes is realized.
- a hybrid imaging device in which different types of semiconductor elements and various sensors that can meet various needs can be stacked.
- it can be widely used in various fields such as wearable devices other than the imaging field, portable communication terminals, robots, small airplanes that require weight reduction, and in-vehicle applications.
- signal charge detection circuit 20 ... Hollow part, 21 ... AD conversion circuit, 22 ... scribe line, 23 ... scanning circuit, 25 ⁇ 4-phase charge transfer electrode, 27... Wiring group, 29... Semiconductor substrate, 30-1... N-well, 30-2. 31 ... Element isolation region, 33 ... High concentration impurity layer on the back surface, 35 ... Output gate terminal, 37 ... Reset terminal, 39 ... Reset drain, 41 ... Floating diffusion, 43. ..High-concentration impurity layer directly under the side wall portion covered with the insulating film, 45... Silicon oxide film layer formed on the side wall, 47... Backside silicon oxide film layer, 49. ... MOS type signal transfer circuit, 53 ...
- Light shielding film on light receiving surface 55-1, 55-2, 55-3 ...
- Signal transfer electrode 57-1, 57-2, 57-3, 59 ...
- Floating diffusion 61 ... Reset Rain, 63 ... Reset terminal, 67 ... Micro bump, 69 ... Input / output pad, 71 ... Adhesive layer, 73 ... Scintillator, 75 ... Color filter, 77 ...
- resist mask 91a impurity distribution immediately after ion implantation 91b ... impurity distribution after thermal diffusion 93 ... resist mask 95 ... silicon oxide film 97 ... Side wall protective deposition film, 101, 102, 103, 201, 201a, 201b, 201c, 301, 302, 303, 401, 402, 403, 501, 5 02, 503, 601, 602, 603, 701, 702, 703, 801, 802, 803, 901, 902, 903, 904...
- Semiconductor element 100, 200a, 200b, 300, 400a, 400b, 500, 600 , 700, 800, 900... Stacked semiconductor elements, W1, W2, W3, W4...
- Semiconductor wafers used in the manufacturing process of semiconductor elements according to the present invention 902-1, 902-2, 902-3 902-4: Semiconductor elements formed concentrically on the semiconductor wafer W4, 1001, 1002 ... Semiconductor elements singulated in the manufacturing process of the semiconductor element according to the present invention.
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Abstract
Description
Claims (12)
- シリコン基板面上に集積回路が形成された半導体素子をn枚(nは2以上の整数)該シリコン基板厚み方向に電気的接続手段を介し積層した積層半導体素子であって、該シリコン基板厚み方向における該積層半導体素子の側面部が絶縁膜で被覆されていることを特徴とする半導体モジュール。
- 前記絶縁膜で被覆された側面部の形状が、平面視座上湾曲し、凸状、凹状、或いは円形であることを特徴とする請求項1に記載の積層半導体素子。
- シリコン基板面上に集積回路が形成された半導体素子をn枚(nは2以上の整数)該シリコン基板厚み方向に電気的接続手段を介し積層した構造からなる積層半導体素子であって、前記第1層から第n層までの半導体素子を前記シリコン基板厚み方向に貫通する中空部を有していることを特徴とする積層半導体素子。
- 前記中空部の壁面が絶縁膜で被覆されていることを特徴とする請求項3に記載の積層半導体素子。
- 前記積層されたn枚の半導体素子間、及び前記中空部の側壁に金属層を有する請求項1乃至請求項4のいずれか一項に記載の積層半導体素子。
- 前記積層半導体素子を構成する1又は2以上の半導体素子の側面部に受光窓を有し、該受光窓から前記集積回路が形成されたシリコン基板面に平行な方向かつ該シリコン基板面に対し平面視座上、放射状に形成された光電変換領域を有することを特徴とする請求項1乃至請求項6のいずれか一項に記載の積層半導体素子。
- 前記半導体素子の側面部に並ぶ受光窓の配列ピッチが前記半導体素子の半導体基板の厚さより大きいことを特徴とする請求項9に記載の積層半導体素子。
- 半導体素子を製造する半導体ウエーハ加工処理工程において、半導体ウエーハ上に形成された個々の半導体素子の外周部の一部又は全てをZ軸方向に完全に露出させる工程を有することを特徴とする半導体素子の製造方法。
- 前記中空部の側面、及び前記半導体素子側面部を露出させる工程の後に、前記半導体ウエーハをダイシングによりスクライブラインに沿って切断し、前記露出部分を残した状態で前記半導体素子を個片化することを特徴とする半導体素子の製造方法。
- 前記半導体ウエーハ上に形成される半導体素子のZ軸方向の側面部に絶縁膜を形成し、該絶縁膜のエッチング工程により該半導体素子を個片化する工程を有することを特徴とする半導体素子の製造方法。
- 前記半導体ウエーハ上に形成される半導体素子の側面部に不純物元素をイオン注入後、該不純物領域の一部をトレンチエッチングし、該トレンチ部の内壁にシリコン酸化膜を形成し、該トレンチ部をCVD法によるシリコン酸化膜により埋め込み後、該埋め込みシリコン酸化膜表面を平坦化し、さらに前記半導体ウエーハ裏面を研削により薄化した後、前記埋め込みシリコン酸化膜の一部をエッチングすることにより前記半導体素子側面部を露出させることを特徴とする請求項8乃至請求項10のいずれか一項に記載の半導体素子の製造方法。
- 前記半導体ウエーハ上に形成される半導体素子の側面部にイオン注入法による高濃度不純物領域を形成後、前記半導体ウエーハ裏面を研削により薄化し、その後に前記高濃度不純物領域を反応性イオンエッチング法により除去しつつ該半導体素子の側面部に側壁保護のための絶縁性堆積膜を形成することを特徴とする請求項8乃至請求項10のいずれか一項に記載の半導体素子の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/544,118 US10468383B2 (en) | 2015-01-16 | 2016-01-15 | Semiconductor device and manufacturing method thereof |
CN201680004876.0A CN107112315B (zh) | 2015-01-16 | 2016-01-15 | 半导体器件及其制造方法 |
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CN107112315B (zh) | 2019-03-29 |
JP6343070B2 (ja) | 2018-06-13 |
US10468383B2 (en) | 2019-11-05 |
JP2017168868A (ja) | 2017-09-21 |
US20200013758A1 (en) | 2020-01-09 |
US20170373042A1 (en) | 2017-12-28 |
JP6251406B2 (ja) | 2017-12-20 |
CN107112315A (zh) | 2017-08-29 |
US11024606B2 (en) | 2021-06-01 |
JPWO2016114377A1 (ja) | 2017-04-27 |
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