WO2016106923A1 - 一种ltps tft像素单元及其制造方法 - Google Patents

一种ltps tft像素单元及其制造方法 Download PDF

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Publication number
WO2016106923A1
WO2016106923A1 PCT/CN2015/071708 CN2015071708W WO2016106923A1 WO 2016106923 A1 WO2016106923 A1 WO 2016106923A1 CN 2015071708 W CN2015071708 W CN 2015071708W WO 2016106923 A1 WO2016106923 A1 WO 2016106923A1
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Prior art keywords
layer
insulating layer
semiconductor pattern
forming
pattern layer
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PCT/CN2015/071708
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English (en)
French (fr)
Inventor
杨祖有
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to KR1020177021418A priority Critical patent/KR101963066B1/ko
Priority to GB1708786.7A priority patent/GB2548732B/en
Priority to US14/433,663 priority patent/US9589999B2/en
Priority to RU2017125766A priority patent/RU2670219C1/ru
Priority to JP2017534662A priority patent/JP6542897B2/ja
Publication of WO2016106923A1 publication Critical patent/WO2016106923A1/zh
Anticipated expiration legal-status Critical
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to an LTPS TFT pixel unit and a method of fabricating the same.
  • the transistor unit of the Transistor (low-temperature polysilicon thin film transistor) is formed by first depositing a buffer layer, then forming a semiconductor pattern layer on the buffer layer, and further forming an insulating layer, a gate electrode, etc. on the semiconductor pattern layer. Other components of the TFT pixel unit.
  • the TFT pixel unit is formed on the buffer layer because the semiconductor pattern layer is protruded from the buffer layer, so that the subsequently formed insulating layer forms a stepped bump structure at both ends of the semiconductor pattern layer, thereby forming the insulating layer.
  • the spacing between the gate on the layer and the semiconductor pattern layer is uneven to cause side effects.
  • the signal is unstable during transmission, thus affecting LTPS.
  • the electrical properties of the TFT pixel unit is formed on the buffer layer because the semiconductor pattern layer is protruded from the buffer layer, so that the subsequently formed insulating layer forms a stepped bump structure at both ends of the semiconductor pattern layer, thereby forming the insulating layer.
  • the spacing between the gate on the layer and the semiconductor pattern layer is uneven to cause side effects.
  • the signal is unstable during transmission, thus affecting LTPS.
  • the electrical properties of the TFT pixel unit is formed on the buffer layer because the semiconductor pattern layer is protruded from the buffer layer, so that the subsequently formed insulating layer forms a
  • the technical problem to be solved by the present invention is to provide an LTPS TFT pixel unit and a manufacturing method thereof, which can reduce side effects and improve LTPS.
  • the electrical properties of the TFT pixel unit are to provide an LTPS TFT pixel unit and a manufacturing method thereof, which can reduce side effects and improve LTPS.
  • a method of manufacturing a TFT pixel unit comprising the steps of: providing a substrate and forming a buffer layer on the substrate; forming a semiconductor pattern layer and a first insulating layer on the buffer layer, the semiconductor pattern layer being in the same layer as the first insulating layer And the height of the semiconductor pattern layer is equal to the height of the first insulating layer; wherein the step of forming a buffer layer on the substrate comprises: sequentially forming a silicon nitride layer and a silicon oxide layer on the substrate; forming a semiconductor pattern on the buffer layer And the first insulating layer, the semiconductor pattern layer is disposed in the same layer as the first insulating layer, and the height of the semiconductor pattern layer is equal to the height of the first insulating layer, including: forming an amorphous silicon layer on the buffer layer, and The crystalline silicon layer is subjected to a crystallization operation to form a polysilicon layer
  • the method further comprises: forming an intrinsic region and a heavily doped region on both sides of the intrinsic region on the semiconductor pattern layer through the third photomask process and the first doping process on the semiconductor pattern layer; further in the semiconductor pattern layer A lightly doped region between the intrinsic region and the heavily doped region is formed on the semiconductor pattern layer by a fourth photomask process and a second doping process.
  • the method further includes: forming a second insulating layer on the semiconductor pattern layer and the first insulating layer; forming a gate layer on the second insulating layer, and patterning the gate layer by a fifth mask process to Forming a gate; forming a third insulating layer on the gate; forming LTPS on the third insulating layer a source and a drain of the TFT unit, wherein the source and the drain are electrically connected to the semiconductor pattern layer through the first via holes passing through the second insulating layer and the third insulating layer, respectively; forming a fourth on the source and the drain An insulating layer is formed on the fourth insulating layer, and the pixel electrode is electrically connected to one of the source or the drain through the second via hole passing through the fourth insulating layer.
  • the method further includes: further forming a fifth insulating layer between the fourth insulating layer and the source and the drain; further forming a common electrode between the fifth insulating layer and the fourth insulating layer for forming a liquid crystal with the pixel electrode capacitance.
  • a method of manufacturing a TFT pixel unit comprising the steps of: providing a substrate and forming a buffer layer on the substrate; forming a semiconductor pattern layer and a first insulating layer on the buffer layer, the semiconductor pattern layer being in the same layer as the first insulating layer
  • the height of the semiconductor pattern layer is set to be equal to the height of the first insulating layer.
  • the step of forming a buffer layer on the substrate comprises: sequentially forming a silicon nitride layer and a silicon oxide layer on the substrate.
  • the step of the semiconductor pattern layer being disposed in the same layer as the first insulating layer and the height of the semiconductor pattern layer being equal to the height of the first insulating layer comprises: forming on the buffer layer An amorphous silicon layer, and crystallization operation of the amorphous silicon layer to form a polysilicon layer; patterning the polysilicon layer by a first mask process to form a semiconductor pattern layer; and forming a semiconductor on the semiconductor pattern layer Forming a silicon nitride layer having the same height as the semiconductor pattern layer on the buffer layer of the pattern layer; coating a negative photoresist on the silicon nitride layer at a position not corresponding to the semiconductor pattern layer; and nitriding through a second mask process
  • the silicon layer is patterned; further etching the silicon nitride layer over the semiconductor pattern layer to etch away the silicon nitride layer on the semiconductor pattern layer such that the height of the semiconductor pattern layer is the same
  • the method further comprises: forming an intrinsic region and a heavily doped region on both sides of the intrinsic region on the semiconductor pattern layer through the third photomask process and the first doping process on the semiconductor pattern layer; further in the semiconductor pattern layer A lightly doped region between the intrinsic region and the heavily doped region is formed on the semiconductor pattern layer by a fourth photomask process and a second doping process.
  • the method further includes: forming a second insulating layer on the semiconductor pattern layer and the first insulating layer; forming a gate layer on the second insulating layer, and patterning the gate layer by a fifth mask process to Forming a gate; forming a third insulating layer on the gate; forming LTPS on the third insulating layer a source and a drain of the TFT unit, wherein the source and the drain are electrically connected to the semiconductor pattern layer through the first via holes passing through the second insulating layer and the third insulating layer, respectively; forming a fourth on the source and the drain An insulating layer is formed on the fourth insulating layer, and the pixel electrode is electrically connected to one of the source or the drain through the second via hole passing through the fourth insulating layer.
  • the method further includes: further forming a fifth insulating layer between the fourth insulating layer and the source and the drain; further forming a common electrode between the fifth insulating layer and the fourth insulating layer for forming a liquid crystal with the pixel electrode capacitance.
  • an LTPS TFT pixel unit the LTPS
  • the TFT unit includes: a substrate; a buffer layer disposed on the substrate; a semiconductor pattern layer and a first insulating layer disposed on the buffer layer in the same layer, and the height of the semiconductor pattern layer is equal to the height of the first insulating layer.
  • the buffer layer comprises a silicon nitride layer and a silicon oxide layer which are sequentially disposed on the substrate.
  • the TFT pixel unit further includes: a second insulating layer disposed on the semiconductor pattern layer and the first insulating layer; a gate disposed on the second insulating layer; a third insulating layer disposed on the gate; source and drain electrodes Provided on the third insulating layer, wherein the source and the drain are electrically connected to the semiconductor pattern layer through the first via holes passing through the second insulating layer and the third insulating layer, respectively; the fourth insulating layer is disposed at the source and a drain electrode; a pixel electrode disposed on the fourth insulating layer and electrically connected to one of the source or the drain through the second via hole passing through the fourth insulating layer.
  • the TFT pixel unit further includes: a fifth insulating layer disposed between the fourth insulating layer and the source and the drain; and a common electrode disposed between the fifth insulating layer and the fourth insulating layer for forming a liquid crystal with the pixel electrode capacitance.
  • the invention has the beneficial effects that, different from the prior art, the present invention forms a semiconductor pattern layer and a first insulating layer which are disposed in the same layer and have the same height on the buffer layer, so as to be subsequently formed on the first insulating layer and the semiconductor pattern layer.
  • the second insulating layer is in a flat state, and has no structure such as protrusions, so that the gate layer can be on the flat second insulating layer, ensuring the same distance from the semiconductor pattern layer, thereby avoiding the second insulation.
  • the structure of the bumps of the layer causes side effects caused by uneven spacing between the gate layer and the semiconductor pattern layer, and also improves LTPS.
  • the electrical properties of the TFT pixel unit The electrical properties of the TFT pixel unit.
  • FIG. 1 is a flowchart of a method for manufacturing a TFT pixel unit according to an embodiment of the present invention
  • Figure 2 is a process diagram corresponding to the method shown in Figure 1;
  • FIG. 3 is a schematic structural diagram of a TFT pixel unit according to an embodiment of the present invention.
  • FIG. 1 is an LTPS according to an embodiment of the present invention.
  • a flowchart of a method of manufacturing a TFT pixel unit and FIG. 2 is a process diagram corresponding to the method shown in FIG. 1.
  • the method provided by the embodiment of the present invention includes the following steps:
  • Step S1 A substrate 11 is provided, and a buffer layer 12 is formed on the substrate 11.
  • a silicon nitride layer 121 and a silicon oxide layer 122 are sequentially formed on the substrate 11 as the buffer layer 12.
  • Step S2 A semiconductor pattern layer 13 and a first insulating layer 14 are formed on the buffer layer 12.
  • the semiconductor pattern layer 13 is disposed in the same layer as the first insulating layer 142 and the height of the semiconductor pattern layer 13 and the height of the first insulating layer 142 are equal.
  • This step is specifically: first, an amorphous silicon layer 133 is formed on the buffer layer 12. Specifically, in this embodiment, an amorphous silicon layer 133 is formed on the silicon oxide layer 122. Then, the amorphous silicon layer 133 is subjected to a crystallization operation to form a polysilicon layer 134, specifically, crystallizing by excimer laser annealing (ELA), and then the polysilicon layer 134 is patterned by a first mask process to form a semiconductor pattern. Layer 13. Further, a silicon nitride layer 14 having the same height as the semiconductor pattern layer 13 is formed on the semiconductor pattern layer 13 and the buffer layer 12 on which the semiconductor pattern layer 13 is not formed, specifically, the silicon oxide layer 122.
  • ELA excimer laser annealing
  • the negative photoresist 141 is applied to the portion of the silicon nitride layer 14 that does not correspond to the semiconductor pattern layer 13, and the silicon nitride layer 14 is patterned by the second mask process. Further, the silicon nitride layer 14 over the semiconductor pattern layer 13 is etched to etch away the silicon nitride layer 14 on the semiconductor pattern layer 13 such that the same height as the semiconductor pattern layer 13 is formed at both ends of the semiconductor pattern layer 13.
  • the first insulating layer 142 is applied to the portion of the silicon nitride layer 14 that does not correspond to the semiconductor pattern layer 13, and the silicon nitride layer 14 is patterned by the second mask process. Further, the silicon nitride layer 14 over the semiconductor pattern layer 13 is etched to etch away the silicon nitride layer 14 on the semiconductor pattern layer 13 such that the same height as the semiconductor pattern layer 13 is formed at both ends of the semiconductor pattern layer 13.
  • the polysilicon layer 134 is patterned by a first photomask process, specifically by first coating a photoresist layer on the polysilicon layer 134, and then performing a process such as exposure and development to remove the excess polysilicon layer 134. It should be understood that the reticle process mentioned later is the same as that of the first reticle process unless otherwise specified.
  • the intrinsic region 130 and the weights on both sides of the intrinsic region 130 are further formed on the semiconductor pattern layer 13 through the third mask process and the first doping process on the semiconductor pattern layer 13. Doping the region 131, and then further forming a lightly doped region between the intrinsic region 130 and the heavily doped region 131 on the semiconductor pattern layer 13 through the fourth mask process and the second doping process on the semiconductor pattern layer 13. 132.
  • the heavily doped region 131 and the lightly doped region 132 are all N-doped by ion implantation, and the difference is that the doping ratio is different.
  • the method of the embodiment of the present invention further includes forming a second insulating layer 15 on the semiconductor pattern layer 13 and the first insulating layer 142.
  • a gate layer 16 is formed on the second insulating layer 15. Since the heights of the semiconductor pattern layer 13 and the first insulating layer 142 are the same, the surface of the second insulating layer 15 is in a flat state, thereby avoiding the unevenness of the surface of the second insulating layer 15, for example, having a structure such as a bump. A side effect caused by uneven spacing between the layer 16 and the semiconductor pattern layer 13. Thereby making the subsequent signal transmission more stable and improving LTPS The electrical properties of the TFT pixel unit 10.
  • the embodiment of the present invention also performs a fifth mask process on the gate layer 16 such that it forms the gate 161. Further, a third insulating layer 17 is formed on the gate electrode 161.
  • the third insulating layer 17 includes a silicon oxide layer 171 and a silicon nitride layer 172 in this embodiment.
  • an LTPS is formed on the third insulating layer 17.
  • the source electrode 18 and the drain electrode 19 are electrically connected to the semiconductor pattern layer 13 through the first via holes M1 passing through the second insulating layer 15 and the third insulating layer 17, respectively.
  • a fourth insulating layer 110 is formed on the source 18 and the drain 19, and a pixel electrode 100 is formed on the fourth insulating layer 110.
  • the pixel electrode 100 passes through the second via hole M2 of the fourth insulating layer 110.
  • One of the source 18 or the drain 19 is electrically connected.
  • the pixel electrode 100 and the drain electrode 19 are electrically connected.
  • the pixel electrode 100 and the source electrode 18 may be electrically connected.
  • a fifth insulating layer 120 is further formed between the fourth insulating layer 110 and the source 18 and the drain 19.
  • a common electrode 130 is further formed between the fifth insulating layer 120 and the fourth insulating layer 110 for forming a liquid crystal capacitor with the pixel electrode 100.
  • the LTPS TFT pixel unit 10 produced by the method of the embodiment of the present invention has a smaller side effect and has higher electrical properties.
  • the embodiment of the present invention further provides an LTPS TFT pixel unit based on the method described above. See Figure 3 for details.
  • the TFT pixel unit 10 includes a substrate 11, a buffer layer 12, a semiconductor pattern layer 13, and a first insulating layer 142.
  • the buffer layer 12 includes a silicon nitride layer 121 and a silicon oxide layer 122, and the silicon nitride layer 121 and the silicon oxide layer 122 are sequentially disposed on the substrate 11.
  • the semiconductor pattern layer 13 and the first insulating layer 142 are disposed on the buffer layer 12 in the same layer, specifically, on the silicon oxide layer 122, and the height of the semiconductor pattern layer 13 is equal to the height of the first insulating layer 142.
  • the manufacturing process of the semiconductor pattern layer 13 and the first insulating layer 142 is as described above. I will not repeat them here.
  • the semiconductor pattern layer 13 further includes an intrinsic region 130 and a heavily doped region 131 on both sides of the intrinsic region 130. Further, the semiconductor pattern layer 13 further includes an intrinsic region 130 and a heavily doped region 131. Lightly doped region 132 between.
  • the TFT pixel unit 10 further includes a second insulating layer 15, a gate electrode 161, a third insulating layer 17, a source electrode 18, a drain electrode 19, a fourth insulating layer 110, and a pixel electrode 100.
  • the second insulating layer 15 is disposed on the semiconductor pattern layer 13 and the first insulating layer 142.
  • the gate electrode 161 is disposed on the second insulating layer 15.
  • the third insulating layer 17 includes a silicon oxide layer 171 and a silicon nitride layer 172, which are sequentially disposed on the gate electrode 161.
  • the source 18 and the drain 19 are disposed on the third insulating layer 17, wherein the source 18 and the drain 19 pass through the first via hole M1 and the semiconductor pattern layer 13 passing through the second insulating layer 15 and the third insulating layer 17, respectively. Electrical connection.
  • the fourth insulating layer 110 is disposed on the source 18 and the drain 19.
  • the pixel electrode 100 is disposed on the fourth insulating layer 110 and electrically connected to one of the source 18 or the drain 19 through the second via M2 passing through the fourth insulating layer 110.
  • the TFT pixel unit 10 further includes a fifth insulating layer 120 and a common electrode 130.
  • the fifth insulating layer 120 is disposed between the fourth insulating layer 110 and the source 18 and the drain 19.
  • the common electrode 130 is disposed between the fifth insulating layer 120 and the fourth insulating layer 110 for forming a liquid crystal capacitance with the pixel electrode 100.
  • the present invention can reduce the side effect of the LTPS TFT pixel unit 10 and can improve its electrical properties.

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Abstract

一种LTPS TFT像素单元及其制造方法。该方法包括以下步骤：提供一基板（11），并在基板（11）上形成一缓冲层（12）；在缓冲层（12）上形成半导体图案层（13）和第一绝缘层（142），半导体图案层（13）与第一绝缘层（142）同层设置且半导体图案层（13）的高度和第一绝缘层（142）的高度相等。通过上述方式，可以减小LTPS TFT像素单元的侧效应，并可以提高其电性。

Description

一种LTPS TFT像素单元及其制造方法
【技术领域】
本发明涉及显示技术领域，尤其是涉及一种LTPS TFT像素单元及其制造方法。
【背景技术】
现有技术的LTPS TFT（Low Temperature Poly-silicon Thin Film Transistor，低温多晶硅薄膜晶体管）像素单元的形成过程为：先沉积缓冲层，然后在缓冲层上形成半导体图案层，进一步在半导体图案层上形成绝缘层、栅极等LTPS TFT像素单元的其他元件。
现有技术的LTPS TFT像素单元因为半导体图案层形成在缓冲层上，也就是说半导体图案层自缓冲层向上凸起，使得后续形成的绝缘层在半导体图案层的两端形成阶梯凸起结构，从而使得形成在绝缘层上的栅极与半导体图案层的间距不均而造成侧效应。另一方面，由于存在缓冲层的阶梯结构，使得信号在传输过程不稳定，从而影响LTPS TFT像素单元的电性。
【发明内容】
本发明主要解决的技术问题是提供一种LTPS TFT像素单元及其制造方法，能够减小侧效应，并提高LTPS TFT像素单元的电性。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种LTPS TFT像素单元的制造方法，该方法包括以下步骤：提供一基板，并在基板上形成一缓冲层；在缓冲层上形成半导体图案层和第一绝缘层，半导体图案层与第一绝缘层同层设置且半导体图案层的高度和第一绝缘层的高度相等；其中，在基板上形成一缓冲层的步骤包括：在基板上依次形成氮化硅层和氧化硅层；在缓冲层上形成半导体图案层和第一绝缘层，半导体图案层与第一绝缘层同层设置且半导体图案层的高度和第一绝缘层的高度相等的步骤包括：在缓冲层上形成一非晶硅层，并对非晶硅层进行结晶操作，以形成多晶硅层；通过第一道光罩工序对多晶硅层进行图案化，以形成半导体图案层；在半导体图案层上和未形成半导体图案层的缓冲层上形成一与半导体图案层高度相同的氮化硅层；在氮化硅层上的未对应半导体图案层的位置涂覆负向光阻；通过第二道光罩工序对氮化硅层进行图案化处理；进一步对半导体图案层上方的氮化硅层进行蚀刻，以蚀刻掉半导体图案层上的氮化硅层，使得在半导体图案层的两端形成与半导体图案层的高度相同的第一绝缘层。
其中，方法还包括：在半导体图案层上通过第三道光罩工序和第一掺杂工序在半导体图案层上形成本征区域和位于本征区域两侧的重掺杂区域；进一步在半导体图案层上通过第四道光罩工序和第二掺杂工序在半导体图案层上形成位于本征区域与重掺杂区域之间的轻掺杂区域。
其中，方法还包括：在半导体图案层和第一绝缘层上形成第二绝缘层；在第二绝缘层上形成栅极层，并通过第五道光罩工序对栅极层进行图案化处理，以形成栅极；在栅极上形成第三绝缘层；在第三绝缘层上形成LTPS TFT单元的源极和漏极，其中源极和漏极分别通过穿过第二绝缘层和第三绝缘层的第一通孔与半导体图案层电连接；在源极和漏极上形成第四绝缘层，并在第四绝缘层上形成像素电极，像素电极通过穿过第四绝缘层的第二通孔与源极或漏极之一电连接。
其中，方法还包括：在第四绝缘层和源极以及漏极之间进一步形成第五绝缘层；在第五绝缘层和第四绝缘层之间进一步形成公共电极，用于与像素电极形成液晶电容。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种LTPS TFT像素单元的制造方法，该方法包括以下步骤：提供一基板，并在基板上形成一缓冲层；在缓冲层上形成半导体图案层和第一绝缘层，半导体图案层与第一绝缘层同层设置且半导体图案层的高度和第一绝缘层的高度相等。
其中，在基板上形成一缓冲层的步骤包括：在基板上依次形成氮化硅层和氧化硅层。
其中，在缓冲层上形成半导体图案层和第一绝缘层，半导体图案层与第一绝缘层同层设置且半导体图案层的高度和第一绝缘层的高度相等的步骤包括：在缓冲层上形成一非晶硅层，并对非晶硅层进行结晶操作，以形成多晶硅层；通过第一道光罩工序对多晶硅层进行图案化，以形成半导体图案层；在半导体图案层上和未形成半导体图案层的缓冲层上形成一与半导体图案层高度相同的氮化硅层；在氮化硅层上的未对应半导体图案层的位置涂覆负向光阻；通过第二道光罩工序对氮化硅层进行图案化处理；进一步对半导体图案层上方的氮化硅层进行蚀刻，以蚀刻掉半导体图案层上的氮化硅层，使得在半导体图案层的两端形成与半导体图案层的高度相同的第一绝缘层。
其中，方法还包括：在半导体图案层上通过第三道光罩工序和第一掺杂工序在半导体图案层上形成本征区域和位于本征区域两侧的重掺杂区域；进一步在半导体图案层上通过第四道光罩工序和第二掺杂工序在半导体图案层上形成位于本征区域与重掺杂区域之间的轻掺杂区域。
其中，方法还包括：在半导体图案层和第一绝缘层上形成第二绝缘层；在第二绝缘层上形成栅极层，并通过第五道光罩工序对栅极层进行图案化处理，以形成栅极；在栅极上形成第三绝缘层；在第三绝缘层上形成LTPS TFT单元的源极和漏极，其中源极和漏极分别通过穿过第二绝缘层和第三绝缘层的第一通孔与半导体图案层电连接；在源极和漏极上形成第四绝缘层，并在第四绝缘层上形成像素电极，像素电极通过穿过第四绝缘层的第二通孔与源极或漏极之一电连接。
其中，方法还包括：在第四绝缘层和源极以及漏极之间进一步形成第五绝缘层；在第五绝缘层和第四绝缘层之间进一步形成公共电极，用于与像素电极形成液晶电容。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种LTPS TFT像素单元，该LTPS TFT单元包括：基板；缓冲层，设置在基板上；半导体图案层和第一绝缘层，同层设置在缓冲层上，且半导体图案层的高度和第一绝缘层的高度相等。
其中，缓冲层包括依次设置在基板上的氮化硅层和氧化硅层。
其中，LTPS TFT像素单元还包括：第二绝缘层，设置在半导体图案层和第一绝缘层上；栅极，设置在第二绝缘层上；第三绝缘层，设置在栅极上；源极和漏极，设置在第三绝缘层上，其中源极和漏极分别通过穿过第二绝缘层和第三绝缘层的第一通孔与半导体图案层电连接；第四绝缘层，设置在源极和漏极上；像素电极，设置在第四绝缘层上，并通过穿过第四绝缘层的第二通孔与源极或漏极之一电连接。
其中，LTPS TFT像素单元还包括：第五绝缘层，设置在第四绝缘层和源极以及漏极之间；公共电极，设置在第五绝缘层和第四绝缘层之间，用于与像素电极形成液晶电容。
本发明的有益效果是：区别于现有技术的情况，本发明在缓冲层上形成同层设置且高度相同的半导体图案层和第一绝缘层，使得后续形成在第一绝缘层和半导体图案层上的第二绝缘层处于平坦的状态，没有凸起等结构，进而使得栅极层可以处于平坦的第二绝缘层上，保证了其与半导体图案层的间距一致，因此避免了因第二绝缘层的凸起等结构使栅极层和半导体图案层间距不均而造成的侧效应，同时也提高了LTPS TFT像素单元的电性。
【附图说明】
图1是本发明实施例提供的一种TFT像素单元的制造方法的流程图；
图2是图1所示的方法对应的制程图；
图3是本发明实施例提供的一种TFT像素单元的结构示意图。
【具体实施方式】
请一并参阅图1和图2，图1是本发明实施例提供的一种LTPS TFT像素单元的制造方法的流程图，图2是图1所示的方法对应的制程图。如图1和图2所示，本发明实施例提供的方法包括以下步骤：
步骤S1：提供一基板11，并在基板11上形成一缓冲层12。
具体为在基板11上依次形成氮化硅层121和氧化硅层122，作为缓冲层12。
步骤S2：在缓冲层12上形成半导体图案层13和第一绝缘层14，半导体图案层13与第一绝缘层142同层设置且半导体图案层13的高度和第一绝缘层142的高度相等。
本步骤具体为：首先在缓冲层12上形成一非晶硅层133，具体的，本实施例是在氧化硅层122上形成非晶硅层133。然后对非晶硅层133进行结晶操作，以形成多晶硅层134，具体可以通过准分子激光退火（ELA）完成结晶，进而通过第一道光罩工序对多晶硅层134进行图案化，以形成半导体图案层13。进一步在半导体图案层13上和未形成半导体图案层13的缓冲层12，具体为氧化硅层122上形成一与半导体图案层13高度相同的氮化硅层14。在氮化硅层14上的未对应半导体图案层13的位置涂覆负向光阻141，通过第二道光罩工序对氮化硅层14进行图案化处理。进一步对半导体图案层13上方的氮化硅层14进行蚀刻，以蚀刻掉半导体图案层13上的氮化硅层14，使得在半导体图案层13的两端形成与半导体图案层13的高度相同的第一绝缘层142。
其中，通过第一道光罩工序对多晶硅层134进行图案化，具体为首先在多晶硅层134上涂覆一光阻层，然后进行曝光和显影等制程，以将多余的多晶硅层134去除。应理解，后文提到的光罩工序，如无特别说明，其原理与第一道光罩工序的相同。
在形成了第一绝缘层142后，进一步在半导体图案层13上通过第三道光罩工序和第一掺杂工序在半导体图案层13上形成本征区域130和位于本征区域130两侧的重掺杂区域131，然后进一步在半导体图案层13上通过第四道光罩工序和第二掺杂工序在半导体图案层13上形成位于本征区域130与重掺杂区域131之间的轻掺杂区域132。
其中，重掺杂区域131和轻掺杂区域132都是通过离子注入的方式进行N型掺杂，其区别为掺杂的比例不同。
本发明实施例的方法还包括：在半导体图案层13和第一绝缘层142上形成第二绝缘层15。在第二绝缘层15上形成栅极层16。由于半导体图案层13和第一绝缘层142的高度相同，使得第二绝缘层15的表面处于平坦状态，从而避免了因第二绝缘层15的表面高低不平，例如具有凸起等结构使得栅极层16与半导体图案层13之间的间距不均匀而造成的侧效应。从而使得后续的信号的传输更加稳定，提高了LTPS TFT像素单元10的电性。
本发明实施例还对栅极层16进行第五道光罩工序，使得其形成栅极161。并进一步在栅极161上形成第三绝缘层17，其中，本实施例中，第三绝缘层17包括氧化硅层171和氮化硅层172。
进一步的，在第三绝缘层17上形成LTPS TFT单元10的源极18和漏极19，其中，源极18和漏极19的形成过程和栅极161的形成过程相同，在此不再赘述。本实施例中，源极18和漏极19分别通过穿过第二绝缘层15和第三绝缘层17的第一通孔M1与半导体图案层13电连接。
进一步的，在源极18和漏极19上形成第四绝缘层110，并在第四绝缘层110上形成像素电极100，像素电极100通过穿过第四绝缘层110的第二通孔M2与源极18或漏极19之一电连接。本实施例具体为像素电极100与漏极19电连接，在其他实施例中，也可以为素电极100与源极18电连接。
进一步的，在第四绝缘层110和源极18以及漏极19之间进一步形成第五绝缘层120。在第五绝缘层120和第四绝缘层110之间进一步形成公共电极130，用于与像素电极100形成液晶电容。
因此，通过本发明实施例的方法制得的LTPS TFT像素单元10具有更小的侧效应，并具有更高的电性。
本发明实施例还基于前文所述的方法提供一种LTPS TFT像素单元。具体请参阅图3。
如图3所示，本发明实施例提供的LTPS TFT像素单元10包括基板11、缓冲层12、半导体图案层13和第一绝缘层142。
其中，缓冲层12包括氮化硅层121和氧化硅层122，氮化硅层121和氧化硅层122依次设置在基板11上。
半导体图案层13和第一绝缘层142同层设置在缓冲层12上，具体是设置在氧化硅层122上，且半导体图案层13的高度和第一绝缘层142的高度相等。其中，半导体图案层13和第一绝缘层142的制造过程如前文所述。在此不再赘述。
本实施例中，半导体图案层13还包括本征区域130和位于本征区域130两侧的重掺杂区域131，进一步的，半导体图案层13还包括位于本征区域130与重掺杂区域131之间的轻掺杂区域132。
进一步的，LTPS TFT像素单元10还包括第二绝缘层15、栅极161、第三绝缘层17、源极18、漏极19、第四绝缘层110和像素电极100。
其中，第二绝缘层15设置在半导体图案层13和第一绝缘层142上。栅极161设置在第二绝缘层15上。第三绝缘层17包括氧化硅层171和氮化硅层172，依次设置在栅极161上。源极18和漏极19设置在第三绝缘层17上，其中源极18和漏极19分别通过穿过第二绝缘层15和第三绝缘层17的第一通孔M1与半导体图案层13电连接。第四绝缘层110设置在源极18和漏极19上。像素电极100设置在第四绝缘层110上，并通过穿过第四绝缘层110的第二通孔M2与源极18或漏极19之一电连接。
进一步的，LTPS TFT像素单元10还包括第五绝缘层120和公共电极130。其中，第五绝缘层120设置在第四绝缘层110和源极18以及漏极19之间。公共电极130设置在第五绝缘层120和第四绝缘层110之间，用于与像素电极100形成液晶电容。
综上所述，本发明可以减小LTPS TFT像素单元10的侧效应，并可以提高其电性。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种LTPS TFT像素单元的制造方法，其中，所述方法包括以下步骤：
    提供一基板，并在所述基板上形成一缓冲层；
    在所述缓冲层上形成半导体图案层和第一绝缘层，所述半导体图案层与所述第一绝缘层同层设置且所述半导体图案层的高度和所述第一绝缘层的高度相等；
    其中，在所述基板上形成一缓冲层的步骤包括：
    在所述基板上依次形成氮化硅层和氧化硅层；
    在所述缓冲层上形成半导体图案层和第一绝缘层，所述半导体图案层与所述第一绝缘层同层设置且所述半导体图案层的高度和所述第一绝缘层的高度相等的步骤包括：
    在所述缓冲层上形成一非晶硅层，并对所述非晶硅层进行结晶操作，以形成多晶硅层；
    通过第一道光罩工序对所述多晶硅层进行图案化，以形成所述半导体图案层；
    在所述半导体图案层上和未形成所述半导体图案层的所述缓冲层上形成一与所述半导体图案层高度相同的氮化硅层；
    在所述氮化硅层上的未对应所述半导体图案层的位置涂覆负向光阻；
    通过第二道光罩工序对所述氮化硅层进行图案化处理；
    进一步对所述半导体图案层上方的所述氮化硅层进行蚀刻，以蚀刻掉所述半导体图案层上的氮化硅层，使得在所述半导体图案层的两端形成与所述半导体图案层的高度相同的所述第一绝缘层。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：
    在所述半导体图案层上通过第三道光罩工序和第一掺杂工序在所述半导体图案层上形成本征区域和位于所述本征区域两侧的重掺杂区域；
    进一步在所述半导体图案层上通过第四道光罩工序和第二掺杂工序在所述半导体图案层上形成位于所述本征区域与所述重掺杂区域之间的轻掺杂区域。
  3. 根据权利要求2所述的方法，其中，所述方法还包括：
    在所述半导体图案层和所述第一绝缘层上形成第二绝缘层；
    在所述第二绝缘层上形成栅极层，并通过第五道光罩工序对所述栅极层进行图案化处理，以形成栅极；
    在所述栅极上形成第三绝缘层；
    在所述第三绝缘层上形成所述LTPS TFT单元的源极和漏极，其中所述源极和漏极分别通过穿过所述第二绝缘层和第三绝缘层的第一通孔与所述半导体图案层电连接；
    在所述源极和漏极上形成第四绝缘层，并在所述第四绝缘层上形成像素电极，所述像素电极通过穿过所述第四绝缘层的第二通孔与所述源极或漏极之一电连接。
  4. 根据权利要求3所述的方法，其中，所述方法还包括：
    在所述第四绝缘层和所述源极以及漏极之间进一步形成第五绝缘层；
    在所述第五绝缘层和所述第四绝缘层之间进一步形成公共电极，用于与所述像素电极形成液晶电容。
  5. 一种LTPS TFT像素单元的制造方法，其中，所述方法包括以下步骤：
    提供一基板，并在所述基板上形成一缓冲层；
    在所述缓冲层上形成半导体图案层和第一绝缘层，所述半导体图案层与所述第一绝缘层同层设置且所述半导体图案层的高度和所述第一绝缘层的高度相等。
  6. 根据权利要求5所述的方法，其中，在所述基板上形成一缓冲层的步骤包括：
    在所述基板上依次形成氮化硅层和氧化硅层。
  7. 根据权利要求5所述的方法，其中，在所述缓冲层上形成半导体图案层和第一绝缘层，所述半导体图案层与所述第一绝缘层同层设置且所述半导体图案层的高度和所述第一绝缘层的高度相等的步骤包括：
    在所述缓冲层上形成一非晶硅层，并对所述非晶硅层进行结晶操作，以形成多晶硅层；
    通过第一道光罩工序对所述多晶硅层进行图案化，以形成所述半导体图案层；
    在所述半导体图案层上和未形成所述半导体图案层的所述缓冲层上形成一与所述半导体图案层高度相同的氮化硅层；
    在所述氮化硅层上的未对应所述半导体图案层的位置涂覆负向光阻；
    通过第二道光罩工序对所述氮化硅层进行图案化处理；
    进一步对所述半导体图案层上方的所述氮化硅层进行蚀刻，以蚀刻掉所述半导体图案层上的氮化硅层，使得在所述半导体图案层的两端形成与所述半导体图案层的高度相同的所述第一绝缘层。
  8. 根据权利要求7所述的方法，其中，所述方法还包括：
    在所述半导体图案层上通过第三道光罩工序和第一掺杂工序在所述半导体图案层上形成本征区域和位于所述本征区域两侧的重掺杂区域；
    进一步在所述半导体图案层上通过第四道光罩工序和第二掺杂工序在所述半导体图案层上形成位于所述本征区域与所述重掺杂区域之间的轻掺杂区域。
  9. 根据权利要求8所述的方法，其中，所述方法还包括：
    在所述半导体图案层和所述第一绝缘层上形成第二绝缘层；
    在所述第二绝缘层上形成栅极层，并通过第五道光罩工序对所述栅极层进行图案化处理，以形成栅极；
    在所述栅极上形成第三绝缘层；
    在所述第三绝缘层上形成所述LTPS TFT单元的源极和漏极，其中所述源极和漏极分别通过穿过所述第二绝缘层和第三绝缘层的第一通孔与所述半导体图案层电连接；
    在所述源极和漏极上形成第四绝缘层，并在所述第四绝缘层上形成像素电极，所述像素电极通过穿过所述第四绝缘层的第二通孔与所述源极或漏极之一电连接。
  10. 根据权利要求9所述的方法，其中，所述方法还包括：
    在所述第四绝缘层和所述源极以及漏极之间进一步形成第五绝缘层；
    在所述第五绝缘层和所述第四绝缘层之间进一步形成公共电极，用于与所述像素电极形成液晶电容。
  11. 一种LTPS TFT像素单元，其中，所述LTPS TFT单元包括：
    基板；
    缓冲层，设置在所述基板上；
    半导体图案层和第一绝缘层，同层设置在所述缓冲层上，且所述半导体图案层的高度和所述第一绝缘层的高度相等。
  12. 根据权利要求11所述的LTPS TFT像素单元，其中，所述缓冲层包括依次设置在所述基板上的氮化硅层和氧化硅层。
  13. 根据权利要求12所述的LTPS TFT像素单元，其中，所述LTPS TFT像素单元还包括：
    第二绝缘层，设置在所述半导体图案层和所述第一绝缘层上；
    栅极，设置在所述第二绝缘层上；
    第三绝缘层，设置在所述栅极上；
    源极和漏极，设置在所述第三绝缘层上，其中所述源极和漏极分别通过穿过所述第二绝缘层和第三绝缘层的第一通孔与所述半导体图案层电连接；
    第四绝缘层，设置在所述源极和漏极上；
    像素电极，设置在所述第四绝缘层上，并通过穿过所述第四绝缘层的第二通孔与所述源极或漏极之一电连接。
  14. 根据权利要求13所述的LTPS TFT像素单元，其中，所述LTPS TFT像素单元还包括：
    第五绝缘层，设置在所述第四绝缘层和所述源极以及漏极之间；
    公共电极，设置在所述第五绝缘层和所述第四绝缘层之间，用于与所述像素电极形成液晶电容。
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