WO2016106899A1 - 阵列基板及阵列基板制造方法 - Google Patents

阵列基板及阵列基板制造方法 Download PDF

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WO2016106899A1
WO2016106899A1 PCT/CN2015/071208 CN2015071208W WO2016106899A1 WO 2016106899 A1 WO2016106899 A1 WO 2016106899A1 CN 2015071208 W CN2015071208 W CN 2015071208W WO 2016106899 A1 WO2016106899 A1 WO 2016106899A1
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layer
region
type
light shielding
polysilicon
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PCT/CN2015/071208
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English (en)
French (fr)
Inventor
戴天明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/436,063 priority Critical patent/US9704884B2/en
Publication of WO2016106899A1 publication Critical patent/WO2016106899A1/zh
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to the field of manufacturing LTPS thin film transistors, and more particularly to an array substrate and an array substrate manufacturing method.
  • Low temperature poly-silicon (LTPS) thin film transistor liquid crystal display is different from traditional amorphous silicon thin film transistor liquid crystal display, and its electron mobility can reach 200cm2/V-sec or more, which can effectively reduce thin film transistor device.
  • the area is increased to achieve an increase in aperture ratio, and the overall brightness can be reduced while increasing the brightness of the display.
  • the higher electron mobility can integrate part of the driving circuit on the glass substrate, which reduces the driving IC, and can also greatly improve the reliability of the liquid crystal display panel, thereby greatly reducing the manufacturing cost of the panel. Therefore, LTPS thin film transistor liquid crystal displays have gradually become a research hotspot.
  • the LTPS thin film transistor liquid crystal display mainly includes an array substrate and a color filter substrate disposed opposite thereto.
  • the number of process paths of the LTPS array substrate is about 9 channels.
  • the overall equipment investment is too large and the yield is too low, the production process is complicated, and the manufacturing cost is correspondingly increased, so LTPS Mask reduction technology has always been the focus of LTPS research and development.
  • the invention provides an array substrate and an array substrate manufacturing method, which can simplify the manufacturing process and reduce the cost.
  • the array substrate includes a substrate, a common electrode, a light shielding layer, an insulating layer, a polysilicon layer, a gate insulating layer, a gate, a dielectric layer, and a source and a drain.
  • the common electrode is formed on the substrate.
  • the light shielding layer is located on the common electrode, and the insulating layer is located on the light shielding layer and the common electrode
  • the gate is connected to the common electrode through a via.
  • the polysilicon layer includes a first polysilicon region and a second polysilicon region, the polysilicon layer is located on the insulating layer, and the gate insulating layer is located on the polysilicon layer and the insulating layer.
  • the gate is located on the gate insulating layer and is orthographically projected on the first polysilicon region and the second polysilicon region, and the dielectric layer is located at the gate and the gate insulating layer on.
  • the array substrate further includes a first type of doping region and a second type of doping region in the same layer as the first polysilicon region and the second polysilicon region, corresponding to the dielectric layer
  • the source and drain electrodes of the first polysilicon region and the second polysilicon region are connected to the first doping region and the second type doping region through via holes.
  • the invention also provides a method for manufacturing an array substrate, comprising
  • the transparent conductive layer and the first metal layer are patterned by two etching processes to form a common electrode and a light shielding layer; wherein the light shielding layer includes a first light shielding area and a second light shielding area which are disposed at intervals in the same layer And an edge region, the edge region is projected onto the common electrode, the second region is projected onto the edge region, and the two first regions are projected onto the first light shielding region and the second light shielding region on;
  • the polysilicon layer includes a first polysilicon region and a second polysilicon region, the first polysilicon region being projected onto the first light shielding layer
  • the second polysilicon region is projected onto the second light shielding region.
  • a gate insulating layer on the polysilicon layer and the insulating layer Forming a gate insulating layer on the polysilicon layer and the insulating layer, forming an electrode via on the gate insulating layer by a mask and an etching process, and defining a first type of doping region; wherein the via hole Exposing the common electrode through the gate insulating layer and the insulating layer; the first type of doping regions are located on both sides of the first polysilicon region;
  • a gate is connected to the common electrode through an electrode via.
  • the method for fabricating an array substrate further includes: defining a second type of doped region and implanting a second type of ion to the second type of doped region; wherein the second type of doped region is located in the second polysilicon region Bilateral; implanting a second type of ion into the second type of doped region;
  • a patterned pixel layer is formed on the source drain and on the dielectric layer.
  • the step of “patterning the transparent conductive layer and the first metal layer by two etching processes to form a common electrode and a light shielding layer” includes: between the two first regions and the first region Drying the first metal layer exposed between the second region to form a first light shielding region, a second light shielding region and an edge region of the light shielding layer;
  • the transparent conductive layer exposing the light shielding layer is wet etched to form the common electrode.
  • the step of “removing the light shielding layer and the edge region on the common electrode by an etching process” includes removing the second region and a portion of the first region by dry etching, and then removing the remaining portion by a dry etching process a first region portion and the edge region of the common electrode.
  • the step of "forming a via via on the gate insulating layer by a mask and an etching process and defining a first type of doped region” includes: passing the semipermeable membrane mask over the gate insulating layer Forming a patterned photoresist layer on the electrode to form an electrode hole and two implant holes;
  • a plurality of implant holes are formed by etching to remove a portion of the photoresist layer and open the two implant holes, and the two implant holes correspond to the first type of doped regions.
  • the first type of ions are P-type ions
  • the second type of ions are N-type ions
  • the second type of ions are P-type ions
  • the first type of ions are N-type ions.
  • the method for fabricating an array substrate of the present invention saves a mask by forming a transparent conductive layer and a first metal layer on a substrate, and then forming a patterned common electrode and a light shielding layer by a single mask and multiple etching; After the mask is etched, an electrode via connecting the common electrode and the gate is formed, and then The dielectric layer and the source and drain are fabricated to save the passivation layer.
  • the overall process uses seven masks to simplify the processing steps of the array substrate tube and reduce the fabrication cost of the array substrate.
  • FIG. 1 is a schematic cross-sectional view showing the structure of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a flow chart of a method of fabricating an array substrate in accordance with a preferred embodiment of the present invention.
  • 3 to 17 are cross-sectional views showing respective manufacturing processes of an array substrate according to a preferred embodiment of the present invention.
  • the present invention provides an array substrate in an LTPS thin film transistor display.
  • the array substrate includes a substrate, a common electrode 11, a light shielding layer 12, an insulating layer 13, a polysilicon layer 14, a gate insulating layer 15, a gate electrode 16, a dielectric layer 17, and source and drain electrodes.
  • the common electrode 11 is formed on the substrate 10
  • the light shielding layer 12 is located on the common electrode 11
  • the insulating layer 13 is located on the light shielding layer 12 and the common electrode 11.
  • a pixel layer 19 is further formed on the source and drain electrodes.
  • the array substrate exemplified in this embodiment is exemplified by one PTFT and one NTFT.
  • the source and drain are source 181, 182 and drains 183, 184, respectively.
  • the polysilicon layer 14 includes a first polysilicon region 141 and a second polysilicon region 143, the polysilicon layer 14 is located on the insulating layer 13, and the gate insulating layer 15 is located in the On the polysilicon layer 14 and the insulating layer 13.
  • the gate 16 is located on the gate insulating layer 15 and is projected onto the first
  • the polysilicon region and the second polysilicon region are located on the gate electrode 16 and the gate insulating layer 15.
  • the array substrate further includes a first type of doping region 145 and a second type of doping region 146 located in the same layer as the first polysilicon region and the second polysilicon region, in the dielectric layer 17 corresponding to the source and drain of the first polysilicon region and the second polysilicon region, wherein the source and drain are connected to the first doping region 145 and the second type doping region 146 through via holes .
  • FIG. 2 there is shown a flowchart of a method for fabricating an array substrate according to a preferred embodiment of the present invention.
  • the method for fabricating an array substrate of the present invention includes the following steps.
  • step S1 the substrate 10 is provided, and a transparent conductive layer 21 and a first metal layer 22 are sequentially deposited on the substrate 10.
  • the substrate 10 is a glass layer.
  • step S2 a photoresist layer is formed on the first metal layer 21, and the photoresist layer is patterned by a single mask, so that the patterned photoresist layer 23 includes two first regions 231 and Second region 232.
  • the thickness of the first region 231 is greater than the thickness of the second region 232.
  • the reticle (not shown) includes three light transmitting portions, a semi-light transmitting portion and a light blocking portion disposed above the photoresist layer, and the two first regions 231 and the second portion are formed by light irradiation. Area 232.
  • the first mask process is used in this step.
  • the reticle technology is a commonly used technique in the art, and will not be described again.
  • step S3 the transparent conductive layer 21 and the first metal layer 22 are patterned by two etching processes to form a common electrode 11 and a light shielding layer 12; wherein the light shielding layer 12 is included in the same layer.
  • the first light shielding area 121, the second light shielding area 122 and the edge area 123 are disposed at intervals.
  • the edge region 123 is projected onto the common electrode 24, the second region 232 is projected onto the edge region 123, and the two first regions 231 are projected onto the first light blocking region 121 and the second On the shading area 122.
  • the first metal layer 22 exposed between the two first regions 231 and between the first region 231 and the second region 231 is dry etched to form the first light shielding layer 12 A light shielding area 121, a second light shielding area 122 and an edge area 123.
  • step S32 the transparent conductive layer 32 exposing the light shielding layer 23 is wet etched to form the common electrode 11.
  • the dry etching gas is CF4, SF6 or a mixed gas of CL2 and O2
  • the wet etching liquid is oxalic acid, sulfuric acid, hydrochloric acid, or a mixture of oxalic acid, sulfuric acid and hydrochloric acid.
  • step S4 the patterned photoresist layer 23 and the edge region 123 on the common electrode 24 are removed by two etching processes.
  • This step includes removing the second region 232 and a portion of the first region 231 by dry etching, and then removing the remaining first region 231 portion and the edge region 123 of the common electrode 11 by a dry etching process.
  • the edge region 123 on the common electrode 11 is exposed to make the first region
  • the thickness of 231 is reduced, and the second dry etching removes the edge region 123 and the remaining first region 231 at one time, without damaging the common electrode 11 due to over-etching.
  • step S5 an insulating layer 13 is formed on the light shielding layer 12 and the common electrode 24.
  • step S6 a patterned polysilicon layer 14 is formed on the insulating layer 13.
  • the polysilicon layer includes a first polysilicon region 141 and a second polysilicon region 142.
  • the first polysilicon region 141 is projected onto the first light shielding region 121, and the second polycrystalline layer
  • the silicon region 142 is projected onto the second light blocking region 122.
  • the patterning of this step means that the polysilicon layer 14 is formed by a second mask process.
  • step S7 a gate insulating layer 15 is formed on the polysilicon layer 14 and the insulating layer 13, and an electrode via 151 is formed on the gate insulating layer 15 by a mask and an etching process, and A first type of doped region 145 is defined.
  • the via hole penetrates the gate insulating layer 15 and the insulating layer 13 to expose the common electrode 12, and the first type of doping region 145 is located on both sides of the first polysilicon region 141;
  • the first type doped region 145 and the position of the electrode via are defined by a semi-transmissive film mask, and the electrode via 151 is formed by dry etching.
  • the reticle refers to passing through a third reticle.
  • a photoresist layer is formed on the gate insulating layer 15 and the photoresist layer is patterned by a photomask, so that the patterned photoresist layer 20 includes electrode holes 2001 and two One implanted hole 2002.
  • the electrode hole position 2001 is located directly above the common electrode 24.
  • the two implant holes 2002 are opposite to both sides of the first polysilicon region 141.
  • step S72 the gate insulating layer 15 and the insulating layer 13 corresponding to the electrode hole position 2001 are dry etched to form the electrode via 151.
  • step S73 a portion of the photoresist layer 20 is removed by etching and the two implant holes 2002 are opened to form two implant holes 2004 in communication with the gate insulating layer 15. Where the two The corresponding position of the implant hole 2004 is the first type doped region 145.
  • step S8 the first type of doping region 145 is implanted with a first type of ions through the two implant holes 2004; the first type of ions are P-type ions or N-type ions. In this embodiment, it is a P-type ion.
  • the step further includes a step S81 of removing the patterned photoresist layer 20 by an etching process.
  • a second metal layer (not shown) is formed on the gate insulating layer 15.
  • the second metal layer is patterned to form a gate electrode 16, and the gate electrode 16 passes through an electrode via.
  • the common electrode 12 is connected.
  • the patterned second metal layer is formed by using a fourth mask process.
  • the via hole is located on the side of the common electrode 11.
  • the gate 16 includes two portions that are respectively projected onto the first polysilicon region 141 and the second polysilicon region 142.
  • the array substrate manufacturing method further includes
  • a second type of doping region 146 is defined, and a second type of doping region 146 is located on both sides of the second polysilicon region 142.
  • a second type of ion is implanted into the second type of doped region 146.
  • the first type of ions are N-type ions or P-type ions. In this embodiment, it is an N-type ion. Defining the second type of doped region 146 is accomplished by the prior art.
  • step S11 a dielectric layer 17 is formed on the gate electrode 16 and the gate insulating layer 15, and a source/drain layer is formed on the dielectric layer 17.
  • the method further includes forming a via 171 communicating with the first type doping region 145 and a via 172 communicating with the second type doping region 146 on the dielectric layer 17 through a fifth mask. .
  • the source and drain layers are patterned by a mask etching process to form a source and a drain corresponding to the first polysilicon region 141 and a source and drain of the second polysilicon region 142.
  • the source and drain electrodes are respectively connected to the first type doping region 145 and the second type doping region 146 through via holes.
  • the source and drain electrodes are the source electrodes 181 and 182 and the drain electrodes 183 and 184, respectively.
  • the source electrode 181 and the drain electrode 183 are connected to the first doping region 145 through a via 171.
  • the source 182 and the drain 184 are connected to the second type of doping region 146 through the via 172.
  • the reticle in this step is a sixth reticle.
  • step S13 a patterned pixel layer 19 is formed on the source and drain electrodes and on the dielectric layer 17, and finally an array substrate as shown in FIG. 1 is formed.
  • the patterning in this step uses a seventh mask process.
  • the first light-shielding region 121, the first polysilicon region 141, and the gate of the first polysilicon region 141 are projected, and the region where the first-type impurity region 145 is located is a PTFT.
  • the second shading The region 122, the second polysilicon region 142, the gate projected on the second polysilicon region 142, and the region where the second type doping region 146 is located are NTFTs.
  • the present invention further provides a method for fabricating a thin film transistor for the above two embodiments.
  • the patterning refers to a patterning process, which may include a photolithography process, or The photolithography process and the etching step are included, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.; the photolithography process refers to the use of a photoresist, including film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • the method for fabricating an array substrate of the present invention saves a mask by forming a transparent conductive layer and a first metal layer on a substrate, and then forming a patterned common electrode and a light shielding layer by a single mask and multiple etching; After the mask is etched, the electrode vias communicating with the common electrode 11 and the gate electrode 16 are formed, and then the dielectric layer and the source and drain electrodes are fabricated to save the passivation layer.
  • the overall process uses seven masks to simplify the array substrate. The processing steps of the tube reduce the fabrication cost of the array substrate.
  • the display device formed by the method for manufacturing a thin film transistor according to the embodiment of the present invention may be: a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED panel, an OLED television, an electronic paper, a digital photo frame, a mobile phone, or the like.

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Abstract

一种阵列基板及其制造方法，所述阵列基板包括基板（10）、公共电极（11）、遮光层（12）、绝缘层（13）、多晶硅层（14）、栅极绝缘层（15）、栅极（16）、介质层（17）及源漏极（181，182，183，184），其中，所述公共电极（11）形成所述基板（10）上，所述遮光层（12）位于所述公共电极（11）上，所述绝缘层（13）位于所述遮光层（12）及公共电极（11）上，所述栅极（16）与所述公共电极（11）通过过孔（151）连接。该阵列基板制造方法通过在基板（10）上形成透明导电层（21）及第一金属层（22）后再通过一次光罩及多次蚀刻形成图案化后的公共电极（11）及遮光层（12），节省了一道光罩；然后通过一次光罩蚀刻后形成连通公共电极（11）及栅极（16）的电极过孔（151），后续再进行介质层（17）及源漏极（181，182，183，184）制作，整体工艺之采用七道光罩，简化阵列基板管的加工工艺步骤，降低阵列基板的制作成本。

Description

阵列基板及阵列基板制造方法
本发明要求2014年12月31日递交的发明名称为“阵列基板及阵列基板制造方法”的申请号201410854124.6的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及LTPS薄膜晶体管的制造领域，尤其涉及一种阵列基板及阵列基板制造方法。
背景技术
低温多晶硅(low temperature poly-silicon，简称为LTPS)薄膜晶体管液晶显示器有别于传统的非晶硅薄膜晶体管液晶显示器，其电子迁移率可以达到200cm2/V-sec以上，可有效减小薄膜晶体管器件的面积，从而达到提高开口率，并且在增进显示器亮度的同时还可以降低整体的功耗。另外，较高的电子迁移率可以将部分驱动电路集成在玻璃基板上，减少了驱动IC，还可以大幅提升液晶显示面板的可靠度，从而使得面板的制造成本大幅降低。因此，LTPS薄膜晶体管液晶显示器逐步成为研究的热点。LTPS薄膜晶体管液晶显示器主要包括阵列基板和与其相对设置的彩膜基板。
但目前由于LTPS阵列基板的制程道数大概在9道左右，相对于非晶硅的制程而言，导致整体的设备投入过大和良率过低，生产工艺要复杂，制作成本相应增加，所以LTPS mask减少技术一直是LTPS研发的重点。
发明内容
本发明提供一种阵列基板及阵列基板制造方法，能够简化制造工艺，降低成本。
提供一种阵列基板，所述阵列基板包括基板、公共电极、遮光层、绝缘层、多晶硅层、栅极绝缘层、栅极、介质层及源漏极，所述公共电极形成所述基板上，所述遮光层位于所述公共电极上，所述绝缘层位于所述遮光层及公共电极 上，所述栅极与所述公共电极通过过孔连接。
其中，所述多晶硅层包括第一多晶硅区域及第二多晶硅区域，所述多晶硅层位于所述绝缘层上，所述栅极绝缘层位于所述多晶硅层及绝缘层上。
其中，所述栅极位于所述栅极绝缘层上并正投影于所述第一多晶硅区域及第二多晶硅区域，所述介质层位于所述栅极及所述栅极绝缘层上。
其中，所述阵列基板还包括与所述第一多晶硅区域及第二多晶硅区域位于同一层的第一类参杂区及第二类参杂区，在介质层上相对应所述第一多晶硅区域及第二多晶硅区域的源漏极，所述源漏极均通过过孔与所述第一参杂区及第二类参杂区连接。
本发明还提供一种阵列基板制造方法，包括，
提供一基板，并在所述基板上依次沉积形成透明导电层及第一金属层；
在所述第一金属层上形成光阻层，通过一次光罩图案化所述光阻层，使图案化的光阻层包括两个第一区域及第二区域，其中，所述第一区域的厚度大于所述第二区域的厚度；
通过两次蚀刻工艺对所述透明导电层及第一金属层进行图案化，形成公共电极及遮光层；其中，所述遮光层包括在同一层的间隔设置的第一遮光区、第二遮光区及边缘区，所述边缘区正投影于所述公共电极上，所述第二区域正投影于边缘区上，所述两个第一区域正投影于所述第一遮光区及第二遮光区上；
通过两次蚀刻工艺去除图案化的光阻层及位于所述公共电极上的边缘区；
在所述遮光层及公共电极上形成绝缘层；
在所述绝缘层上形成图案化的多晶硅层；其中，所述多晶硅层包括第一多晶硅区域及第二多晶硅区域，所述第一多晶硅区域正投影于所述第一遮光区上，所述第二多晶硅区域正投影于所述第二遮光区上。
在所述多晶硅层及所述绝缘层上形成栅极绝缘层，通过光罩及蚀刻工艺在所述栅极绝缘层上形成电极过孔并定义第一类掺杂区；其中，所述过孔贯穿所述栅极绝缘层及绝缘层露出所述公共电极；所述第一类参杂区位于所述第一多晶硅区域两侧；
对所述第一类掺杂区注入第一类型离子；
在所述栅极绝缘层上形成第二金属层，图案化第二金属层形成栅极，所述 栅极通过电极过孔与所述公共电极连接。
其中，所述阵列基板制造方法还包括，定义第二类掺杂区及对所述第二类掺杂区注入第二类型离子；其中第二类掺杂区位于所述第二多晶硅区域两侧；对所述第二类掺杂区注入第二类型离子；
在栅极及所述栅极绝缘层上形成介质层，并且在介质层上形成源漏极层；
通过光罩蚀刻工艺对源漏极层图案化，形成相对应所述第一多晶硅区域的源漏极，及相对应第二多晶硅区域的源漏极，其中，所述源漏极通过过孔分别与所述第一类掺杂区及第二类掺杂区连接；
在所述源漏极上及介质层上形成图案化的像素层。
其中，所述“通过两次蚀刻工艺对所述透明导电层及第一金属层进行图案化，形成公共电极及遮光层”的步骤包括，对两个所述第一区域之间及第一区域与第二区域之间露出的第一金属层进行干蚀刻，形成所述遮光层的第一遮光区、第二遮光区及边缘区；
对露出遮光层的所述透明导电层进行湿蚀刻，形成所述公共电极。
其中，所述“通过蚀刻工艺去除遮光层及位于所述公共电极上的边缘区”的步骤包括，通过干蚀刻去除所述第二区域及部分第一区域后，再通过干蚀刻工艺去除剩下的第一区域部分及位于所述公共电极的所述边缘区。
其中，所述“通过光罩及蚀刻工艺在所述栅极绝缘层上形成电极过孔，并且定义第一类掺杂区”的步骤包括，通过半透膜光罩在所述栅极绝缘层上形成图案化的光阻层，形成电极孔位及两个植入孔位；
对所述电极孔位所对应的栅极绝缘层及绝缘层进行干蚀刻形成所述电极过孔；
通过蚀刻去除部分光阻层并打通所述两个植入孔位形成与栅极绝缘层连通的两个植入孔，所述两个植入孔对应位置为所述第一类掺杂区。
其中，所述第一类型离子为P型离子，所述第二类型离子为N型离子，或者，所述第二类型离子为P型离子，所述第一类型离子为N型离子。。
本发明的阵列基板制造方法通过在基板上形成透明导电层及第一金属层后再通过一次光罩及多次蚀刻形成图案化后的公共电极及遮光层，节省了一道光罩；然后通过一次光罩蚀刻后形成连通公共电极及栅极的电极过孔，后续再 进行介质层及源漏极制作，节省钝化层(Passivation layer)层，整体工艺之采用七道光罩，简化阵列基板管的加工工艺步骤，降低阵列基板的制作成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明较佳实施方式的阵列基板结构剖面示意图。
图2为本发明较佳实施方式的阵列基板的制造方法的流程图。
图3至图17为本发明较佳实施方式的阵列基板的各个制造流程中的剖面图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明提供一种LTPS薄膜晶体管显示中的阵列基板。所述阵列基板包括基板、公共电极11、遮光层12、绝缘层13、多晶硅层14、栅极绝缘层15、栅极16、介质层17及源漏极。所述公共电极11形成所述基板10上，所述遮光层12位于所述公共电极11上，所述绝缘层13位于所述遮光层12及公共电极11上。本实施例中，所述源漏极上还形成有像素层19。本实施例中列举的阵列基板以一个PTFT和一个NTFT为例。所述源漏极分别为源极181、182及漏极183、184。
本实施例中，所述多晶硅层14包括第一多晶硅区域141及第二多晶硅区域143，所述多晶硅层14位于所述绝缘层13上，所述栅极绝缘层15位于所述多晶硅层14及绝缘层13上。
本实施例中，所述栅极16位于所述栅极绝缘层15上并正投影于所述第一 多晶硅区域及第二多晶硅区域，所述介质层17位于所述栅极16及所述栅极绝缘层15上。
本实施例中，所述阵列基板还包括与所述第一多晶硅区域及第二多晶硅区域位于同一层的第一类参杂区145及第二类参杂区146，在介质层17上相对应所述第一多晶硅区域及第二多晶硅区域的源漏极，所述源漏极通过过孔与所述第一参杂区145及第二类参杂区146连接。
请参阅图2，图中所示的是本发明较佳实施方式的阵列基板的制造方法的流程图，本发明的阵列基板制造方法包括如下步骤，
请参阅图3，步骤S1，提供所述基板10，并在所述基板10上依次沉积形成透明导电层21及第一金属层22。本实施例中，所述基板10为玻璃层。
请参阅图4，步骤S2，在所述第一金属层21上形成光阻层并通过一次光罩图案化所述光阻层，使图案化的光阻层23包括两个第一区域231及第二区域232。其中，所述第一区域231的厚度大于所述第二区域232的厚度。所述光罩(图未示)包括设置于所述光阻层的上方的三个透光部、半透光部及遮光部，通过光照射形成所述的两个第一区域231及第二区域232。本步骤中使用第一道光罩工艺。该光罩技术为本领域常用技术，再次不做赘述。
请参阅图5，步骤S3，通过两次蚀刻工艺对所述透明导电层21及第一金属层22进行图案化，形成公共电极11及遮光层12；其中，所述遮光层12包括在同一层的间隔设置的第一遮光区121、第二遮光区122及边缘区123。所述边缘区123正投影于所述公共电极24上，所述第二区域232正投影于边缘区123上，所述两个第一区域231正投影于所述第一遮光区121及第二遮光区122上。
在本步骤中包括步骤S31，对两个所述第一区域231之间及第一区域231与第二区域231之间露出的第一金属层22进行干蚀刻，形成所述遮光层12的第一遮光区121、第二遮光区122及边缘区123。
步骤S32，对露出遮光层23的所述透明导电层32进行湿蚀刻，形成所述公共电极11。
本实施例中，所述干蚀刻的气体为CF4，SF6或CL2和O2的混合气体，湿蚀刻液为草酸，硫酸，盐酸，或草酸、硫酸及盐酸的混合液。
请参阅图6与图7，步骤S4，通过两次蚀刻工艺去除图案化的光阻层23及位于所述公共电极24上的边缘区123。本步骤中包括通过干蚀刻去除所述第二区域232及部分第一区域231后，再通过干蚀刻工艺去除剩下的第一区域231部分及位于所述公共电极11的所述边缘区123。具体的，第一次干蚀刻去除所述第二区域232及与所述第二区域232厚度相同的部分第一区域231后，露出公共电极11的上的所述边缘区123，使第一区域231厚度减小，第二次干蚀刻一次性去除所述边缘区123及剩下的第一区域231，不会因为过度蚀刻而破坏所述公共电极11。
请参阅图8，步骤S5，在所述遮光层12及公共电极24上形成绝缘层13。
请参阅图9，步骤S6，在所述绝缘层13上形成图案化的多晶硅层14。其中，所述多晶硅层包括第一多晶硅区域141及第二多晶硅区域142，所述第一多晶硅区域141正投影于所述第一遮光区121上，所述第二多晶硅区域142正投影于所述第二遮光区122上。本步骤的图案化即指通过第二道光罩工艺形成多晶硅层14。
请参阅图10，步骤S7，在所述多晶硅层14及所述绝缘层13上形成栅极绝缘层15，通过光罩及蚀刻工艺在所述栅极绝缘层15上形成电极过孔151，并且定义第一类掺杂区145。其中，所述过孔贯穿所述栅极绝缘层15及绝缘层13露出所述公共电极12，所述第一类参杂区145位于所述第一多晶硅区域141两侧；本步骤中，通过半透膜光罩定义出并且定义第一类掺杂区145及所述电极过孔的位置，再通过干蚀刻形成所述电极过孔151。所述光罩指通过第三道光罩。
请参阅图11，具体包括步骤S71，在所述栅极绝缘层15上形成光阻层并通过光罩图案化所述光阻层，使图案化的光阻层20包括电极孔位2001及两个植入孔位2002。所述电极孔位2001位于所述公共电极24正上方。所述两个植入孔位2002与所述第一多晶硅区域141两侧相对。
请参阅图12，步骤S72，对所述电极孔位2001所对应的栅极绝缘层15及绝缘层13进行干蚀刻，形成所述电极过孔151。
请参阅图13，步骤S73，通过蚀刻去除部分光阻层20并打通所述两个植入孔位2002形成与栅极绝缘层15连通的两个植入孔2004。其中，所述两个 植入孔2004对应位置为第一类掺杂区145。
请参阅图14，步骤S8，穿过两个植入孔2004对所述第一类掺杂区145注入第一类型离子；所述第一类型离子为P型离子或N型离子。本实施例中为P型离子。本步骤中还包括步骤S81，通过蚀刻工艺去除图案化的光阻层20。
请参阅图15，步骤S9，在所述栅极绝缘层15上形成第二金属层(图未示)，图案化第二金属层形成栅极16，所述栅极16通过电极过孔与所述公共电极12连接。本实施例中，所述图案化第二金属层为采用第四道光罩工艺形成栅极。所述过孔位于所述公共电极11一侧。所述栅极16包括分别正投影于所述第一多晶硅区域141及第二多晶硅区域142的两部分。
所述阵列基板制造方法还包括，
步骤S10，定义第二类掺杂区146，第二类掺杂区146位于所述第二多晶硅区域142两侧。对所述第二类掺杂区146注入第二类型离子。所述第一类型离子为N型离子或P型离子。本实施例中为N型离子。定义第二类掺杂区146通过现有技术实现。
请参阅图16，步骤S11，在栅极16及所述栅极绝缘层15上形成介质层17，并且在介质层17上形成源漏极层。在本步骤中，还包括对通过第五道光罩在所述介质层17上形成与所述第一类掺杂区145连通的过孔171及与第二类掺杂区146连通的过孔172。
请参阅图17，步骤S12，通过光罩蚀刻工艺对源漏极层图案化形成相对应所述第一多晶硅区域141的源漏极，及第二多晶硅区域142的源漏极。所述源漏极通过过孔分别与所述第一类掺杂区145及第二类掺杂区146连接。具体的，所述源漏极分别为源极181、182及漏极183、184。所述源极181及漏极183与所述第一参杂区145通过过孔171连接。所述源极182及漏极184与第二类参杂区146通过过孔172连接。本步骤中的光罩为第六道光罩。
请再次参阅图1，步骤S13，在所述源漏极上及介质层17上形成图案化的像素层19，最后形成如图1所示的阵列基板。本步骤中的图案化采用第七道光罩工艺。
本实施例中，所述第一遮光区121、第一多晶硅区域141、正投影于第一多晶硅区域141的栅极，第一类参杂区145所在区域为PTFT。所述第二遮光 区122、第二多晶硅区域142、正投影于第二多晶硅区域142的栅极、第二类掺杂区146所在区域为NTFT。
本发明针对上述两种实施例还提供了薄膜晶体管的制造方法，在阐述具体制备方法之前，应该理解，在本发明中，所述图案化即是指构图工艺，可包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影，等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明中所形成的结构选择相应的构图工艺。
本发明的阵列基板制造方法通过在基板上形成透明导电层及第一金属层后再通过一次光罩及多次蚀刻形成图案化后的公共电极及遮光层，节省了一道光罩；然后通过一次光罩蚀刻后形成连通公共电极11及栅极16的电极过孔，后续再进行介质层及源漏极制作，节省钝化层(Passivation layer)层，整体工艺之采用七道光罩，简化阵列基板管的加工工艺步骤，降低阵列基板的制作成本。
通过本发明实施例薄膜晶体管的制造方法形成的显示器件，可以为：液晶面板、液晶电视、液晶显示器、OLED面板、OLED电视、电子纸、数码相框、手机等。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种阵列基板，所述阵列基板包括基板、公共电极、遮光层、绝缘层、多晶硅层、栅极绝缘层、栅极、介质层及源漏极，其中，所述公共电极形成所述基板上，所述遮光层位于所述公共电极上，所述绝缘层位于所述遮光层及公共电极上，所述栅极与所述公共电极通过过孔连接。
  2. 如权利要求1所述的阵列基板，其中，所述多晶硅层包括第一多晶硅区域及第二多晶硅区域，所述多晶硅层位于所述绝缘层上，所述栅极绝缘层位于所述多晶硅层及绝缘层上。
  3. 如权利要求2所述的阵列基板，其中，所述栅极位于所述栅极绝缘层上并正投影于所述第一多晶硅区域及第二多晶硅区域，所述介质层位于所述栅极及所述栅极绝缘层上。
  4. 如权利要求3所述的阵列基板，其中，所述阵列基板还包括与所述第一多晶硅区域及第二多晶硅区域位于同一层的第一类参杂区及第二类参杂区，在介质层上相对应所述第一多晶硅区域及第二多晶硅区域的源漏极，所述源漏极均通过过孔与所述第一参杂区及第二类参杂区连接。
  5. 一种阵列基板制造方法，所述方法包括，
    提供一基板，并在所述基板上依次沉积形成透明导电层及第一金属层；
    在所述第一金属层上形成光阻层，通过一次光罩图案化所述光阻层，使图案化的光阻层包括两个第一区域及第二区域，其中，所述第一区域的厚度大于所述第二区域的厚度；
    通过两次蚀刻工艺对所述透明导电层及第一金属层进行图案化，形成公共电极及遮光层；其中，所述遮光层包括在同一层的间隔设置的第一遮光区、第二遮光区及边缘区，所述边缘区正投影于所述公共电极上，所述第二区域正投影于边缘区上，所述两个第一区域正投影于所述第一遮光区及第二遮光区上；
    通过两次蚀刻工艺去除图案化的光阻层及位于所述公共电极上的边缘区；
    在所述遮光层及公共电极上形成绝缘层；
    在所述绝缘层上形成图案化的多晶硅层；其中，所述多晶硅层包括第一多晶硅区域及第二多晶硅区域，所述第一多晶硅区域正投影于所述第一遮光区 上，所述第二多晶硅区域正投影于所述第二遮光区上；
    在所述多晶硅层及所述绝缘层上形成栅极绝缘层，通过光罩及蚀刻工艺在所述栅极绝缘层上形成电极过孔并定义第一类掺杂区；其中，所述过孔贯穿所述栅极绝缘层及绝缘层露出所述公共电极；所述第一类参杂区位于所述第一多晶硅区域两侧；
    对所述第一类掺杂区注入第一类型离子；
    在所述栅极绝缘层上形成第二金属层，图案化第二金属层形成栅极，所述栅极通过电极过孔与所述公共电极连接。
  6. 如权利要求5所述的阵列基板制造方法，其中，所述阵列基板制造方法还包括，定义第二类掺杂区及对所述第二类掺杂区注入第二类型离子；其中第二类掺杂区位于所述第二多晶硅区域两侧；
    在栅极及所述栅极绝缘层上形成介质层，并且在介质层上形成源漏极层；
    通过光罩蚀刻工艺对源漏极层图案化，形成相对应所述第一多晶硅区域的源漏极，及相对应第二多晶硅区域的源漏极，其中，所述源漏极通过过孔分别与所述第一类掺杂区及第二类掺杂区连接；
    在所述源漏极上及介质层上形成图案化的像素层。
  7. 如权利要求6所述的阵列基板制造方法，其中，所述“通过两次蚀刻工艺对所述透明导电层及第一金属层进行图案化，形成公共电极及遮光层”的步骤包括，对两个所述第一区域之间及第一区域与第二区域之间露出的第一金属层进行干蚀刻，形成所述遮光层的第一遮光区、第二遮光区及边缘区；
    对露出遮光层的所述透明导电层进行湿蚀刻，形成所述公共电极。
  8. 如权利要求7所述的阵列基板制造方法，其中，所述“通过蚀刻工艺去除遮光层及位于所述公共电极上的边缘区”的步骤包括，通过干蚀刻去除所述第二区域及部分第一区域后，再通过干蚀刻工艺去除剩下的第一区域部分及位于所述公共电极的所述边缘区。
  9. 如权利要求6所述的阵列基板制造方法，其中，所述“通过光罩及蚀刻工艺在所述栅极绝缘层上形成电极过孔，并且定义第一类掺杂区”的步骤包括，
    通过半透膜光罩在所述栅极绝缘层上形成图案化的光阻层，形成电极孔位 及两个植入孔位；
    对所述电极孔位所对应的栅极绝缘层及绝缘层进行干蚀刻形成所述电极过孔；
    通过蚀刻去除部分光阻层并打通所述两个植入孔位形成与栅极绝缘层连通的两个植入孔，所述两个植入孔对应位置为所述第一类掺杂区。
  10. 如权利要求1所述的阵列基板制造方法，其中，所述第一类型离子为P型离子，所述第二类型离子为N型离子，或者，所述第二类型离子为P型离子，所述第一类型离子为N型离子。
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