CN105206568B - 一种低温多晶硅tft阵列基板的制备方法及其阵列基板 - Google Patents

一种低温多晶硅tft阵列基板的制备方法及其阵列基板 Download PDF

Info

Publication number
CN105206568B
CN105206568B CN201510673823.5A CN201510673823A CN105206568B CN 105206568 B CN105206568 B CN 105206568B CN 201510673823 A CN201510673823 A CN 201510673823A CN 105206568 B CN105206568 B CN 105206568B
Authority
CN
China
Prior art keywords
layer
photoresist
source
type tft
patterning processes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510673823.5A
Other languages
English (en)
Other versions
CN105206568A (zh
Inventor
孙双
牛菁
张方振
吕志军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201510673823.5A priority Critical patent/CN105206568B/zh
Publication of CN105206568A publication Critical patent/CN105206568A/zh
Priority to US15/212,871 priority patent/US9653496B2/en
Application granted granted Critical
Publication of CN105206568B publication Critical patent/CN105206568B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

本发明涉及显示技术领域，公开一种低温多晶硅TFT阵列基板的制备方法及其阵列基板，制备方法包括在多晶硅层上形成光刻胶层，并采用灰度掩膜板进行曝光并显影，形成光刻胶完全保留区域、光刻胶半保留区域和光刻胶完全去除区域的图形；采用刻蚀工艺去除多晶硅层位于光刻胶完全去除区域的部分，形成有源层的图形；对光刻胶进行灰化处理，使位于光刻胶半保留区域的部分有源层露出并对部分有源层进行高浓度P+离子注入，形成P型TFT的源漏极图形的掺杂区；在形成公共电极的图形时形成源漏极和有源层的连接电极，该制备方法可减少低温多晶硅阵列基板制备过程中的光刻工艺数量，进而降低低温多晶硅显示设备的生产成本。

Description

一种低温多晶硅TFT阵列基板的制备方法及其阵列基板
技术领域
本发明涉及显示技术领域，特别涉及一种低温多晶硅TFT阵列基板的制备方法及其阵列基板。
背景技术
低温多晶硅(Low Temperature Poly-silicon；LTPS)是平板显示器领域中继非晶硅(Amorphous-Silicon，a-Si)之后的下一代技术。传统的非晶硅材料的电子迁移率只有0.5cm2/V·S，而低温多晶硅材料的电子迁移率可达50～200cm2/V·S，因此与传统的非晶硅薄膜晶体管液晶显示器(a-Si TFT-LCD)相比，低温多晶硅薄膜晶体管液晶显示器具有解析度更高、反应速度快、亮度高等优点，同时可以将周边驱动电路同时制作在玻璃衬底基板上，达到在玻璃上集成系统的目标，所以能够节省空间和成本，此外，低温多晶硅技术又是发展主动式有机电致发光(AM-OLED)的技术平台，因此，低温多晶硅技术的发展受到了广泛的重视。
现有技术中，由于低温多晶硅TFT阵列基板的制备工艺较为复杂，一般需进行10-11道光刻工艺，增加了低温多晶硅显示设备的生产成本。
发明内容
本发明提供了一种低温多晶硅TFT阵列基板的制备方法及其阵列基板，可减少低温多晶硅阵列基板制备过程中的光刻工艺数量，进而降低低温多晶硅显示设备的生产成本。
为实现上述目的，本发明提供如下的技术方案：
一种低温多晶硅TFT阵列基板的制备方法，包括：
通过第一道构图工艺在衬底基板上形成遮光层的图形；
在形成遮光层图形的衬底基板上形成非晶硅层、并对所述非晶硅层进行脱氢处理；
对所述进行脱氢处理后的非晶硅层进行结晶化处理，使所述非晶硅层转换为多晶硅层；
进行第二道构图工艺，在所述多晶硅层上形成光刻胶层，并采用灰度掩膜板进行曝光并显影，形成光刻胶完全保留区域、光刻胶半保留区域和光刻胶完全去除区域的图形；采用刻蚀工艺去除所述多晶硅层位于所述光刻胶完全去除区域的部分，形成有源层的图形；对光刻胶进行灰化处理，使位于所述光刻胶半保留区域的部分所述有源层露出并对所述部分有源层进行高浓度P+离子注入，形成P型TFT的源漏极图形的掺杂区；剥离剩余的光刻胶；
通过第三道构图工艺形成N型TFT栅极的图形和P型TFT栅极的图形；
通过第四道构图工艺形成层间绝缘层和第一层接触孔的图形；
通过第五道构图工艺形成源漏极图形和数据线图形；
通过第六道构图工艺形成平坦化绝缘层图形，并形成第二层接触孔的图形；
通过第七道构图工艺形成公共电极的图形，以及所述源漏极和所述有源层的连接电极。
采用上述方法制备低温多晶硅TFT阵列基板时，由于在形成有源层的图形后，对位于P型TFT区域的有源层进行高浓度离子注入形成P型TFT的源漏极图形的掺杂区，省去了单独形成P型TFT的源漏极图形的掺杂区的光刻工艺；且在形成公共电极的图形的同时形成源漏极和有源层的连接电极，省去了形成P型TFT源漏极图形的光刻工艺，因此，上述制备方法可减少两道光刻工艺，简化了低温多晶硅TFT阵列基板的制备工艺，降低了TFT阵列基板的生产成本。
优选地，所述在形成遮光层图形的衬底基板上形成非晶硅层之前还包括，在所述形成遮光层图形的衬底基板上沉积缓冲层。
优选地，所述通过第三道构图工艺形成N型TFT栅极的图形和P型TFT栅极的图形具体包括：
在所述有源层上形成栅绝缘层和栅金属层；
采用光刻工艺形成N型TFT和P型TFT栅极的图形；
对位于N型TFT区域的有源层进行高浓度N+离子注入，形成N型TFT的源漏极图形的掺杂区；
对位于N型TFT区域的有源层进行低浓度N-离子注入，形成轻掺杂漏极图形。
进一步地，采用磷化氢对位于N型TFT区域的有源层进行高浓度N+离子注入。
优选地，所述通过第四道构图工艺形成层间绝缘层和第一层接触孔的图形具体包括：
在所述栅金属层上形成层间绝缘层；
采用刻蚀工艺对所述层间绝缘层和所述栅金属层刻蚀，形成第一层接触孔的图形。
优选地，所述第五道构图工艺形成源漏极图形和数据线图形具体包括：
在所述层间绝缘层上形成源漏金属层和数据线层；
采用光刻工艺形成所述源漏金属层和所述数据线层的图形。
优选地，所述通过第六道构图工艺形成平坦化绝缘层并形成第二层接触孔的图形具体包括：
在所述数据线层上形成平坦化绝缘层；
采用刻蚀工艺对所述平坦化绝缘层进行刻蚀，形成第二层接触孔的图形。
优选地，所述通过第七道构图工艺形成公共电极的图形，以及源漏极和有源层的连接电极具体包括：
在所述平坦化绝缘层上形成公共电极层，所述公共电极层填充于所述第二层接触孔内，以连接所述源漏极和所述有源层；
采用刻蚀工艺对所述公共电极层进行刻蚀，形成公共电极层的图形和连接电极的图形。
优选地，所述形成公共电极的图形，以及源漏极和有源层的连接电极之后还包括：
通过第八道构图工艺在所述公共电极层上形成保护层图形；
通过第九道构图工艺在所述保护层上形成像素电极层图形。
本发明还提供了一种低温多晶硅TFT阵列基板，所述阵列基板中的P型TFT的源漏极图形的掺杂区与P型TFT的源漏极通过透明的连接电极相连接。
该低温多晶硅TFT阵列基板中，P型TFT的有源层和源漏极由位于N型TFT与P型TFT之间的透明的连接电极连接，提高了TFT的开口率。
附图说明
图1是本发明具体实施方式提供的一种低温多晶硅TFT阵列基板的制备方法的流程图；
图2是通过第一道构图工艺在衬底基板上形成遮光层的图形后的阵列基板结构示意图；
图3是在图2中的形成遮光层图形后的衬底基板上形成非晶硅层后的阵列基板结构示意图；
图4是使图3中的非晶硅层转换为多晶硅层并形成光刻胶完全保留区域、光刻胶半保留区域和光刻胶完全去除区域的图形后的阵列基板结构示意图；
图5是采用刻蚀工艺去除图4中所示的部分多晶硅层并形成有源层图形后的阵列基板结构示意图；
图6是对图5中所示的光刻胶进行灰化处理，并形成P型TFT的源漏极图形的掺杂区后的阵列基板结构示意图；
图7是剥离图6中所示的光刻胶后的阵列基板结构示意图；
图8是图1所示的步骤S106的具体过程流程图；
图9是在图7中所示的有源层上形成栅绝缘层和栅金属层后的阵列基板结构示意图；
图10是刻蚀图9中所示的栅金属层后形成N型TFT和P型TFT栅极的图形后的阵列基板结构示意图；
图11是对图10中所示的位于N型TFT区域的有源层进行高浓度N+离子注入，形成N型TFT的有源层源漏极图形后的阵列基板结构示意图；
图12是对图11中所示的位于N型TFT区域的有源层进行低浓度N-离子注入，形成轻掺杂漏极图形后的阵列基板结构示意图；
图13是图1所示的步骤S107的具体过程流程图；
图14是在图12所示的栅金属层上形成层间绝缘层并形成第一层接触孔的图形后的阵列基板结构示意图；
图15是图1所示的步骤S108的具体过程流程图；
图16是在图14所示的层间绝缘层上形成源漏金属层和数据线层图形后的阵列基板结构示意图；
图17是图1所示的步骤S109的具体过程流程图；
图18是在图16所示的数据线层上形成平坦化绝缘层并形成第二层接触孔的图形后的阵列基板结构示意图；
图19是图1所示的步骤S110的具体过程流程图；
图20是在图18中所示的平坦化绝缘层上形成公共电极层，并形成连接电极后的阵列基板结构示意图；
图21是图1所示的步骤S111的具体过程流程图；
图22是在图20中所示的公共电极层上形成保护层图形后的阵列基板结构示意图；
图23是是图1所示的步骤S112的具体过程流程图；
图24是在图22中所示的保护层上形成像素电极层图形后的阵列基板结构示意图。
附图标记：
10，衬底基板；20，遮光层；30，缓冲层；40，非晶硅层；
50，多晶硅层；51、52、53，有源层；521、522，P型TFT的源漏极图形的掺杂区；
511、531，N型TFT的源漏极图形的掺杂区；
512、532，轻掺杂漏极图形；61、62、63、64，光刻胶层图形；
70，栅绝缘层；80，栅金属层；81、83、84，N型TFT栅极；
82，P型TFT栅极；90，层间绝缘层；91，第一层接触孔；
101，源漏金属层图形；110，平坦化绝缘层；111，第二层接触孔；
120，公共电极层；121，连接电极；130，保护层；140，像素电极层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参见图1-图7，本发明具体实施方式提供了一种低温多晶硅TFT阵列基板的制备方法，包括如图1所示的以下步骤：
步骤S101，如图2所示，通过第一道构图工艺在衬底基板10上形成遮光层20的图形；
步骤S103，如图3所示，在形成遮光层20图形的衬底基板10上形成非晶硅层40、并对非晶硅层40进行脱氢处理；
步骤S104，如图4所示，对进行脱氢处理后的非晶硅层40进行结晶化处理，使非晶硅层40转换为多晶硅层50；
步骤S105，如图4所示，进行第二道构图工艺，在多晶硅层50上形成光刻胶层，并采用灰度掩膜板进行曝光并显影，形成光刻胶完全保留区域、光刻胶半保留区域和光刻胶完全去除区域，其中，光刻胶层图形61和63为光刻胶完全保留区域，光刻胶层图形63为光刻胶半保留区域，光刻胶层图形61、62、63之间的无光刻胶区域为光刻胶完全去除区域；
如图5所示，采用刻蚀工艺去除多晶硅层50位于光刻胶完全去除区域的部分，形成有源层51、52、53的图形；
如图6所示，对光刻胶层图形61、62、63进行灰化处理，使位于光刻胶半保留区域的有源层52部分露出并对有源层52进行高浓度P+离子注入，形成P型TFT的源漏极图形的掺杂区521、522；
如图7所示，剥离剩余的光刻胶；
步骤S106，通过第三道构图工艺形成N型TFT栅极的图形和P型TFT栅极的图形；
步骤S107，通过第四道构图工艺形成层间绝缘层和第一层接触孔的图形；
步骤S108，通过第五道构图工艺形成源漏极图形和数据线图形；
步骤S109，通过第六道构图工艺形成平坦化绝缘层图形，并形成第二层接触孔的图形；
步骤S110，通过第七道构图工艺形成公共电极的图形，以及源漏极和有源层的连接电极。
采用上述方法制备低温多晶硅TFT阵列基板时，在步骤S105中，在形成有源层51、52、53的图形后，对位于P型TFT区域的有源层进行高浓度离子注入形成P型TFT的源漏极图形的掺杂区，与现有技术中的制备方法相比，上述制备方法可省去形成P型TFT的源漏极图形的掺杂区的光刻工艺；且在步骤S110中，在形成公共电极的图形的同时，形成连接P型TFT的有源层和源漏极的连接电极，与现有技术中的制备方法相比，上述制备方法可省去形成P型TFT源漏极图形的光刻工艺，因此，上述制备方法可减少两道光刻工艺，简化了低温多晶硅TFT阵列基板的制备工艺，降低了低温多晶硅TFT阵列基板的生产成本。
如图1所示的一种优选方式中，在步骤S103形成遮光层图形的衬底基板上形成非晶硅层之前还包括，
步骤S102，在形成遮光层20图形的衬底基板10上沉积缓冲层30。
参见图8，一种优选方式中，步骤S106，通过第三道构图工艺形成N型TFT栅极的图形和P型TFT栅极的图形，具体包括：
步骤S1061，如图9所示，在有源层51、52、53上形成栅绝缘层70和栅金属层80，并在栅金属层80上形成光刻胶层，通过曝光、显影形成光刻胶层图形64；
步骤S1062，如图10所示，采用光刻工艺，对位于光刻胶层图形64以外的栅金属层80进行刻蚀，形成N型TFT栅极81、83、84的图形和P型TFT栅极82的图形；
步骤S1063，如图11所示，对位于N型TFT区域的有源层进行高浓度N+离子注入，形成N型TFT的源漏极图形的掺杂区511、531；
步骤S1064，如图12所示，对光刻胶层图形64进行灰化，并对位于N型TFT区域的有源层51、53进行低浓度N-离子注入，形成轻掺杂漏极图形512、532。
优选地，采用磷化氢对位于N型TFT区域的有源层进行高浓度N+离子注入。
参见图13，一种优选方式中，步骤S107，通过第四道构图工艺形成层间绝缘层和第一层接触孔的图形，具体包括：
步骤S1071，如图14所示，在栅金属层80上形成层间绝缘层90；
步骤S1072，如图14所示，采用刻蚀工艺对层间绝缘层90、栅金属层80刻蚀，形成第一层接触孔91的图形。
参见图15，一种优选方式中，步骤S108，第五道构图工艺形成源漏极图形和数据线图形，具体包括：
步骤S1081，在层间绝缘层90上形成源漏金属层和数据线层；
步骤S1082，如图16所示，采用光刻工艺形成源漏金属层图形101和数据线层的图形。
参见图17，步骤S109，通过第六道构图工艺形成平坦化绝缘层并形成第二层接触孔的图形，具体包括：
步骤S1091，如图18所示，在数据线层上形成平坦化绝缘层110；
步骤S1092，如图18所示，采用刻蚀工艺对平坦化绝缘层110进行刻蚀，形成第二层接触孔111的图形。
参见图19，一种优选方式中，步骤S110，通过第七道构图工艺形成公共电极的图形，以及所述源漏极和所述有源层的连接电极，具体包括：
步骤S1101，如图20所示，在平坦化绝缘层110上形成公共电极层120，公共电极层120填充于第二层接触孔111的图形，并连接有源层52和源漏金属层图形101；
步骤S1102，如图20所示，采用光刻工艺对公共电极层120进行刻蚀，形成公共电极层120的图形，和连接电极121。
在步骤S110中，在形成公共电极层120的同时形成了用于连接P型TFT的有源层52和源漏金属层图形101的连接电极121，省去了形成P型TFT源漏极图形的光刻工艺，降低了TFT阵列基板的生产成本；且由于连接电极121为透明材料，提高了TFT的开口率。
参见图1，一种优选方式中，在步骤S100，在N型TFT与P型TFT之间形成公共电极的图形，并使公共电极与P型TFT的有源层源漏极接触之后，还包括：
步骤S111，通过第八道构图工艺在所述公共电极层上形成保护层图形，参见图21，具体包括，
步骤S1111,如图22所示，在公共电极层120上形成保护层130；
步骤S1112,采用刻蚀工艺对保护层130进行刻蚀，形成保护层图形；
步骤S112，通过第九道构图工艺在保护层上形成像素电极层图形，参见图23，具体包括，
步骤S1121，如图24所示，在保护层130上形成像素电极层140；
步骤S1122，采用光刻工艺对像素电极层140进行刻蚀，形成像素电极层图形。
综上所述，该制备方法共采用九道构图工艺，与现有技术相比，省去了单独形成P型TFT有源层图形的构图工艺和单独形成P型TFT的源漏极图形的构图工艺，减少了光刻工艺次数，简化了阵列基板的制造工艺，降低了阵列基板的制造成本。
如图24所示，本发明具体实施方式还提供了一种采用上述制备方法制备的低温多晶硅TFT阵列基板，阵列基板中的P型TFT的源漏极图形的掺杂区521、522与P型TFT的源漏极通过透明的连接电极121相连接。
该低温多晶硅TFT阵列基板中，P型TFT的源漏极图形的掺杂区521、522与位于N型TFT与P型TFT之间的透明的连接电极121接触，因采用了透明的连接电极121作为P型TFT的源漏极，提高了TFT的开口率。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (9)

1.一种低温多晶硅TFT阵列基板的制备方法，其特征在于，包括：
通过第一道构图工艺在衬底基板上形成遮光层的图形；
在形成遮光层图形的衬底基板上形成非晶硅层、并对所述非晶硅层进行脱氢处理；
对所述进行脱氢处理后的非晶硅层进行结晶化处理，使所述非晶硅层转换为多晶硅层；
进行第二道构图工艺，在所述多晶硅层上形成光刻胶层，并采用灰度掩膜板进行曝光并显影，形成光刻胶完全保留区域、光刻胶半保留区域和光刻胶完全去除区域的图形；采用刻蚀工艺去除所述多晶硅层位于所述光刻胶完全去除区域的部分，形成有源层的图形；对光刻胶进行灰化处理，使位于所述光刻胶半保留区域的部分所述有源层露出并对所述部分有源层进行高浓度P型离子注入，形成P型TFT的源漏极图形的掺杂区；剥离剩余的光刻胶；
通过第三道构图工艺形成N型TFT栅极的图形和P型TFT栅极的图形；
通过第四道构图工艺形成层间绝缘层和第一层接触孔的图形；
通过第五道构图工艺形成源漏极图形和数据线图形；
通过第六道构图工艺形成平坦化绝缘层图形，并形成第二层接触孔的图形；
通过第七道构图工艺形成公共电极的图形，以及所述源漏极和所述有源层的连接电极；其中，
所述通过第三道构图工艺形成N型TFT栅极的图形和P型TFT栅极的图形具体包括：
在所述有源层上形成栅绝缘层和栅金属层，并在所述栅金属层上形成光刻胶层，通过曝光、显影形成光刻胶层图形；
采用光刻工艺，对位于所述光刻胶层图形以外的所述栅金属层进行刻蚀，形成N型TFT栅极的图形和P型TFT栅极的图形；
对位于N型TFT区域的所述有源层进行高浓度N型离子注入，形成N型TFT的有源层源漏极的图形；
对所述光刻胶层图形进行灰化，并对位于新形成的N型TFT区域的所述有源层进行低浓度N型离子注入，形成轻掺杂漏极图形。
2.根据权利要求1所述的制备方法，其特征在于，所述在形成遮光层图形的衬底基板上形成非晶硅层之前还包括，在所述形成遮光层图形的衬底基板上沉积缓冲层。
3.根据权利要求1所述的制备方法，其特征在于，采用磷化氢对位于N型TFT区域的有源层进行高浓度N型离子注入。
4.根据权利要求1所述的制备方法，其特征在于，所述通过第四道构图工艺形成层间绝缘层和第一层接触孔的图形具体包括：
在所述栅金属层上形成层间绝缘层；
采用刻蚀工艺对所述层间绝缘层和所述栅金属层刻蚀，形成第一层接触孔的图形。
5.根据权利要求1所述的制备方法，其特征在于，所述第五道构图工艺形成源漏极图形和数据线图形具体包括：
在所述层间绝缘层上形成源漏金属层和数据线层；
采用光刻工艺形成所述源漏金属层和所述数据线层的图形。
6.根据权利要求5所述的制备方法，其特征在于，所述通过第六道构图工艺形成平坦化绝缘层并形成第二层接触孔的图形具体包括：
在所述数据线层上形成平坦化绝缘层；
采用刻蚀工艺对所述平坦化绝缘层进行刻蚀，形成第二层接触孔的图形。
7.根据权利要求1所述的制备方法，其特征在于，所述通过第七道构图工艺形成公共电极的图形，以及源漏极和有源层的连接电极具体包括：
在所述平坦化绝缘层上形成公共电极层，所述公共电极层填充于所述第二层接触孔内，以连接所述源漏极和所述有源层；
采用刻蚀工艺对所述公共电极层进行刻蚀，形成所述公共电极层的图形和所述连接电极的图形。
8.根据权利要求1所述的制备方法，其特征在于，所述形成公共电极的图形，以及源漏极和有源层的连接电极之后还包括：
通过第八道构图工艺在所述公共电极层上形成保护层图形；
通过第九道构图工艺在所述保护层上形成像素电极层图形。
9.一种根据权利要求1-8任一项所述的制备方法制备的低温多晶硅TFT阵列基板，其特征在于，所述阵列基板中的P型TFT的源漏极图形的掺杂区与P型TFT的源漏极通过透明的连接电极相连接。
CN201510673823.5A 2015-10-16 2015-10-16 一种低温多晶硅tft阵列基板的制备方法及其阵列基板 Active CN105206568B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201510673823.5A CN105206568B (zh) 2015-10-16 2015-10-16 一种低温多晶硅tft阵列基板的制备方法及其阵列基板
US15/212,871 US9653496B2 (en) 2015-10-16 2016-07-18 Preparation method of poly-silicon TFT array substrate and array substrate thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510673823.5A CN105206568B (zh) 2015-10-16 2015-10-16 一种低温多晶硅tft阵列基板的制备方法及其阵列基板

Publications (2)

Publication Number Publication Date
CN105206568A CN105206568A (zh) 2015-12-30
CN105206568B true CN105206568B (zh) 2018-06-05

Family

ID=54954154

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510673823.5A Active CN105206568B (zh) 2015-10-16 2015-10-16 一种低温多晶硅tft阵列基板的制备方法及其阵列基板

Country Status (2)

Country Link
US (1) US9653496B2 (zh)
CN (1) CN105206568B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105655352B (zh) * 2016-01-14 2018-08-14 武汉华星光电技术有限公司 低温多晶硅tft阵列基板的制作方法
CN107340934B (zh) 2016-04-29 2020-10-20 瀚宇彩晶股份有限公司 电容式触控显示面板
CN107634068A (zh) * 2017-06-23 2018-01-26 深圳市华星光电半导体显示技术有限公司 阵列基板及其制备方法、显示装置
TWI630590B (zh) 2017-07-05 2018-07-21 Industrial Technology Research Institute 畫素結構以及顯示面板
US10340387B2 (en) * 2017-09-20 2019-07-02 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Low temperature poly-silicon thin film transistor, manufacturing method thereof, and array substrate
CN107895713B (zh) * 2017-11-30 2020-05-05 深圳市华星光电半导体显示技术有限公司 Tft基板制作方法
CN108288586A (zh) * 2018-01-08 2018-07-17 深圳市华星光电半导体显示技术有限公司 一种p型薄膜晶体管及其制备方法
CN108511503B (zh) * 2018-05-28 2020-11-24 京东方科技集团股份有限公司 一种电致发光显示面板、其制作方法及显示装置
CN108807549B (zh) * 2018-06-01 2021-03-23 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、阵列基板及其制造方法
WO2020154981A1 (zh) * 2019-01-30 2020-08-06 深圳市柔宇科技有限公司 阵列基板及其制造方法、显示面板
CN110047800B (zh) * 2019-04-18 2021-01-15 武汉华星光电技术有限公司 阵列基板及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543860A (zh) * 2010-12-29 2012-07-04 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制造方法
CN102683354A (zh) * 2012-03-22 2012-09-19 京东方科技集团股份有限公司 顶栅型n-tft、阵列基板及其制备方法和显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4471522A (en) * 1980-07-08 1984-09-18 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4691219A (en) * 1980-07-08 1987-09-01 International Business Machines Corporation Self-aligned polysilicon base contact structure
US4608589A (en) * 1980-07-08 1986-08-26 International Business Machines Corporation Self-aligned metal structure for integrated circuits
US4488162A (en) * 1980-07-08 1984-12-11 International Business Machines Corporation Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4758528A (en) * 1980-07-08 1988-07-19 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
US4400865A (en) * 1980-07-08 1983-08-30 International Business Machines Corporation Self-aligned metal process for integrated circuit metallization
KR100500581B1 (ko) * 2003-02-20 2005-07-18 삼성전자주식회사 반도체 장치에서 게이트 전극 형성 방법
KR100585873B1 (ko) * 2003-11-03 2006-06-07 엘지.필립스 엘시디 주식회사 폴리실리콘 액정표시소자 및 그 제조방법
KR101267499B1 (ko) * 2005-08-18 2013-05-31 삼성디스플레이 주식회사 박막 트랜지스터 기판의 제조 방법 및 그에 의해 제조된박막 트랜지스터

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543860A (zh) * 2010-12-29 2012-07-04 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制造方法
CN102683354A (zh) * 2012-03-22 2012-09-19 京东方科技集团股份有限公司 顶栅型n-tft、阵列基板及其制备方法和显示装置

Also Published As

Publication number Publication date
US20170110488A1 (en) 2017-04-20
US9653496B2 (en) 2017-05-16
CN105206568A (zh) 2015-12-30

Similar Documents

Publication Publication Date Title
CN105206568B (zh) 一种低温多晶硅tft阵列基板的制备方法及其阵列基板
CN104617102B (zh) 阵列基板及阵列基板制造方法
CN103151388B (zh) 一种多晶硅薄膜晶体管及其制备方法、阵列基板
CN105789327B (zh) 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN108538860B (zh) 顶栅型非晶硅tft基板的制作方法
CN104022126B (zh) 一种阵列基板、其制作方法及显示装置
CN109037150B (zh) 金属氧化物半导体薄膜晶体管阵列基板及其制作方法
CN103745955B (zh) 显示装置、阵列基板及其制造方法
CN104409416B (zh) 用于制作阵列基板的方法及阵列基板
CN107482066A (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
US10042211B2 (en) Liquid crystal display panel, array substrate and manufacturing method thereof
CN105118808A (zh) 一种阵列基板及其制作方法
CN104282696A (zh) 一种阵列基板及其制作方法、显示装置
CN107275340A (zh) 薄膜晶体管制备方法、阵列基板、其制备方法及显示装置
CN105304500A (zh) N型tft的制作方法
CN104576399A (zh) 一种薄膜晶体管及其制造方法
CN105097552A (zh) 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
TWI419336B (zh) 半導體元件及其製作方法
CN103985716B (zh) 薄膜晶体管阵列基板制造方法及薄膜晶体管阵列基板
US10283536B2 (en) Array substrate, method for manufacturing the same, display device and mask plate
CN104882415B (zh) Ltps阵列基板及其制造方法
US10629746B2 (en) Array substrate and manufacturing method thereof
CN103681350B (zh) 薄膜晶体管的制作方法
CN107275191B (zh) 一种薄膜晶体管及制备方法、阵列基板和显示面板
CN110504164A (zh) 薄膜晶体管及其制造方法和显示装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant