WO2020154981A1 - 阵列基板及其制造方法、显示面板 - Google Patents

阵列基板及其制造方法、显示面板 Download PDF

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Publication number
WO2020154981A1
WO2020154981A1 PCT/CN2019/074003 CN2019074003W WO2020154981A1 WO 2020154981 A1 WO2020154981 A1 WO 2020154981A1 CN 2019074003 W CN2019074003 W CN 2019074003W WO 2020154981 A1 WO2020154981 A1 WO 2020154981A1
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Prior art keywords
region
semiconductor layer
drain
source
layer
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PCT/CN2019/074003
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English (en)
French (fr)
Inventor
蔡武卫
高伟程
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深圳市柔宇科技有限公司
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Priority to CN201980073507.0A priority Critical patent/CN113261083A/zh
Priority to PCT/CN2019/074003 priority patent/WO2020154981A1/zh
Publication of WO2020154981A1 publication Critical patent/WO2020154981A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

Definitions

  • the embodiments of the present application relate to the field of display technology, and in particular to an array substrate, a manufacturing method of the array substrate, and a display panel using the array substrate.
  • the display resolution of mobile electronic products is getting higher and higher. Due to the improvement of the resolution, the current supplied to the organic light-emitting diode is reduced due to the reduction in area, in order to reduce The switching current reaches the working range of the device.
  • the device size aspect ratio (W/L) of the field effect transistor must also be reduced to meet the current demand of the organic light emitting diode. However, when the length of the field effect transistor increases, the relative design space will be affected. The impact is not conducive to the subsequent development of higher resolution.
  • low-temperature polycrystalline oxide technology is the development direction.
  • the existing low-temperature polycrystalline oxide technology uses ion implantation to define the components as N-type or P-type semiconductors.
  • the implanted dose will affect the characteristics of the device, but because it is synchronous The manufacturing process, so the implanted dose of each drain/source electrode block is the same, which limits the design size.
  • the embodiments of the present application aim to provide an array substrate, a manufacturing method thereof, and a display panel, so as to solve the technical problem of low utilization rate of layout space of the array substrate in the prior art.
  • a method for manufacturing an array substrate includes: forming a first semiconductor layer and a second semiconductor layer spaced apart on a base;
  • first semiconductor layer Two opposite sides of the first semiconductor layer are defined as a first source region and a first drain region, and the first semiconductor layer is located between the first source region and the first drain region.
  • the part is the first channel region, and the two opposite sides defining the second semiconductor layer are respectively a second source region and a second drain region.
  • the second semiconductor layer is located in the second source region and the The part between the second drain regions is the second channel region;
  • the region is doped with ions, so that the ion doping amount of the first source region, the first drain region, the second source region, and the second drain region are different.
  • the two opposite sides defining the first semiconductor layer are respectively a first source region and a first drain region, and the first semiconductor layer is located in the first source region and the first drain region.
  • the portion between the drain regions is the first channel region, and the two opposite sides defining the second semiconductor layer are the second source region and the second drain region respectively.
  • the second semiconductor layer is located in the second The portion between the source region and the second drain region is the second channel region, including:
  • a first gate corresponding to the first semiconductor and a second gate corresponding to the second semiconductor are respectively formed on the substrate, and the first gate and the second gate are both connected to the first gate.
  • the semiconductor and the second semiconductor are insulated from each other, the portion of the first semiconductor layer directly opposite to the first gate is the first channel region, and the first semiconductor layer is not covered by the first gate.
  • the two sides of the shield are defined as the first source region and the first drain region, and the portion of the second semiconductor layer directly opposite to the second gate is the second channel region, so The two sides of the second semiconductor layer that are not blocked by the second gate are respectively defined as the second source region and the second drain region.
  • the shielding the second source region and the second drain region includes:
  • a first shielding layer for shielding the second source region and a second shielding layer for shielding the second drain region are respectively formed on both sides of the second gate.
  • the respectively forming a first gate corresponding to the first semiconductor and a second gate corresponding to the first semiconductor on the substrate includes:
  • An insulating layer is formed on the first semiconductor layer, the second semiconductor layer, and the substrate, and the insulating layer makes the first gate and the second gate connect to the first semiconductor and the substrate.
  • the second semiconductors are insulated from each other, and both the first shielding layer and the second shielding layer are formed on the insulating layer.
  • the method further includes:
  • a first transistor corresponding to the first source region, the first drain region, the second source region, and the second drain region in sequence is formed on the insulating layer.
  • a first source, a first drain, a second source, and a second drain are respectively formed on the insulating layer, and the first source is electrically connected to the first source region through the first via hole.
  • the first drain is electrically connected to the first drain region through the second via hole
  • the second source is electrically connected to the second source region through the third via hole
  • the second drain is electrically connected to the second drain region through the fourth via hole.
  • the shielding the second source region and the second drain region includes:
  • the insulating layer Partially etch the insulating layer to form a first insulating layer and a second insulating layer, the first insulating layer shields the first semiconductor layer, and the second insulating layer shields the second semiconductor layer, The thickness of the second insulating layer is greater than the thickness of the first insulating layer.
  • the method includes:
  • a first gate facing the first channel region is formed on the first insulating layer, and a second gate facing the second channel region is formed on the second insulating layer, the Neither the first source region nor the first drain region is blocked by the first gate, and neither the second source region nor the second drain region is blocked by the second gate.
  • the step of simultaneously performing ion doping on the first source region, the first drain region, the second source region, and the second drain region occurs when the After the steps of the first grid and the second grid.
  • the method further includes:
  • a first via hole and a second via hole respectively corresponding to the first source region and the first drain region are formed on the first insulating layer, and a first via hole and a second via hole are formed on the second insulating layer respectively.
  • a first source, a first drain, a second source, and a second drain are respectively formed on the insulating layer, and the first source is electrically connected to the first source region through the first via hole.
  • the first drain is electrically connected to the first drain region through the second via hole
  • the second source is electrically connected to the second source region through the third via hole
  • the second drain is electrically connected to the second drain region through the fourth via hole.
  • the two opposite sides defining the first semiconductor layer are respectively a first source region and a first drain region, and the first semiconductor layer is located in the first source region and the first drain region.
  • the portion between the drain regions is the first channel region, and the two opposite sides defining the second semiconductor layer are the second source region and the second drain region respectively.
  • the second semiconductor layer is located in the second The portion between the source region and the second drain region is the second channel region, including:
  • a first barrier layer and a second barrier layer are respectively formed directly above the first semiconductor layer and the second semiconductor layer, the first barrier layer has a uniform thickness structure, and the second barrier layer has an intermediate thickness. Thin structure on both sides;
  • the area where the first semiconductor layer and the first barrier layer are directly opposite is defined as the first channel region, and the two sides of the first semiconductor layer that are not blocked by the first barrier layer are defined as the The first source region and the first drain region, the region where the second semiconductor layer and the thick part of the second barrier layer are directly opposite are defined as the second channel region, and the first The portions of the second semiconductor layer and the two sides of the second barrier layer that are opposite to each other with a thin thickness are defined as the second source region and the second drain region, respectively.
  • the simultaneous ion doping of the first source region, the first drain region, the second source region, and the second drain region includes:
  • a first gate corresponding to the first channel region and a second gate corresponding to the second channel region are formed on the insulating layer.
  • the method further includes:
  • a first via hole, a second via hole corresponding to the first source region, the first drain region, the second source region, and the second drain region are formed on the insulating layer. Vias, third vias and fourth vias;
  • a first source, a first drain, a second source, and a second drain are respectively formed on the insulating layer, and the first source is electrically connected to the first source region through the first via hole.
  • the first drain is electrically connected to the first drain region through the second via hole
  • the second source is electrically connected to the second source region through the third via hole
  • the second drain is electrically connected to the second drain region through the fourth via hole.
  • the ion doping is P-type ion doping, and the P-type ion is boron.
  • the ion doping is N-type ion doping
  • the N-type ion is one or a combination of boron, arsenic, antimony, and bismuth.
  • An array substrate including: a first field effect transistor, including a first gate electrode and a first semiconductor layer insulated from each other, the first semiconductor layer including first source regions located on two opposite sides of the first semiconductor layer , A first drain region and a first channel region located between the first source region and the first drain region, and the first gate is arranged directly opposite to the first channel region;
  • the second field effect transistor is arranged spaced apart from the first field effect transistor.
  • the second field effect transistor includes a second gate and a second semiconductor layer that are insulated from each other.
  • the second semiconductor layer includes The second source region, the second drain region, and the second channel region located between the second source region and the second drain region on two opposite sides of the semiconductor layer, the second gate electrode is positive Provided to the second channel region;
  • the ion doping amount of the first source region and the first drain region are different from the ion doping amount of the second source region and the second drain region.
  • the first field effect transistor further includes a first source and a first drain, the first source is electrically connected to the first source region, and the first drain is connected to the first drain.
  • a drain region is electrically connected;
  • the second field effect transistor further includes a second source and a second drain, the second source is electrically connected to the second source region, and the second drain is The second drain region is electrically connected.
  • the array substrate further includes a base and an insulating layer
  • the first field effect transistor and the second field effect transistor share a common substrate and insulating layer, and the substrate serves as a substrate for carrying the first field effect transistor and the second field effect transistor.
  • the layer is located between the first gate, the second gate, the first semiconductor layer, and the second semiconductor layer, so that the first gate and the first semiconductor layer are insulated from each other, And the second gate and the second semiconductor layer are insulated from each other.
  • the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer is located between the first gate and the first semiconductor layer, and the second insulating layer is located on the Between the second gate and the second semiconductor layer, the thickness of the second insulating layer is greater than the thickness of the first insulating layer.
  • a display panel includes: the above-mentioned array substrate.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by one of the embodiments of the present application.
  • FIG. 2 is a schematic structural diagram of an array substrate provided by another embodiment of the present application.
  • FIG. 3 is a flowchart of a manufacturing method of an array substrate provided by one of the embodiments of the present application.
  • 4a to 4f are schematic diagrams of preparation at different stages of the manufacturing method of the array substrate shown in FIG. 3;
  • FIG. 5 is a flowchart of a manufacturing method of an array substrate provided by another embodiment of the present application.
  • 6a to 6e are schematic diagrams of preparation at different stages of the manufacturing method of the array substrate shown in FIG. 5;
  • FIG. 7 is a flowchart of a manufacturing method of an array substrate provided by still another embodiment of the present application.
  • 8a to 8e are schematic diagrams of the manufacturing method of the array substrate shown in FIG. 7 at different stages.
  • the array substrate 100 provided by one embodiment of the present application includes: a first field effect transistor 10 and a second field effect transistor 20, the first field effect transistor 10 and the second field effect transistor 20 are spaced apart It is provided that the first field effect transistor 10 and the second field effect transistor 20 are manufactured simultaneously by the same process.
  • the first field effect transistor 10 and the second field effect transistor 20 share a common substrate 2 and an insulating layer 4.
  • the base 2 serves as a substrate for carrying the first field effect transistor 10 and the second field effect transistor 20, and the insulating layer 4 is formed on the base 2.
  • a flexible substrate, a buffer layer, and the insulating layer 4 are sequentially formed on the base 2.
  • the first field effect transistor 10 includes a first semiconductor layer 12; the second field effect transistor 20 includes a second semiconductor layer 22, and the first semiconductor layer 12 and the second semiconductor layer 22 are located on the substrate 2 and the substrate. Between the insulating layers 4, and the first semiconductor layer 12 and the second semiconductor layer 22 are separated by a predetermined distance. In this embodiment, both the first semiconductor layer 12 and the second semiconductor layer 22 are It is a polysilicon layer. In some embodiments, the first semiconductor layer 12 and the second semiconductor layer 22 may also be other semiconductor materials.
  • the first semiconductor layer 12 includes a first source region 122 located on two opposite sides of the first semiconductor layer 12, a first drain region 124, and a first source region 122 and a first drain region.
  • the first channel region 126 between the regions 124.
  • the second semiconductor layer 22 includes a second source region 222 located on opposite sides of the second semiconductor layer 22, a second drain region 224, and a second source region 222 and the second drain region.
  • the first source region 122, the first drain region 124, the second source region 222, and the second drain region 224 are ion-doped at the same time, but the first source region 122 , The first drain region 124, the second source region 222, and the second drain region 224 have different ion doping amounts, so that the first semiconductor layer 12 and the second semiconductor layer 12
  • the electrical properties of 22 are different, so the first field effect transistor 10 and the second field effect transistor 20 have different device characteristics.
  • the electrical properties of the first semiconductor layer 12 and the second semiconductor layer 22 include the type of semiconductor layer, carrier concentration, and Hall carrier migration.
  • the first field-effect transistor 10 further includes a first gate 14 formed on the insulating layer 4, and the first gate 14 is located in the first channel region 126 Directly above.
  • the second field effect transistor 20 further includes a second gate 24, the second gate 24 is formed on the insulating layer 4, and the second gate 24 is located in the second channel region 226 Directly above.
  • the insulating layer 4 is located between the first gate 14, the second gate 24, the first semiconductor layer 12, the second semiconductor layer 22, so that the first gate 14 and The first semiconductor layer 12 is insulated from each other, and the second gate 22 and the second semiconductor layer 22 are insulated from each other.
  • the first field effect transistor 10 also includes a first source and a first drain, the first source is electrically connected to the first source region, and the first drain is connected to the first drain. Area electrical connection.
  • the second field effect transistor 20 also includes a second source and a second drain, the second source is electrically connected to the second source region, and the second drain is connected to the second drain. Area electrical connection.
  • the first source region 122, the first drain region 124, the second source region 222, and the second drain region 224 in the above-mentioned array substrate 100 have different ion doping amounts.
  • the electrical properties of the first semiconductor layer 12 and the second semiconductor layer 22 are different, so the first field effect transistor 10 and the second field effect transistor 20 have different device characteristics, and they are in an array Field-effect transistor devices with different device characteristics are obtained on the substrate 100 without adjusting the size of the field-effect transistor, which improves the utilization rate of the layout space and is beneficial to the development of the display screen in the direction of higher resolution.
  • the substrate 2 is made of transparent materials such as glass and has been pre-cleaned. In some embodiments, due to the relatively high content of metal impurities such as aluminum, barium, and sodium in the traditional alkali glass, the diffusion of metal impurities is likely to occur in the high-temperature treatment process, so the substrate 2 can also be made of alkali-free glass.
  • the substrate 2 can also be made of flexible materials. In some embodiments, when a flexible substrate and a buffer layer are sequentially formed between the base 2 and the insulating layer 4, the flexible substrate is a substrate for supporting and protecting various elements that can be formed thereon. When necessary, the flexible substrate can be peeled off from the base 2.
  • the flexible substrate may be formed of various materials.
  • the flexible substrate when the field effect transistor is used in a flexible application such as a flexible display device, the flexible substrate may be formed of a flexible insulating material.
  • flexible insulating materials may include polyimide (PI), polyetherimide (PEI), polyethylene terephthalate (PES), polycarbonate (PC), polystyrene (PS) , Styrene-acrylonitrile copolymer, and silicone acrylic resin.
  • PI polyimide
  • PEI polyetherimide
  • PES polyethylene terephthalate
  • PC polycarbonate
  • PS polystyrene
  • Styrene-acrylonitrile copolymer silicone acrylic resin.
  • the flexible substrate when the field effect transistor is used in an application with high transmittance, such as a transparent display device, the flexible substrate may be formed of a flexible transparent insulating material.
  • the buffer layer is located between the flexible substrate and the insulating layer 4, and is used to prevent the impurities contained in the flexible substrate from diffusing into the semiconductor layer of the field effect transistor, so as to prevent the device performance of the field effect transistor from being affected.
  • the buffer layer can enhance the adhesion between the semiconductor layer and the flexible substrate, increase the firmness of the contact between the semiconductor layer and the flexible substrate, thereby preventing the semiconductor layer from falling off, and improving the stability of the field effect transistor.
  • the material of the buffer layer is an insulating material, such as SiOx, SiNx or any combination of the two.
  • the insulating layer 4 uses nitrogen oxide (N 2 O) and monosilane (SiH 4 ) as reaction source gases, and a series of hydrogenated amorphous silicon nitride ( a-SiNx: H) film, the silicon nitride film has excellent insulation and withstand voltage performance and better interface characteristics.
  • a-SiNx: H hydrogenated amorphous silicon nitride
  • the thickness of the insulating layer 4 is 100-400 nm. Because of its good interface characteristics, the prepared semiconductor device has a smaller leakage current, which improves the electrical performance of the device.
  • the insulating layer 4 may also adopt a single-layer silicon dioxide (SiO 2 ) or double-layer silicon dioxide/silicon nitride (SiO 2 /SiNx) structure.
  • the materials of the first gate 14 and the second gate 24 can be selected from metals such as Al, Ti, Mo, Cu, Ni, ITO, metal layers of mixtures, or metal oxides.
  • the first gate 14 and the second gate 24 may have a multilayer structure.
  • the multilayer electrode includes a metal layer having Al, Ti, Mo, Cu, Ni, ITO or a mixture thereof, and a transparent conductive oxide layer including a transparent conductive oxide material.
  • the transparent conductive oxide material may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ISZO), and the like.
  • the multilayer electrode may have a three-layer structure configured to include a first transparent conductive oxide layer, a metal layer, and a second transparent conductive oxide layer.
  • the multilayer electrode may also have a two-layer structure configured to include a transparent conductive oxide layer and a metal layer.
  • the array substrate 100a provided by some embodiments of the present application is basically the same as the array substrate 100 shown in FIG. 1, except that the array substrate 100a includes a first insulating layer 42 and a second insulating layer 44.
  • the first insulating layer 42 and the second insulating layer 44 replace the insulating layer 4 in the array substrate 100, and the thickness of the second insulating layer 44 is greater than the thickness of the first insulating layer 42.
  • the first semiconductor layer 12 is located between the substrate 2 and the first insulating layer 42
  • the second semiconductor layer 22 is located between the substrate 2 and the second insulating layer 44
  • the first The gate 14 and the second gate 24 are respectively formed on the first insulating layer 42 and the second insulating layer 44, and are respectively located directly above the first semiconductor layer 12 and the second semiconductor layer 22 .
  • the first insulating layer 42 is located between the first gate 14 and the first semiconductor layer 12
  • the second insulating layer 44 is located between the second gate 24 and the second semiconductor layer 22 between.
  • the first insulating layer 42 and the second insulating layer 44 are simultaneously formed of the same material.
  • the materials of the first insulating layer 42 and the second insulating layer 44 are the same as the material of the insulating layer 4 in the embodiment shown in FIG. 1, and will not be repeated here.
  • the present invention also provides a manufacturing method (not shown) of the array substrate, which at least includes the following steps:
  • first semiconductor layer Two opposite sides of the first semiconductor layer are defined as a first source region and a first drain region, and the first semiconductor layer is located between the first source region and the first drain region.
  • the part is the first channel region, and the two opposite sides defining the second semiconductor layer are respectively a second source region and a second drain region.
  • the second semiconductor layer is located in the second source region and the The part between the second drain regions is the second channel region;
  • the region is doped with ions, so that the ion doping amount of the first source region, the first drain region, the second source region, and the second drain region are different.
  • FIG. 3 and FIG. 4 Please refer to FIG. 3 and FIG. 4 together.
  • One of the embodiments of the present application provides a method for manufacturing an array substrate. It should be noted that the above explanation of the embodiments of the array substrate is also applicable to the array substrate of this embodiment. The preparation method, in order to avoid redundancy, will not be detailed here.
  • the manufacturing method of the array substrate includes:
  • Step S31 forming a semiconductor layer on the substrate.
  • Step S32 Perform a patterning process on the semiconductor layer to form a first semiconductor layer 12 and a second semiconductor layer 22, and the first semiconductor layer 12 and the second semiconductor layer 22 are separated by a predetermined distance.
  • the patterning process may include only a photolithography process, or a photolithography process and an etching step, and may also include printing, inkjet, and other processes for forming predetermined patterns;
  • photolithography Process refers to the process of forming patterns by using photoresist, mask, exposure machine, etc., including film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present invention.
  • a layer of photoresist is formed on the semiconductor layer, the photoresist is exposed and developed, and then the semiconductor layer is dry-etched to form the first semiconductor layer 12 and The second semiconductor layer 22.
  • Step S33 forming an insulating layer on the first semiconductor layer 12, the second semiconductor layer 22 and the substrate 2.
  • an enhanced chemical vapor deposition (PECVD) method may be used to deposit the first semiconductor layer 12, the second semiconductor layer 22, and the substrate 2 after step S32 to a thickness of about
  • the insulating layer 4 can be made of oxide, nitride or oxynitride, and the insulating layer 4 can be a single-layer, double-layer or multilayer structure. Specifically, the insulating layer 4 may be SiNx, SiOx or Si(ON)x.
  • Step S34 forming a first gate corresponding to the first semiconductor layer and a second gate corresponding to the second semiconductor layer on the insulating layer, the first gate and the second gate Both are insulated from the first semiconductor layer and the second semiconductor layer, the portion of the first semiconductor layer directly opposite to the first gate is the first channel region, and the first semiconductor layer
  • the two sides that are not blocked by the first gate are defined as the first source region and the first drain region, and the portion of the second semiconductor layer directly opposite to the second gate is In the second channel region, two sides of the second semiconductor layer not blocked by the second gate are defined as the second source region and the second drain region, respectively.
  • magnetron sputtering, thermal evaporation or other film forming methods can be used to deposit a layer with a thickness of about
  • For the gate metal layer coat a layer of photoresist on the gate metal layer, and use a mask to expose and develop the photoresist, so that the photoresist forms a photoresist non-reserved area and a photoresist reserved area;
  • the etching process etches away the gate metal layer in the region where the photoresist is not reserved, and strips the remaining photoresist to form the first gate 14 and the second gate 24.
  • Step S35 forming a first shielding layer for shielding the second source region and a second shielding layer for shielding the second drain region on both sides of the second gate.
  • a layer of photoresist is coated on the insulating layer 4, the first gate 14 and the second gate 24 after step S34, and a mask is used to expose the photoresist.
  • Development to make the photoresist form a photoresist non-reserved area and a photoresist reserved area; the photoresist reserved area is above the second source region 222 and the second drain region 224, the photolithography
  • the non-retained area is another area.
  • the photoresist in the non-retained area is photoetched by a photolithography process, and the first shielding layer 23 and the second shielding layer 25 are formed in the reserved area of the photoresist.
  • Step S36 Perform ion doping on the first source region, the first drain region, the second source region, and the second drain region at the same time.
  • the first drain region is a heavily doped region
  • the second source region and the second drain region are lightly doped regions.
  • the ion doping is P-type ion doping
  • the P-type ion is boron (B). Because the ion radius of the P-type ions is small, the P-type ions can respectively pass through the The first insulating layer 4, the first shielding layer 23, and the second shielding layer 25 simultaneously realize the protection of the first source region 122, the first drain region 124, the second source region 222, and the The second drain region 224 is doped with P-type ions.
  • the P-type ions pass through all the The first shielding layer 23 and the second shielding layer 25 perform ion doping on the second source region 222 and the second drain region 224, so the first source region 122 and the first drain region 124.
  • P-type ion doping amounts of the second source region 222 and the second drain region 224 are different, and the first source region 122 and the first drain region 124 are heavily doped Impurity regions, the second source region 222 and the second drain region 224 are lightly doped regions, and because the difference in ion doping amount will affect the first semiconductor layer 12 and the second semiconductor layer 22 Electrical properties, so the electrical properties of the first semiconductor layer 12 and the second semiconductor layer 22 are also different.
  • Step S37 Peel off the first shielding layer and the second shielding layer.
  • the photoresist of the first shielding layer and the second shielding layer is stripped.
  • the manufacturing method of the array substrate further includes: forming on the insulating layer sequentially and separately with the first source region, the first drain region, and the second source region. Region, the first via hole, the second via hole, the third via hole and the fourth via hole corresponding to the second drain region;
  • a first source, a first drain, a second source, and a second drain are respectively formed on the insulating layer, and the first source is electrically connected to the first source region through the first via hole.
  • the first drain is electrically connected to the first drain region through the second via hole
  • the second source is electrically connected to the second source region through the third via hole
  • the second drain is electrically connected to the second drain region through the fourth via hole.
  • a photolithography process is used to form a mask layer above the insulating layer 4, and dry etching is used to form the first via hole, the second via hole, the third via hole, and the fourth via hole.
  • Dry etching can use plasma etching, reactive ion etching, inductively coupled plasma etching, etc.
  • the etching gas can be gas containing fluorine and chlorine, such as CF 4 , CHF 3 , SF 6 , CC1 2 Gas such as F 2 or a mixed gas formed by the above gas and O 2 .
  • Another embodiment of the present application provides a method for manufacturing an array substrate. It should be noted that the above explanation of the embodiment of the array substrate is also applicable to the method for manufacturing the array substrate of this embodiment. To avoid redundancy, here is Do not expand in detail.
  • the manufacturing method of the array substrate includes:
  • Step S51 forming a semiconductor layer on the substrate.
  • Step S52 processing the semiconductor layer to form a first semiconductor layer and a second semiconductor layer.
  • step S52 patterning the semiconductor layer to form a first semiconductor layer 12 and a second semiconductor layer 22, the first semiconductor layer 12 and the second semiconductor layer 22 are separated by a predetermined distance .
  • Step S53 forming a first barrier layer 17 and a second barrier layer 27 directly above the first semiconductor layer 12 and the second semiconductor layer 22, respectively, the first barrier layer 17 has a uniform thickness structure, and the The second barrier layer 27 has a structure with a thick middle thickness and a thin thickness on both sides.
  • the area directly opposite to the first semiconductor layer 12 and the first barrier layer 17 is defined as the first channel region 126, and the two sides of the first semiconductor layer 12 that are not blocked by the first barrier layer 17 Defined as the first source region 122 and the first drain region 124, respectively, and the area directly opposite to the middle thick portion of the second semiconductor layer 22 and the second barrier layer 27 is defined as the The second channel region 226, the portions of the second semiconductor layer 22 and the second barrier layer 27 opposite to each other with a thin thickness are respectively defined as the second source region 222 and the second drain ⁇ 224.
  • a layer of photoresist is coated on the first semiconductor layer 12, the second semiconductor layer 22, and the substrate 2 after step S52, and a mask is used to expose the photoresist , Developing to make the photoresist form a photoresist non-reserved area and a photoresist reserved area; the photoresist reserved area is the middle of the first semiconductor layer 12 and the second semiconductor layer 22, the photoresist The areas where the resist is not reserved are other areas.
  • the photoresist in the areas where the photoresist is not reserved is photoetched by a photolithography process, and the first barrier layer 17 and the second barrier layer 27 are formed in the photoresist reserved area. When ion doping is performed, the first barrier layer 17 and the second barrier layer 27 are used to prevent ions from doping the middle of the first semiconductor layer 12 and the second semiconductor layer 22.
  • Step S54 Perform ion doping on the first source region 122, the first drain region 124, the second source region 222, and the second drain region 224 simultaneously, and the first source
  • the pole region 122 and the first drain region 124 are heavily doped regions
  • the second source region 222 and the second drain region 224 are lightly doped regions.
  • the ion doping may be P-type ion doping or N-type ion doping, the P-type ion is B, and the N-type ion is P, As, Sb. A combination of one or more of, Bi.
  • the p-type ions pass through the first A barrier layer 17 and a second barrier layer 27 ion-doped the second source region 222 and the second drain region 224, so the first source region 122, the first drain region 124,
  • the doping amounts of P-type ions in the second source region 222 and the second drain region 224 are different, and the first source region 122 and the first drain region 124 are heavily doped Region, the second source region 222 and the second drain region 224 are lightly doped regions, and the electrical properties of the first semiconductor layer 12 and the second semiconductor layer 22 are affected by the difference in doping amount Therefore, the electrical properties of the first semiconductor layer 12 and the second semiconductor layer 22 are also different.
  • Step S55 Remove the first barrier layer 17 and the second barrier layer 27.
  • Step S56 forming an insulating layer 4 on the first semiconductor layer 12, the second semiconductor layer 22 and the substrate 2.
  • an enhanced chemical vapor deposition (PECVD) method may be used to deposit the first semiconductor layer 12, the second semiconductor layer 22, and the substrate 2 after step S32 to a thickness of about
  • the insulating layer 4 can be made of oxide, nitride or oxynitride, and the insulating layer 4 can be a single-layer, double-layer or multilayer structure. Specifically, the insulating layer 4 may be SiNx, SiOx or Si(ON)x.
  • Step S57 forming a first gate 14 corresponding to the first channel region 126 and a second gate 24 corresponding to the second channel region 226 on the insulating layer 4.
  • magnetron sputtering, thermal evaporation or other film forming methods may be used to deposit a layer with a thickness of about
  • For the gate metal layer coat a layer of photoresist on the gate metal layer, and use a mask to expose and develop the photoresist, so that the photoresist forms a photoresist non-reserved area and a photoresist reserved area;
  • the etching process etches away the gate metal layer in the region where the photoresist is not reserved, and strips the remaining photoresist to form the first gate 14 and the second gate 24.
  • the manufacturing method of the array substrate further includes: forming on the insulating layer 4 sequentially and respectively with the first source region 122, the first drain region 124, and the second The second source region 222, the first via hole, the second via hole, the third via hole and the fourth via hole corresponding to the second drain region 224.
  • a first source, a first drain, a second source, and a second drain are respectively formed on the insulating layer 4, and the first source passes through the first via hole and the first source region 122 is electrically connected, the first drain is electrically connected to the first drain region 124 through the second via hole, and the second source is electrically connected to the second source region through the third via hole. 222 is electrically connected, and the second drain is electrically connected to the second drain region 224 through the fourth via.
  • a photolithography process is used to form a mask layer above the insulating layer 4, and dry etching is used to form a first via, a second via, a third via, and a fourth via.
  • Dry etching can use plasma etching, reactive ion etching, inductively coupled plasma etching, etc.
  • the etching gas can be gas containing fluorine and chlorine, such as CF 4 , CHF 3 , SF 6 , CC1 2 Gas such as F 2 or a mixed gas formed by the above gas and O 2 .
  • FIGS. 7 and 8 Another embodiment of the present application provides a method for manufacturing an array substrate. It should be noted that the above explanation of the embodiment of the array substrate is also applicable to the array substrate of this embodiment. The preparation method, in order to avoid redundancy, will not be detailed here
  • the manufacturing method of the array substrate includes:
  • Step S71 forming a semiconductor layer on the substrate 2.
  • Step S72 Perform a patterning process on the semiconductor layer to form a first semiconductor layer 12 and a second semiconductor layer 22, and the first semiconductor layer 12 and the second semiconductor layer 22 are separated by a predetermined distance.
  • the two opposite sides of the first semiconductor layer 12 are defined as a first source region 122 and a first drain region 124, respectively, and the first semiconductor layer 12 is located in the first source region 122 and the first drain region.
  • the portion between the electrode regions 124 is the first channel region, and the two opposite sides of the second semiconductor layer 22 are defined as the second source region 222 and the second drain region 224 respectively.
  • the second semiconductor layer 22 is located The portion between the second source region 222 and the second drain region 224 is a second channel region.
  • the patterning treatment may include only a photolithography process, or a photolithography process and an etching step, and may also include printing, inkjet, and other processes for forming predetermined patterns;
  • photolithography Process refers to the process of forming patterns by using photoresist, mask, exposure machine, etc., including film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed in the embodiment of the present invention.
  • Step S73 forming an insulating layer on the first semiconductor layer 12, the second semiconductor layer 22 and the substrate 2.
  • an enhanced chemical vapor deposition (PECVD) method may be used to deposit the first semiconductor layer 12, the second semiconductor layer 22, and the substrate 2 after step S32 to a thickness of about
  • the insulating layer 4 can be made of oxide, nitride or oxynitride, and the insulating layer 4 can be a single-layer, double-layer or multilayer structure. Specifically, the insulating layer 4 may be SiNx, SiOx or Si(ON)x.
  • Step S74 Partially etch the insulating layer 4 to form a first insulating layer 42 and a second insulating layer 44, the first insulating layer 42 shields the first semiconductor layer 12, and the second insulating layer 44 shields the second semiconductor layer 22, and the thickness of the second insulating layer 44 is greater than the thickness of the first insulating layer 42.
  • a layer of photoresist is coated on the insulating layer 4 after step S73, and a mask is used to expose and develop the photoresist, so that the photoresist is not retained.
  • Area and photoresist reserved area; the photoresist unreserved area is a half area of the insulating layer 4, and the photoresist reserved area is the other half area of the insulating layer 4, which is etched by an etching process
  • the insulating layer of a certain thickness in the area where the photoresist is not reserved is removed, and the remaining photoresist is stripped to form the first insulating layer 42 and the second insulating layer 44. It can be understood that the first insulating layer 42 It is different from the thickness of the second insulating layer 44.
  • Step S75 forming a first gate 14 on the first insulating layer 42 facing the first channel region 126, and forming on the second insulating layer 44 facing the second channel region 226
  • the second gate 24, the first source region 122 and the first drain region 124 are not blocked by the first gate 14, the second source region 222 and the second drain None of the pole regions 224 is blocked by the second gate 24.
  • magnetron sputtering, thermal evaporation or other film forming methods can be used to deposit a layer with a thickness of about
  • For the gate metal layer coat a layer of photoresist on the gate metal layer, and use a mask to expose and develop the photoresist, so that the photoresist forms a photoresist non-reserved area and a photoresist reserved area;
  • the etching process etches away the gate metal layer in the region where the photoresist is not reserved, and strips the remaining photoresist to form the first gate 14 and the second gate 24.
  • Step S76 Perform ion doping on the first source region 122, the first drain region 124, the second source region 222, and the second drain region 224 at the same time, and the first source
  • the pole region 122 and the first drain region 124 are heavily doped regions
  • the second source region 222 and the second drain region 224 are lightly doped regions.
  • the ion doping is P-type ion doping
  • the P-type ion is boron (B). Because the ion radius of P-type ions is small, the P-type ions can pass through the The first insulating layer 42 and the second insulating layer 44 simultaneously realize the protection of the first source region 122, the first drain region 124, the second source region 222, and the second drain region 224. P-type ion doping.
  • the thicknesses of the first insulating layer 42 and the second insulating layer 44 are different, and the thickness of the second insulating layer 44 is greater than the thickness of the first insulating layer 44, so the P-type ions are respectively Through the first insulating layer 42 and the second insulating layer 44, the ion doping amount of the first source region 122, the first drain region 124 and the second source region 222 and the The ion doping amount of the second drain region 224 is different, the first source region 122 and the first drain region 124 are heavily doped regions, and the second source region 222 and the The second drain region 224 is a lightly doped region, and because the difference in ion doping will affect the electrical properties of the first semiconductor layer 12 and the second semiconductor layer 22, the first semiconductor layer 12 and the second semiconductor layer 22 The electrical properties of the semiconductor layer 22 are also different.
  • the manufacturing method of the array substrate further includes: forming on the first insulating layer 42 the first source region 122 and the first drain region 124 respectively.
  • a via hole and a second via hole, and a third via hole and a fourth via hole respectively corresponding to the second source region 222 and the second drain region 224 are formed on the second insulating layer 44 .
  • a first source, a first drain, a second source, and a second drain are respectively formed on the first insulating layer 42 and the second insulating layer 44, and the first source passes through the first
  • the via hole is electrically connected to the first source region
  • the first drain electrode is electrically connected to the first drain region through the second via hole
  • the second source electrode is electrically connected through the third via hole
  • the second drain is electrically connected to the second source region
  • the second drain is electrically connected to the second drain region through the fourth via hole.
  • the amount may be The first channel region 126 and the second channel region 226 are not shielded or are shielded to the same degree, that is, the first channel region 126 and the second channel region 226 are also the same.
  • ion doping is performed. Since neither the first channel region 126 and the second channel region 226 are blocked or blocked to the same degree, the amount of doping is the same and will not affect the first field The electrical performance of the effect transistor 10 and the second field effect transistor 20 are different.
  • the display panel includes the array substrate 100/100a in any one of the above embodiments, the array substrate is used for driving to realize the display function of the display device, and the protective layer covers the display panel for protection.
  • the array substrate further includes a plurality of data lines arranged in parallel and a plurality of scan lines arranged in parallel. The data lines and the scan lines are perpendicular to and insulated from each other, and two adjacent data lines and two adjacent scan lines define In one pixel unit, a plurality of pixel units are arranged in a matrix, and each pixel unit has the first field effect transistor 10 and the second field effect transistor 20 formed therein.
  • both the base 2 and the protective layer are made of flexible materials, or the base is used as a rigid carrier, and a flexible substrate is formed on the base and then formed on the flexible substrate.
  • Electronic components such as field effect transistors, data lines, and scan lines are then peeled off the rigid base from the flexible substrate.
  • the display device can implement various application functions by providing a bending sensor and using bending parameters detected by the bending sensor, thereby greatly improving the user experience.
  • an array substrate 100 or 100a is provided in the display panel of the display device of the present application, and the first source region, the first drain region, and the second source region are Perform ion doping at the same time as the second drain region, but the first source region, the first drain region, the second source region, and the second drain region have different ion doping amounts , which in turn makes the electrical properties of the first semiconductor layer and the second semiconductor layer different. Therefore, the first field effect transistor 10 and the second field effect transistor 20 have different device characteristics. Field effect transistor devices with different device characteristics are obtained on the substrate 100 or 100a, and the size of the field effect transistor does not need to be adjusted, which improves the utilization rate of the layout space and facilitates the development of the display screen in the direction of higher resolution.

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Abstract

一种阵列基板及其制造方法、显示面板，其中阵列基板的制造方法包括：定义第一半导体层(12)的两相对侧分别为第一源极区(122)和第一漏极区(124)，定义所述第二半导体层(22)的两相对侧分别为第二源极区(222)和第二漏极区(224)；遮挡所述第二源极区(222)和所述第二漏极区(224)，并同时对所述第一源极区(122)、所述第一漏极区(124)、所述第二源极区(222)和所述第二漏极区(224)进行离子掺杂,使得所述第一半导体层(12)和所述第二半导体层(22)的电学性能不同，因此同时在一种阵列基板上得到具有不同器件特性的场效应晶体管，提高了布局空间的使用率。

Description

阵列基板及其制造方法、显示面板 技术领域
本申请实施例涉及显示技术领域，尤其涉及一种阵列基板、阵列基板的制造方法以及使用该阵列基板的显示面板。
背景技术
随着有源矩阵有机发光二极体工艺技术提升,可移动电子产品的显示屏解析度越做越高,由于解析度提高,供给有机发光二极管的电流因面积减小而减小,为了能降低开关电流,达到器件的工作范围,场效应晶体管的器件尺寸宽长比(W/L)也必须降低，才能满足有机发光二极管的需求电流，但当场效应晶体管的的长度增加,相对设计空间会受到影响,不利于后续往更高解析度发展。
目前以低温多晶氧化物技术为开发方向，现有低温多晶氧化物工艺利用离子柨植去定义元件为N型或P型半导体,植入的剂量会影响到器件的特性,然而由于是同步的制程工艺,因此每个漏/源电极区块所植入的剂量是相同的,限缩了设计尺寸。
发明内容
本申请实施例旨在提供一种阵列基板及其制造方法、显示面板，以解决现有技术中阵列基板的布局空间使用率不高的技术问题。
本申请实施例解决其技术问题提供以下技术方案：
一种阵列基板的制造方法，包括：在基底上形成间隔设置的第一半导体层和第二半导体层；
定义所述第一半导体层的两相对侧分别为第一源极区和第一漏极区、所述第一半导体层位于所述第一源极区和所述第一漏极区之间的部分为第一沟道区，定义所述第二半导体层的两相对侧分别为第二源极区和第二漏极区、所述第二半导体层位于所述第二源极区和所述第二漏极区之间的部分为第二沟道区；
遮挡所述第二源极区和所述第二漏极区，并同时对所述第一源极区、所述第一漏极区、所述第二源极区和所述第二漏极区进行离子掺杂,使所述第一源极区、所述第一漏极区与所述第二源极区、所述二漏极区的离子掺杂量不同。
可选地，所述定义所述第一半导体层的两相对侧分别为第一源极区和第一漏极区、所述第一半导体层位于所述第一源极区和所述第一漏极区之间的部分为第一沟道区，定义所述第二半导体层的两相对侧分别为第二源极区和第二漏极区、所述第二半导体层位于所述第二源极区和所述第二漏极区之间的部分为第二沟道区，包括：
在所述基底上分别形成对应所述第一半导体的第一栅极和对应所述第二半导体的第二栅极，所述第一栅极、所述第二栅极均与所述第一半导体、所述第二半导体相互绝缘，所述第一半导体层与所述第一栅极正对的部分为所述第一沟道区，所述第一半导体层未被所述第一栅极遮挡的两侧分别定义为所述第一源极区和所述第一漏极区，所述第二半导体层与所述第二栅极正对的部分为所述第二沟道区，所述第二半导体层未被所述第二栅极遮挡的两侧分别定义为所述第二源极区和所述第二漏极区。
可选地，所述遮挡所述第二源极区和所述第二漏极区，包括：
在所述第二栅极两侧分别形成遮挡所述第二源极区的第一遮挡层和遮挡所述第二漏极区的第二遮挡层。
可选地，所述在所述基底上分别形成对应所述第一半导体的第一栅极和对应所述第一半导体的第二栅极，包括：
在所述第一半导体层、所述第二半导体层和所述基底上形成绝缘层，所述绝缘层使所述第一栅极、所述第二栅极均与所述第一半导体、所述第二半导体相互绝缘，所述第一遮挡层和所述第二遮挡层均形成于所述绝缘层上。
可选地，所述同时对所述第一源极区、所述第一漏极区、所述第二源极区和所述第二漏极区进行离子掺杂之后，还包括：
去除所述第一遮挡层和所述第二遮挡层。
可选地，在所述绝缘层上形成依次分别与所述第一源极区、所述第一漏极区、所述第二源极区、所述第二漏极区对应的第一过孔、第二过孔、第三过孔和第四过孔；
在所述绝缘层上分别形成第一源极、第一漏极、第二源极、第二漏极，所述第一源极通过所述第一过孔与所述第一源极区电连接，所述第一漏极通过所述第二过孔与所述第一漏极区电连接，所述第二源极通过所述第三过孔与所述第二源极区电连接，所述第二漏极通过所述第四过孔与所述第二漏极区电连接。
可选地，所述遮挡所述第二源极区和所述第二漏极区，包括：
在所述第一半导体层、所述第二半导体层和所述基底上形成绝缘层；
对所述绝缘层进行部分刻蚀，以形成第一绝缘层和第二绝缘层，所述第一绝缘层遮挡所述第一半导体层，所述第二绝缘层遮挡所述第二半导体层，所述第二绝缘层的厚度大于所述第一绝缘层的厚度。
可选地，所述形成第一绝缘层和第二绝缘层的步骤之后，包括：
在所述第一绝缘层上形成正对所述第一沟道区的第一栅极，在所述第二绝缘层上形成正对所述第二沟道区的第二栅极，所述第一源极区和所述第一漏极区均未被所述第一栅极遮挡，所述第二源极区和所述第二漏极区均未被所述第二栅极遮挡。
可选地，所述同时对所述第一源极区、所述第一漏极区、所述第二源极区和所述第二漏极区进行离子掺杂的步骤，发生在形成所述第一栅极和所述第二栅极的步骤之后。
可选地，所述方法还包括：
在所述第一绝缘层上形成分别与所述第一源极区和所述第一漏极区对应的第一过孔和第二过孔，并在所述第二绝缘层上形成分别与所述第二源极区和所述第二漏极区对应的第三过孔和第四过孔；
在所述绝缘层上分别形成第一源极、第一漏极、第二源极、第二漏极，所述第一源极通过所述第一过孔与所述第一源极区电连接，所述第一漏极通过所述第二过孔与所述第一漏极区电连接，所述第二源极通过所述第三过孔与所述第二源极区电连接，所述第二漏极通过所述第四过 孔与所述第二漏极区电连接。
可选地，所述定义所述第一半导体层的两相对侧分别为第一源极区和第一漏极区、所述第一半导体层位于所述第一源极区和所述第一漏极区之间的部分为第一沟道区，定义所述第二半导体层的两相对侧分别为第二源极区和第二漏极区、所述第二半导体层位于所述第二源极区和所述第二漏极区之间的部分为第二沟道区，包括：
在所述第一半导体层和所述第二半导体层的正上方分别形成第一阻隔层和第二阻隔层，所述第一阻隔层呈均匀厚度结构，所述第二阻隔层呈中间厚度厚两侧厚度薄的结构；
所述第一半导体层与所述第一阻隔层正对的区域定义为所述第一沟道区，所述第一半导体层未被所述第一阻隔层遮挡的两侧分别定义为所述第一源极区和所述第一漏极区，所述第二半导体层与所述第二阻隔层的中间厚度厚的部分正对的区域定义为所述第二沟道区，所述第二半导体层与所述第二阻隔层的厚度薄的两侧正对的部分分别定义为所述第二源极区和所述第二漏极区。
可选地，所述同时对所述第一源极区、所述第一漏极区、所述第二源极区和所述第二漏极区进行离子掺杂之后，包括：
去除所述第一阻隔层和所述第二阻隔层；
在所述基底上形成覆盖所述第一半导体和所述第二半导体的绝缘层；
在所述绝缘层上形成对应所述第一沟道区的第一栅极和形成对应所述第二沟道区的第二栅极。
可选地，所述方法还包括：
在所述绝缘层上形成依次分别与所述第一源极区、所述第一漏极区、所述第二源极区、所述第二漏极区对应的第一过孔、第二过孔、第三过孔和第四过孔；
在所述绝缘层上分别形成第一源极、第一漏极、第二源极、第二漏极，所述第一源极通过所述第一过孔与所述第一源极区电连接，所述第一漏极通过所述第二过孔与所述第一漏极区电连接，所述第二源极通过 所述第三过孔与所述第二源极区电连接，所述第二漏极通过所述第四过孔与所述第二漏极区电连接。
可选地，所述离子掺杂为P型离子掺杂，所述P型离子为硼。
可选地，所述离子掺杂为N型离子掺杂，所述N型离子为硼、砷、锑、铋中一种或多种的组合。
本申请实施例解决其技术问题还提供以下技术方案：
一种阵列基板，包括：第一场效应晶体管,包括相互绝缘的第一栅极和第一半导体层，所述第一半导体层包括位于所述第一半导体层两相对侧的第一源极区、第一漏极区以及位于所述第一源极区和所述第一漏极区之间的第一沟道区，所述第一栅极正对所述第一沟道区设置；
第二场效应晶体管,与所述第一场效应晶体管间隔设置，所述第二场效应晶体管包括相互绝缘的第二栅极和第二半导体层，所述第二半导体层包括位于所述第二半导体层两相对侧的第二源极区、第二漏极区以及位于所述第二源极区和所述第二漏极区之间的第二沟道区，所述第二栅极正对所述第二沟道区设置；
所述第一源极区、所述第一漏极区的离子掺杂量均与所述第二源极区、所述二漏极区的离子掺杂量不同。
可选地，所述第一场效应晶体管还包括第一源极、第一漏极，所述第一源极与所述第一源极区电连接，所述第一漏极与所述第一漏极区电连接；所述第二场效应晶体管还包括第二源极、第二漏极，所述第二源极与所述第二源极区电连接，所述第二漏极与所述第二漏极区电连接。
可选地，所述阵列基板还包括基底和绝缘层；
所述第一场效应晶体管和所述第二场效应晶体管共用共同的基底和绝缘层，所述基底作为承载所述第一场效应晶体管和所述第二场效应晶体管的衬底，所述绝缘层位于所述第一栅极、所述第二栅极与所述第一半导体层、所述第二半导体层之间，从而使所述第一栅极与所述第一半导体层相互绝缘，以及所述第二栅极与所述第二半导体层相互绝缘。
可选地，所述绝缘层包括第一绝缘层和第二绝缘层，所述第一绝缘层位于所述第一栅极与所述第一半导体层之间，所述第二绝缘层位于所 述第二栅极与所述第二半导体层之间，所述第二绝缘层的厚度大于所述第一绝缘层的厚度。
本申请实施例解决其技术问题还提供以下技术方案：
一种显示面板，包括：以上所述的阵列基板。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1是本申请其中一个实施例提供的一种阵列基板的结构示意图；
图2是本申请另一个实施例提供的一种阵列基板的结构示意图；
图3是本申请其中一个实施例提供的一种阵列基板的制造方法的流程图；
图4a至图4f是图3示出的阵列基板的制造方法在不同阶段的制备示意图；
图5是本申请另一实施例提供的一种阵列基板的制造方法的流程图；
图6a至图6e是图5示出的阵列基板的制造方法在不同阶段的制备示意图；
图7是本申请再一实施例提供的一种阵列基板的制造方法的流程图；
图8a至图8e是图7示出的阵列基板的制造方法在不同阶段的制备示意图。
具体实施方式
为了便于理解本申请，下面结合附图和具体实施例，对本申请进行更详细的说明。需要说明的是，当元件被表述“固定于”另一个元件，它可以直接在另一个元件上、或者其间可以存在一个或多个居中的元件。 当一个元件被表述“连接”另一个元件，它可以是直接连接到另一个元件、或者其间可以存在一个或多个居中的元件。本说明书所使用的术语“垂直的”、“水平的”、“左”、“右”、“内”、“外”以及类似的表述只是为了说明的目的，并且仅表达实质上的位置关系，例如对于“垂直的”，如果某位置关系因为了实现某目的的缘故并非严格垂直，但实质上是垂直的，或者利用了垂直的特性，则属于本说明书所述“垂直的”范畴。
除非另有定义，本说明书所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。在本申请的说明书中所使用的术语只是为了描述具体地实施例的目的，不是用于限制本申请。本说明书所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
此外，下面所描述的本申请不同实施例中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
请参阅图1，本申请其中一个实施例提供的阵列基板100包括：第一场效应晶体管10和第二场效应晶体管20，所述第一场效应晶体管10和所述第二场效应晶体管20间隔设置，所述第一场效应晶体管10和所述第二场效应晶体管20由同一工艺同时制备而成。
所述第一场效应晶体管10和所述第二场效应晶体管20共用共同的基底2和绝缘层4。所述基底2作为承载所述第一场效应晶体管10和所述第二场效应晶体管20的衬底，所述基底2上形成有所述绝缘层4。
在一些实施例中，所述基底2上依次形成有柔性基板、缓冲层和所述绝缘层4。
所述第一场效应晶体管10包括第一半导体层12；所述第二场效应晶体管20包括第二半导体层22，所述第一半导体层12和第二半导体层22位于所述基底2和所述绝缘层4之间，且所述第一半导体层12和所述第二半导体层22间隔预设距离，在本实施例中，所述第一半导体层12和所述第二半导体层22均为多晶硅层，在一些实施例中，所述第一半导体层12和所述第二半导体层22也可为其他半导体材料。
所述第一半导体层12包括位于所述第一半导体层12两相对侧的第一源极区122、第一漏极区124以及位于所述第一源极区122和所述第一漏极区124之间的第一沟道区126。
所述第二半导体层22包括位于所述第二半导体层22两相对侧的第二源极区222、第二漏极区224以及位于所述第二源极区222和所述第二漏极区224之间的第二沟道区226。
所述第一源极区122、所述第一漏极区124、所述第二源极区222和所述第二漏极区224同时进行离子掺杂，但所述第一源极区122、所述第一漏极区124与所述第二源极区222、所述第二漏极区224的离子掺杂量不同，进而使得所述第一半导体层12和所述第二半导体层22的电学性能不同，因此所述第一场效应晶体管10和所述第二场效应晶体管20具有不同的器件特性。
所述第一半导体层12和第二半导体层22的电学性能包括半导体层的类型、载流子浓度和霍尔载流子迁移等。
所述第一场效应晶体管10还包括第一栅极14，所述第一栅极14形成于所述绝缘层4上，且所述第一栅极14位于所述第一沟道区126的正上方。
所述第二场效应晶体管20还包括第二栅极24，所述第二栅极24形成于所述绝缘层4上，且所述第二栅极24位于所述第二沟道区226的正上方。
所述绝缘层4位于所述第一栅极14、所述第二栅极24与所述第一半导体层12、所述第二半导体层22之间，从而使所述第一栅极14与所述第一半导体层12相互绝缘，以及所述第二栅极22与所述第二半导体层22相互绝缘。
所述第一场效应晶体管10还包括第一源极、第一漏极，所述第一源极与所述第一源极区电连接，所述第一漏极与所述第一漏极区电连接。
所述第二场效应晶体管20还包括第二源极、第二漏极，所述第二源极与所述第二源极区电连接，所述第二漏极与所述第二漏极区电连接。
上述阵列基板100的中的所述第一源极区122、所述第一漏极区124 与所述第二源极区222、所述第二漏极区224的离子掺杂量不同，进而使得所述第一半导体层12和所述第二半导体层22的电学性能不同，因此所述第一场效应晶体管10和所述第二场效应晶体管20具有不同的器件特性，同时在一种阵列基板100上得到具有不同器件特性的场效应晶体管器件，不需调整场效应晶体管的尺寸,提高了布局空间的使用率，有利于显示屏往更高解析度的方向发展。
所述基底2采用玻璃等透明材料制成，且经过预先清洗。在一些实施例中，因传统碱玻璃中铝、钡和钠等金属杂质含量较高，容易在高温处理工艺中发生金属杂质的扩散，因此所述基底2也可以采用无碱玻璃制成。所述基底2也可采用柔性材料制成。在一些实施方式中，当所述基底2和所述绝缘层4之间依次形成有柔性基板、缓冲层时，所述柔性基板是用于支撑和保护可以在其上形成的多种元件的基板，在必要时，所述柔性基板可与所述基底2剥离。所述柔性基板可以由多种材料形成。例如，当场效应晶体管在诸如柔性显示设备的柔性应用中使用时，柔性基板可以由柔性绝缘材料形成。柔性绝缘材料的示例可以包括聚酰亚胺(PI)、聚醚酰亚胺(PEI)、聚对苯二甲酸乙二醇酯(PES)、聚碳酸酯(PC)、聚苯乙烯(PS)、苯乙烯-丙烯腈共聚物、以及硅丙烯酸树脂。而且，当场效应晶体管在具有高透射率的应用(诸如，透明显示设备)中使用时，柔性基板可以由柔性透明绝缘材料形成。
所述缓冲层位于柔性基板与绝缘层4之间，用于阻挡柔性基板中所含的杂质扩散进入场效应晶体管的半导体层中，防止对场效应晶体管的器件性能产生影响。同时所述缓冲层能够增强半导体层与柔性基板之间的密接性，增大半导体层与柔性基板的接触牢固度，进而避免半导体层的脱落，提高了场效应晶体管的稳定性。其中,所述缓冲层的材料为绝缘材料,如SiOx、SiNx或两者任意组合。
所述绝缘层4是以氧化氮(N 2O)和甲硅烷(SiH 4)为反应源气体，采用增强化学气相沉积(PECVD)法在缓冲层上沉积了一系列氢化非晶氮化硅(a-SiNx∶H)薄膜，所述氮化硅薄膜具有优良的绝缘耐压性能以及较好的界面特性。同时通过调整所述绝缘层4的厚度可改善有源层 背面界面的质量，防止在所述有源层界面形成漏电的途径。所述绝缘层4的厚度为100-400nm，因为其良好的界面特性，所制备的半导体器件具有较小的泄露电流，提高了器件的电学性能。
在一些实施例中，所述绝缘层4也可采用单层二氧化硅(SiO 2)或双层二氧化硅/氮化硅(SiO 2/SiNx)结构。
所述第一栅极14和所述第二栅极24的材料可选择Al、Ti、Mo、Cu、Ni、ITO等金属、混合物的金属层或金属氧化物。
在一些实施例中，所述第一栅极14和所述第二栅极24可以多层结构。所述多层电极包括具有Al、Ti、Mo、Cu、Ni、ITO或其混合物的金属层和包括透明导电氧化物材料的透明导电氧化物层。所述透明导电氧化物材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟锡锌(ISZO)等。所述多层电极可以具有被配置为包括第一透明导电氧化物层、金属层和第二透明导电氧化物层的三层结构。所述多层电极也可以具有被配置为包括透明导电氧化物层和金属层的两层结构。
请参阅图2，本申请一些实施例提供的阵列基板100a与图1所示的阵列基板100基本相同，区别在于所述阵列基板100a中包括第一绝缘层42和第二绝缘层44，所述第一绝缘层42和第二绝缘层44代替所述阵列基板100中的绝缘层4，所述第二绝缘层44的厚度大于所述第一绝缘层42的厚度不同。所述第一半导体层12位于所述基底2和所述第一绝缘层42之间，所述第二半导体层22位于所述基底2和所述第二绝缘层44之间，所述第一栅极14和第二栅极24分别形成于所述第一绝缘层42和所述第二绝缘层44上，且分别位于所述第一半导体层12和所述第二半导体层22的正上方。所述第一绝缘层42位于所述第一栅极14与所述第一半导体层12之间，所述第二绝缘层44位于所述第二栅极24与所述第二半导体层22之间。
所述第一绝缘层42和所述第二绝缘层44由同一材料同时形成。所述第一绝缘层42和第二绝缘层44的材料与图1所示的实施例中的所述绝缘层4的材料相同，在此不再赘述。
本发明还提供阵列基板的制造方法(未图示)，至少包括以下步骤：
在基底上形成间隔设置的第一半导体层和第二半导体层；
定义所述第一半导体层的两相对侧分别为第一源极区和第一漏极区、所述第一半导体层位于所述第一源极区和所述第一漏极区之间的部分为第一沟道区，定义所述第二半导体层的两相对侧分别为第二源极区和第二漏极区、所述第二半导体层位于所述第二源极区和所述第二漏极区之间的部分为第二沟道区；
遮挡所述第二源极区和所述第二漏极区，并同时对所述第一源极区、所述第一漏极区、所述第二源极区和所述第二漏极区进行离子掺杂,使所述第一源极区、所述第一漏极区与所述第二源极区、所述二漏极区的离子掺杂量不同。
为了更清楚地描述阵列基板的制造方法，下文给出其中几种不同的具体实施方式。
请一并参阅图3和图4，本申请其中一个实施例提供一种阵列基板的制造方法，需要说明的是，上述对阵列基板的实施例的解释说明也适用于本实施例的阵列基板的制备方法，为避免冗余，在此不再详细展开。
所述阵列基板的制造方法包括：
步骤S31:在基底上形成半导体层。
步骤S32:对所述半导体层进行图案化处理以形成第一半导体层12和第二半导体层22，所述第一半导体层12和所述第二半导体层22间隔预设距离。
请参阅图4a,具体地，所述图案化处理可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明实施例中所形成的结构选择相应的构图工艺。
在本实施例中，在所述半导体层上形成一层光刻胶，对光刻胶进行曝光和显影，然后对所述半导体层进行干法刻蚀，以形成所述第一半导体层12和第二半导体层22。
步骤S33:在所述第一半导体层12、所述第二半导体层22和所述基 底2上形成绝缘层。
请参阅图4b,具体地，可以采用增强化学气相沉积(PECVD)方法，在经过步骤S32的所述第一半导体层12、第二半导体层22以及所述基底2上沉积厚度约为
Figure PCTCN2019074003-appb-000001
的绝缘层4，其中，绝缘层4材料可以选用氧化物、氮化物或者氮氧化物，绝缘层4可以为单层、双层或多层结构。具体地，绝缘层4可以是SiNx，SiOx或Si(ON)x。
步骤S34：在所述绝缘层上分别形成对应所述第一半导体层的第一栅极和对应所述第二半导体层的第二栅极，所述第一栅极、所述第二栅极均与所述第一半导体层、所述第二半导体层相互绝缘，所述第一半导体层与所述第一栅极正对的部分为所述第一沟道区，所述第一半导体层未被所述第一栅极遮挡的两侧分别定义为所述第一源极区和所述第一漏极区，所述第二半导体层与所述第二栅极正对的部分为所述第二沟道区，所述第二半导体层未被所述第二栅极遮挡的两侧分别定义为所述第二源极区和所述第二漏极区。
请参阅图4c,具体地，可以在经过步骤S33的所述绝缘层4上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2019074003-appb-000002
的栅金属层，在栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域；通过刻蚀工艺刻蚀掉光刻胶不保留区域的栅金属层，剥离剩余的光刻胶，形成所述第一栅极14和所述第二栅极24。
步骤S35：在所述第二栅极两侧分别形成遮挡所述第二源极区的第一遮挡层和遮挡所述第二漏极区的第二遮挡层。
请参阅图4d,具体地，在经过步骤S34的所述绝缘层4、第一栅极14和第二栅极24上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域；所述光刻胶保留区域为所述第二源极区222和第二漏极区224的上方，所述光刻胶不保留区域为其他区域，通过光刻工艺光刻掉光刻胶不保留区域的光刻胶，在所述光刻胶保留区域形成第一遮挡层23和第二遮挡层25。
步骤S36：对所述第一源极区、所述第一漏极区、所述第二源极区 和所述第二漏极区同时进行离子掺杂，所述第一源极区和所述第一漏极区为重掺杂区域，所述第二源极区和所述第二漏极区为轻掺杂区域。
请参阅图4e,具体的，所述离子掺杂为P型离子掺杂，P型离子为硼(B)，因为P型离子的离子半径较小，所述P型离子可以分别穿过所述第一绝缘层4、所述第一遮挡层23和第二遮挡层25，同时实现对所述第一源极区122、所述第一漏极区124、所述第二源极区222和所述第二漏极区224的P型离子掺杂。
可以理解的是，在离子掺杂的过程中，由于第一遮挡层23和第二遮挡层25对第二源极区222和第二漏极区224的遮挡作用，P性离子少量穿过所述第一遮挡层23和第二遮挡层25对所述第二源极区222和第二漏极区224进行离子掺杂，因此所述第一源极区122、所述第一漏极区124、所述第二源极区222和所述第二漏极区224的P型离子掺杂量是不同的，所述第一源极区122和所述第一漏极区124为重掺杂区域，所述第二源极区222和所述第二漏极区224为轻掺杂区域，又因为离子掺杂量的不同会影响所述第一半导体层12和第二半导体层22的电学性能，因此所述第一半导体层12和第二半导体层22的电学性能也是不同的。
步骤S37：剥离所述第一遮挡层和第二遮挡层。
请参阅图4f,将所述第一遮挡层和第二遮挡层的光刻胶进行剥离。
在一些实施例中，步骤S37之后，阵列基板的制造方法还包括：在所述绝缘层上形成依次分别与所述第一源极区、所述第一漏极区、所述第二源极区、所述第二漏极区对应的第一过孔、第二过孔、第三过孔和第四过孔；
在所述绝缘层上分别形成第一源极、第一漏极、第二源极、第二漏极，所述第一源极通过所述第一过孔与所述第一源极区电连接，所述第一漏极通过所述第二过孔与所述第一漏极区电连接，所述第二源极通过所述第三过孔与所述第二源极区电连接，所述第二漏极通过所述第四过孔与所述第二漏极区电连接。
具体地，在所述绝缘层4的上方采用光刻工艺形成掩模层，并采用 干法刻蚀形成所述第一过孔、第二过孔、第三过孔和第四过孔。干法刻蚀可采用等离子刻蚀、反应离子刻蚀、电感耦合等离子体刻蚀等多种方式，刻蚀气体可采用含氟、氯的气体，如CF 4、CHF 3、SF 6、CC1 2F 2等气体或者上述气体与0 2形成的混合气体。
本申请另一实施例提供一种阵列基板的制造方法，需要说明的是，上述对阵列基板的实施例的解释说明也适用于本实施例的阵列基板的制备方法，为避免冗余，在此不再详细展开。
所述阵列基板的制造方法包括：
步骤S51:在基底上形成半导体层。
步骤S52:对所述半导体层进行处理以形成第一半导体层和第二半导体层。
请参阅图6a,步骤S52:对所述半导体层进行图案化处理以形成第一半导体层12和第二半导体层22，所述第一半导体层12和所述第二半导体层22间隔预设距离。
步骤S53:在所述第一半导体层12和所述第二半导体层22的正上方分别形成第一阻隔层17和第二阻隔层27，所述第一阻隔层17呈均匀厚度结构，所述第二阻隔层27呈中间厚度厚两侧厚度薄的结构。
所述第一半导体层12与所述第一阻隔层17正对的区域定义为所述第一沟道区126，所述第一半导体层12未被所述第一阻隔层17遮挡的两侧分别定义为所述第一源极区122和所述第一漏极区124，所述第二半导体层22与所述第二阻隔层27的中间厚度厚的部分正对的区域定义为所述第二沟道区226，所述第二半导体层22与所述第二阻隔层27的厚度薄的两侧正对的部分分别定义为所述第二源极区222和所述第二漏极区224。
请参阅图6b,具体地，在经过步骤S52的所述第一半导体层12和所述第二半导体层22和基底2上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域；所述光刻胶保留区域为所述第一半导体层12和所述第二半导体层22的中部，所述光刻胶不保留区域为其他区域，通过光刻工艺光刻掉光刻胶 不保留区域的的光刻胶，在所述光刻胶保留区域形成第一阻隔层17和第二阻隔层27。当进行离子掺杂时，所述第一阻隔层17和第二阻隔层27用于避免离子对所述第一半导体层12和所述第二半导体层22的中部进行掺杂。
步骤S54：对所述第一源极区122、所述第一漏极区124、所述第二源极区222和所述第二漏极区224同时进行离子掺杂，所述第一源极区122和所述第一漏极区124为重掺杂区域，所述第二源极区222和所述第二漏极区224为轻掺杂区域。
请参阅图6c,具体的，所述离子掺杂为可为P型离子掺杂，也可为N型离子掺杂，所述P型离子为B，所述N型离子为P、As、Sb、Bi中一种或多种的组合。
可以理解的是，在离子掺杂的过程中，由于第一阻隔层17和第二阻隔层27对所述离子的阻隔作用，使离子无法穿过所述第一阻隔层17和第二阻隔层27对所述第一半导体层12和所述第二半导体层22的中部进行掺杂。
可以理解的是，在离子掺杂的过程中，由于第一阻隔层17和第二阻隔层27对第二源极区222和第二漏极区224的遮挡作用，P性离子少量穿过第一阻隔层17和第二阻隔层27对所述第二源极区222和第二漏极区224进行离子掺杂，因此所述第一源极区122、所述第一漏极区124、所述第二源极区222和所述第二漏极区224的P型离子的掺杂量是不同的，所述第一源极区122和所述第一漏极区124为重掺杂区域，所述第二源极区222和所述第二漏极区224为轻掺杂区域，又因为掺杂量的不同会影响所述第一半导体层12和第二半导体层22的电学性能，因此所述第一半导体层12和第二半导体层22的电学性能也是不同的。
步骤S55：去除所述第一阻隔层17和第二阻隔层27。
步骤S56：在所述第一半导体层12、所述第二半导体层22和所述基底2上形成绝缘层4。
请参阅图6d,具体地，可以采用增强化学气相沉积(PECVD)方法， 在经过步骤S32的所述第一半导体层12、第二半导体层22以及所述基底2上沉积厚度约为
Figure PCTCN2019074003-appb-000003
的绝缘层4，其中，绝缘层4材料可以选用氧化物、氮化物或者氮氧化物，绝缘层4可以为单层、双层或多层结构。具体地，绝缘层4可以是SiNx，SiOx或Si(ON)x。
步骤S57：在所述绝缘层4上形成对应所述第一沟道区126的第一栅极14和形成对应所述第二沟道区226的第二栅极24。
请参阅图6e,具体地，可以在经过步骤S57的所述绝缘层4上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2019074003-appb-000004
的栅金属层，在栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域；通过刻蚀工艺刻蚀掉光刻胶不保留区域的栅金属层，剥离剩余的光刻胶，形成所述第一栅极14和所述第二栅极24。
在一些实施例中，步骤S58之后，阵列基板的制造方法还包括：在所述绝缘层4上形成依次分别与所述第一源极区122、所述第一漏极区124、所述第二源极区222、所述第二漏极区224对应的第一过孔、第二过孔、第三过孔和第四过孔。
在所述绝缘层4上分别形成第一源极、第一漏极、第二源极、第二漏极，所述第一源极通过所述第一过孔与所述第一源极区122电连接，所述第一漏极通过所述第二过孔与所述第一漏极区124电连接，所述第二源极通过所述第三过孔与所述第二源极区222电连接，所述第二漏极通过所述第四过孔与所述第二漏极区224电连接。
具体地，在所述绝缘层4的上方采用光刻工艺形成掩模层，并采用干法刻蚀形成第一过孔、第二过孔、第三过孔和第四过孔。干法刻蚀可采用等离子刻蚀、反应离子刻蚀、电感耦合等离子体刻蚀等多种方式，刻蚀气体可采用含氟、氯的气体，如CF 4、CHF 3、SF 6、CC1 2F 2等气体或者上述气体与0 2形成的混合气体。
请一并参阅图7和图8，本申请另一实施例提供一种阵列基板的制造方法，需要说明的是，上述对阵列基板的实施例的解释说明也适用于 本实施例的阵列基板的制备方法，为避免冗余，在此不再详细展开
所述阵列基板的制造方法包括：
步骤S71:在基底2上形成半导体层。
步骤S72:对所述半导体层进行图案化处理以形成第一半导体层12和第二半导体层22，所述第一半导体层12和所述第二半导体层22间隔预设距离。定义所述第一半导体层12的两相对侧分别为第一源极区122和第一漏极区124、所述第一半导体层12位于所述第一源极区122和所述第一漏极区124之间的部分为第一沟道区，定义所述第二半导体层22的两相对侧分别为第二源极区222和第二漏极区224、所述第二半导体层22位于所述第二源极区222和所述第二漏极区224之间的部分为第二沟道区。
请参阅图8a,具体地，所述图案化处理可只包括光刻工艺，或包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明实施例中所形成的结构选择相应的构图工艺。
步骤S73:在所述第一半导体层12、第二半导体层22和所述基底2上形成绝缘层。
请参阅图8b,具体地，可以采用增强化学气相沉积(PECVD)方法，在经过步骤S32的所述第一半导体层12、第二半导体层22以及所述基底2上沉积厚度约为
Figure PCTCN2019074003-appb-000005
的绝缘层4，其中，绝缘层4材料可以选用氧化物、氮化物或者氮氧化物，绝缘层4可以为单层、双层或多层结构。具体地，绝缘层4可以是SiNx，SiOx或Si(ON)x。
步骤S74:对所述绝缘层4进行部分刻蚀，以形成第一绝缘层42和第二绝缘层44，所述第一绝缘层42遮挡所述第一半导体层12，所述第二绝缘层44遮挡所述第二半导体层22，所述第二绝缘层44的厚度大于所述第一绝缘层42的厚度不同。
请参阅图8c,具体地，在经过步骤S73的所述绝缘层4上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不 保留区域和光刻胶保留区域；所述光刻胶不保留区域为所述绝缘层4的一半区域，所述光刻胶保留区域为所述绝缘层4的另一半区域，通过刻蚀工艺刻蚀掉光刻胶不保留区域的一定厚度的绝缘层，剥离剩余的光刻胶，形成所述第一绝缘层42和所述第二绝缘层44，可以理解的是，所述第一绝缘层42和第二绝缘层44的厚度不同。
步骤S75：在所述第一绝缘层42上形成正对所述第一沟道区126的第一栅极14，在所述第二绝缘层44上形成正对所述第二沟道区226的第二栅极24，所述第一源极区122和所述第一漏极区124均未被所述第一栅极14遮挡，所述第二源极区222和所述第二漏极区224均未被所述第二栅极24遮挡。
请参阅图8d,具体地，可以在所述绝缘层4上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2019074003-appb-000006
的栅金属层，在栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域；通过刻蚀工艺刻蚀掉光刻胶不保留区域的栅金属层，剥离剩余的光刻胶，形成所述第一栅极14和所述第二栅极24。
步骤S76：对所述第一源极区122、所述第一漏极区124、所述第二源极区222和所述第二漏极224区同时进行离子掺杂，所述第一源极区122和所述第一漏极区124为重掺杂区域，所述第二源极区222和所述第二漏极区224为轻掺杂区域。
请参阅图8e,具体的，所述离子掺杂为P型离子掺杂，P型离子为硼(B)，因为P型离子的离子半径较小，所述P型离子可以分别穿过所述第一绝缘层42和第二绝缘层44，同时实现对所述第一源极区122、所述第一漏极区124、所述第二源极区222和所述第二漏极区224的P型离子掺杂。
可以理解的是，所述第一绝缘层42与所述第二绝缘层44的厚度不同,且第二绝缘层44的厚度大于所述第一绝缘层44的厚度，因此所述P型离子分别穿过所述第一绝缘层42和第二绝缘层44，对所述第一源极区122、所述第一漏极区124、所述第二源极区222的离子掺杂量和所 述第二漏极区224的离子掺杂量是不同的，所述第一源极区122和所述第一漏极区124为重掺杂区域，所述第二源极区222和所述第二漏极区224为轻掺杂区域，又因为离子掺杂量的不同会影响所述第一半导体层12和第二半导体层22的电学性能，因此所述第一半导体层12和第二半导体层22的电学性能也是不同的。
在一些实施例中，步骤S76之后，阵列基板的制造方法还包括：在所述第一绝缘层42上形成分别与所述第一源极区122和所述第一漏极区124对应的第一过孔和第二过孔，并在所述第二绝缘层44上形成分别与所述第二源极区222和所述第二漏极区224对应的第三过孔和第四过孔。
在所述第一绝缘层42和所述第二绝缘层44上分别形成第一源极、第一漏极、第二源极、第二漏极，所述第一源极通过所述第一过孔与所述第一源极区电连接，所述第一漏极通过所述第二过孔与所述第一漏极区电连接，所述第二源极通过所述第三过孔与所述第二源极区电连接，所述第二漏极通过所述第四过孔与所述第二漏极区电连接。
上述各实施方式中，对所述第一源极区122、所述第一漏极区124、所述第二源极区222和所述第二漏极区224进行离子掺杂量时，可以不对所述第一沟道区126和所述第二沟道区226进行遮挡或者对二者的遮挡程度相同，也就是所述第一沟道区126和所述第二沟道区226也一并进行离子掺杂，由于所述第一沟道区126和所述第二沟道区226均没有被遮挡或遮挡的程度相同，因此被掺杂的量相等，不会影响所述第一场效应晶体管10和所述第二场效应晶体管20的电性能差异。
本申请又一实施例还提供一种显示装置，包括显示面板和保护层。显示面板包括上述任一实施例中的阵列基板100/100a，所述阵列基板用于驱动以实现所述显示装置的显示功能，所述保护层覆盖于所述显示面板以起保护作用。所述阵列基板还包括多条平行排列的数据线和多条平行排列的扫描线，数据线和扫描线相互垂直且相互绝缘，相邻的两条数据线和相邻的两条扫描线定义出一个像素单元，多个像素单元呈矩阵排列，每一像素单元内形成有一所述第一场效应晶体管10和一所述第二 场效应晶体管20。
所述显示装置为柔性显示装置时，所述基底2和所述保护层均采用柔性材料，或者所述基底作为刚性承载体，在所述基底上形成柔性基板后再在所述柔性基板上形成场效应晶体管、数据线、扫描线等电子元件，之后再将刚性的基底与所述柔性基板剥离。
借助柔性性质，所述显示装置可通过设置诸如弯曲传感器之类，利用弯曲传感器检测的弯曲参数，以实现各类应用功能的执行，从而极大提升用户的体验感。
与现有技术相比较，本申请显示装置的显示面板中提供了一种阵列基板100或100a，通过对所述第一源极区、所述第一漏极区、所述第二源极区和所述二漏极区同时进行离子掺杂，但所述第一源极区、所述第一漏极区与所述第二源极区、所述二漏极区的离子掺杂量不同，进而使得所述第一半导体层和所述第二半导体层的电学性能不同，因此所述第一场效应晶体管10和所述第二场效应晶体管20具有不同的器件特性，同时在一种阵列基板100或100a上得到具有不同器件特性的场效应晶体管器件，不需调整场效应晶体管的尺寸,提高了布局空间的使用率，有利于显示屏往更高解析度的方向发展。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；在本申请的思路下，以上实施例或者不同实施例中的技术特征之间也可以进行组合，步骤可以以任意顺序实现，并存在如上所述的本申请的不同方面的许多其它变化，为了简明，它们没有在细节中提供；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (20)

  1. 一种阵列基板的制造方法，其特征在于，包括：
    在基底上形成间隔设置的第一半导体层和第二半导体层；
    定义所述第一半导体层的两相对侧分别为第一源极区和第一漏极区、所述第一半导体层位于所述第一源极区和所述第一漏极区之间的部分为第一沟道区，定义所述第二半导体层的两相对侧分别为第二源极区和第二漏极区、所述第二半导体层位于所述第二源极区和所述第二漏极区之间的部分为第二沟道区；
    遮挡所述第二源极区和所述第二漏极区，并同时对所述第一源极区、所述第一漏极区、所述第二源极区和所述第二漏极区进行离子掺杂,使所述第一源极区、所述第一漏极区与所述第二源极区、所述二漏极区的离子掺杂量不同。
  2. 根据权利要求1所述的方法，其特征在于：
    所述定义所述第一半导体层的两相对侧分别为第一源极区和第一漏极区、所述第一半导体层位于所述第一源极区和所述第一漏极区之间的部分为第一沟道区，定义所述第二半导体层的两相对侧分别为第二源极区和第二漏极区、所述第二半导体层位于所述第二源极区和所述第二漏极区之间的部分为第二沟道区，包括：
    在所述基底上分别形成对应所述第一半导体层的第一栅极和对应所述第二半导体层的第二栅极，所述第一栅极、所述第二栅极均与所述第一半导体层、所述第二半导体层相互绝缘，所述第一半导体层与所述第一栅极正对的部分为所述第一沟道区，所述第一半导体层未被所述第一栅极遮挡的两侧分别定义为所述第一源极区和所述第一漏极区，所述第二半导体层与所述第二栅极正对的部分为所述第二沟道区，所述第二半导体层未被所述第二栅极遮挡的两侧分别定义为所述第二源极区和所述第二漏极区。
  3. 根据权利要求2所述的方法，其特征在于：
    所述遮挡所述第二源极区和所述第二漏极区，包括：
    在所述第二栅极两侧分别形成遮挡所述第二源极区的第一遮挡层和遮挡所述第二漏极区的第二遮挡层。
  4. 根据权利要求3所述的方法，其特征在于：
    所述在所述基底上分别形成对应所述第一半导体层的第一栅极和对应所述第一半导体层的第二栅极，包括：
    在所述第一半导体层、所述第二半导体层和所述基底上形成绝缘层，所述绝缘层使所述第一栅极、所述第二栅极均与所述第一半导体层、所述第二半导体层相互绝缘，所述第一遮挡层和所述第二遮挡层均形成于所述绝缘层上。
  5. 根据权利要求4所述的方法，其特征在于：所述同时对所述第一源极区、所述第一漏极区、所述第二源极区和所述第二漏极区进行离子掺杂之后，还包括：
    去除所述第一遮挡层和所述第二遮挡层。
  6. 根据权利要求5所述的方法，其特征在于：所述方法还包括：
    在所述绝缘层上形成依次分别与所述第一源极区、所述第一漏极区、所述第二源极区、所述第二漏极区对应的第一过孔、第二过孔、第三过孔和第四过孔；
    在所述绝缘层上分别形成第一源极、第一漏极、第二源极、第二漏极，所述第一源极通过所述第一过孔与所述第一源极区电连接，所述第一漏极通过所述第二过孔与所述第一漏极区电连接，所述第二源极通过所述第三过孔与所述第二源极区电连接，所述第二漏极通过所述第四过孔与所述第二漏极区电连接。
  7. 根据权利要求1所述的方法，其特征在于：
    所述遮挡所述第二源极区和所述第二漏极区，包括：
    在所述第一半导体层、所述第二半导体层和所述基底上形成绝缘层；
    对所述绝缘层进行部分刻蚀，以形成第一绝缘层和第二绝缘层，所述第一绝缘层遮挡所述第一半导体层，所述第二绝缘层遮挡所述第二半导体层，所述第二绝缘层的厚度大于所述第一绝缘层的厚度。
  8. 根据权利要求7所述的方法，其特征在于：
    所述形成第一绝缘层和第二绝缘层的步骤之后，包括：
    在所述第一绝缘层上形成正对所述第一沟道区的第一栅极，在所述第二绝缘层上形成正对所述第二沟道区的第二栅极，所述第一源极区和所述第一漏极区均未被所述第一栅极遮挡，所述第二源极区和所述第二漏极区均未被所述第二栅极遮挡。
  9. 根据权利要求8所述的方法，其特征在于：所述同时对所述第一源极区、所述第一漏极区、所述第二源极区和所述第二漏极区进行离子掺杂的步骤，发生在形成所述第一栅极和所述第二栅极的步骤之后。
  10. 根据权利要求9所述的方法，其特征在于：所述方法还包括：
    在所述第一绝缘层上形成分别与所述第一源极区和所述第一漏极区对应的第一过孔和第二过孔，并在所述第二绝缘层上形成分别与所述第二源极区和所述第二漏极区对应的第三过孔和第四过孔；
    在所述绝缘层上分别形成第一源极、第一漏极、第二源极、第二漏极，所述第一源极通过所述第一过孔与所述第一源极区电连接，所述第一漏极通过所述第二过孔与所述第一漏极区电连接，所述第二源极通过所述第三过孔与所述第二源极区电连接，所述第二漏极通过所述第四过孔与所述第二漏极区电连接。
  11. 根据权利要求1所述的方法，其特征在于：
    所述定义所述第一半导体层的两相对侧分别为第一源极区和第一 漏极区、所述第一半导体层位于所述第一源极区和所述第一漏极区之间的部分为第一沟道区，定义所述第二半导体层的两相对侧分别为第二源极区和第二漏极区、所述第二半导体层位于所述第二源极区和所述第二漏极区之间的部分为第二沟道区，包括：
    在所述第一半导体层和所述第二半导体层的正上方分别形成第一阻隔层和第二阻隔层，所述第一阻隔层呈均匀厚度结构，所述第二阻隔层呈中间厚度厚两侧厚度薄的结构；
    所述第一半导体层与所述第一阻隔层正对的区域定义为所述第一沟道区，所述第一半导体层未被所述第一阻隔层遮挡的两侧分别定义为所述第一源极区和所述第一漏极区，所述第二半导体层与所述第二阻隔层的中间厚度厚的部分正对的区域定义为所述第二沟道区，所述第二半导体层与所述第二阻隔层的厚度薄的两侧正对的部分分别定义为所述第二源极区和所述第二漏极区。
  12. 根据权利要求11所述的方法，其特征在于：
    所述同时对所述第一源极区、所述第一漏极区、所述第二源极区和所述第二漏极区进行离子掺杂之后，包括：
    去除所述第一阻隔层和所述第二阻隔层；
    在所述基底上形成覆盖所述第一半导体层和所述第二半导体层的绝缘层；
    在所述绝缘层上形成对应所述第一沟道区的第一栅极和形成对应所述第二沟道区的第二栅极。
  13. 根据权利要求12所述的方法，其特征在于：所述方法还包括：
    在所述绝缘层上形成依次分别与所述第一源极区、所述第一漏极区、所述第二源极区、所述第二漏极区对应的第一过孔、第二过孔、第三过孔和第四过孔；
    在所述绝缘层上分别形成第一源极、第一漏极、第二源极、第二漏极，所述第一源极通过所述第一过孔与所述第一源极区电连接，所述第 一漏极通过所述第二过孔与所述第一漏极区电连接，所述第二源极通过所述第三过孔与所述第二源极区电连接，所述第二漏极通过所述第四过孔与所述第二漏极区电连接。
  14. 根据权利要求1所述的方法，其特征在于：
    所述离子掺杂为P型离子掺杂，所述P型离子为硼。
  15. 根据权利要求1所述的方法，其特征在于：
    所述离子掺杂为N型离子掺杂，所述N型离子为硼、砷、锑、铋中一种或多种的组合。
  16. 一种阵列基板，其特征在于，包括：
    第一场效应晶体管,包括相互绝缘的第一栅极和第一半导体层，所述第一半导体层包括位于所述第一半导体层两相对侧的第一源极区、第一漏极区以及位于所述第一源极区和所述第一漏极区之间的第一沟道区，所述第一栅极正对所述第一沟道区设置；
    第二场效应晶体管,与所述第一场效应晶体管间隔设置，所述第二场效应晶体管包括相互绝缘的第二栅极和第二半导体层，所述第二半导体层包括位于所述第二半导体层两相对侧的第二源极区、第二漏极区以及位于所述第二源极区和所述第二漏极区之间的第二沟道区，所述第二栅极正对所述第二沟道区设置；
    所述第一源极区、所述第一漏极区的离子掺杂量均与所述第二源极区、所述二漏极区的离子掺杂量不同。
  17. 根据权利要求16所述的阵列基板，其特征在于，
    所述第一场效应晶体管还包括第一源极、第一漏极，所述第一源极与所述第一源极区电连接，所述第一漏极与所述第一漏极区电连接；所述第二场效应晶体管还包括第二源极、第二漏极，所述第二源极与所述第二源极区电连接，所述第二漏极与所述第二漏极区电连接。
  18. 根据权利要求17所述的阵列基板，其特征在于，
    所述阵列基板还包括基底和绝缘层；
    所述第一场效应晶体管和所述第二场效应晶体管共用共同的基底和绝缘层，所述基底作为承载所述第一场效应晶体管和所述第二场效应晶体管的衬底，所述绝缘层位于所述第一栅极、所述第二栅极与所述第一半导体层、所述第二半导体层之间，从而使所述第一栅极与所述第一半导体层相互绝缘，以及所述第二栅极与所述第二半导体层相互绝缘。
  19. 根据权利要求18所述的阵列基板，其特征在于，
    所述绝缘层包括第一绝缘层和第二绝缘层，所述第一绝缘层位于所述第一栅极与所述第一半导体层之间，所述第二绝缘层位于所述第二栅极与所述第二半导体层之间，所述第二绝缘层的厚度大于所述第一绝缘层的厚度。
  20. 一种显示面板，其特征在于，包括如权利要求16至19任一项所述的阵列基板。
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