WO2010084534A1 - 薄膜ダイオード及びその製造方法 - Google Patents
薄膜ダイオード及びその製造方法 Download PDFInfo
- Publication number
- WO2010084534A1 WO2010084534A1 PCT/JP2009/004123 JP2009004123W WO2010084534A1 WO 2010084534 A1 WO2010084534 A1 WO 2010084534A1 JP 2009004123 W JP2009004123 W JP 2009004123W WO 2010084534 A1 WO2010084534 A1 WO 2010084534A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- polysilicon layer
- type semiconductor
- semiconductor region
- insulating film
- impurity ions
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 title description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 150
- 229920005591 polysilicon Polymers 0.000 claims abstract description 149
- 239000004065 semiconductor Substances 0.000 claims abstract description 120
- 239000012535 impurity Substances 0.000 claims abstract description 93
- 150000002500 ions Chemical class 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 239000011521 glass Substances 0.000 claims abstract description 53
- 239000010408 film Substances 0.000 claims description 93
- 238000010438 heat treatment Methods 0.000 claims description 25
- 230000001133 acceleration Effects 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims description 2
- 239000012528 membrane Substances 0.000 claims 1
- 238000011084 recovery Methods 0.000 description 25
- 230000003287 optical effect Effects 0.000 description 18
- 239000004973 liquid crystal related substance Substances 0.000 description 13
- 238000001237 Raman spectrum Methods 0.000 description 10
- -1 boron ions Chemical class 0.000 description 10
- 238000002513 implantation Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000003595 spectral effect Effects 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000001069 Raman spectroscopy Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 239000004988 Nematic liquid crystal Substances 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
Definitions
- the present invention relates to a thin film diode and a manufacturing method thereof, and more particularly to a thin film diode provided on a glass substrate and a manufacturing method thereof.
- a thin film diode (hereinafter referred to as “TFD”) is, for example, a poly (polycrystalline) silicon layer having a P-type semiconductor region doped with boron ions and an N-type semiconductor region doped with phosphorus ions. It has.
- Patent Document 1 an increase in reverse diode leakage current is realized by making the concentration gradient of the PN junction surface of a diode made of polycrystalline silicon steep or by making the vicinity of the junction surface non-crystalline.
- a semiconductor device is disclosed.
- TFD functions as an optical sensor element for converting an optical signal into an electrical signal
- a thin film transistor hereinafter referred to as “TFT”
- TFT thin film transistor
- Patent Document 2 discloses that an active layer of a thin film transistor on a glass substrate and a photoelectric conversion part of a PIN diode are formed of an amorphous silicon thin film, and the active layer and the photoelectric conversion part are doped with impurities in the same process as necessary.
- a method for manufacturing an array substrate with different doping concentrations is disclosed. According to this, it is described that a thin film transistor having desired characteristics and a PIN diode with improved photosensitivity can be simultaneously manufactured on a glass substrate easily and with a small number of steps.
- FIG. 13 is a cross-sectional view schematically showing a conventional TFD 121.
- the TFD 121 includes a polysilicon layer 112 provided on a glass substrate 110 via a base coat film 111 and an insulating film 113 provided so as to cover the polysilicon layer 112.
- the polysilicon layer 112 includes a P-type semiconductor region 112p doped with boron ions as impurities, an N-type semiconductor region 112n doped with phosphorus ions as impurities, and impurities. And an undoped I-type semiconductor region 112i to form a PIN structure diode.
- the crystallinity of the polysilicon layer 112 collapsed by the doping of the impurity ions is restored and the doped impurity ions are activated. Therefore, it is necessary to heat the substrate.
- the crystal recovery of the polysilicon layer 112 tends to be insufficient. Therefore, in the polysilicon layer 112, the crystallinity of the junction between the P-type semiconductor region 112p and the I-type semiconductor region 112i and the junction between the N-type semiconductor region 112n and the I-type semiconductor region 112i is reduced. The characteristics will deteriorate.
- the present invention has been made in view of such a point, and an object thereof is to improve the crystallinity of the junction as much as possible and to improve the diode characteristics.
- the concentration of impurity ions in the polysilicon layer and the insulating film along the thickness direction is the thickness of the polysilicon layer.
- the maximum is on the insulating film side with respect to the intermediate position in the direction.
- a thin film diode includes a glass substrate, a polysilicon layer provided on the glass substrate, each having a P-type semiconductor region and an N-type semiconductor region doped with impurity ions in the same plane, A thickness of impurity ions in the polysilicon layer and the insulating film in at least one of the P-type semiconductor region and the N-type semiconductor region, the thin film diode including an insulating film provided to cover the polysilicon layer The concentration along the direction is maximum on the insulating film side than the intermediate position in the thickness direction of the polysilicon layer.
- the concentration of impurity ions in the polysilicon layer and the insulating film along the thickness direction is maximum on the insulating film side with respect to the intermediate position in the thickness direction of the polysilicon layer, the P-type In at least one of the semiconductor region and the N-type semiconductor region, the concentration of impurity ions in the polysilicon layer along the thickness direction is minimized on the surface on the glass substrate side, and crystallinity collapse occurs on the glass substrate side of the polysilicon layer. It is suppressed.
- FIG. 9A is a photograph of the optical microscope before the heat treatment in the region Aa into which the impurity ions are implanted and the periphery thereof
- FIG. 9B shows the X portion in FIG. It is a Raman spectrum in the Y part.
- the Y portion of the non-implanted region has a sharp peak attributed to polysilicon in the vicinity of a wave number of 520 cm ⁇ 1 , so that the crystallinity is good and the implanted region Aa In the X portion at the center of the film, it almost matches the spectral shape of amorphous silicon. Therefore, it is presumed that the crystallinity of polysilicon is destroyed by the implantation of impurity ions.
- FIG. 10A is a photograph of an optical microscope after the heat treatment in the region Aa into which the impurity ions are implanted and the periphery thereof
- FIG. 10B shows the Xa portion and Xb in FIG. It is a Raman spectrum in a part and a Xc part.
- the Xc portion at the inner peripheral end of the implantation region Aa has a sharp peak attributed to polysilicon in the vicinity of the wave number of 520 cm ⁇ 1 , so that the crystallinity is recovered. It is inferred that
- the acceleration voltage is relatively low (for example, so that the concentration of impurity ions in the polysilicon layer along the thickness direction is maximized on the insulating film side of the polysilicon layer). 20 keV), the polysilicon layer region Aa is doped with impurity ions.
- the acceleration voltage is relatively set so that the concentration of impurity ions in the polysilicon layer along the thickness direction becomes maximum on the glass substrate side of the polysilicon layer. Therefore, the region Ab of the polysilicon layer is doped with impurity ions.
- FIG. 11 and 12 the acceleration voltage is relatively set so that the concentration of impurity ions in the polysilicon layer along the thickness direction becomes maximum on the glass substrate side of the polysilicon layer. Therefore, the region Ab of the polysilicon layer is doped with impurity ions.
- FIG. 11A is a photograph of the optical microscope before the heat treatment in the region Ab in which the impurity ions are implanted and the periphery thereof, and FIG. 11B shows the X portion in FIG. It is a Raman spectrum in the Y part.
- FIG. 12A is a photograph of an optical microscope after the heat treatment in and around the region Ab into which impurity ions are implanted
- FIG. 12B is a Raman diagram at a portion Xc in FIG. It is a spectrum. Then, as shown in FIG. 12B, the Xc portion at the inner peripheral end of the implantation region Ab is close to the spectral shape of amorphous silicon, so that the crystallinity recovery by the heat treatment is insufficient. Inferred.
- the crystallinity recovery of the portion in contact with the non-implantation region is fast, and the crystallinity recovery of the central portion away from the non-implantation region is slow. It is found that the crystallinity recovery is promoted when the crystallinity of the starting point is high.
- the polysilicon layer has the P-type semiconductor region and the N-type as described above. Since at least one of the semiconductor regions has a portion on the glass substrate side where the collapse of crystallinity is suppressed, the glass substrate side becomes a starting point for the recovery of crystallinity, and the recovery of crystallinity is promoted. For this reason, the crystallinity of at least one of the P-type semiconductor region and the N-type semiconductor region of the polysilicon layer becomes as high as possible, so that the crystallinity of the junction portion of the polysilicon layer becomes as high as possible. Therefore, the crystallinity of the junction can be increased as much as possible, and the diode characteristics can be improved.
- the concentration of impurity ions on the surface of the polysilicon layer on the glass substrate side is along the thickness direction of impurity ions in the polysilicon layer and the insulating film. It may be 1/10 or less of the maximum value of density.
- the concentration of impurity ions on the surface of the polysilicon layer on the glass substrate side is in the thickness direction of the impurity ions in the polysilicon layer and the insulating film. Since it is 1/10 or less of the maximum value of the concentration along the line, the concentration along the thickness direction of the impurity ions in the polysilicon layer is specifically minimized on the surface on the glass substrate side.
- An I-type semiconductor region that is not doped with impurity ions may be provided between the P-type semiconductor region and the N-type semiconductor region.
- the I-type semiconductor region is provided between the P-type semiconductor region and the N-type semiconductor region, a PIN structure diode is specifically configured, and an optical sensor element with good response is obtained. Can be realized.
- the other polysilicon layer may be provided in the same layer as the polysilicon layer, and the other polysilicon layer may constitute a part of the thin film transistor.
- the thin film transistor can be used as a driver for reading the current value of the thin film diode that functions as the photosensor element.
- the method for manufacturing a thin film diode according to the present invention includes a polysilicon layer forming step of forming a polysilicon layer on a glass substrate, an insulating film forming step of forming an insulating film so as to cover the polysilicon layer, and the insulating Doping impurity ions into the polysilicon layer through the film to form a P-type semiconductor region, and doping the impurity ions into the polysilicon layer through the insulating film, N N-type semiconductor region forming step for forming a semiconductor region, and heating the glass substrate on which the P-type semiconductor region and the N-type semiconductor region are formed, thereby recovering the crystallinity of the polysilicon layer and the doping
- a method of manufacturing a thin film diode comprising a heating step of activating activated impurity ions, the P-type semiconductor region forming step and the N-type semiconductor region type In at least one of the steps, the impurity is adjusted such that the concentration of impurity ions in the polysilicon
- the concentration along the thickness direction of the impurity ions in the polysilicon layer and the insulating film is the thickness direction of the polysilicon layer. Since the impurity ions are doped so as to be maximized on the insulating film side with respect to the intermediate position, the concentration of impurity ions in the polysilicon layer along the thickness direction is at least one of the P-type semiconductor region and the N-type semiconductor region. Is minimized on the surface of the glass substrate side, and the collapse of the crystallinity of the polysilicon layer on the glass substrate side is suppressed.
- FIG. 9A is a photograph of the optical microscope before the heat treatment in the region Aa into which the impurity ions are implanted and the periphery thereof
- FIG. 9B shows the X portion in FIG. It is a Raman spectrum in the Y part.
- the Y portion of the non-implanted region has a sharp peak attributed to polysilicon in the vicinity of a wave number of 520 cm ⁇ 1 , so that the crystallinity is good and the implanted region Aa In the X portion at the center of the film, it almost matches the spectral shape of amorphous silicon. Therefore, it is presumed that the crystallinity of polysilicon is destroyed by the implantation of impurity ions.
- FIG. 10A is a photograph of an optical microscope after the heat treatment in the region Aa into which the impurity ions are implanted and the periphery thereof
- FIG. 10B shows the Xa portion and Xb in FIG. It is a Raman spectrum in a part and a Xc part.
- the Xc portion at the inner peripheral end of the implantation region Aa has a sharp peak attributed to polysilicon in the vicinity of the wave number of 520 cm ⁇ 1 , so that the crystallinity is recovered. It is inferred that
- the acceleration voltage is relatively low (for example, so that the concentration of impurity ions in the polysilicon layer along the thickness direction is maximized on the insulating film side of the polysilicon layer). 20 keV), the polysilicon layer region Aa is doped with impurity ions.
- the acceleration voltage is relatively set so that the concentration of impurity ions in the polysilicon layer along the thickness direction becomes maximum on the glass substrate side of the polysilicon layer. Therefore, the region Ab of the polysilicon layer is doped with impurity ions.
- FIG. 11 and 12 the acceleration voltage is relatively set so that the concentration of impurity ions in the polysilicon layer along the thickness direction becomes maximum on the glass substrate side of the polysilicon layer. Therefore, the region Ab of the polysilicon layer is doped with impurity ions.
- FIG. 11A is a photograph of the optical microscope before the heat treatment in the region Ab in which the impurity ions are implanted and the periphery thereof, and FIG. 11B shows the X portion in FIG. It is a Raman spectrum in the Y part.
- FIG. 12A is a photograph of an optical microscope after the heat treatment in and around the region Ab into which impurity ions are implanted
- FIG. 12B is a Raman diagram at a portion Xc in FIG. It is a spectrum. Then, as shown in FIG. 12B, the Xc portion at the inner peripheral end of the implantation region Ab is close to the spectral shape of amorphous silicon, so that the crystallinity recovery by the heat treatment is insufficient. Inferred.
- the crystallinity of the portion in contact with the non-implanted region is recovered quickly, and the recovery of the crystallinity of the central portion away from the non-implanted region is delayed. It is found that the crystallinity recovery is promoted when the crystallinity of the starting point is high.
- the polysilicon layer has the P-type semiconductor region and the N-type semiconductor as described above.
- the glass substrate side has a portion in which the collapse of the crystallinity is suppressed, so that the glass substrate side becomes a starting point for the recovery of crystallinity in the heating step, and the recovery of the crystallinity is promoted.
- the crystallinity of at least one of the P-type semiconductor region and the N-type semiconductor region of the polysilicon layer becomes as high as possible, so that the crystallinity of the junction portion of the polysilicon layer becomes as high as possible. Therefore, the crystallinity of the junction can be increased as much as possible, and the diode characteristics can be improved.
- the concentration of impurity ions in the polysilicon layer and the insulating film along the thickness direction is higher than the intermediate position in the thickness direction of the polysilicon layer.
- the acceleration voltage at the time of doping the impurity ions may be set low so as to be maximized on the insulating film side.
- the concentration of impurity ions in the polysilicon layer along the thickness direction is specifically minimized on the glass substrate side surface.
- the concentration of impurity ions in the polysilicon layer and the insulating film along the thickness direction is increased in at least one of the region to be the P-type semiconductor region and the region to be the N-type semiconductor region.
- the insulating film may be formed thick so as to be maximum on the insulating film side with respect to the intermediate position in the thickness direction of the silicon layer.
- the concentration along the thickness direction of impurity ions in the polysilicon layer is specifically minimized on the glass substrate side surface in at least one of the P-type semiconductor region and the N-type semiconductor region.
- the concentration along the thickness direction of the impurity ions in the polysilicon layer and the insulating film is at least one of the region to be the P-type semiconductor region and the region to be the N-type semiconductor region.
- the polysilicon layer may be formed thick so as to be maximum on the insulating film side with respect to the intermediate position in the thickness direction of the polysilicon layer.
- the concentration of impurity ions in the polysilicon layer along the thickness direction is specifically minimized on the surface on the glass substrate side.
- the concentration along the thickness direction of the impurity ions in the polysilicon layer and the insulating film is higher than the intermediate position in the thickness direction of the polysilicon layer. Since it is maximized on the insulating film side, the crystallinity of the junction can be increased as much as possible, and the diode characteristics can be improved.
- FIG. 1 is a plan view schematically showing a liquid crystal display device 50 according to an embodiment of the present invention.
- FIG. 2 is a cross-sectional view of the TFD 21 and the TFT 22 that constitute the liquid crystal display device 50.
- FIG. 3 is a cross-sectional view schematically showing an ion implantation profile C in the TFD 21.
- FIG. 4 is a cross-sectional view schematically showing another ion implantation profile C in the TFD 21.
- FIG. 5 is a cross-sectional view showing a process of forming the TFD 21 and the TFT 22 constituting the liquid crystal display device 50.
- FIG. 6 is a cross-sectional view schematically showing the direction of crystal recovery in TFD 21.
- FIG. 1 is a plan view schematically showing a liquid crystal display device 50 according to an embodiment of the present invention.
- FIG. 2 is a cross-sectional view of the TFD 21 and the TFT 22 that constitute the liquid crystal display device 50.
- FIG. 3 is a cross-
- FIG. 7 is a graph showing the relationship between dark current and anode / cathode voltage in TFD.
- FIG. 8 is a graph showing the relationship between the light / dark current ratio and the anode / cathode voltage in TFD.
- FIG. 9 is a photograph (a) and a Raman spectrum (b) of the optical microscope before the heat treatment in the region Aa into which the impurity ions are implanted and the periphery thereof.
- FIG. 10 is a photograph (a) of the optical microscope after the heat treatment in the region Aa into which the impurity ions are implanted and the periphery thereof, and the Raman spectrum (b) thereof.
- FIG. 11 is a photograph (a) of the optical microscope before the heat treatment in the region Ab in which the impurity ions are implanted and the periphery thereof, and the Raman spectrum (b) thereof.
- FIG. 12 is a photograph (a) and a Raman spectrum (b) of an optical microscope after heat treatment in and around the region Ab into which impurity ions are implanted.
- FIG. 13 is a cross-sectional view schematically showing a conventional TFD 121.
- FIG. 1 is a plan view schematically showing a liquid crystal display device 50 of the present embodiment
- FIG. 2 is a cross-sectional view of a TFD 21 and a TFT 22 constituting the liquid crystal display device 50
- 3 is a cross-sectional view schematically showing an ion implantation profile C in the TFD
- FIG. 4 is a cross-sectional view schematically showing another ion implantation profile C in the TFD 21.
- the liquid crystal display device 50 includes a TFT substrate 30, a CF substrate (not shown) disposed to face the TFT substrate 30, and a liquid crystal layer provided between the TFT substrate 30 and the CF substrate. And a sealing material (not shown) provided in a frame shape for adhering the TFT substrate 30 and the CF substrate to each other and enclosing a liquid crystal layer between the TFT substrate and the CF substrate.
- a plurality of pixels P are provided in a matrix.
- each pixel P performs image display in which a pixel region R that performs red display, a pixel region G that performs green display, and a pixel region B that performs blue display are vertically arranged in a line.
- a display area D and a sensor area S adjacent to the display area D for detecting a touched position are provided.
- Each pixel region R, G, and B includes a pixel electrode 20 and a TFT 22 connected to the pixel electrode 20, as shown in FIG.
- a gate line (not shown) is provided around the pixel electrode 20 so as to extend along the upper side (or lower side) in the drawing, and the source extends so as to extend along the left side (or right side) in the drawing.
- a line (not shown) is provided.
- the TFT 22 includes a polysilicon layer 12b provided on the glass substrate 10 via the base coat film 11, a gate insulating film 13 provided so as to cover the polysilicon layer 12b, and a gate insulating film. 13 and a gate electrode 14 connected to the gate line.
- the polysilicon layer 12b includes a source region 12bs connected to the source line, a drain region 12bd connected to the pixel electrode 20, and a gate electrode 14 between the source region 12bs and the drain region 12bd. And a channel region 12bi provided so as to overlap.
- each sensor region S includes a TFD 21 provided as an optical sensor element, and a capacitor 23 connected to the TFD 21.
- the capacitor 23 is charged by applying a voltage for a predetermined time in the forward direction of the TFD 21, and when light L enters the TFD 21, current leaks from the capacitor 23 and the potential of the capacitor 23 decreases. Therefore, the incidence of the light L is detected by measuring the voltage of the capacitor 23 after a predetermined time.
- the TFD 21 includes a polysilicon layer 12a provided on the glass substrate 10 via a base coat film 11, and a gate insulating film 13 provided so as to cover the polysilicon layer 12a. .
- the polysilicon layer 12a includes, for example, an anode P-type semiconductor region 12ap doped with boron ions as a high impurity concentration, and a cathode N-type semiconductor doped with phosphorus ions as a high impurity concentration.
- a PIN structure diode is configured by including a region 12an and an I-type semiconductor region 12ai in which no impurity is doped between the P-type semiconductor region 12ap and the N-type semiconductor region 12an.
- the concentration of impurity ions in the polysilicon layer 12a and the gate insulating film 13 along the thickness direction It is the maximum on the gate insulating film 13 side than the middle position in the thickness direction.
- the maximum concentration points along the thickness direction of the impurity ions in the polysilicon layer 12a and the gate insulating film 13 are in the gate insulating film 13 as shown in FIG. b), the interface between the N-type semiconductor region 12an (polysilicon layer 12a) and the gate insulating film 13, or as shown in FIG. 4C, the N-type semiconductor region 12an (polysilicon layer 12a).
- the concentration of impurity ions on the surface of the polysilicon layer 12a on the glass substrate 10 side is the maximum concentration value along the thickness direction of impurity ions in the polysilicon layer 12a and the gate insulating film 13 ( For example, it is preferably 1/10 or less of 1 ⁇ 10 +20 / cm 3 to 1 ⁇ 10 +21 / cm 3 ).
- the CF substrate includes a red layer (not shown) provided so as to overlap the pixel region R of the TFT substrate 30, a green layer (not shown) provided so as to overlap the pixel region G, and a pixel region B. Between the blue layer (not shown) provided so as to overlap with the transparent layer (not shown) provided so as to overlap with the sensor region S, and between the red layer, the green layer, the blue layer and the transparent layer.
- the liquid crystal layer is made of a nematic liquid crystal material having electro-optical characteristics.
- the liquid crystal display device 50 configured as described above transmits, for example, light incident from a backlight by applying a predetermined voltage to the liquid crystal layer between the TFT substrate 30 and the CF substrate for each of the pixel regions R, G, and B.
- the rate is adjusted to display an image, and the display screen is touched to change the amount of light received by the TFD 21 provided in each sensor region S. Based on the voltage value of the capacitor 23 at that time, The touched position is configured to be detected.
- FIG. 5 is a cross-sectional view showing a process of forming the TFD 21 and the TFT 22 constituting the liquid crystal display device 50
- FIG. 6 is a cross-sectional view schematically showing a crystal recovery direction in the TFD 21.
- the manufacturing method of this embodiment includes a polysilicon layer forming step, a gate insulating film forming step, a gate electrode forming step, an N-type semiconductor region forming step, a P-type semiconductor region forming step, and a heating step.
- a silicon oxide film is formed on the entire glass substrate 10 by a plasma CVD (Chemical Vapor Deposition) method to form the base coat film 11.
- an amorphous silicon film (for example, about 50 nm in thickness) is formed on the entire substrate by plasma CVD using disilane or the like as a source gas, and then by laser light irradiation or the like. Heat treatment is performed to transform the film into a polysilicon film. Thereafter, the polysilicon film is patterned by photolithography to form polysilicon layers 12pa and 12pb as shown in FIG.
- a silicon oxide film (for example, a thickness of about 30 nm) is formed by plasma CVD on the entire substrate on which the polysilicon layers 12pa and 12pb have been formed in the polysilicon layer forming step, and the gate insulating film 13 is formed. .
- ⁇ Gate electrode formation process> A tantalum nitride film and a tungsten film are sequentially formed by sputtering on the entire substrate on which the gate insulating film 13 has been formed in the gate insulating film forming step, and then patterned by photolithography, as shown in FIG. As shown, a gate electrode 14 is formed.
- a photosensitive resin is applied to the entire substrate on which the gate electrode 14 has been formed in the gate electrode formation step by spin coating, and then partially exposed and developed to form a photoresist 15 (FIG. 5). (See (c)).
- the polysilicon layers 12pa and 12pb are doped into the polysilicon layers 12pa and 12pb through the gate insulating film 13 with, for example, phosphorus ions as impurity ions at a predetermined acceleration voltage (for example, 20 keV) (for example, , Average doping amount: 8 ⁇ 10 +14 / cm 2 ), as shown in FIG. 5C, in the polysilicon layer 12pb, the channel region 12bi overlaps the gate electrode 14 and the source region 12bs outside thereof. Then, the drain region 12db is formed, and the N-type semiconductor region 12an is formed in the polysilicon layer 12pa in the portion exposed from the photoresist 15.
- a predetermined acceleration voltage for example, 20 keV
- the channel region 12bi overlaps the gate electrode 14 and the source region 12bs outside thereof.
- the drain region 12db is formed, and the N-type semiconductor region 12an is formed in the polysilicon layer 12pa in the portion exposed from the photoresist
- ⁇ P-type semiconductor region forming process First, after removing the photoresist 15 from the substrate on which the N-type semiconductor region 12an and the like are formed in the N-type semiconductor region forming step, a photosensitive resin is applied to the entire substrate by a spin coat method, and then partially. The photoresist 16 is formed by exposing and developing (see FIG. 5D).
- the polysilicon layer 12pa is doped with, for example, boron ions as impurity ions through the gate insulating film 13, thereby forming a polysilicon layer as shown in FIG.
- a P-type semiconductor region 12 ap is formed in a portion exposed from the photoresist 16.
- the substrate After removing the photoresist 16 from the substrate on which the P-type semiconductor region 12ap is formed in the P-type semiconductor region forming step, the substrate is heated at 550 ° C. for 1 hour to change the crystallinity of the polysilicon layers 12a and 12b.
- the impurity ions doped in the N-type semiconductor region forming step and the P-type semiconductor region forming step are activated.
- the crystallinity of the polysilicon layer 12a recovers from the glass substrate 10 side where the impurity ion doping amount is relatively small and the crystallinity collapse is suppressed, as shown in FIG. Middle arrow).
- the TFD 21 and the TFT 22 of this embodiment can be manufactured. After that, an inorganic insulating film is formed so as to cover the TFD 21 and the TFT 22, a contact hole is formed in the inorganic insulating film, a source line is formed, and an organic insulating film is formed so as to cover the source line, etc.
- the TFT substrate 30 can be manufactured by forming the pixel electrode 20 after forming the contact hole in the organic insulating film, and forming the alignment film so as to cover the pixel electrode 20.
- FIG. 7 is a graph showing the relationship between the dark current and the anode / cathode voltage in TFD
- FIG. 8 is a graph showing the relationship between the light / dark current ratio and the anode / cathode voltage in TFD. is there.
- a TFD is manufactured by the above-described manufacturing method, and as a comparative example of the present invention, the acceleration voltage when doping phosphorus ions in the above-described manufacturing method is 35 keV (conventional conditions).
- TFDs were manufactured by setting the average doping amount to 3 ⁇ 10 +14 / cm 2, and their diode characteristics were evaluated.
- the relationship between the dark current (0 lx) and the anode / cathode voltage in each TFD was evaluated.
- the concentration of impurity ions in the polysilicon layer 12a and the gate insulating film 13 in the thickness direction in the N-type semiconductor region forming step is polysilicon. Since the impurity ions are doped so as to be maximum on the gate insulating film 13 side with respect to the intermediate position in the thickness direction of the layer 12a, in the N-type semiconductor region 12an, along the thickness direction of the impurity ions in the polysilicon layer 12a. The concentration is minimized on the surface on the glass substrate 10 side, and the collapse of crystallinity on the glass substrate 10 side of the polysilicon layer 12a is suppressed.
- the crystallinity recovery of the portion in contact with the non-implantation region is fast, and the crystallinity recovery of the central portion away from the non-implantation region is slow.
- the polysilicon layer 12a has a portion in which the collapse of the crystallinity is suppressed on the glass substrate 10 side in the N-type semiconductor region 12an, so that the glass substrate 10 side becomes a starting point for the recovery of the crystallinity in the heating step. Recovery is promoted.
- the crystallinity of the N-type semiconductor region 12an of the polysilicon layer 12a is as high as possible, the crystallinity of the junction of the polysilicon layer 12a can be as high as possible. Therefore, the crystallinity of the junction can be increased as much as possible, and the diode characteristics can be improved.
- the acceleration voltage when doping phosphorus ions is set low, and a method of forming a portion in which the collapse of crystallinity is suppressed on the glass substrate 10 side of the polysilicon layer 12a is exemplified.
- the thickness of the polysilicon layer is increased from, for example, 50 nm to 60 nm, or the thickness of the portion of the gate insulating film that overlaps the TFD is, for example, 20 nm thicker than the thickness of the portion that overlaps the TFT.
- a portion in which the collapse of crystallinity is suppressed may be formed on the glass substrate side of the polysilicon layer.
- the configuration in which the TFT 22 is provided as the switching element in each of the pixel regions R, G, and B is illustrated.
- the TFT is charged with a circuit for charging the capacitor 23 in each sensor region S or for reading. It may be used for drivers.
- this invention is crystalline on the glass substrate side of P type semiconductor region. It may be a configuration having a portion in which the collapse of the crystal is suppressed, or a configuration having a portion in which the collapse of crystallinity is suppressed on the glass substrate side of both the N-type semiconductor region and the P-type semiconductor region. .
- the TFD 21 provided on the glass substrate 10 is exemplified, but the present invention can also be applied to a TFD provided on another substrate such as a plastic substrate or a stainless steel substrate.
- the present invention can improve the diode characteristics of TFD, and thus is useful for a display device, a touch panel, an image sensor, and the like provided with TFD.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
まず、ガラス基板10の基板全体に、プラズマCVD(Chemical Vapor Deposition)法により、例えば、酸化シリコン膜を成膜して、ベースコート膜11を形成する。
上記ポリシリコン層形成工程でポリシリコン層12pa及び12pbが形成された基板全体に、プラズマCVD法により、酸化シリコン膜(例えば、厚さ30nm程度)を成膜して、ゲート絶縁膜13を形成する。
上記ゲート絶縁膜形成工程でゲート絶縁膜13が形成された基板全体に、スパッタリング法により、窒化タンタル膜及びタングステン膜を順次成膜し、その後、フォトリソグラフィによりパターニングして、図5(b)に示すように、ゲート電極14を形成する。
まず、上記ゲート電極形成工程でゲート電極14が形成された基板全体に、スピンコート法により、感光性樹脂を塗布した後に、部分的に露光及び現像して、フォトレジスト15を形成する(図5(c)参照)。
まず、上記N型半導体領域形成工程でN型半導体領域12anなどが形成された基板からフォトレジスト15を除去した後に、その基板全体に、スピンコート法により、感光性樹脂を塗布した後に、部分的に露光及び現像して、フォトレジスト16を形成する(図5(d)参照)。
上記P型半導体領域形成工程でP型半導体領域12apが形成された基板からフォトレジスト16を除去した後に、その基板を550℃で1時間、加熱して、ポリシリコン層12a及び12bの結晶性を回復させると共に、上記N型半導体領域形成工程及びP型半導体領域形成工程でドープされた不純物イオンを活性化する。ここで、加熱工程において、ポリシリコン層12aの結晶性は、図6に示すように、不純物イオンのドープ量が相対的に少なく結晶性の崩壊が抑制されたガラス基板10側から回復する(図中矢印参照)。
12a,12b ポリシリコン層
12ai I型半導体領域
12an N型半導体領域
12ap P型半導体領域
13 ゲート絶縁膜
21 TFD
22 TFT
Claims (8)
- ガラス基板と、
上記ガラス基板に設けられ、各々、不純物イオンがドープされたP型半導体領域及びN型半導体領域を同一平面に有するポリシリコン層と、
上記ポリシリコン層を覆うように設けられた絶縁膜とを備えた薄膜ダイオードであって、
上記P型半導体領域及びN型半導体領域の少なくとも一方において、上記ポリシリコン層及び絶縁膜における不純物イオンの厚さ方向に沿った濃度は、上記ポリシリコン層の厚さ方向の中間位置よりも上記絶縁膜側で最大になっていることを特徴とする薄膜ダイオード。 - 請求項1に記載された薄膜ダイオードにおいて、
上記P型半導体領域及びN型半導体領域の少なくとも一方において、上記ポリシリコン層の上記ガラス基板側の面における不純物イオンの濃度は、上記ポリシリコン層及び絶縁膜における不純物イオンの厚さ方向に沿った濃度の最大値の1/10以下であることを特徴とする薄膜ダイオード。 - 請求項1又は2に記載された薄膜ダイオードにおいて、
上記P型半導体領域及びN型半導体領域の間には、不純物イオンがドープされていないI型半導体領域が設けられていることを特徴とする薄膜ダイオード。 - 請求項1乃至3の何れか1つに記載された薄膜ダイオードにおいて、
上記ポリシリコン層と同一層に他のポリシリコン層を有し、
上記他のポリシリコン層は、薄膜トランジスタの一部を構成していることを特徴とする薄膜ダイオード。 - ガラス基板にポリシリコン層を形成するポリシリコン層形成工程と、
上記ポリシリコン層を覆うように絶縁膜を形成する絶縁膜形成工程と、
上記絶縁膜を介して上記ポリシリコン層に不純物イオンをドープして、P型半導体領域を形成するP型半導体領域形成工程と、
上記絶縁膜を介して上記ポリシリコン層に不純物イオンをドープして、N型半導体領域を形成するN型半導体領域形成工程と、
上記P型半導体領域及びN型半導体領域が形成されたガラス基板を加熱することにより、上記ポリシリコン層の結晶性を回復させると共に、上記ドープされた不純物イオンを活性化する加熱工程とを備える薄膜ダイオードの製造方法であって、
上記P型半導体領域形成工程及びN型半導体領域形成工程の少なくとも一方では、上記ポリシリコン層及び絶縁膜における不純物イオンの厚さ方向に沿った濃度が上記ポリシリコン層の厚さ方向の中間位置よりも上記絶縁膜側で最大になるように、不純物イオンをドープすることを特徴とする薄膜ダイオードの製造方法。 - 請求項5に記載された薄膜ダイオードの製造方法において、
上記P型半導体領域形成工程及びN型半導体領域形成工程の少なくとも一方では、上記ポリシリコン層及び絶縁膜における不純物イオンの厚さ方向に沿った濃度が上記ポリシリコン層の厚さ方向の中間位置よりも上記絶縁膜側で最大になるように、上記不純物イオンをドープする際の加速電圧を低く設定することを特徴とする薄膜ダイオードの製造方法。 - 請求項5に記載された薄膜ダイオードの製造方法において、
上記絶縁膜形成工程では、上記P型半導体領域となる領域、及びN型半導体領域となる領域の少なくとも一方において、上記ポリシリコン層及び絶縁膜における不純物イオンの厚さ方向に沿った濃度が上記ポリシリコン層の厚さ方向の中間位置よりも上記絶縁膜側で最大になるように、上記絶縁膜を厚く形成することを特徴とする薄膜ダイオードの製造方法。 - 請求項5に記載された薄膜ダイオードの製造方法において、
上記ポリシリコン層形成工程では、上記P型半導体領域となる領域、及びN型半導体領域となる領域の少なくとも一方において、上記ポリシリコン層及び絶縁膜における不純物イオンの厚さ方向に沿った濃度が上記ポリシリコン層の厚さ方向の中間位置よりも上記絶縁膜側で最大になるように、上記ポリシリコン層を厚く形成することを特徴とする薄膜ダイオードの製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2009801439206A CN102203922A (zh) | 2009-01-20 | 2009-08-26 | 薄膜二极管及其制造方法 |
US13/126,562 US20110204374A1 (en) | 2009-01-20 | 2009-08-26 | Thin film diode and method for fabricating the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009-010164 | 2009-01-20 | ||
JP2009010164 | 2009-01-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010084534A1 true WO2010084534A1 (ja) | 2010-07-29 |
Family
ID=42355613
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2009/004123 WO2010084534A1 (ja) | 2009-01-20 | 2009-08-26 | 薄膜ダイオード及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20110204374A1 (ja) |
CN (1) | CN102203922A (ja) |
WO (1) | WO2010084534A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5905654B1 (ja) * | 2014-10-15 | 2016-04-20 | 株式会社フローディア | 半導体集積回路装置の製造方法、および半導体集積回路装置 |
JP5951096B1 (ja) * | 2015-10-01 | 2016-07-13 | 株式会社フローディア | 不揮発性半導体記憶装置 |
JP5951097B1 (ja) * | 2015-10-28 | 2016-07-13 | 株式会社フローディア | 不揮発性半導体記憶装置 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101735587B1 (ko) * | 2010-09-06 | 2017-05-25 | 삼성디스플레이 주식회사 | 포토 센서, 포토 센서 제조 방법 및 표시 장치 |
JP2015046502A (ja) * | 2013-08-28 | 2015-03-12 | 住友電気工業株式会社 | 炭化珪素半導体装置およびその製造方法 |
WO2020154981A1 (zh) * | 2019-01-30 | 2020-08-06 | 深圳市柔宇科技有限公司 | 阵列基板及其制造方法、显示面板 |
US11843022B2 (en) * | 2020-12-03 | 2023-12-12 | Sharp Kabushiki Kaisha | X-ray imaging panel and method of manufacturing X-ray imaging panel |
US11916094B2 (en) * | 2021-08-02 | 2024-02-27 | Sharp Display Technology Corporation | Photoelectric conversion panel and method for manufacturing photoelectric conversion panel |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02114672A (ja) * | 1988-10-25 | 1990-04-26 | Ricoh Co Ltd | 半導体装置 |
JPH10256557A (ja) * | 1997-03-14 | 1998-09-25 | Toshiba Corp | 薄膜トランジスタおよび液晶表示装置 |
JP2000299454A (ja) * | 1993-03-22 | 2000-10-24 | Semiconductor Energy Lab Co Ltd | 半導体回路 |
JP2005079319A (ja) * | 2003-08-29 | 2005-03-24 | Mitsubishi Electric Corp | 半導体装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5501989A (en) * | 1993-03-22 | 1996-03-26 | Semiconductor Energy Laboratory Co., Ltd. | Method of making semiconductor device/circuit having at least partially crystallized semiconductor layer |
US5844256A (en) * | 1995-04-17 | 1998-12-01 | Seiko Epson Corporation | Semiconductor device comprising polysilicon interconnection layers separated by insulation films |
JP2005043672A (ja) * | 2003-07-22 | 2005-02-17 | Toshiba Matsushita Display Technology Co Ltd | アレイ基板およびその製造方法 |
-
2009
- 2009-08-26 WO PCT/JP2009/004123 patent/WO2010084534A1/ja active Application Filing
- 2009-08-26 CN CN2009801439206A patent/CN102203922A/zh active Pending
- 2009-08-26 US US13/126,562 patent/US20110204374A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02114672A (ja) * | 1988-10-25 | 1990-04-26 | Ricoh Co Ltd | 半導体装置 |
JP2000299454A (ja) * | 1993-03-22 | 2000-10-24 | Semiconductor Energy Lab Co Ltd | 半導体回路 |
JPH10256557A (ja) * | 1997-03-14 | 1998-09-25 | Toshiba Corp | 薄膜トランジスタおよび液晶表示装置 |
JP2005079319A (ja) * | 2003-08-29 | 2005-03-24 | Mitsubishi Electric Corp | 半導体装置 |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5905654B1 (ja) * | 2014-10-15 | 2016-04-20 | 株式会社フローディア | 半導体集積回路装置の製造方法、および半導体集積回路装置 |
WO2016060013A1 (ja) * | 2014-10-15 | 2016-04-21 | 株式会社フローディア | 半導体集積回路装置の製造方法、および半導体集積回路装置 |
CN106796940A (zh) * | 2014-10-15 | 2017-05-31 | 株式会社佛罗迪亚 | 半导体集成电路装置的制造方法及半导体集成电路装置 |
JP5951096B1 (ja) * | 2015-10-01 | 2016-07-13 | 株式会社フローディア | 不揮発性半導体記憶装置 |
WO2017057242A1 (ja) * | 2015-10-01 | 2017-04-06 | 株式会社フローディア | 不揮発性半導体記憶装置 |
JP5951097B1 (ja) * | 2015-10-28 | 2016-07-13 | 株式会社フローディア | 不揮発性半導体記憶装置 |
WO2017073394A1 (ja) * | 2015-10-28 | 2017-05-04 | 株式会社フローディア | 不揮発性半導体記憶装置 |
CN108352386A (zh) * | 2015-10-28 | 2018-07-31 | 株式会社佛罗迪亚 | 非易失性半导体存储装置 |
CN108352386B (zh) * | 2015-10-28 | 2021-06-25 | 株式会社佛罗迪亚 | 非易失性半导体存储装置 |
Also Published As
Publication number | Publication date |
---|---|
CN102203922A (zh) | 2011-09-28 |
US20110204374A1 (en) | 2011-08-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2010084534A1 (ja) | 薄膜ダイオード及びその製造方法 | |
US8097927B2 (en) | Highly sensitive photo-sensing element and photo-sensing device using the same | |
JP4446292B2 (ja) | 光子感知エレメント及びこれを用いたデバイス | |
US8735893B2 (en) | Visible sensing transistor, display panel and manufacturing method thereof | |
WO2017128575A1 (zh) | Ltps阵列基板的制作方法 | |
WO2017092142A1 (zh) | 低温多晶硅tft基板的制作方法 | |
TWI478330B (zh) | 光電變換元件及其製造方法 | |
KR20120063928A (ko) | 미세 결정 실리콘 박막 트랜지스터와 이를 포함하는 표시장치 및 그 제조 방법 | |
GB2548759A (en) | Array substrate, display panel, and manufacturing method for array substrate | |
US20100193848A1 (en) | Image sensor of stacked layer structure and manufacturing method thereof | |
JP2006332287A (ja) | 薄膜ダイオード | |
CN112713161A (zh) | 一种阵列基板及其制备方法 | |
US7176074B1 (en) | Manufacturing method of thin film transistor array substrate | |
CN112259556A (zh) | 阵列基板及其制备方法 | |
US8093596B2 (en) | Pixel structure | |
WO2021184430A1 (zh) | 感光传感器及其制备方法、显示面板 | |
CN113629069B (zh) | 阵列基板及制备方法、光探测器 | |
JP3163844B2 (ja) | 逆スタガード型薄膜電界効果トランジスタの製造方法 | |
US20120270365A1 (en) | Method for manufacturing solar cell | |
US6731352B2 (en) | Method for fabricating liquid crystal display | |
KR20120079724A (ko) | 포토센서 및 그의 제조방법 | |
JP4811397B2 (ja) | 受光素子および表示装置 | |
KR20150089299A (ko) | 디스플레이 소자, 그 제조 방법, 및 이미지 센서 소자의 제조방법 | |
CN110600424B (zh) | 阵列基板的制备方法及阵列基板 | |
US20160093660A1 (en) | Semiconductor apparatus and method of manufacturing semiconductor apparatus |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980143920.6 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09838728 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13126562 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 09838728 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: JP |