WO2016095321A1 - 栅极驱动电路、阵列基板及显示装置 - Google Patents

栅极驱动电路、阵列基板及显示装置 Download PDF

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Publication number
WO2016095321A1
WO2016095321A1 PCT/CN2015/071245 CN2015071245W WO2016095321A1 WO 2016095321 A1 WO2016095321 A1 WO 2016095321A1 CN 2015071245 W CN2015071245 W CN 2015071245W WO 2016095321 A1 WO2016095321 A1 WO 2016095321A1
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Prior art keywords
pull
circuit
scan line
reference point
transistor
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Ceased
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PCT/CN2015/071245
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English (en)
French (fr)
Inventor
曹尚操
戴超
李长晔
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/418,598 priority Critical patent/US9704437B2/en
Publication of WO2016095321A1 publication Critical patent/WO2016095321A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections

Definitions

  • the present invention relates to the field of display technologies, and in particular to a gate driving circuit, an array substrate, and a display device.
  • a Thin Film Transistor is generally used to drive each pixel unit.
  • the gate driver circuit for driving the thin film transistor can be fabricated on the array substrate by using the Gate Driver on Array (GOA) technology to replace the original external integrated circuit, thereby reducing the soldering process of the external integrated circuit.
  • GOA Gate Driver on Array
  • the present invention provides a gate driving circuit for outputting a gate driving signal to an nth scanning line
  • the gate driving circuit includes a pull-up circuit, a down transistor, and a pull-down circuit
  • the pull-up circuit is configured to output a high potential to a reference point in the gate driving circuit, a first input end of the pull-up circuit is connected to an n-1th scan line, and a second input end of the pull-up circuit is Connecting the n-2th scan line, the output end of the pull-up circuit is connected to the reference point;
  • a gate of the pass transistor is connected to the reference point, and a source of the down transistor is connected to a clock signal line.
  • the drain of the lower pass transistor is connected to the nth scan line, and when the reference point and the clock signal line are both high, the drain of the down pass transistor outputs a high potential to the nth scan line;
  • the pull-down circuit is configured to output a low potential to the reference point and the nth scan line, the first input end of the pull-down circuit is connected to the n+1th scan line, and the output end of the pull-down circuit is connected to the reference point.
  • the gate driving circuit further includes a coupling capacitor connected between the reference point and the nth scan line.
  • the pull-up circuit includes a first transistor and a second transistor;
  • the gate of the first transistor is connected to the n-1th scan line, the source is connected to the first signal line, and the drain is connected to the reference point;
  • the gate of the second transistor is connected to the n-2th scan line, the source is connected to the first signal line, and the drain is connected to the reference point.
  • the pull-down circuit is further provided with a second input end, and the second input end of the pull-down circuit is connected to the n+2th scan line.
  • the pull-down circuit includes a third transistor and a fourth transistor;
  • the gate of the third transistor is connected to the n+1th scanning line, the source is connected to the second signal line, and the drain is connected to the reference point;
  • the gate of the fourth transistor is connected to the n+2th scan line, the source is connected to the second signal line, and the drain is connected to the reference point.
  • the first signal line outputs a high potential
  • the second signal line outputs a low potential
  • the first signal line outputs a low potential
  • the second signal line outputs a high potential
  • the gate driving circuit further includes a first pull-down maintaining circuit and a second pull-down maintaining circuit
  • the first pull-down maintaining circuit is configured to maintain a low potential of the reference point and the nth scan line during forward scanning
  • the second pull-down maintaining circuit is configured to maintain a low potential of the reference point and the nth scan line during reverse scanning.
  • the present invention also provides an array substrate comprising a plurality of cascaded gate drive circuits, each of which is configured to output a gate drive signal to a scan line.
  • the sources of the downstream transistors of the respective gate driving circuits are respectively connected to the four clock signal lines in one-to-one correspondence, and the four clock signal lines sequentially output a high potential.
  • the present invention also provides a display device comprising the above array substrate.
  • the pull-up circuit has a first input end and a second input end, respectively connecting the n-1th scan line and the n-2th scan line .
  • the first charging can be performed by the pull-up circuit as the reference point (ie, the gate of the downstream transistor); the gate driving is outputted at the n-1th scanning line
  • the reference point can be charged a second time by the pull-up circuit.
  • the reference point Since the reference point is charged twice, the reference point can reach a higher potential.
  • the clock signal line is at a high potential and the drain output of the down transistor is outputting the gate drive signal
  • the potential difference Vgs between the gate and the source of the down transistor can be significantly increased to reduce the output impedance of the down transistor, thereby optimizing
  • the waveform of the gate drive signal output to the nth scan line improves the display effect of the display.
  • FIG. 1 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram of a gate driving circuit according to Embodiment 1 of the present invention.
  • FIG. 3 is a waveform diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a gate driving circuit according to Embodiment 2 of the present invention.
  • FIG. 5 is a schematic diagram of a cascaded gate driving circuit in an array substrate according to Embodiment 3 of the present invention.
  • an embodiment of the present invention provides a gate driving circuit for outputting a gate driving signal to an nth scanning line Gn.
  • the gate driving circuit includes a pull-up circuit, a down transistor, and a pull-down circuit.
  • the pull-up circuit is configured to output a high potential to the reference point Q in the gate driving circuit, the first input terminal of the pull-up circuit is connected to the n-1th scan line Gn-1, and the second input terminal of the pull-up circuit is connected to the n-th Two scanning lines Gn-2, the output of the pull-up circuit is connected to the Q point.
  • the gate of the down transistor T is connected to Q point, the source of T is connected to the clock signal line CK, and the drain of T is connected to Gn. When both Q point and CK are high, the drain of T outputs a high potential to Gn. Pole drive signal).
  • the pull-down circuit is used to output a low potential to the Q point and Gn after the Gn output gate drive signal, the first input end of the pull-down circuit is connected to the n+1th scan line Gn+1, and the output end of the pull-down circuit is connected to the Q point.
  • the pull-up circuit has a first input end and a second input end, which are respectively connected to Gn-1 and Gn-2.
  • the first charge can be performed for the Q point (ie, the gate of T) by the pull-up circuit; when the gate drive signal is output by Gn-1, the pull-up circuit can be used for Q. Click for a second charge.
  • the Q point Since the Q point is charged twice, the Q point can reach a higher potential.
  • the potential difference Vgs between the gate and the source of T can be significantly increased to lower the output impedance of T, thereby optimizing the output to the gate of Gn.
  • the waveform of the drive signal improves the display of the display.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the gate driving circuit provided in this embodiment is preferably implemented by GOA technology.
  • the gate driving circuit includes a pull-up circuit, a down transistor, and a pull-down circuit.
  • the pull-up circuit includes a first transistor T1 and a second transistor T2.
  • the gate of T1 is connected to STn-1, the source of T1 is connected to the first signal line Vf, and the drain of T1 is connected to Q point.
  • the gate of T2 is connected to STn-2, the source of T2 is connected to Vf (high potential), and the drain of T2 is connected to Q point.
  • two down transistors T21 and T22 are provided, which are respectively connected to Gn and STn.
  • the gate of T21 is connected to Q point, the source of T21 is connected to the clock signal line, and the drain of T21 is connected to Gn.
  • the gate of T22 is connected to Q point, the source of T22 is connected to the clock signal line, and the drain of T22 is connected to STn.
  • T21 and T22 are the same, and the signals output by Gn and STn are also the same. among them,
  • the gate drive signal output by Gn is used to drive the thin film transistor in the display area, and the signal output by STn is used to be transferred between the plurality of cascaded gate drive circuits (refer to FIG. 5).
  • STn-2, STn-1, STn+1, STn+2, and the like in other gate drive circuits are also the same as STn. Separating Gn and STn with identical output signals can avoid mutual interference between Gn and STn to ensure the quality of the waveform of the gate drive signal output by Gn.
  • the first input end and the second input end of the pull-up circuit are respectively connected to STn-1 and STn-2.
  • STn-2 output When the STn-2 output is high, the first charge can be performed for the Q point (ie, the gates of T21 and T22) by the pull-up circuit; when the STn-1 output is high, the pull-up circuit can be used for the Q point.
  • the second charge When the STn-2 output is high, the first charge can be performed for the Q point (ie, the gates of T21 and T22) by the pull-up circuit; when the STn-1 output is high, the pull-up circuit can be used for the Q point. The second charge.
  • the Q point Since the Q point is charged twice, the Q point can reach a higher potential.
  • the potential difference Vgs between the gate and source of T21 and T22 can be significantly increased to reduce the output impedance of T21 and T22, thereby optimizing
  • the waveforms of the gate drive signals output to Gn and STn improve the display effect of the display.
  • a coupling capacitor C is further provided, and C is connected between the Q point and the STn.
  • the pull-up circuit charges the Q point, the two ends of the coupling capacitor C are maintained at a certain potential difference.
  • STn outputs a high potential signal
  • the coupling of the coupling capacitor C can further increase the potential of the Q point, thereby further increasing the Vgs of T21 and T22, lowering the output impedance of T21 and T22, and optimizing the output to Gn and STn.
  • the waveform of the gate drive signal improves the display of the display.
  • the pull-down circuit includes a first input end and a second input end.
  • the first input terminal of the pull-down circuit is connected to STn+1
  • the second input terminal is connected to the n+2th scan line STn+2
  • the output end of the pull-down circuit is connected to the Q point.
  • the pull-down circuit includes a third transistor T3 and a fourth transistor T4.
  • the gate of T3 is connected to STn+1
  • the source of T3 is connected to the second signal line Vr
  • the drain of T3 is connected to Q point.
  • the gate of T4 is connected to STn+2, the source of T4 is connected to Vr (low potential), and the drain of T4 is connected to Q point.
  • the Q point When the STn+1 output is high, the Q point can be pulled down for the first time through the pull-down circuit; when the STn+2 output is high, the Q point can be pulled down a second time by the pull-down circuit. By pulling down twice, it is guaranteed that Q point and Gn are at a low potential to avoid signal fluctuation and interference of Gn.
  • the gate driving circuit provided by the embodiment of the invention can also implement two scanning modes of forward scanning and reverse scanning.
  • a first pull-down maintaining circuit and a second pull-down maintaining circuit are further provided.
  • the first pull-down sustain circuit is configured to maintain the low potential of the Q point and Gn, STn after the Gn outputs the gate drive signal during the forward scan.
  • the second pull-down sustain circuit is configured to maintain the low potential of the Q point and Gn, STn after the gate drive signal is output by Gn during the reverse scan.
  • the first pull-down maintaining circuit is mainly composed of a low potential signal line Vss and transistors T51, T54, T43, T33, T36, T56, T52 and the like.
  • the second pull-down sustain circuit is mainly composed of Vss and transistors T61, T64, T42, T32, T35, T66, T62 and the like.
  • the signals output by the signal lines LC1 and Vf are the same, and the signals output by the signal lines LC2 and Vr are the same.
  • Vf and LC1 output high potential
  • Vr and LC2 output low potential.
  • the waveform diagram is shown in Figure 3.
  • STn-2 outputs a high potential
  • T2 turns on
  • Vf charges the Q point through T2.
  • T51 and T56 are turned on, pulling down the potential of K point. Since the Q point is charged at a high potential, T52 and T62 are turned on, and the potentials of the P point and the K point are pulled down, and T32, T33, T35, T36, T42, and T43 are all turned off.
  • CK corresponding to CK3 in Fig. 3 outputs a low potential, so Gn and STn are at a low potential.
  • STn-1 In the second scan period, STn-1 outputs a high potential, T1 is turned on, and Vf continues to charge the Q point through T1. At the same time, T64 turns on, releasing the potential of point P to the same level as LC2, and continues to maintain a low potential. T32, T33, T35, T36, T42 and T43 are all off. In addition, CK continues to output a low potential, so Gn and STn continue to be at a low potential.
  • both STn-1 and STn-2 are low, and T2 and T1 are off.
  • the Q point remains high, turning T22 and T21 on, and the CK output is high, so that Gn outputs the gate drive signal and STn also outputs a high potential.
  • the Q point rises to a higher potential, further increases the Vgs of T22 and T21, and Vgs can remain substantially unchanged, keeping the smooth output of the gate drive signal.
  • T52 and T62 continue to open, pulling down the potential of P and K, so that T32, T33, T35, T36, T42 and T43 continue to be off.
  • CK In the fourth scan period, CK outputs a low potential. STn+1 outputs high potential, T3 turns on, and pulls down Q point. At the same time, T54 is turned on, so that the K point is charged at the fastest speed, so that T36, T33, T43 are quickly turned on, and the potentials of Gn, STn, and Q are pulled down, respectively, and T22 and T21 are turned off.
  • the STn+2 output high potential is high, T4 is turned on, and the Q point is pulled down again.
  • LC1 in the first pull-down sustain circuit continuously outputs a high potential to the K point through T51, the K point will remain at a high potential for the rest of the frame, so that T36, T33, and T43 are continuously turned on, thereby enabling The low potential of Gn, STn, and Q points is maintained.
  • both STn+1 and STn+2 are low, and T3 and T4 are off.
  • the Q point remains high, turning T22 and T21 on, and the CK output is high, so that Gn outputs the gate drive signal and STn also outputs a high potential.
  • the Q point rises to a higher potential, further increases the Vgs of T22 and T21, and Vgs can remain substantially unchanged, keeping the smooth output of the gate drive signal.
  • T52 and T62 continue to open, pulling down the potential of P and K, so that T32, T33, T35, T36, T42 and T43 continue to be off.
  • CK In the fourth scan period, CK outputs a low potential.
  • STn-1 outputs a high potential, T1 turns on, and pulls down Q point.
  • T64 is turned on, so that the P point is charged at the fastest speed, and T35, T32, and T42 are quickly turned on, and the potentials of Gn, STn, and Q are pulled down, respectively, and T22 and T21 are turned off.
  • the STn-2 output high potential is high, T2 is turned on, and the Q point is pulled down again. Because LC2 in the second pull-down sustain circuit will continue to output high potential to point P through T61, the P point will remain at a high potential for the rest of the frame, so that T35, T32, and T42 are continuously turned on, thereby maintaining Low potential of Gn, STn, and Q points.
  • the display performance during forward scan and reverse scan will be different.
  • two scanning modes of forward scanning and reverse scanning can be realized, so that the display effect is optimized.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • this embodiment is basically the same as the first embodiment, except that the embodiment is based on the first embodiment, the transistor T56 is connected between the K point and the Vr, and the T66 is connected to the P point. Between Vr, and the gate of T66 is connected to STn-2.
  • transistors T10 and T12 are added, T10 is connected between point K and Vf, T12 is connected between point P and Vf, and gates of T10 and T12 are connected to STn+2.
  • T55 is also connected between P and K, and the gate of T55 is connected to Q.
  • the gate of T54 is changed to be connected to LC2; in the second pull-down sustain circuit, the gate of T64 is changed to be connected to LC1.
  • Vf and LC1 output high potential
  • Vr and LC2 output low potential
  • the waveform diagram is shown in Figure 3.
  • T64 is always on, so point P is always at a low potential.
  • STn-2 outputs a high potential
  • T2 turns on
  • Vf charges the Q point through T2.
  • T66 and T56 are turned on, pulling down the potentials of points K and P. Since the Q point is charged at a high potential, T52 and T62 are turned on, and the potential of the P point and the K point can be lowered, and T32, T33, T35, T36, T42, and T43 are all turned off.
  • the T55 can be turned on, and the K point and the P point are connected, so that the K point and the P point are kept at a low potential together.
  • CK (corresponding to CK3 in Fig. 3) outputs a low potential, so Gn and STn are at a low potential.
  • STn-1 In the second scan period, STn-1 outputs a high potential, T1 is turned on, and Vf continues to charge the Q point through T1. T32, T33, T35, T36, T42 and T43 continue to be off. In addition, CK continues to output a low potential, so Gn and STn continue to be at a low potential.
  • both STn-1 and STn-2 are low, and T2 and T1 are off.
  • the Q point remains high, turning T22 and T21 on, and the CK output is high, so that Gn outputs the gate drive signal and STn also outputs a high potential.
  • the Q point rises to a higher potential, further increases the Vgs of T22 and T21, and Vgs can remain substantially unchanged, keeping the smooth output of the gate drive signal.
  • T52 and T62 continue to open, pulling down the potential of P and K, so that T32, T33, T35, T36, T42 and T43 continue to be off.
  • CK In the fourth scan period, CK outputs a low potential. STn+1 outputs high potential, T3 is turned on, Vr pulls down Q point, turns off T55, and disconnects between point P and point K. At the same time, T52 and T62 are also turned off, and LC1 inputs a high potential to point K through T51, so that T36, T33, and T43 are turned on, and the potentials of Gn, STn, and Q are pulled down, respectively, and T22 and T21 are turned off.
  • the STn+2 output high potential is high, T4 and T10 are turned on, and the Q point is pulled down again, and Vf can continue to think of the K point input high potential through T10.
  • LC1 in the first pull-down sustain circuit continuously outputs a high potential to the K point through T51, the K point will remain at a high potential for the rest of the frame, so that T36, T33, and T43 are continuously turned on, thereby enabling The low potential of Gn, STn, and Q points is maintained.
  • Vf and LC1 output low potential
  • Vr and LC2 output high potential
  • the waveform diagram is shown in Figure 3.
  • T54 In the first pull-down sustain circuit, T54 is always on, so the K point is always at a low potential.
  • STn+2 outputs a high potential
  • T4 turns on
  • Vr charges the Q point through T4.
  • T10 and T12 are turned on, pulling down the potentials of points K and P. Since the Q point is charged after being charged, T52 and T62 When turned on, it can also lower the potential of P point and K point, and T32, T33, T35, T36, T42 and T43 are all turned off.
  • the T55 can be turned on, and the K point and the P point are connected, so that the K point and the P point are kept at a low potential together.
  • CK (corresponding to CK3 in Fig. 3) outputs a low potential, so Gn and STn are at a low potential.
  • both STn+1 and STn+2 are low, and T3 and T4 are off.
  • the Q point remains high, turning T22 and T21 on, and the CK output is high, so that Gn outputs the gate drive signal and STn also outputs a high potential.
  • the Q point rises to a higher potential, further increases the Vgs of T22 and T21, and Vgs can remain substantially unchanged, keeping the smooth output of the gate drive signal.
  • T52 and T62 continue to open, pulling down the potential of P and K, so that T32, T33, T35, T36, T42 and T43 continue to be off.
  • CK In the fourth scan period, CK outputs a low potential.
  • STn-1 outputs a high potential
  • T1 is turned on
  • Vf pulls down the Q point
  • T52 and T62 are also turned off
  • LC2 inputs a high potential to P point through T61, so that T35, T32, and T42 are turned on, and the potentials of Gn, STn, and Q are pulled down, respectively, and T22 and T21 are turned off.
  • the STn-2 output high potential is high, T2 and T66 are turned on, and the Q point is pulled down again.
  • Vf can also continue to think of the P point input high potential through T66.
  • LC2 in the second pull-down sustain circuit continuously outputs a high potential to the P point through T61, the P point will remain at a high potential for the rest of the frame, so that T35, T32, and T42 are continuously turned on, thereby maintaining Low potential of Gn, STn, and Q points.
  • the present embodiment controls the potential of the K point and the P point more accurately, and further improves the waveform quality of the gate driving signal.
  • the switching between the forward scanning and the reverse scanning is also more flexible, and can be converted once in one frame or once in multiple frames.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the embodiment of the present invention provides an array substrate, which can adopt a GOA technology, in which a plurality of cascaded gate driving circuits in the first embodiment or the second embodiment are disposed, as shown in FIG.
  • the driving circuit is for outputting a gate driving signal to one scanning line.
  • each gate driving circuit the source of the lower pass transistor of each gate driving circuit
  • Each of the four clock signal lines CK1, CK2, CK3, and CK4 is connected in one-to-one correspondence, and the four clock signal lines sequentially output a high potential (see FIG. 3 for waveforms), thereby sequentially outputting gate driving signals for each scanning line, and having a positive direction. Scan and inverse scan two scan modes.
  • the embodiment of the present invention further provides a display device, which may be a narrow-framed liquid crystal display, including a color film substrate and the array substrate provided in this embodiment.
  • the display device provided in this embodiment may also be an OLED display including the above array substrate.
  • the array substrate and the display device provided in this embodiment have the same technical features as the gate driving circuit provided in the first embodiment and the second embodiment. Therefore, the same technical problem can be solved and the same technical effects can be achieved.

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Abstract

一种栅极驱动电路、阵列基板及显示装置，该栅极驱动电路用于向第n条扫描线输出栅极驱动信号，包括上拉电路、下传晶体管和下拉电路；其中，上拉电路用于向所述栅极驱动电路中的基准点输出高电位，上拉电路的第一输入端连接第n-1条扫描线，上拉电路的第二输入端连接第n-2条扫描线，上拉电路的输出端连接所述基准点；所述下传晶体管的栅极连接所述基准点，所述下传晶体管的源极连接时钟信号线，所述下传晶体管的漏极连接第n条扫描线，当所述基准点和所述时钟信号线均为高电位时，所述下传晶体管的漏极向第n条扫描线输出高电位；所述下拉电路用于向所述基准点以及第n条扫描线输出低电位，所述下拉电路的第一输入端连接第n+1条扫描线，所述下拉电路的输出端连接所述基准点。

Description

栅极驱动电路、阵列基板及显示装置
本申请要求享有2014年12月18日提交的名称为“栅极驱动电路、阵列基板及显示装置”的中国专利申请CN201410797938.0的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示技术领域，具体地说，涉及一种栅极驱动电路、阵列基板及显示装置。
背景技术
目前，在液晶显示器以及有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示器中，普遍采用薄膜晶体管(Thin Film Transistor，简称TFT)来驱动各个像素单元。
另一方面，运用Gate Driver on Array(简称GOA)技术可以将用于驱动薄膜晶体管的栅极驱动电路制作在阵列基板上，以替代原有的外接集成电路，能够减少外接集成电路的焊接工序，提高生产效率，降低生产成本，还能够实现窄边框，甚至无边框的显示产品。
但现有的GOA电路输出的栅极驱动信号的波形质量较差，这将导致显示器显示的图像质量较差。
发明内容
本发明的目的在于提供一种栅极驱动电路、阵列基板及显示装置，以解决现有的GOA电路输出的栅极驱动信号的波形质量较差的技术问题。
本发明提供一种栅极驱动电路，用于向第n条扫描线输出栅极驱动信号；
所述栅极驱动电路包括上拉电路、下传晶体管和下拉电路；
所述上拉电路用于向所述栅极驱动电路中的基准点输出高电位，所述上拉电路的第一输入端连接第n-1条扫描线，所述上拉电路第二输入端连接第n-2条扫描线，所述上拉电路的输出端连接所述基准点；
所述下传晶体管的栅极连接所述基准点，所述下传晶体管的源极连接时钟信号线，所 述下传晶体管的漏极连接第n条扫描线，当所述基准点和所述时钟信号线均为高电位时，所述下传晶体管的漏极向第n条扫描线输出高电位；
所述下拉电路用于向所述基准点以及第n条扫描线输出低电位，所述下拉电路的第一输入端连接第n+1条扫描线，所述下拉电路的输出端连接所述基准点。
进一步的是，所述栅极驱动电路还包括连接于所述基准点与第n条扫描线之间的耦合电容。
优选的是，所述上拉电路包括第一晶体管和第二晶体管；
所述第一晶体管的栅极连接第n-1条扫描线，源极连接第一信号线，漏极连接所述基准点；
所述第二晶体管的栅极连接第n-2条扫描线，源极连接所述第一信号线，漏极连接所述基准点。
进一步的是，所述下拉电路还设置有第二输入端，且所述下拉电路的第二输入端连接第n+2条扫描线。
优选的是，所述下拉电路包括第三晶体管和第四晶体管；
所述第三晶体管的栅极连接第n+1条扫描线，源极连接第二信号线，漏极连接所述基准点；
所述第四晶体管的栅极连接第n+2条扫描线，源极连接所述第二信号线，漏极连接所述基准点。
优选的是，在正向扫描时，所述第一信号线输出高电位，所述第二信号线输出低电位；
在反向扫描时，所述第一信号线输出低电位，所述第二信号线输出高电位。
进一步的是，所述栅极驱动电路还包括第一下拉维持电路和第二下拉维持电路；
在正向扫描时，所述第一下拉维持电路用于维持所述基准点及第n条扫描线的低电位；
在反向扫描时，所述第二下拉维持电路用于维持所述基准点及第n条扫描线的低电位。
本发明还提供一种阵列基板，包括若干级连的上述的栅极驱动电路，每个所述栅极驱动电路用于向一条扫描线输出栅极驱动信号。
进一步的是，在相邻的四个栅极驱动电路中，各个栅极驱动电路的下传晶体管的源极分别与四条时钟信号线一一对应连接，所述四条时钟信号线依次输出高电位。
本发明还提供一种显示装置，包括上述的阵列基板。
本发明带来了以下有益效果：本发明提供的栅极驱动电路中，上拉电路具有第一输入端和第二输入端，分别连接第n-1条扫描线和第n-2条扫描线。在第n-2条扫描线输出栅极驱动信号时，可通过上拉电路为基准点(即下传晶体管的栅极)进行第一次充电；在第n-1条扫描线输出栅极驱动信号时，可通过上拉电路为基准点进行第二次充电。
因为对基准点进行了两次充电，所以基准点能够达到更高的电位。在时钟信号线处于高电位，下传晶体管的漏极输出栅极驱动信号时，能够使下传晶体管的栅极与源极之间的电势差Vgs显著提高，以降低下传晶体管的输出阻抗，从而优化了输出至第n条扫描线的栅极驱动信号的波形，改善了显示器的显示效果。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是本发明实施例提供的栅极驱动电路的示意图；
图2是本发明实施例一提供的栅极驱动电路的电路图；
图3是本发明实施例提供的栅极驱动电路的波形图；
图4是本发明实施例二提供的栅极驱动电路的电路图；
图5是本发明实施例三提供的阵列基板中级连栅极驱动电路的示意图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是， 只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
如图1所示，本发明实施例提供一种栅极驱动电路，用于向第n条扫描线Gn输出栅极驱动信号。该栅极驱动电路包括上拉电路、下传晶体管和下拉电路。
上拉电路用于向栅极驱动电路中的基准点Q输出高电位，上拉电路的第一输入端连接第n-1条扫描线Gn-1，上拉电路第二输入端连接第n-2条扫描线Gn-2，上拉电路的输出端连接Q点。
下传晶体管T的栅极连接Q点，T的源极连接时钟信号线CK，T的漏极连接Gn，当Q点和CK均为高电位时，T的漏极向Gn输出高电位(栅极驱动信号)。
下拉电路用于在Gn输出栅极驱动信号之后，向Q点以及Gn输出低电位，下拉电路的第一输入端连接第n+1条扫描线Gn+1，下拉电路的输出端连接Q点。
本发明实施例提供的栅极驱动电路中，上拉电路具有第一输入端和第二输入端，分别连接Gn-1和Gn-2。在Gn-2输出栅极驱动信号时，可通过上拉电路为Q点(即T的栅极)进行第一次充电；在Gn-1输出栅极驱动信号时，可通过上拉电路为Q点进行第二次充电。
因为对Q点进行了两次充电，所以Q点能够达到更高的电位。在CK处于高电位，T的漏极输出栅极驱动信号时，能够使T的栅极与源极之间的电势差Vgs显著提高，以降低T的输出阻抗，从而优化了输出至Gn的栅极驱动信号的波形，改善了显示器的显示效果。
实施例一：
本实施例提供的栅极驱动电路，该栅极驱动电路优选的以GOA技术实现。该栅极驱动电路包括上拉电路、下传晶体管和下拉电路。
如图2所示，上拉电路包括第一晶体管T1和第二晶体管T2。T1的栅极连接STn-1，T1的源极连接第一信号线Vf，T1的漏极连接Q点。T2的栅极连接STn-2，T2的源极连接Vf(高电位)，T2的漏极连接Q点。
本实施例中设置有两个下传晶体管T21、T22，分别对应连接Gn和STn。T21的栅极连接Q点，T21的源极连接时钟信号线，T21的漏极连接Gn。T22的栅极连接Q点，T22的源极连接时钟信号线，T22的漏极连接STn。
可以看出，T21和T22的用途是相同的，Gn和STn输出的信号也是相同的。其中， Gn输出的栅极驱动信号用于驱动显示区域中的薄膜晶体管，而STn输出的信号用于在多个级连的栅极驱动电路之间传递(参照图5)。其他栅极驱动电路中的STn-2、STn-1、STn+1、STn+2等也与STn的功能相同。将输出信号完全相同的Gn和STn分开，可以避免Gn与STn之间相互干扰，以保证Gn输出的栅极驱动信号的波形的质量。
本发明实施例提供的栅极驱动电路中，上拉电路的第一输入端和第二输入端分别连接STn-1和STn-2。在STn-2输出高电位时，可通过上拉电路为Q点(即T21、T22的栅极)进行第一次充电；在STn-1输出高电位时，可通过上拉电路为Q点进行第二次充电。
因为对Q点进行了两次充电，所以Q点能够达到更高的电位。在CK处于高电位，T21、T22的漏极输出栅极驱动信号时，能够使T21、T22的栅极与源极之间的电势差Vgs显著提高，以降低T21、T22的输出阻抗，从而优化了输出至Gn及STn的栅极驱动信号的波形，改善了显示器的显示效果。
进一步的是，本实施例中，还设置有耦合电容C，C连接于Q点与STn之间。在上拉电路为Q点充电时，使耦合电容C的两端保持有一定的电势差。当STn输出高电位信号时，由于耦合电容C的耦合作用，能够使Q点的电位进一步升高，从而能够进一步提高T21、T22的Vgs，降低T21、T22的输出阻抗，优化输出至Gn及STn的栅极驱动信号的波形，改善了显示器的显示效果。
本实施例中，下拉电路包括第一输入端和第二输入端。下拉电路的第一输入端连接STn+1，第二输入端连接第n+2条扫描线STn+2，下拉电路的输出端连接Q点。具体的，下拉电路包括第三晶体管T3和第四晶体管T4。T3的栅极连接STn+1，T3的源极连接第二信号线Vr，T3的漏极连接Q点。T4的栅极连接STn+2，T4的源极连接Vr(低电位)，T4的漏极连接Q点。在STn+1输出高电位时，可通过下拉电路对Q点进行第一次下拉；在STn+2输出高电位时，可通过下拉电路对Q点进行第二次下拉。通过两次下拉，保证Q点及Gn处于低电位，避免Gn出现信号波动及干扰。
本发明实施例提供的栅极驱动电路还能够实现正向扫描和反相扫描两种扫描方式。
此外，本实施例中还进一步设置有第一下拉维持电路和第二下拉维持电路。第一下拉维持电路用于在正向扫描过程中，在Gn输出栅极驱动信号之后，维持Q点及Gn、STn的低电位。第二下拉维持电路用于在反向扫描过程中，在Gn输出栅极驱动信号之后，维持Q点及Gn、STn的低电位。
如图2所示，第一下拉维持电路主要由低电位信号线Vss以及晶体管T51、T54、T43、T33、T36、T56、T52等器件组成。第二下拉维持电路主要由Vss以及晶体管T61、T64、T42、T32、T35、T66、T62等器件组成。其中，信号线LC1与Vf输出的信号相同，信号线LC2与Vr输出的信号相同。
在正向扫描时，Vf、LC1输出高电位，Vr、LC2输出低电位，其波形图如图3所示。
在第一扫描周期，STn-2输出高电位，T2打开，Vf通过T2向Q点充电。同时，T51和T56打开，拉低K点的电位。由于Q点被充电后处于高电位，所以T52和T62打开，拉低P点及K点的电位，T32、T33、T35、T36、T42和T43均处于关闭状态。此外，虽然T22和T21也被打开，但此时CK(对应于图3中的CK3)输出低电位，所以Gn和STn处于低电位。
在第二扫描周期，STn-1输出高电位，T1打开，Vf通过T1继续对Q点充电。同时，T64打开，将P点电位释放至与LC2相同，继续保持低电位。T32、T33、T35、T36、T42和T43均处于关闭状态。此外，CK继续输出低电位，所以Gn和STn继续处于低电位。
在第三扫描周期，STn-1和STn-2均为低电位，T2和T1关闭。Q点仍保持为高电位，使T22和T21打开，同时CK输出高电位，使Gn输出栅极驱动信号，STn也输出高电位。并且，在C的耦合作用下，Q点抬升到更高电位，进一步提高T22、T21的Vgs，且Vgs能够基本保持不变，保持栅极驱动信号的顺利输出。此外，T52和T62继续打开，拉低P点和K点的电位，使T32、T33、T35、T36、T42和T43继续处于关闭状态。
在第四扫描周期，CK输出低电位。STn+1输出高电位，T3打开，对Q点进行下拉。同时，T54打开，从而以最快的速度向K点充电，使T36、T33、T43快速打开，分别拉低Gn、STn、Q点的电位，进而使T22和T21关闭。
在第五扫描周期，STn+2输出高电位为高，T4打开，对Q点再一次进行下拉。因为第一下拉维持电路中的LC1会通过T51向K点持续输出高电位，所以K点在这一帧余下的时间内会一直保持在高电位，使T36、T33、T43持续打开，从而能够维持Gn、STn、Q点的低电位。
在反向扫描时，Vf、LC1输出低电位，Vr、LC2输出高电位，其波形图如图3所示。
在第一扫描周期，STn+2输出高电位，T4打开，Vr通过T4向Q点充电。同时，T61和T66打开，拉低P点的电位。由于Q点被充电后处于高电位，所以T52和T62打开， 拉低K点及P点的电位，T32、T33、T35、T36、T42和T43均处于关闭状态。此外，虽然T22和T21也被打开，但此时CK(对应于图3中的CK3)输出低电位，所以Gn和STn处于低电位。
在第二扫描周期，STn+1输出高电位，T3打开，Vr通过T3继续对Q点充电。同时，T54打开，将K点电位释放至与LC1相同，继续保持低电位。T32、T33、T35、T36、T42和T43均处于关闭状态。此外，CK继续输出低电位，所以Gn和STn继续处于低电位。
在第三扫描周期，STn+1和STn+2均为低电位，T3和T4关闭。Q点仍保持为高电位，使T22和T21打开，同时CK输出高电位，使Gn输出栅极驱动信号，STn也输出高电位。并且，在C的耦合作用下，Q点抬升到更高电位，进一步提高T22、T21的Vgs，且Vgs能够基本保持不变，保持栅极驱动信号的顺利输出。此外，T52和T62继续打开，拉低P点和K点的电位，使T32、T33、T35、T36、T42和T43继续处于关闭状态。
在第四扫描周期，CK输出低电位。STn-1输出高电位，T1打开，对Q点进行下拉。同时，T64打开，从而以最快的速度向P点充电，使T35、T32、T42快速打开，分别拉低Gn、STn、Q点的电位，进而使T22和T21关闭。
在第五扫描周期，STn-2输出高电位为高，T2打开，对Q点再一次进行下拉。因为第二下拉维持电路中的LC2会通过T61持续向P点输出高电位，所以P点在这一帧余下的时间内会一直保持在高电位，使T35、T32、T42持续打开，从而能够维持Gn、STn、Q点的低电位。
由于器件负载的差异，正向扫描时与反相扫描时的显示效果会有所差异。将本发明实施例提供的栅极驱动电路进行级连，能够实现正向扫描和反相扫描两种扫描模式，从而使显示效果达到最优。
实施例二：
如图4所示，本实施例与实施例一基本相同，其不同点在于，本实施例在实施例一的基础上，将晶体管T56连接于K点与Vr之间，T66连接于P点与Vr之间，并且T66的栅极连接STn-2。此外，增设了晶体管T10和T12，T10连接于K点与Vf之间，T12连接于P点与Vf之间，T10和T12的栅极连接STn+2。而在P点与K点之间还连接有T55，T55栅极连接Q点。在第一下拉维持电路中，将T54的栅极改为连接至LC2；在第二下拉维持电路中，将T64的栅极改为连接至LC1。
在正向扫描时，Vf、LC1输出高电位，Vr、LC2输出低电位，其波形图如图3所示。在第二下拉维持电路中，T64始终打开，所以P点始终处于低电位。
在第一扫描周期，STn-2输出高电位，T2打开，Vf通过T2向Q点充电。同时，T66和T56打开，拉低K点和P点的电位。由于Q点被充电后处于高电位，所以T52、T62打开，也能够起到拉低P点和K点的电位的作用，T32、T33、T35、T36、T42和T43均处于关闭状态。Q点被充电后还能够打开T55，连通K点和P点，使K点和P点共同保持在低电位。此外，虽然T22和T21也被打开，但此时CK(对应于图3中的CK3)输出低电位，所以Gn和STn处于低电位。
在第二扫描周期，STn-1输出高电位，T1打开，Vf通过T1继续对Q点充电。T32、T33、T35、T36、T42和T43继续处于关闭状态。此外，CK继续输出低电位，所以Gn和STn继续处于低电位。
在第三扫描周期，STn-1和STn-2均为低电位，T2和T1关闭。Q点仍保持为高电位，使T22和T21打开，同时CK输出高电位，使Gn输出栅极驱动信号，STn也输出高电位。并且，在C的耦合作用下，Q点抬升到更高电位，进一步提高T22、T21的Vgs，且Vgs能够基本保持不变，保持栅极驱动信号的顺利输出。此外，T52和T62继续打开，拉低P点和K点的电位，使T32、T33、T35、T36、T42和T43继续处于关闭状态。
在第四扫描周期，CK输出低电位。STn+1输出高电位，T3打开，Vr对Q点进行下拉，使T55关闭，断开P点和K点之间的连接。同时，T52、T62也关闭，LC1通过T51向K点输入高电位，使T36、T33、T43打开，分别拉低Gn、STn、Q点的电位，进而使T22和T21关闭。
在第五扫描周期，STn+2输出高电位为高，T4和T10打开，对Q点再一次进行下拉，Vf也可以通过T10继续想K点输入高电位。因为第一下拉维持电路中的LC1会通过T51向K点持续输出高电位，所以K点在这一帧余下的时间内会一直保持在高电位，使T36、T33、T43持续打开，从而能够维持Gn、STn、Q点的低电位。
在反向扫描时，Vf、LC1输出低电位，Vr、LC2输出高电位，其波形图如图3所示。在第一下拉维持电路中，T54始终打开，所以K点始终处于低电位。
在第一扫描周期，STn+2输出高电位，T4打开，Vr通过T4向Q点充电。同时，T10和T12打开，拉低K点和P点的电位。由于Q点被充电后处于高电位，所以T52、T62 打开，也能够起到拉低P点和K点的电位的作用，T32、T33、T35、T36、T42和T43均处于关闭状态。Q点被充电后还能够打开T55，连通K点和P点，使K点和P点共同保持在低电位。此外，虽然T22和T21也被打开，但此时CK(对应于图3中的CK3)输出低电位，所以Gn和STn处于低电位。
在第二扫描周期，STn+1输出高电位，T3打开，Vr通过T3继续对Q点充电。T32、T33、T35、T36、T42和T43继续处于关闭状态。此外，CK继续输出低电位，所以Gn和STn继续处于低电位。
在第三扫描周期，STn+1和STn+2均为低电位，T3和T4关闭。Q点仍保持为高电位，使T22和T21打开，同时CK输出高电位，使Gn输出栅极驱动信号，STn也输出高电位。并且，在C的耦合作用下，Q点抬升到更高电位，进一步提高T22、T21的Vgs，且Vgs能够基本保持不变，保持栅极驱动信号的顺利输出。此外，T52和T62继续打开，拉低P点和K点的电位，使T32、T33、T35、T36、T42和T43继续处于关闭状态。
在第四扫描周期，CK输出低电位。STn-1输出高电位，T1打开，Vf对Q点进行下拉，使T55关闭，断开P点和K点之间的连接。同时，T52、T62也关闭，LC2通过T61向P点输入高电位，使T35、T32、T42打开，分别拉低Gn、STn、Q点的电位，进而使T22和T21关闭。
在第五扫描周期，STn-2输出高电位为高，T2和T66打开，对Q点再一次进行下拉，Vf也可以通过T66继续想P点输入高电位。因为第二下拉维持电路中的LC2会通过T61向P点持续输出高电位，所以P点在这一帧余下的时间内会一直保持在高电位，使T35、T32、T42持续打开，从而能够维持Gn、STn、Q点的低电位。
本实施例相比于实施例一，对K点、P点的电位控制更加精确，进一步提高了栅极驱动信号的波形质量。此外，本实施例中对正向扫描与反相扫描的切换也更加灵活，可以一帧转换一次，也可以多帧转换一次。
实施例三：
本发明实施例提供一种阵列基板，该阵列基板可以采用GOA技术，其中设置有若干级连的上述实施例一或实施例二中的栅极驱动电路，如图5所示，每个栅极驱动电路用于向一条扫描线输出栅极驱动信号。
进一步的是，在相邻的四个栅极驱动电路中，各个栅极驱动电路的下传晶体管的源极 分别与四条时钟信号线CK1、CK2、CK3、CK4一一对应连接，四条时钟信号线依次输出高电位(波形参照图3)，从而实现各条扫描线依次输出栅极驱动信号，并且具有正向扫描和反相扫描两种扫描模式。
本发明实施例还提供一种显示装置，该显示装置可以为窄边框的液晶显示器，其中包括彩膜基板和本实施例提供的阵列基板。
本实施例提供的显示装置也可以是包括上述阵列基板的OLED显示器。通过采用GOA，实现窄边框甚至无边框的显示产品。
本实施例提供的阵列基板及显示装置，与上述实施例一、实施例二提供的栅极驱动电路具有相同的技术特征，所以也能解决相同的技术问题，达到相同的技术效果。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (16)

  1. 一种栅极驱动电路，用于向第n条扫描线输出栅极驱动信号；
    所述栅极驱动电路包括上拉电路、下传晶体管和下拉电路；
    所述上拉电路用于向所述栅极驱动电路中的基准点输出高电位，所述上拉电路的第一输入端连接第n-1条扫描线，所述上拉电路第二输入端连接第n-2条扫描线，所述上拉电路的输出端连接所述基准点；
    所述下传晶体管的栅极连接所述基准点，所述下传晶体管的源极连接时钟信号线，所述下传晶体管的漏极连接第n条扫描线，当所述基准点和所述时钟信号线均为高电位时，所述下传晶体管的漏极向第n条扫描线输出高电位；
    所述下拉电路用于向所述基准点以及第n条扫描线输出低电位，所述下拉电路的第一输入端连接第n+1条扫描线，所述下拉电路的输出端连接所述基准点。
  2. 如权利要求1所述的栅极驱动电路，其中，还包括连接于所述基准点与第n条扫描线之间的耦合电容。
  3. 如权利要求1所述的栅极驱动电路，其中，所述上拉电路包括第一晶体管和第二晶体管；
    所述第一晶体管的栅极连接第n-1条扫描线，源极连接第一信号线，漏极连接所述基准点；
    所述第二晶体管的栅极连接第n-2条扫描线，源极连接所述第一信号线，漏极连接所述基准点。
  4. 如权利要求3所述的栅极驱动电路，其中，所述下拉电路还设置有第二输入端，且所述下拉电路的第二输入端连接第n+2条扫描线。
  5. 如权利要求4所述的栅极驱动电路，其中，所述下拉电路包括第三晶体管和第四晶体管；
    所述第三晶体管的栅极连接第n+1条扫描线，源极连接第二信号线，漏极连接所述基准点；
    所述第四晶体管的栅极连接第n+2条扫描线，源极连接所述第二信号线，漏极连接所述基准点。
  6. 如权利要求5所述的栅极驱动电路，其中，在正向扫描时，所述第一信号线输出高电位，所述第二信号线输出低电位；
    在反向扫描时，所述第一信号线输出低电位，所述第二信号线输出高电位。
  7. 如权利要求6所述的栅极驱动电路，其中，还包括第一下拉维持电路和第二下拉维持电路；
    在正向扫描时，所述第一下拉维持电路用于维持所述基准点及第n条扫描线的低电位；
    在反向扫描时，所述第二下拉维持电路用于维持所述基准点及第n条扫描线的低电位。
  8. 一种阵列基板，包括若干级连的栅极驱动电路，每个所述栅极驱动电路用于向一条扫描线输出栅极驱动信号；
    其中，第n个栅极驱动电路用于向第n条扫描线输出栅极驱动信号；
    所述第n个栅极驱动电路包括上拉电路、下传晶体管和下拉电路；
    所述上拉电路用于向所述第n个栅极驱动电路中的基准点输出高电位，所述上拉电路的第一输入端连接第n-1条扫描线，所述上拉电路第二输入端连接第n-2条扫描线，所述上拉电路的输出端连接所述基准点；
    所述下传晶体管的栅极连接所述基准点，所述下传晶体管的源极连接时钟信号线，所述下传晶体管的漏极连接第n条扫描线，当所述基准点和所述时钟信号线均为高电位时，所述下传晶体管的漏极向第n条扫描线输出高电位；
    所述下拉电路用于向所述基准点以及第n条扫描线输出低电位，所述下拉电路的第一输入端连接第n+1条扫描线，所述下拉电路的输出端连接所述基准点。
  9. 如权利要求8所述的阵列基板，其中，所述第n个栅极驱动电路还包括连接于所述基准点与第n条扫描线之间的耦合电容。
  10. 如权利要求8所述的阵列基板，其中，所述上拉电路包括第一晶体管和第二晶体管；
    所述第一晶体管的栅极连接第n-1条扫描线，源极连接第一信号线，漏极连接所述基准点；
    所述第二晶体管的栅极连接第n-2条扫描线，源极连接所述第一信号线，漏极连接所述基准点。
  11. 如权利要求10所述的阵列基板，其中，所述下拉电路还设置有第二输入端，且所述下拉电路的第二输入端连接第n+2条扫描线。
  12. 如权利要求11所述的阵列基板，其中，所述下拉电路包括第三晶体管和第四晶体管；
    所述第三晶体管的栅极连接第n+1条扫描线，源极连接第二信号线，漏极连接所述基准点；
    所述第四晶体管的栅极连接第n+2条扫描线，源极连接所述第二信号线，漏极连接所述基准点。
  13. 如权利要求12所述的阵列基板，其中，在正向扫描时，所述第一信号线输出高电位，所述第二信号线输出低电位；
    在反向扫描时，所述第一信号线输出低电位，所述第二信号线输出高电位。
  14. 如权利要求13所述的阵列基板，其中，还包括第一下拉维持电路和第二下拉维持电路；
    在正向扫描时，所述第一下拉维持电路用于维持所述基准点及第n条扫描线的低电位；
    在反向扫描时，所述第二下拉维持电路用于维持所述基准点及第n条扫描线的低电位。
  15. 如权利要求8所述的阵列基板，其中，在相邻的四个栅极驱动电路中，各个栅极驱动电路的下传晶体管的源极分别与四条时钟信号线一一对应连接，所述四条时钟信号线依次输出高电位。
  16. 一种显示装置，包括阵列基板；
    所述阵列基板包括若干级连的栅极驱动电路，每个所述栅极驱动电路用于向一条扫描线输出栅极驱动信号；
    其中，第n个栅极驱动电路用于向第n条扫描线输出栅极驱动信号；
    所述第n个栅极驱动电路包括上拉电路、下传晶体管和下拉电路；
    所述上拉电路用于向所述第n个栅极驱动电路中的基准点输出高电位，所述上拉电路的第一输入端连接第n-1条扫描线，所述上拉电路第二输入端连接第n-2条扫描线，所述上拉电路的输出端连接所述基准点；
    所述下传晶体管的栅极连接所述基准点，所述下传晶体管的源极连接时钟信号线，所述下传晶体管的漏极连接第n条扫描线，当所述基准点和所述时钟信号线均为高电位时，所述下传晶体管的漏极向第n条扫描线输出高电位；
    所述下拉电路用于向所述基准点以及第n条扫描线输出低电位，所述下拉电路的第一输入端连接第n+1条扫描线，所述下拉电路的输出端连接所述基准点。。
PCT/CN2015/071245 2014-12-18 2015-01-21 栅极驱动电路、阵列基板及显示装置 Ceased WO2016095321A1 (zh)

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