WO2017124731A1 - 移位寄存器及其驱动方法、goa电路以及显示装置 - Google Patents

移位寄存器及其驱动方法、goa电路以及显示装置 Download PDF

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Publication number
WO2017124731A1
WO2017124731A1 PCT/CN2016/094163 CN2016094163W WO2017124731A1 WO 2017124731 A1 WO2017124731 A1 WO 2017124731A1 CN 2016094163 W CN2016094163 W CN 2016094163W WO 2017124731 A1 WO2017124731 A1 WO 2017124731A1
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Prior art keywords
shift register
thin film
film transistor
output
pull
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PCT/CN2016/094163
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English (en)
French (fr)
Inventor
王俊伟
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/515,216 priority Critical patent/US10096373B2/en
Publication of WO2017124731A1 publication Critical patent/WO2017124731A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display, and in particular, to a shift register and a driving method thereof, a GOA circuit, and a display device.
  • Gate driver circuit is set on the Gate Driver on Array (GOA) technology, which not only reduces the production process, improves the integration, but also eliminates the gate chip bonding area and fan-out (Fan- Out) The wiring space to achieve a narrow border.
  • GOA Gate Driver on Array
  • the present disclosure provides a shift register and a driving method thereof, a GOA circuit, and a display device, which solve the display unevenness caused by insufficient gate signal output of a large-sized GOA display product.
  • An embodiment of the present disclosure provides a shift register for a GOA circuit, including: a pull-up node, a capacitor, and an output control module, the output control module including: a first thin film transistor, and a control end of the first thin film transistor The first end of the capacitor is connected to the pull-up node, the first end of the first thin film transistor inputs a first clock signal, and the second end is connected to the second end of the capacitor, and further includes: a pre-charge module And receiving a signal of the pull-up node, and outputting a pre-charge voltage having the same polarity as the effective voltage to an output end of the shift register before the shift register outputs an effective voltage.
  • the pre-charging module includes: a second thin film transistor having a control end connected to the first end thereof and inputting a precharge control signal; and a third thin film transistor having a control end connected to the second end of the second thin film transistor a first end connected to the output of the shift register; a fourth thin film transistor having a first end connected to the second end of the third thin film transistor, a control end connected to the second end thereof, and connected to a pull-up node; a fifth thin film transistor having a control end connected to the first end thereof and connected to the a second end of the capacitor and a second end of the first thin film transistor; a second end of which is coupled to an output of the shift register.
  • the precharge control signal is a second clock signal that is inverted from the first clock signal.
  • the embodiment of the present disclosure further provides a GOA circuit, comprising: the shift register of any of the above.
  • the shift registers are cascaded with each other, and an output end of any one of the shift registers is connected to a gate line, and the precharge control signal is a second clock inverted from the first clock signal. signal.
  • an output of any one of the shift registers is connected to a gate line; the shift registers connected to the odd-numbered gate lines are cascaded with each other, and the shift register connected to the even-numbered gate lines is also Cascading with each other; the precharge control signal used by any of the shift registers is a clock signal used by the shift register connected to the gate line of the previous row.
  • An embodiment of the present disclosure further provides a display device provided with the GOA circuit of any of the above.
  • the embodiment of the present disclosure further provides a driving method of a shift register, wherein the shift register includes: a pull-up node, a capacitor and an output control module, the output control module includes: a first thin film transistor, the first thin film transistor The control terminal and the first end of the capacitor are connected to the pull-up node, the first end of the first thin film transistor inputs a first clock signal, and the second end is connected to the second end of the capacitor,
  • the shift register further includes: a pre-charging module, configured to receive a signal of the pull-up node, and output the same polarity as the effective voltage to an output end of the shift register before the shift register outputs an effective voltage a precharge voltage; wherein the driving method comprises: a pull-up phase before the shift register outputs an effective voltage, the precharge module outputs a precharge having the same polarity as the effective voltage to an output of the shift register Pressure.
  • the pre-charging module includes: a second thin film transistor having a control end connected to the first end thereof and inputting a precharge control signal; and a third thin film transistor having a control end and a second end of the second thin film transistor Connected, the first end thereof is connected to the output end of the shift register;
  • the fourth thin film transistor has a first end connected to the second end of the third thin film transistor, and a control end connected to the second end thereof and connected a fifth thin film transistor having a control terminal connected to the first end thereof and connected to the second end of the capacitor and the second end of the first thin film transistor, the second end of which is connected to the An output terminal of the shift register;
  • the precharge module outputs a precharge voltage having the same polarity as the effective voltage to an output terminal of the shift register before the shift register outputs an effective voltage, including When the pull-up node is raised to a high level and the precharge control signal is high, the precharge control signal is supplied to the output of the shift register through the second thin film transistor and
  • the pre-charge control signal becomes a low level
  • the first clock signal becomes a high level
  • the third thin film transistor is turned off
  • the first and fifth thin film transistors are turned on
  • the pre-charge control is performed.
  • the signal stops outputting the precharge voltage to the output of the shift register, and the output voltage of the shift register is normally outputted by the first clock signal.
  • the shift register and the driving method thereof, the GOA circuit and the display device provided by the embodiment of the present disclosure add a pre-charge module to the shift register, and receive signals from the pull-up node before the shift register outputs the effective voltage. Outputting the precharge voltage of the same polarity as the effective voltage to the output of the shift register. Due to the presence of the precharge voltage, before scanning to the gate line of the bank (corresponding to the output of the output voltage of the shift register of the line), The thin film transistor connected to the gate line has accumulated charge, so when scanning the gate line of the current line, when the effective line is driven by the gate line, the thin film transistor of the line can be opened very quickly due to the accumulation of electric charge.
  • the large-size GOA shows that the gate signal output of the product is insufficient, and the resulting display unevenness is avoided.
  • 1 is a circuit diagram of an output control portion of a shift register in the related art
  • FIG. 2 is a partial circuit structural diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 3 is a timing chart showing the operation of the shift register shown in FIG. 2;
  • FIG. 4 is a schematic diagram of a single-group drive type GOA circuit in an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a GOA circuit of a dual-group driving type according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of control signals of the GOA circuit shown in FIG.
  • FIG. 7 is a schematic diagram of a shift register in the GOA circuit shown in FIG. 5.
  • the GOA circuit includes a plurality of shift registers that are cascaded with each other, and FIG. 1 shows an output control portion of the shift register in the related art.
  • the shift register in the related art controls the purpose of the output of the first thin film transistor M1 through the pull-up node (PU point) (the signal of the PU point contains information on when M1 is turned on and when the effective voltage is output).
  • the present disclosure improves the shift register circuit, so that the shift register unit itself adds a precharge function, that is, the signal itself precharge function of the shift register output provided by the embodiment of the present disclosure.
  • control signal can be received from the PU point, and the information of the working phase of the shift register can be obtained therefrom, and the precharge voltage having the same polarity as the effective voltage can be output to the output end of the shift register before the shift register outputs the effective voltage.
  • the shift register has a precharge function to solve the problem of insufficient gate signal output.
  • an embodiment of the present disclosure provides a shift register for a GOA circuit, as shown in FIG. 2 (only the circuit of the relevant part of the disclosure is shown), the shift register includes: a PU point, a capacitor C1, and The output control module 11 includes a first thin film transistor M1.
  • the control terminal of the first thin film transistor M1 and the first end of the capacitor C1 are connected to the PU node, and the first end of the first thin film transistor M1 is input with the first clock.
  • the signal CLK is connected to the second end of the capacitor C1.
  • the shift register further includes: a pre-charging module 12, the pre-charging module 12 is configured to receive a signal of the PU node, and output an effective voltage in the shift register. Previously, the precharge voltage of the same polarity as the effective voltage was output to the output terminal Output of the shift register.
  • the pre-charging function is implemented by adding a pre-charging module 12, and the pre-charging module 12 obtains the information of the working phase of the shift register by receiving the control signal from the PU point, so that the pre-charging module 12 can output in the shift register.
  • the precharge voltage is output to the output terminal Output of the shift register to solve the problem that the gate signal output is insufficient.
  • the specific structure of the pre-charging module 12 is not limited in this embodiment, as long as the pre-charging voltage of the same polarity as the effective voltage can be output before the shift register outputs the effective voltage under the control of the PU point signal, those skilled in the art can It can be set according to the actual situation.
  • the pre-charge voltage and the effective voltage have the same polarity to accumulate charge in advance and shorten the gate signal transmission time.
  • the specific size of the pre-charge voltage is not limited, and can be determined inversely by experiments according to actual needs.
  • the embodiment further provides the driving method of the above shift register, as follows: in the pull-up phase before the shift register outputs the effective voltage, the pre-charge module outputs and outputs to the output of the shift register. Precharge voltage with the same voltage polarity.
  • the pre-charging module 12 specifically includes: a second thin film transistor M2 whose control terminal is connected to its first terminal and inputs a precharge control signal (for example, CLKB); and a third thin film transistor M3.
  • the control terminal is connected to the second end of the second thin film transistor M2, and the first end thereof is connected to the output terminal Output of the shift register; the fourth thin film transistor M4 has a first end connected to the second end of the third thin film transistor M3.
  • the control terminal is connected to the second end thereof and is connected to the PU node;
  • the fifth thin film transistor M4 has a control terminal connected to the first end thereof and is connected to the second end of the capacitor C1 and the second end of the first thin film transistor M1; Its second end is connected to the output of the shift register Output.
  • the precharge control signal is a second clock signal CLKB that is inverted from the first clock signal CLK, and another clock signal (another clock signal other than CLK) used by the shift register of the stage can be directly used.
  • CLKB first clock signal
  • CLK second clock signal
  • the PU node is pulled high to the high level, and the precharge control signal (CLKB) is high.
  • the precharge control signal (CLKB) supplies the precharge voltage V1 of the same polarity as the effective voltage V to the output terminal Output of the shift register through the second thin film transistor film M2 and the third thin film transistor M3, and the first clock signal CLK at this time
  • the fifth thin film transistor M5 is turned off, and the output signal of the output terminal of the shift register does not affect the potential of the second end (right end) of the capacitor C1.
  • the PU node normally completes charging of the capacitor C1; when the PU node is high Level, the precharge control signal becomes a low level, the first clock signal CLK becomes a high level (corresponding to the B phase in FIG. 3), so that the third thin film transistor M3 is turned off, the first and fifth thin film transistors (M1) And M5) is turned on, the precharge control signal stops outputting the precharge voltage V1 to the output terminal Output of the shift register, and the output voltage Output of the shift register is normally outputted by the first clock signal CLK to the output terminal of the shift register.
  • stage A CLKB outputs a high level, M3 is turned on, and the second clock signal CLKB supplies a precharge voltage V1 to the output terminal Output of the shift register through the second thin film transistor film M2 and the third thin film transistor M3, and the precharge voltage V1 is output.
  • M3 and other TFT units M4 will also affect the output of M3, so the pre-charge voltage V1 can be obtained according to the pre-charge requirements, according to which the electrical properties of M2, M3 and M4 are determined (ie, M2, M3 and The width to length ratio of the M4 channel is W/L) to control the strength of the precharge capability.
  • stage B CLKB outputs a low level, M3 is turned off, CLKB stops outputting the precharge voltage to the output of the shift register Output; CLK outputs a high level, the PU node maintains a high level, M1, M5 are turned on, by the first clock signal CLK outputs the effective voltage V to the output of the shift register normally.
  • the precharge module provided in this embodiment can output the precharge voltage V1 in the previous clock cycle of outputting the effective voltage V without affecting the normal output effective voltage V in the output phase.
  • the shift register including the above precharge module itself has a precharge function.
  • An embodiment of the present disclosure further provides a GOA circuit, including: the shift register of any of the above. It can solve the display unevenness caused by the insufficient gate signal output of the GOA large-size product, and the GOA circuit provided by the present scheme can ensure the pixel charging as compared with the related art method of increasing the effective voltage of the gate signal for ensuring the charging effect. The effect can avoid the problems of large power consumption and high voltage brought by the methods in the related art.
  • a single group drive type GOA circuit shift registers 10 are cascaded with each other, and the output of any shift register 10 is connected to a gate line, and any shift register 10 uses two The clock signal CLK and CLKB, wherein the shift register 10 is the shift register described above in the embodiment of the present disclosure, wherein the precharge control signal is the second clock signal CLKB, inverting from the first clock signal CLK, and The second clock signal CLKB of the shift register 10 of this stage can be directly used.
  • the specific working process of the GOA circuit shown in FIG. 4 is shown in FIG. 3 and will not be described in detail herein.
  • a GOA circuit of a two-group drive type the output of any shift register 10 is connected to a gate line; the shift registers 10 connected to the odd-numbered gate lines are cascaded with each other, as used.
  • the two clock signals are CLK2 and CLKB2; the shift registers 10 connected to the even-numbered gate lines are also cascaded with each other, and the two clock signals used are CLK1 and CLKB1, wherein the shift register 10 is on the disclosed embodiment.
  • the shift register described in the above, and the precharge control signal used in any shift register 10 may be a clock signal used by the shift register 10 connected to the gate line of the previous row, that is, the precharge control signal is used in a different group. Any clock signal.
  • the shift register 10 connected to the first row of gate lines uses clock signals CLK2 and CLKB2, and the precharge control signal used may be CLK1 or CLKB1; the clock used by the shift register 10 of the second row gate line.
  • the signals are CLK1 and CLKB1, and the precharge control signal used can be CLK2 or CLKB2.
  • the GOA circuit shown in Figure 5 is similar to the shift register shown in Figure 3, and has worked specifically. Referring to the timing shown in FIG. 6, the following is as follows: If the odd-numbered gate lines correspond to the GOA controlled by CLK1 and CLKB1, the even-numbered gate lines correspond to the GOA controlled by CLK2 and CLKB2, and the timing relationship of FIG. 6 shows that CLKB2 is 1/4 cycle ahead of CLK1. Therefore, as shown in Figure 7, the GOA controlled by CLK1 and CLKB1 uses CLKB2 as the precharge control signal. When CLK1 is low but CLKB2 is high, the precharge voltage is output to complete the precharge function.
  • the embodiment of the present disclosure provides a GOA circuit with pre-charging function, which is suitable for single-side driving (single-group GOA architecture), and is also applicable to bilateral driving (two-group GOA architecture), and can solve the insufficient gate signal output of large-size GOA products.
  • the display is uneven and the pixel charging effect is guaranteed.
  • the embodiment of the present disclosure further provides a display device provided with the GOA circuit of any of the above.
  • the effective voltage of the gate signal output of the display device is small, energy saving and power saving, and also solves the display unevenness caused by insufficient gate signal output of the large-sized GOA product, thereby ensuring the pixel charging effect.
  • the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • first, second, etc. are used in the present disclosure to classify similar items.
  • the first and second words are not limited in number to the present disclosure, but are an example of a preferred mode. It is to be understood that a person skilled in the art, in light of the disclosure of the present disclosure, will be apparent to the scope of the disclosure.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

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Abstract

一种移位寄存器及其驱动方法、GOA电路以及显示装置，涉及显示领域，能够解决了大尺寸GOA显示产品栅极信号输出不足造成的显示不均。用于GOA电路的移位寄存器（10），包括：上拉节点、电容和输出控制模块（11），所述输出控制模块（11）包括：第一薄膜晶体管，所述第一薄膜晶体管的控制端与所述电容的第一端连接于所述上拉节点，所述第一薄膜晶体管的第一端输入第一时钟信号，第二端连接至所述电容的第二端，还包括：预充模块（12），用于接收所述上拉节点的信号，在所述移位寄存器（10）输出有效电压之前，向所述移位寄存器（10）的输出端输出与所述有效电压极性相同的预充电压。

Description

移位寄存器及其驱动方法、GOA电路以及显示装置
相关申请的交叉引用
本申请主张在2016年1月19日在中国提交的中国专利申请号No.201610035713.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示领域，尤其涉及一种移位寄存器及其驱动方法、GOA电路以及显示装置。
背景技术
栅极驱动电路设置在阵列基板上(Gate Driver on Array，GOA)的技术，不仅可减少生产工艺程序，提高集成度，还可以省去栅极芯片绑定(Bonding)区域以及扇出(Fan-out)布线空间，实现窄边框。
发明内容
本公开提供一种移位寄存器及其驱动方法、GOA电路以及显示装置，解决了大尺寸GOA显示产品栅极信号输出不足造成的显示不均。
为达到上述目的，本公开的实施例采用如下技术方案：
本公开实施例提供一种用于GOA电路的移位寄存器，包括：上拉节点、电容和输出控制模块，所述输出控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的控制端与所述电容的第一端连接于所述上拉节点，所述第一薄膜晶体管的第一端输入第一时钟信号，第二端连接至所述电容的第二端，还包括：预充模块，用于接收所述上拉节点的信号，在所述移位寄存器输出有效电压之前，向所述移位寄存器的输出端输出与所述有效电压极性相同的预充电压。
具体地，所述预充模块包括：第二薄膜晶体管，其控制端与其第一端相连并输入预充控制信号；第三薄膜晶体管，其控制端与所述第二薄膜晶体管的第二端相连，其第一端与所述移位寄存器的输出端相连；第四薄膜晶体管，其第一端与所述第三薄膜晶体管的第二端相连，其控制端与其第二端相连，并连接至所述上拉节点；第五薄膜晶体管，其控制端与其第一端相连，并连接至所述 电容的第二端及所述第一薄膜晶体管的第二端；其第二端连接至所述移位寄存器的输出端。
可选地，所述预充控制信号为与所述第一时钟信号反相的第二时钟信号。
本公开实施例还提供一种GOA电路，包括：上述任一项所述的移位寄存器。
可选地，所述移位寄存器相互级联，任一所述移位寄存器的输出端均与一栅线相连，所述预充控制信号为与所述第一时钟信号反相的第二时钟信号。
可选地，任一所述移位寄存器的输出端均与一栅线相连；与奇数行栅线相连的所述移位寄存器相互级联，与偶数行栅线相连的所述移位寄存器也相互级联；任意所述移位寄存器使用的预充控制信号为，与上一行栅线相连的所述移位寄存器使用的时钟信号。
本公开实施例还提供一种显示装置，设置有上述任一项所述的GOA电路。
本公开实施例还提供移位寄存器的驱动方法，其中，所述移位寄存器包括：上拉节点、电容和输出控制模块，所述输出控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的控制端与所述电容的第一端连接于所述上拉节点，所述第一薄膜晶体管的第一端输入第一时钟信号，第二端连接至所述电容的第二端，所述移位寄存器还包括：预充模块，用于接收所述上拉节点的信号，在所述移位寄存器输出有效电压之前，向所述移位寄存器的输出端输出与所述有效电压极性相同的预充电压；其中，所述驱动方法包括：在移位寄存器输出有效电压之前的上拉阶段，预充模块向所述移位寄存器的输出端输出与所述有效电压极性相同的预充电压。
可选地，所述预充模块包括：第二薄膜晶体管，其控制端与其第一端相连并输入预充控制信号；第三薄膜晶体管，其控制端与所述第二薄膜晶体管的第二端相连，其第一端与所述移位寄存器的输出端相连；第四薄膜晶体管，其第一端与所述第三薄膜晶体管的第二端相连，其控制端与其第二端相连，并连接至所述上拉节点；第五薄膜晶体管，其控制端与其第一端相连，并连接至所述电容的第二端及所述第一薄膜晶体管的第二端，其第二端连接至所述移位寄存器的输出端；所述在移位寄存器输出有效电压之前的上拉阶段，预充模块向所述移位寄存器的输出端输出与所述有效电压极性相同的预充电压，包括：当上拉节点被抬高为高电平，且预充控制信号为高电平时，预充控制信号通过第二薄膜晶体管和第三薄膜晶体管向移位寄存器的输出端提供与有效电压极性 相同的预充电压；此时第一时钟信号为低电平，第五薄膜晶体管截止，移位寄存器的输出端信号不影响电容第二端的电位，此阶段上拉节点正常完成对电容的充电；
当上拉节点为高电平，所述预充控制信号变为低电平，第一时钟信号变为高电平，使得第三薄膜晶体管截止，第一、第五薄膜晶体管开启，预充控制信号停止向移位寄存器的输出端输出预充电压，由第一时钟信号对移位寄存器的输出端正常输出有效电压。
本公开实施例提供的移位寄存器及其驱动方法、GOA电路以及显示装置，在移位寄存器中增加一预充模块，从上拉节点的接收信号，在所述移位寄存器输出有效电压之前，向移位寄存器的输出端输出与有效电压极性相同的预充电压，由于预充电压的存在，在扫描到本行栅线(对应本行移位寄存器输出端输出有效电压)之前，与本行栅线相连的薄膜晶体管处已经在积累电荷，这样扫描到本行栅线时，有效电压驱动时本行栅线时，本行薄膜晶体管由于已经有电荷积累，可以极快地打开，从而解决大尺寸GOA显示产品栅极信号输出不足的问题，避免由此造成的显示不均。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为相关技术中的移位寄存器的输出控制部分的电路示意图；
图2为本公开实施例提供的移位寄存器的部分电路结构图；
图3为图2所示移位寄存器的工作时序图；
图4为本公开实施例中的一种单组驱动类型的GOA电路示意图；
图5为本公开实施例中的一种双组驱动类型的GOA电路示意图；
图6为图5所示GOA电路的控制信号示意图
图7为图5所示GOA电路中移位寄存器的示意图。
附图标记
10-移位寄存器，11-输出控制模块，12-预充模块。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。
GOA电路包括若干相互级联的移位寄存器，图1所示为相关技术中的移位寄存器的输出控制部分。相关技术中的移位寄存器通过上拉节点(PU点)控制第一薄膜晶体管M1实现输出的目的(PU点的信号包含何时M1开启，何时输出有效电压的信息)。本公开对移位寄存器电路进行改进，使移位寄存器单元自身新增预充功能，即本公开实施例提供的移位寄存器输出的信号本身预充功能。具体可以从PU点接收控制信号，从中获取移位寄存器工作阶段的信息，在移位寄存器输出有效电压之前，向移位寄存器的输出端输出与有效电压极性相同的预充电压，即可使移位寄存器具备预充功能，解决栅极信号输出不足的问题。
具体地，本公开实施例提供一种用于GOA电路的移位寄存器，如图2所示(图中只示出本公开相关部分的电路)，该移位寄存器包括：PU点、电容C1和输出控制模块11，输出控制模块11包括：第一薄膜晶体管M1，第一薄膜晶体管M1的控制端与电容C1的第一端连接于PU节点，第一薄膜晶体管M1的第一端输入第一时钟信号CLK，第二端连接至电容C1的第二端；除此之外，移位寄存器还包括：预充模块12，预充模块12用于接收PU节点的信号，在移位寄存器输出有效电压之前，向移位寄存器的输出端Output输出与有效电压极性相同的预充电压。
本公开通过新增一预充模块12来实现预充功能，预充模块12通过从PU点接收控制信号，获取移位寄存器工作阶段的信息，从而使预充模块12恰能在移位寄存器输出有效电压之前，向移位寄存器的输出端Output输出预充电压，解决栅极信号输出不足的问题。预充模块12的具体结构本实施例不做限定，只要能在从PU点信号控制下，在移位寄存器输出有效电压之前输出与有效电压极性相同的预充电压即可，本领域技术人员可以根据实际情况进行设置。预充电压与有效电压极性相同才可以起到提前积累电荷，缩短栅极信号传递时间，预充电压的具体大小也不做限定，可以通过实验根据实际需要达到效果来反向确定。
对应地，本实施例还提供上述移位寄存器的驱动方法，如下：在移位寄存器输出有效电压之前的上拉阶段，预充模块向移位寄存器的输出端输出与有效 电压极性相同的预充电压。
在另一更为具体的实施例中，预充模块12具体包括：第二薄膜晶体管M2，其控制端与其第一端相连并输入预充控制信号(例如CLKB)；第三薄膜晶体管M3，其控制端与第二薄膜晶体管M2的第二端相连，其第一端与移位寄存器的输出端Output相连；第四薄膜晶体管M4，其第一端与第三薄膜晶体管M3的第二端相连，其控制端与其第二端相连，并连接至PU节点；第五薄膜晶体管M4，其控制端与其第一端相连，并连接至电容C1的第二端和第一薄膜晶体管M1的第二端；其第二端连接至移位寄存器的输出端Output。
预充控制信号为与第一时钟信号CLK反相的第二时钟信号CLKB，可以直接使用本级移位寄存器使用的另一时钟信号(除CLK之外的另一时钟信号)。对应驱动方法(工作过程)如下：
参照图3所示，在移位寄存器输出有效电压之前的上拉阶段(对应图3中的A阶段)，PU节点被拉高为高电平，且预充控制信号(CLKB)为高电平时，预充控制信号(CLKB)通过第二薄膜晶体管膜M2和第三薄膜晶体管M3向移位寄存器的输出端Output提供与有效电压V极性相同的预充电压V1，此时第一时钟信号CLK为低电平，第五薄膜晶体管M5截止，移位寄存器的输出端Output信号不影响电容C1第二端(右端)的电位，此阶段PU节点正常完成对电容C1的充电；当PU节点为高电平，预充控制信号变为低电平，第一时钟信号CLK变为高电平(对应图3中的B阶段)，使得第三薄膜晶体管M3截止，第一、第五薄膜晶体管(M1和M5)开启，预充控制信号停止向移位寄存器的输出端Output输出预充电压V1，由第一时钟信号CLK对移位寄存器的输出端Output正常输出有效电压V。
A阶段，CLKB输出高电平，M3开启，第二时钟信号CLKB通过第二薄膜晶体管膜M2和第三薄膜晶体管M3向移位寄存器的输出端Output提供预充电压V1，预充电压V1输出时会经过M2、M3等TFT单元，M4也会影响M3的输出，所以可根据预充要求得到预充电压V1大小，据此决定M2、M3和M4的电学性质(即调整制备时M2、M3和M4沟道的宽长比W/L)，以控制预充能力的强弱。实际实施时，为控制预充功能，必须设计评估不同TFT单元(主要是M2、M3和M4)之间的相互关系，设计不同的沟道宽长比W/L(主要是通过调整图中M3沟道的宽长比)。此时，CLK输出低电平，PU节点电平抬高，M5截止，移位寄存器的输出端Output输出的预充电压V1不影响电容C1第二端的电位，C1第二端维持低电位。
B阶段，CLKB输出低电平，M3截止，CLKB停止向移位寄存器的输出端Output输出预充电压；CLK输出高电平，PU节点维持高电平，M1、M5开启，由第一时钟信号CLK对移位寄存器的输出端Output正常输出有效电压V。
本实施例提供的预充模块可以在输出有效电压V的前一时钟周期输出预充电压V1，而又不影响输出阶段正常输出有效电压V。包含上述预充模块的移位寄存器自身具有预充功能。
本公开实施例还提供一种GOA电路，包括：上述任一项的移位寄存器。可以解决GOA大尺寸产品栅极信号输出不足造成的显示不均，与为保证充电效果而加大栅极信号有效电压的相关技术中的方法相比，本方案提供的GOA电路既可以保证像素充电效果，又可以避免相关技术中的方法带来的大功耗、高电压等问题。
为了本领域技术人员更好的理解本公开实施例提供的方案，下面通过具体的实施例对本公开提供的GOA电路进行详细说明。
如图4所示，一种单组驱动类型的GOA电路：移位寄存器10相互级联，任一移位寄存器10的输出端Output均与一栅线相连，任一移位寄存器10使用两个时钟信号CLK和CLKB，其中，移位寄存器10为本公开实施例中上文所述的移位寄存器，其中的预充控制信号为第二时钟信号CLKB，与第一时钟信号CLK反相，且可以直接使用本级移位寄存器10的第二时钟信号CLKB。图4所示GOA电路的具体工作过程参考图3所示，此处不再详述。
如图5所示，一种双组驱动类型的GOA电路：任一移位寄存器10的输出端Output均与一栅线相连；与奇数行栅线相连的移位寄存器10相互级联，所使用的两个时钟信号为CLK2和CLKB2；与偶数行栅线相连的移位寄存器10也相互级联，所使用的两个时钟信号为CLK1和CLKB1，其中，移位寄存器10为本公开实施例上文所述的移位寄存器，且任意移位寄存器10使用的预充控制信号可以为，与上一行栅线相连的移位寄存器10所使用的时钟信号，即预充控制信号采用异组使用的任一时钟信号。例如，与第一行栅线相连的移位寄存器10使用的时钟信号为CLK2和CLKB2，其使用的预充控制信号可以是CLK1或者CLKB1；与第二行栅线的移位寄存器10使用的时钟信号为CLK1和CLKB1，其使用的预充控制信号可以为CLK2或者CLKB2。
图5所示GOA电路的与图3所示移位寄存器工作过程大致类似，具体工作过 程参考图6所示时序，如下：如奇数行栅线对应CLK1和CLKB1控制的GOA，偶数行栅线对应CLK2和CLKB2控制的GOA，由图6时序关系可知CLKB2比CLK1提前1/4周期。因此，如图7所示，CLK1和CLKB1控制的GOA，若采用CLKB2作为预充控制信号，在CLK1为低但CLKB2为高时，输出预充电压，完成预充功能；当CLK1为高，CLKB2也为高时，CLK1和CLKB2信号均向输出端Output输出高电平，增强输出，当CLK1为高，CLKB2跳变为低电平时，只有CLK1信号均向输出端Output输出高电平，此阶段为有效电压输出阶段。
本公开实施例提供一种具有预充功能的GOA电路，适用于单边驱动(单组GOA架构)，也适用于双边驱动(双组GOA架构)，能够解决大尺寸GOA产品栅极信号输出不足造成的显示不均，保证像素充电效果。
本公开实施例还提供一种显示装置，设置有上述任一项的GOA电路。所述显示装置的栅极信号输出的有效电压小，节能省电，同时还解决大尺寸GOA产品栅极信号输出不足造成显示不均，保证了像素充电效果。所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
为了便于清楚说明，在本公开中采用了第一、第二等字样对相似项进行类别区分，该第一、第二字样并不在数量上对本公开进行限制，只是对一种优选的方式的举例说明，本领域技术人员根据本公开公开的内容，想到的显而易见的相似变形或相关扩展均属于本公开的保护范围内。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应该以权利要求的保护范围为准。

Claims (11)

  1. 一种移位寄存器，包括：上拉节点、电容和输出控制模块；所述输出控制模块包括：第一薄膜晶体管；所述第一薄膜晶体管的控制端与所述电容的第一端连接于所述上拉节点，所述第一薄膜晶体管的第一端输入第一时钟信号，第二端连接至所述电容的第二端；
    所述移位寄存器还包括：预充模块，用于接收所述上拉节点的信号，在所述移位寄存器输出有效电压之前，向所述移位寄存器的输出端输出与所述有效电压极性相同的预充电压。
  2. 根据权利要求1所述的移位寄存器，其中，所述预充模块包括：
    第二薄膜晶体管，其控制端与其第一端相连并输入预充控制信号；
    第三薄膜晶体管，其控制端与所述第二薄膜晶体管的第二端相连，其第一端与所述移位寄存器的输出端相连；
    第四薄膜晶体管，其第一端与所述第三薄膜晶体管的第二端相连，其控制端与其第二端相连，并连接至所述上拉节点；
    第五薄膜晶体管，其控制端与其第一端相连，并连接至所述电容的第二端及所述第一薄膜晶体管的第二端，其第二端连接至所述移位寄存器的输出端。
  3. 根据权利要求2所述的移位寄存器，其中，所述预充控制信号为与所述第一时钟信号反相的第二时钟信号。
  4. 一种GOA电路，包括移位寄存器，其中，所述移位寄存器包括：上拉节点、电容和输出控制模块，所述输出控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的控制端与所述电容的第一端连接于所述上拉节点，所述第一薄膜晶体管的第一端输入第一时钟信号，第二端连接至所述电容的第二端，所述移位寄存器还包括：
    预充模块，用于接收所述上拉节点的信号，在所述移位寄存器输出有效电压之前，向所述移位寄存器的输出端输出与所述有效电压极性相同的预充电压。
  5. 根据权利要求4所述的GOA电路，其中，所述预充模块包括：
    第二薄膜晶体管，其控制端与其第一端相连并输入预充控制信号；
    第三薄膜晶体管，其控制端与所述第二薄膜晶体管的第二端相连，其第一端与所述移位寄存器的输出端相连；
    第四薄膜晶体管，其第一端与所述第三薄膜晶体管的第二端相连，其控制端与其第二端相连，并连接至所述上拉节点；
    第五薄膜晶体管，其控制端与其第一端相连，并连接至所述电容的第二端及所述第一薄膜晶体管的第二端，其第二端连接至所述移位寄存器的输出端。
  6. 根据权利要求5所述的GOA电路，其中，所述预充控制信号为与所述第一时钟信号反相的第二时钟信号。
  7. 根据权利要求4所述的GOA电路，其中，所述移位寄存器相互级联，任一所述移位寄存器的输出端均与一栅线相连，所述预充控制信号为与所述第一时钟信号反相的第二时钟信号。
  8. 根据权利要求4所述的GOA电路，其中，任一所述移位寄存器的输出端均与一栅线相连；与奇数行栅线相连的所述移位寄存器相互级联，与偶数行栅线相连的所述移位寄存器也相互级联；
    任意所述移位寄存器使用的预充控制信号为，与上一行栅线相连的所述移位寄存器使用的时钟信号。
  9. 一种显示装置，设置有权利要求4-8任一项所述的GOA电路。
  10. 一种移位寄存器的驱动方法，
    其中，所述移位寄存器包括：上拉节点、电容和输出控制模块，所述输出控制模块包括：第一薄膜晶体管，所述第一薄膜晶体管的控制端与所述电容的第一端连接于所述上拉节点，所述第一薄膜晶体管的第一端输入第一时钟信号，第二端连接至所述电容的第二端，所述移位寄存器还包括：
    预充模块，用于接收所述上拉节点的信号，在所述移位寄存器输出有效电压之前，向所述移位寄存器的输出端输出与所述有效电压极性相同的预充电压；
    其中，所述驱动方法包括：
    在所述移位寄存器输出有效电压之前的上拉阶段，所述预充模块向所述移位寄存器的输出端输出与所述有效电压极性相同的预充电压。
  11. 根据权利要求10所述的驱动方法，其中，
    所述预充模块包括：
    第二薄膜晶体管，其控制端与其第一端相连并输入预充控制信号；
    第三薄膜晶体管，其控制端与所述第二薄膜晶体管的第二端相连，其第一端与所述移位寄存器的输出端相连；
    第四薄膜晶体管，其第一端与所述第三薄膜晶体管的第二端相连，其控制端与其第二端相连，并连接至所述上拉节点；
    第五薄膜晶体管，其控制端与其第一端相连，并连接至所述电容的第二端及所述第一薄膜晶体管的第二端，其第二端连接至所述移位寄存器的输出端；
    其中，所述在移位寄存器输出有效电压之前的上拉阶段，预充模块向所述移位寄存器的输出端输出与所述有效电压极性相同的预充电压，包括：
    当上拉节点被抬高为高电平，且所述预充控制信号为高电平时，所述预充控制信号通过所述第二薄膜晶体管和所述第三薄膜晶体管向所述移位寄存器的输出端提供与所述有效电压极性相同的所述预充电压；此时所述第一时钟信号为低电平，所述第五薄膜晶体管截止，所述移位寄存器的输出端信号不影响电容第二端的电位，此阶段上拉节点正常完成对电容的充电；
    当上拉节点为高电平，所述预充控制信号变为低电平，所述第一时钟信号变为高电平，使得所述第三薄膜晶体管截止，所述第一、第五薄膜晶体管开启，所述预充控制信号停止向所述移位寄存器的输出端输出所述预充电压，由所述第一时钟信号对所述移位寄存器的输出端正常输出所述有效电压。
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