WO2019024481A1 - 移位寄存器及其驱动方法、栅极驱动电路及显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2019024481A1
WO2019024481A1 PCT/CN2018/075853 CN2018075853W WO2019024481A1 WO 2019024481 A1 WO2019024481 A1 WO 2019024481A1 CN 2018075853 W CN2018075853 W CN 2018075853W WO 2019024481 A1 WO2019024481 A1 WO 2019024481A1
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WIPO (PCT)
Prior art keywords
pull
pole
control
transistor
node
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PCT/CN2018/075853
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English (en)
French (fr)
Inventor
郭旺
李彦辰
李月
李金钰
冯大伟
赵宇
侯少军
王冬
吕明阳
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US16/304,952 priority Critical patent/US11308853B2/en
Publication of WO2019024481A1 publication Critical patent/WO2019024481A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to a shift register unit, a gate drive circuit, and a display device.
  • the driver of the TFT-LCD mainly includes a data driver and a gate driver.
  • the gate driver circuit can be disposed in the display panel in a COF (Chip On Film) or COG (Chip On Glass) package, or an integrated circuit unit can be formed by using a TFT.
  • the gate driving circuit Formed in the display panel, the gate driving circuit generally connects one pole of the shift register with one gate line, and inputs a signal through the gate driving circuit, thereby implementing progressive scanning of the pixel.
  • the gate driver GOA design allows the LCD panel to be less expensive, while reducing one process and increasing throughput.
  • the present disclosure is directed to at least one of the technical problems existing in the prior art, and provides a shift register and a driving method thereof, a gate driving circuit, and a display device for solving a long-term forward scanning of an existing shift register. After switching the reverse scan, there is a problem that the shift register has poor reliability and horizontal stripes.
  • a shift register comprising: a forward scan input sub-circuit for forward scanning, under control of a forward input signal and a forward scan signal, by a working level signal pair The potential of the pull-up node is pre-charged; the reverse scan input sub-circuit is used for reverse scanning, and the potential of the pull-up node is pre-processed by the working level signal under the control of the reverse input signal and the reverse scan signal.
  • a charging sub-circuit configured to output a clock signal through the signal output end under the potential control of the pull-up node; wherein the pull-up node is the forward scan input sub-circuit, the reverse The input subcircuit and the connection node of the output subcircuit are scanned.
  • the shift register further includes: a forward scan reset sub-circuit for forward scanning, under the control of the forward reset signal and the forward scan signal, passing the non-working level signal Resetting the pull-up node; and performing a reverse scan reset sub-circuit for the reverse pull, under the control of the reverse reset signal and the reverse scan signal, by the non-working level signal The node is reset.
  • the shift register further includes: a pull-down control sub-circuit for controlling a potential of the pull-down node under control of the operating level and the potential of the pull-up node; and a pull-down sub-circuit for Pulling down the potential of the pull-down node by the non-working level signal under the control of the potential of the pull-up node; the noise reduction sub-circuit is configured to pass the control of the pull-down node The non-working level signal reduces output noise of the pull-up node and the signal output terminal; wherein the pull-down node is between the pull-down control sub-circuit, the pull-down sub-circuit, and the noise reduction sub-circuit Connect the node.
  • the forward scan input subcircuit includes: a first forward scan input transistor and a second forward scan input transistor; wherein a gate of the second forward scan input transistor is connected to a forward scan An input terminal, a first pole connected to the second pole of the first forward scan input transistor, and a second pole connected to the pull-up node; a control pole of the first forward scan input transistor is connected to the first pole, and Connect to the forward scan control.
  • the reverse scan input sub-circuit includes: a first reverse scan input transistor and a second reverse scan input transistor; wherein a control pole and a first pole of the first reverse scan input transistor Connected to and connected to the reverse scan control terminal; the control electrode of the second reverse scan input transistor is connected to the reverse scan input terminal, the first pole is connected to the second pole of the first reverse scan input transistor, and the second pole is connected The pull-up node.
  • the forward scan reset sub-circuit includes: a first forward scan reset transistor and a second forward scan reset transistor; wherein a first pole of the first forward scan reset transistor is coupled to the a pull-up node, a second pole connected to the first pole of the second forward scan reset transistor, and a control pole connected to the reverse scan input terminal; a first pole of the second forward scan reset transistor connected to the first positive To scan the second pole of the reset transistor, the second pole is connected to the reverse scan control terminal, and the control pole is connected to the forward scan control terminal.
  • the reverse scan reset sub-circuit includes: a first reverse scan reset transistor and a second reverse scan reset transistor; wherein a first pole of the first reverse scan reset transistor is coupled to the a second reverse scan resets a second pole of the transistor, a second pole is connected to the pull-up node, and a control pole is connected to the forward scan input terminal; and a first pole of the second reverse scan reset transistor is connected to the forward scan control terminal The second pole is connected to the first pole of the first reverse scan reset transistor, and the control pole is connected to the reverse scan control terminal.
  • the output sub-circuit includes an output transistor and an output capacitor; wherein a control electrode of the output transistor is connected to the pull-up node, the first end is connected to the first clock signal end, and the second end is connected to the output end; The first end of the output capacitor is connected to the pull-up node, and the second end is connected to the output end.
  • the pull-down control sub-circuit includes a first pull-down control transistor and a second pull-down control transistor; wherein a first pole of the first pull-down control transistor is coupled to a first pole of the second pull-down control transistor a second pole is connected to the pull-down node, and a control pole is connected to the second pole of the second pull-down control transistor; a first pole and a control pole of the second pull-down control transistor are connected to the first control signal end, and the second pole A control electrode and a pull-down sub-circuit of the first pull-down control transistor are connected.
  • the pull-down sub-circuit includes: a first pull-down transistor and a second pull-down transistor; wherein a first pole of the first pull-down transistor is connected to the pull-down node, and a second pole is connected to a low-level terminal
  • the control electrode is connected to the pull-up node; the first pole of the second pull-down transistor is connected to the pull-down control sub-circuit, the second pole is connected to the low-level end, and the control pole is connected to the pull-up node.
  • the noise reduction sub-circuit includes: a first noise reduction transistor and a second noise reduction transistor; wherein the first pole of the first noise reduction transistor is connected to the pull-up node, and the second pole is connected to the second The control signal terminal is connected to the pull-down node; the first pole of the second noise reduction transistor is connected to the pull-up node, the second pole is connected to the second control signal end, and the control pole is connected to the pull-down node.
  • the shift register further includes: an output reset sub-circuit for pairing the signal by a non-working level signal under control of the second control signal after each frame picture scan ends The signal output at the output is reset.
  • the output reset sub-circuit includes: an output reset transistor; wherein a first pole of the output reset transistor is coupled to the signal output terminal, and a second pole is coupled to a low-level signal terminal, and is controlled The pole is connected to the second control signal terminal.
  • a driving method of a shift register comprising: in a precharge phase of forward scanning, using a forward scan input sub-circuit to pre-stage a pull-up node Charging; in the pre-charge phase of the reverse scan, the pull-up node is pre-charged using a reverse scan input sub-circuit.
  • the driving method further includes: in a reset phase of the forward scan, using a forward scan reset sub-circuit to reset the pull-up node; and in a reset phase of the reverse scan, using a reverse scan reset The circuit resets the pull-up node.
  • the forward scan precharge phase includes: controlling a forward scan input sub-circuit to be turned on by a forward input signal provided by the first signal terminal and a working level signal provided by the forward scan control terminal, and The working level signal provided by the forward scanning control terminal pre-charges the pull-up node;
  • the reverse scanning pre-charging phase includes: providing the reverse input signal provided by the second signal and the reverse scanning control terminal The working level signal controls the reverse scan input sub-circuit to be turned on, and the working level signal provided by the reverse scan control terminal is precharged to the pull-up node.
  • the forward scan reset phase includes: controlling a forward scan reset sub-circuit to be turned on by a forward reset signal provided by the second signal terminal and a working level signal provided by the forward scan control terminal, and The pull-up node is reset by a non-working level signal provided to the scan control terminal;
  • the reverse scan reset phase includes: a reverse reset signal provided by the first signal terminal and a working power provided by the reverse scan control terminal The flat signal control reverse scan reset sub-circuit is turned on, and the pull-up node is reset by the non-working level signal provided by the forward scan control terminal.
  • a gate driving circuit comprising a plurality of cascaded stage shift registers, the shift register unit being a shift register unit as previously described.
  • a display device comprising a gate drive circuit as previously described.
  • the shift register of the present disclosure includes a forward scan input module and a forward scan reset module for forward scan, and an inverse input module and a reverse scan reset module for reverse scan, that is, In the forward and reverse scans of the display panel, different input modules and reset modules are used respectively, so that the input signal and the reset signal are switched to different loops during forward scanning and reverse scanning, thereby ensuring for forward direction.
  • the forward direction scan input module and the forward scan reset module of the scan, as well as the reverse scan input module and the reverse scan reset module used for the reverse scan do not change the current direction under the working state, thereby solving the existing shift register The problem of poor reliability of horizontal stripes.
  • 1 is a schematic structural diagram of a conventional shift register
  • FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 3 is a timing diagram of forward scanning in a driving method of a shift register according to an embodiment of the present disclosure
  • FIG. 4 is a timing diagram of reverse scanning in a driving method of a shift register according to an embodiment of the present disclosure
  • Figure 5a is a flowchart of an exemplary driving method of a shift register according to the present embodiment
  • FIG. 5b is a flowchart of an exemplary driving method of the shift register according to the present embodiment.
  • FIG. 6 illustrates an exemplary display device in accordance with an embodiment of the present disclosure.
  • the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or the like having the same characteristics. Since the source and the drain of the transistor used are interchangeable under certain conditions, the source thereof, There is no difference in the description of the drain from the connection relationship.
  • one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a gate.
  • the transistors can be classified into an N-type and a P-type according to the characteristics of the transistors. In the following embodiments, the transistors are N-type transistors.
  • the drain of the first very N-type transistor and the source of the second N-type transistor have a source-drain conduction when the gate input is high, and the P-type is opposite. It is conceivable that the implementation of a transistor using a P-type transistor is easily conceivable by those skilled in the art without any inventive effort, and is therefore within the scope of protection of the embodiments of the present disclosure.
  • the operating level described in the embodiments provided by the present disclosure refers to a high level signal, and the non-operating level refers to a low level signal. It will be understood by those skilled in the art that when the embodiments described in the present disclosure are implemented using different types of transistors, the driving timing of the transistors can be changed according to actual conditions to implement the principles provided by the present disclosure.
  • 1 is a block diagram showing the structure of a conventional shift register composed of 10 transistors and an output capacitor. The inventors have found that the shift register is switched between forward scan and reverse scan. The direction of the current in the transistors of the two signals input by the control signal input terminal and the reset signal terminal changes, resulting in shift register trustworthy horizontal stripes after switching for reverse scanning after a long time of forward scanning under high temperature conditions. bad.
  • FIG. 2 is a schematic diagram of a shift register of one embodiment of the present disclosure. As shown in FIG. 2, the present disclosure provides a shift register including a forward scan input sub-circuit 1, a reverse scan input sub-circuit 2, and an output sub-circuit 5.
  • the first end of the forward scan input sub-circuit 1 is connected to the forward scan control terminal VDS, the second end is connected to the forward scan input terminal INPUT1, and the third end is connected to the pull-up node PU.
  • the first end of the reverse scan input sub-circuit 2 is connected to the reverse scan control terminal VSD, the second end is connected to the reverse scan input terminal INPUT2, and the third end is connected to the pull-up node PU.
  • the forward scan mode input block 1 inputs the forward input signal to the pull-up node PU under the control of the forward scan control terminal.
  • the reverse scan input sub-circuit 2 is configured to be in an inoperative state under the control of the reverse scan control signal input from the reverse scan control terminal VSD.
  • the reverse scan input sub-circuit 2 inputs the inverted input signal to the pull-up node PU under the control of the reverse scan control terminal.
  • the forward scan input sub-circuit 1 is configured to be in an inoperative state under the control of the forward scan control signal input from the forward scan control terminal VDS.
  • the output sub-circuit 5 is configured to output a clock signal input by the first clock signal terminal CLK through the signal output terminal OUTPUT under the potential control of the pull-up node PU.
  • the forward scan input subcircuit 1 includes a first forward scan input transistor M12 and a second forward scan input transistor M1.
  • the control electrode of the first forward scan input transistor M12 is connected to the first pole and is connected to the forward scan control terminal VDS.
  • the control electrode of the second forward scan input transistor M1 is connected to the forward scan input terminal INPUT1, the first pole is connected to the second pole of the first forward scan input transistor M12, and the second pole is connected to the pull-up node PU.
  • the reverse scan input subcircuit 2 includes a first reverse scan input transistor M4 and a second reverse scan input transistor M2.
  • the control electrode of the first reverse scan input transistor M4 is connected to the first electrode and is connected to the reverse scan control terminal VSD.
  • the control electrode of the second reverse scan input transistor M2 is connected to the reverse scan input terminal INPUT2, the first pole is connected to the second pole of the first reverse scan input transistor M12, and the second pole is connected to the pull-up node PU.
  • the output sub-circuit 5 includes an output transistor M3 and an output capacitor C1.
  • the control electrode of the output transistor M3 is connected to the pull-up node PU, the first end is connected to the first clock signal terminal CLK, and the second end is connected to the output terminal OUTPUT.
  • the first end of the output capacitor C1 is connected to the pull-up node PU, and the second end is connected to the output terminal OUTPUT.
  • the shift register unit may further include: a forward scan reset sub-circuit 3, a reverse scan reset sub-circuit 4, a pull-down control sub-circuit 6, a pull-down sub-circuit 7, and a drop Noise circuit 8.
  • the pull-up node PU is reset by the non-working level signal under the control of the forward reset signal and the forward scan signal.
  • the forward scan reset sub-circuit 3 may include a first forward scan reset transistor M15 and a second forward scan reset transistor M16.
  • the first pole of the first forward scan reset transistor M15 is connected to the pull-up node PU, the second pole is connected to the first pole of the second forward scan reset transistor M16, and the gate is connected to the reverse scan input terminal INPUT2.
  • the first pole of the second forward scan reset transistor M16 is connected to the second pole of the first forward scan reset transistor M15, the second pole is connected to the reverse scan control terminal VSD, and the gate is connected to the forward scan control terminal VDS.
  • the pull-up node PU is reset by the non-operating level signal under the control of the reverse reset signal and the reverse scan signal.
  • the reverse scan reset sub-circuit 4 may include a first reverse scan reset transistor M13 and a second reverse scan reset transistor M14.
  • the first pole of the first reverse scan reset transistor M13 is connected to the second pole of the second reverse scan reset transistor M14, the second pole is connected to the pull-up node PU, and the control pole is connected to the forward scan input terminal INPUT1.
  • the first pole of the second reverse scan reset transistor M14 is connected to the forward scan control terminal VDS, the second pole is connected to the first pole of the first reverse scan reset transistor M13, and the gate is connected to the reverse scan control terminal VSD.
  • the pull-down control sub-circuit 6 is for controlling the potential of the pull-down node PD under the control of the operating level and the potential of the pull-up node PU.
  • the pull-down node PD is a connection node between the pull-down control sub-circuit 6, the pull-down sub-circuit 7, and the noise reduction sub-circuit 8.
  • the pull-down control subcircuit 6 includes a first pull-down control transistor M5 and a second pull-down control transistor M9.
  • the first pole of the first pull-down control transistor M5 is connected to the first pole of the second pull-down control transistor M9, the second pole is connected to the pull-down node PD, and the control pole is connected to the second pole of the second pull-down control transistor M9.
  • the first and control terminals of the second pull-down control transistor M9 are connected to the first control signal terminal GCH, and the second electrode is connected to the control electrode of the first pull-down control transistor M5 and the pull-down sub-circuit 7.
  • the first control signal terminal GCH can input a signal of a high level.
  • the pull-down sub-circuit 7 is for pulling down the potential of the pull-down node PD by a non-operating level signal under the control of the potential of the pull-up node PU.
  • the pull-down sub-circuit 7 includes a first pull-down transistor M6 and a second pull-down transistor M8.
  • the first pole of the first pull-down transistor M6 is connected to the pull-down node PD, the second pole is connected to the low-level end, and the control pole is connected to the pull-up node PU.
  • the first pole of the second pull-down transistor M8 is connected to the pull-down control sub-circuit 6, the second pole is connected to the low-level terminal, and the control pole is connected to the pull-up node PU.
  • the noise reduction sub-circuit 8 is for reducing the output noise of the pull-up node PU and the signal output terminal OUTPUT by the non-working level signal under the control of the pull-down node PD.
  • the noise reduction subcircuit 8 includes a first noise reduction transistor M10 and a second noise reduction transistor M11.
  • the first pole of the first noise reduction transistor M10 is connected to the pull-up node PU, the second pole is connected to the second control signal terminal VGL, and the control pole is connected to the pull-down node PD.
  • the first pole of the second noise reduction transistor M11 is connected to the pull-up node PU, the second pole is connected to the second control signal terminal VGL, and the control pole is connected to the pull-down node PD.
  • the second control signal terminal VGL can input a signal of a low level.
  • the shift register unit as shown in FIG. 2 may further include an output reset sub-circuit 9 for passing non-working power under the control of the second control signal after the end of each frame picture scan.
  • the flat signal resets the signal output by the signal output terminal OUTPUT.
  • the output reset sub-circuit 9 may include an output reset transistor M7.
  • the first pole of the output reset transistor M7 is connected to the signal output terminal OUTPUT, the second pole is connected to the low-level signal terminal, and the control pole is connected to the second control signal terminal GCL.
  • the shift register provided by the present disclosure includes a forward scan input sub-circuit 1 and a forward scan reset sub-circuit 3 for forward scanning, and a reverse scan input sub-circuit 2 and counter for reverse scanning
  • the scan reset sub-circuit 4 that is, the forward and reverse scans of the display panel, respectively, uses different input sub-circuits and reset sub-circuits to switch the input signal and the reset signal into a forward scan and a reverse scan.
  • Different loops to ensure forward scan input sub-circuit 1 and forward scan reset sub-circuit 3, and reverse scan input sub-circuit 2 and reverse scan reset sub-circuit 4 for reverse scanning in operation The current direction is unchanged, thereby solving the problem of poor reliability and horizontal stripes in the existing shift register.
  • FIG. 3 illustrates a timing diagram of a shift register during a forward scan, in accordance with an embodiment of the present disclosure.
  • the signal input by the forward scan control terminal VDS is a constant high signal
  • the signal input by the reverse scan control terminal VSD is a normally low signal.
  • the forward scan input terminal INPUT1 inputs a high level signal, and therefore, the second forward scan input transistor M1 and the first forward scan input transistor M12 are turned on and controlled by forward scan.
  • the high level input by the terminal VDS is precharged by the pull-up node PU.
  • the first reverse scan input transistor M4 is turned off under the control of the reverse scan control terminal VSD, so that the reverse scan input sub-circuit 2 is in an inactive state during the forward scan.
  • the output transistor M3 is turned on under the control of the pull-up node PU.
  • the first clock signal terminal CLK is written with a high level signal
  • the signal output terminal OUTPUT is output with a high level signal.
  • the reverse scan input terminal INPUT2 inputs a high level signal
  • the signal input to the forward scan control terminal VDS is a constant high signal
  • the signal input by the reverse scan control terminal VSD is a normally low signal. Therefore, the first forward scan reset transistor M15 and the second forward scan reset transistor M16 are turned on, and the low level signal input by the reverse scan control terminal VSD is pulled down to lower the potential of the pull-up node PU to complete Reset of the pull-up node PU.
  • FIG. 4 shows a timing diagram of a shift register during a reverse scan, in accordance with an embodiment of the present disclosure.
  • the signal input by the reverse scan control terminal VSD is a constant high signal
  • the signal input by the forward scan control terminal VDS is a normally low signal.
  • the reverse scan input terminal INPUT2 inputs a high level signal, and therefore, the second reverse scan input transistor M2 and the first reverse scan input transistor M4 are turned on and controlled by reverse scan.
  • the high level signal input by the terminal is precharged by the pull-up node PU.
  • the first forward scan input transistor M12 is turned off under the control of the forward scan control terminal VDS, so that the forward scan input sub-circuit 1 is in an inactive state during the reverse scan.
  • the output transistor M3 is turned on under the control of the pull-up node PU.
  • the first clock signal terminal CLK is written with a high level signal
  • the signal output terminal OUTPUT is output with a high level signal.
  • the positive scan input terminal INPUT1 inputs a high level signal
  • the signal input by the forward scan control terminal VDS is a normally low signal
  • the reverse scan control terminal VSD inputs
  • the signal is a constant high signal. Therefore, the first reverse scan reset transistor M13 and the second reverse scan reset transistor M14 are turned on, and the potential of the pull-up node PU is pulled down by the low-level signal input by the forward-scan control terminal VDS to complete Pull the reset of the node PU.
  • the first control signal terminal GCH is input with a constant high signal as an example.
  • the first pull-down control transistor M5 and the second pull-down control transistor M9 are turned on, and the potential of the pull-down node PD is pulled high. Potential.
  • the signal input by the first control signal terminal may also be a clock signal as long as the clock signal is different from the signal input by the first clock signal terminal CLK by half a cycle.
  • the pull-up node PU When the pull-up node PU is at a high potential, the first pull-down transistor M6 and the second pull-down transistor M8 are turned on, and the pull-down node PD is pulled down to a low level by the low-level signal input by the low-level signal terminal, and The output of the pull-down control sub-circuit 6 is also pulled down to a low level.
  • the first noise reduction transistor M10 and the second noise reduction transistor M11 are turned on under the control of the pull-down node PD, and the low-level signal input through the low-level signal terminal is used to lower the pull-up.
  • FIG. 5a and 5b are flowcharts of an exemplary driving method of a shift register according to the present embodiment. This method can be used to drive the shift register operation in the previous embodiment.
  • Figure 5a shows a flow chart of the drive method of the shift register during forward scan
  • Figure 5b shows the reverse scan of the drive method of the shift register during reverse scan.
  • the forward scan input sub-circuit 1 is used to pre-charge the pull-up node PU.
  • the pull-up node sub-circuit 2 is used to pre-charge the pull-up node PU.
  • the driving method may include:
  • the positive scan input sub-circuit is turned on by the forward input signal provided by the forward scan input and the working level signal provided by the forward scan control terminal, and the working level signal provided by the forward scan control terminal is Pre-charge the pull-up node.
  • the driving method may include:
  • the reverse scan input sub-circuit is turned on by the reverse input signal provided by the reverse scan input and the operating level signal provided by the reverse scan control terminal, and the operation level signal provided by the reverse scan control terminal is Pre-charge the pull-up node.
  • the forward scan reset phase is used to reset the pull-up node PU.
  • the pull-up reset sub-circuit 4 is used to reset the pull-up node PU.
  • the driving method may include:
  • the forward-reset reset sub-circuit is controlled by the forward reset signal provided by the reverse scan input and the working level signal provided by the forward scan control terminal, and the non-operating level signal pair provided by the reverse scan control terminal is provided
  • the pull-up node is reset.
  • the driving method can include:
  • the reverse scan reset sub-circuit is turned on by the reverse reset signal provided by the forward scan input and the work level signal provided by the reverse scan control terminal, and the non-operating level signal provided by the forward scan control terminal is provided. Reset the pull-up node.
  • the forward scan input is used to provide a forward input signal during forward scan and a reverse reset signal during reverse scan.
  • the reverse scan input is used to provide a positive reset signal during forward scan and an inverted input signal during reverse scan.
  • the forward scan control terminal is used to provide an operating level signal during forward scanning and a non-working level signal during reverse scanning.
  • the reverse scan control terminal is used to provide a non-working level signal during forward scanning and an operating level signal during reverse scanning.
  • the forward scan control signal input by the forward scan control terminal VDS is a constant high signal; the reverse scan control signal input by the reverse scan control terminal VSD is a normally low signal.
  • the first stage (precharge stage): a high level signal is input to the INPUT1 of the forward scan input terminal, and a high level signal is input to the forward scan control terminal VDS, and the first forward scan input transistor M1 and the second forward scan input transistor M12 Both are turned on. At this time, the high-level signal input through the forward scanning control terminal is pre-charged for the pull-up node PU, and the output capacitor C1 is charged.
  • the output transistor M3 is turned on under the control of the high level of the pull-up node PU, and the low-level signal input by the first clock signal terminal CLK is output through the signal output terminal OUTPUT.
  • Second stage (output stage): The signal input from the forward scan input terminal INPUT1 changes from a high level to a low level, and controls the first forward scan input transistor M1 to be turned off at this time. At this time, the pull-up node PU is still at the high level, and the output transistor M3 remains on. The first pull-down transistor M6 is turned on under the control of the pull-up node PU, and controls the pull-down node PD to be at a low level. At the same time, the signal input by the first clock signal terminal CLK is a high level signal, and therefore, the signal output terminal OUTPUT outputs a high level signal at this moment.
  • the third stage (reset phase): the reverse scan input terminal INPUT2 inputs a high level signal, and the first forward scan reset transistor M15 and the second forward scan reset transistor M16 respectively input a high level signal at the reverse scan input end. And the conduction of the high level signal input to the forward scanning control terminal is turned on. At this time, the low level signal input by the reverse scan control terminal VSD pulls down the potential of the pull-up node PU through the first forward scan reset transistor M15 and the second forward scan reset transistor M16 to complete the reset of the pull-up node PU. .
  • the first pull-down control transistor M5 and the second pull-down control transistor M9 are turned on, the potential of the pull-down node PD is pulled to a high level, and passes through the first noise reduction transistor
  • the M10 and the second noise reduction transistor M11 accelerate the discharge of the output capacitor C1 and the signal output terminal OUTPUT.
  • the fourth stage (noise reduction stage): the pull-down node PD remains at a low level, the first noise reduction transistor M10 and the second noise reduction transistor M11 remain turned on, and the pull-up node PU and the signal output terminal OUTPUT remain at a low level.
  • the low level input by the second control signal terminal GCL is turned to a high level, so that the output reset transistor M7 is turned on to reset the signal outputted by the signal output terminal OUTPUT to low. Level.
  • the forward scan control signal input by the forward scan control terminal VDS is a low high signal; the reverse scan control signal input by the reverse scan control terminal VSD is a constant high signal.
  • the first stage (precharge stage): the reverse scan input terminal INPUT2 inputs a high level signal, the reverse scan control terminal VSD inputs a high level signal, the second reverse scan input transistor M2 and the first reverse scan input transistor M4 Both are turned on.
  • the high-level signal input through the reverse scan control terminal is pre-charged for the pull-up node PU, and at the same time, the output capacitor C1 is charged, and the output transistor M3 is turned on by the high-level of the pull-up node PU.
  • the low level signal input by the first clock signal terminal CLK is output through the signal output terminal OUTPUT.
  • the second stage (output stage): the signal input by the INPUT2 signal terminal of the reverse scan input changes from a high level to a low level, and the second forward scan input transistor M1 is turned off at this time, and the output capacitor C1 is discharged and pulled up.
  • the node PU bootstraps, is still at a high level, the output transistor M3 remains on, the first pull-down transistor M6 is turned on, and the pull-down node PD is at a low level; at the same time, the signal input by the first clock signal terminal CLK is at a high level.
  • the signal therefore, the signal output OUTPUT now outputs a high level signal.
  • the low level signal input by the control terminal VDS pulls down the potential of the pull-up node PU through the first reverse scan input transistor M13 and the second reverse scan input transistor M14 to complete the reset of the pull-up node PU.
  • the signal of the first control signal terminal GCH is at a high level
  • the first pull-down control transistor M5 and the second pull-down control transistor M9 are turned on, and the potential of the pull-down node PD is pulled to a high level, at this time, the first noise reduction transistor M10 And the second noise reduction transistor M11 accelerates the discharge of the output capacitor C1 and the signal output terminal OUTPUT.
  • the fourth stage (noise reduction stage): the pull-down node PD remains low, the first noise reduction transistor M10 and the second noise reduction transistor M11 remain open, and the pull-up node PU and the signal output terminal OUTPUT remain low.
  • the second control signal terminal GCL is input to a low level to be turned high, so that the output reset transistor M7 is turned on to reset the signal outputted from the signal output terminal OUTPUT to a low level.
  • the transistors used in the precharge phase of the forward scan are the first forward scan input transistor M1 and the second forward scan input transistor M12, and the precharge phase of the reverse scan
  • the transistor used is the second reverse scan input transistor M2 and the first reverse scan input transistor M4, and the transistors used in the reset phase of the forward scan are the first forward scan reset transistor M15 and the second forward scan reset transistor.
  • M16, the transistors used in the reset phase of the reverse scan are the first reverse scan input transistor M13 and the second reverse scan input transistor M14, so that the input signal and the reset signal are switched during forward scan and reverse scan.
  • Different loops ensure that the current direction of the transistor used for reverse scanning does not change during the operating state, thereby solving the problem of poor reliability of the existing shift register.
  • FIG. 6 illustrates an exemplary display device in accordance with an embodiment of the present disclosure.
  • this embodiment provides a gate driving circuit including a shift register unit as described above.
  • the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device of the embodiment may further include other conventional structures such as a power supply unit, a display driving unit, and the like.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路及显示装置，属于显示技术领域。该移位寄存器，包括：正向扫描输入子电路(1)，用于正向扫描时，在正向输入信号和正向扫描信号的控制下，通过工作电平信号对上拉节点的电位进行预充电；反向扫描输入子电路(2)，用于反向扫描时，在反向输入信号和反向扫描信号的控制下，通过工作电平信号对上拉节点的电位进行预充电；输出子电路(5)，用于在所述上拉节点的电位控制下，将时钟信号通过信号输出端进行输出；其中，所述上拉节点是所述正向扫描输入子电路(1)、所述反向扫描输入子电路(2)以及所述输出子电路(5)的连接节点。

Description

移位寄存器及其驱动方法、栅极驱动电路及显示装置
相关申请的交叉引用
本公开要求于2017年7月31日递交的中国专利申请第201710643411.6号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及一种移位寄存器单元、栅极驱动电路及显示装置。
背景技术
TFT-LCD的驱动器主要包括数据驱动器与栅极驱动器，栅级驱动电路可以以COF(Chip On Film)或者COG(Chip On Glass)的封装方式设置在显示面板中，也可以用TFT构成集成电路单元形成在显示面板中，栅极驱动电路一般为移位寄存器一个极与一根栅极线对接，通过栅极驱动电路输入信号，从而实现像素的逐行扫描。与传统的COF或者COG设计不同，栅极驱动器GOA设计可以使得液晶显示面板成本更低，同时减少了一道工序，提高了产量。随着平板显示的发展，高分辨率，窄边框成为发展的潮流，而要实现高分辨率，窄边框显示，面板上集成栅极驱动电路是一种解决办法。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种移位寄存器及其驱动方法、栅极驱动电路及显示装置，用于解决现有的移位寄存器长时间正向扫描后切换反向扫描会发生移位寄存器信赖性横纹不良的问题。
根据本公开的一个方面，提供了一种移位寄存器，包括：正向扫描输入子电路，用于正向扫描时，在正向输入信号和正向扫描信号的控制下，通过工作电平信号对上拉节点的电位进行预充电；反向扫描输入子电路，用于反向扫描时，在反向输入信号和反向扫描信号的控制下，通过工作电平信号对 上拉节点的电位进行预充电；输出子电路，用于在所述上拉节点的电位控制下，将时钟信号通过信号输出端进行输出；其中，所述上拉节点是所述正向扫描输入子电路、所述反向扫描输入子电路以及所述输出子电路的连接节点。
在一些实施例中，所述移位寄存器还包括：正向扫描复位子电路，用于正向扫描时，在正向复位信号和所述正向扫描信号的控制下，通过非工作电平信号对所述上拉节点进行复位；反向扫描复位子电路，用于反向扫描时，在反向复位信号和所述反向扫描信号的控制下，通过非工作电平信号对所述上拉节点进行复位。
在一些实施例中，所述移位寄存器还包括：下拉控制子电路，用于在所述工作电平和所述上拉节点的电位的控制下，控制下拉节点的电位；下拉子电路，用于在所述上拉节点的电位的控制下，通过所述非工作电平信号对所述下拉节点的电位进行下拉；所述降噪子电路，用于在所述下拉节点的控制下，通过所述非工作电平信号降低所述上拉节点和所述信号输出端的输出噪声；其中，所述下拉节点是所述下拉控制子电路、所述下拉子电路和所述降噪子电路之间的连接节点。
在一些实施例中，所述正向扫描输入子电路包括：第一正向扫描输入晶体管和第二正向扫描输入晶体管；其中，所述第二正向扫描输入晶体管的控制极连接正向扫描输入端，第一极连接所述第一正向扫描输入晶体管的第二极，第二极连接所述上拉节点；所述第一正向扫描输入晶体管的控制极与第一极相连，并连接到正向扫描控制端。
在一些实施例中，所述反向扫描输入子电路包括：第一反向扫描输入晶体管和第二反向扫描输入晶体管；其中，所述第一反向扫描输入晶体管的控制极与第一极相连，并连接到反向扫描控制端；所述第二反向扫描输入晶体管的控制极连接反向扫描输入端，第一极连接第一反向扫描输入晶体管的第二极，第二极连接所述上拉节点。
在一些实施例中，所述正向扫描复位子电路包括：第一正向扫描复位晶体管和第二正向扫描复位晶体管；其中，所述第一正向扫描复位晶体管的第一极连接所述上拉节点，第二极连接所述第二正向扫描复位晶体管的第一极， 控制极连接反向扫描输入端；所述第二正向扫描复位晶体管的第一极连接所述第一正向扫描复位晶体管的第二极，第二极连接反向扫描控制端，控制极连接正向扫描控制端。
在一些实施例中，所述反向扫描复位子电路包括：第一反向扫描复位晶体管和第二反向扫描复位晶体管；其中，所述第一反向扫描复位晶体管的第一极连接所述第二反向扫描复位晶体管的第二极，第二极连接所述上拉节点，控制极连接正向扫描输入端；所述第二反向扫描复位晶体管的第一极连接正向扫描控制端，第二极连接第一反向扫描复位晶体管的第一极，控制极连接反向扫描控制端。
在一些实施例中，所述输出子电路包括输出晶体管和输出电容；其中，所述输出晶体管的控制极连接上拉节点，第一端连接第一时钟信号端，第二端连接输出端；所述输出电容的第一端连接上拉节点，第二端连接输出端。
在一些实施例中，所述下拉控制子电路包括第一下拉控制晶体管和第二下拉控制晶体管；其中，所述第一下拉控制晶体管的第一极连接第二下拉控制晶体管的第一极，第二极连接所述下拉节点，控制极连接所述第二下拉控制晶体管的第二极；所述第二下拉控制晶体管的第一极和控制极均连接第一控制信号端，第二极连接第一下拉控制晶体管的控制极和下拉子电路。
在一些实施例中，所述下拉子电路包括：第一下拉晶体管和第二下拉晶体管；其中，所述第一下拉晶体管的第一极连接所述下拉节点，第二极连接低电平端，控制极连接所述上拉节点；所述第二下拉晶体管的第一极连接下拉控制子电路，第二极连接低电平端，控制极连接上拉节点。
在一些实施例中，所述降噪子电路包括：第一降噪晶体管和第二降噪晶体管；其中，所述第一降噪晶体管的第一极连接上拉节点，第二极连接第二控制信号端，控制极连接下拉节点；所述第二降噪晶体管的第一极连接上拉节点，第二极连接第二控制信号端，控制极连接所述下拉节点。
在一些实施例中，所述移位寄存器还包括：输出重置子电路，用于在每一帧画面扫描结束后，在第二控制信号的控制下，通过非工作电平信号对所述信号输出端所输出的信号重置。
在一些实施例中，所述输出重置子电路包括：输出重置晶体管；其中，所述输出重置晶体管的第一极连接所述信号输出端，第二极连接低电平信号端，控制极连接第二控制信号端。
根据本公开的另一方面，还提供了一种如前所述的移位寄存器的驱动方法，包括：在正向扫描的预充阶段，采用正向扫描输入子电路，对上拉节点进行预充电；在反向扫描的预充阶段，采用反向扫描输入子电路，对上拉节点进行预充电。
在一些实施例中，所述驱动方法还包括：在正向扫描的复位阶段，采用正向扫描复位子电路，对上拉节点进行复位；在反向扫描的复位阶段，采用反向扫描复位子电路，对上拉节点进行复位。
在一些实施例中，所述正向扫描预充阶段包括：通过第一信号端所提供正向输入信号和正向扫描控制端所提供的工作电平信号控制正向扫描输入子电路打开，并将正向扫描控制端所提供的工作电平信号，对上拉节点进行预充电；所述反向扫描预充阶段包括：通过第二信号所提供反向输入信号和反向扫描控制端所提供的工作电平信号控制反向扫描输入子电路打开，并将反向扫描控制端所提供的工作电平信号，对上拉节点进行预充电。
在一些实施例中，所述正向扫描复位阶段包括：通过第二信号端所提供正向复位信号和正向扫描控制端所提供的工作电平信号控制正向扫描复位子电路打开，并通过反向扫描控制端所提供的非工作电平信号对上拉节点进行复位；所述反向扫描复位阶段包括：通过第一信号端所提供反向复位信号和反向扫描控制端所提供的工作电平信号控制反向扫描复位子电路打开，并通过正向扫描控制端所提供的非工作电平信号对上拉节点进行复位。
根据本公开的另一方面，还提供了一种栅极驱动电路，包括多个级联级的移位寄存器，所述移位寄存器单元为如前所述的移位寄存器单元。
根据本公开的另一方面，还提供了一种显示装置，包括如前所述的栅极驱动电路。
由于，本公开的移位寄存器包括用于正向扫描时用的正向扫描输入模块和正向扫描复位模块，以及用于反向扫描时用的反向输入模块和反向扫描复 位模块，也即，在对显示面板正向扫描和反向扫描分别用不同输入模块和复位模块，以使输入信号和复位信号在正向扫描和反向扫描时被切换成不同的回路，从而保证用于正向扫描的正向扫描输入模块和正向扫描复位模块，以及用于反向扫描时用的反向扫描输入模块和反向扫描复位模块在工作状态下的电流方向不变，进而解决现有移位寄存器中信赖性横纹不良的问题。
附图说明
图1为现有的移位寄存器的结构示意图；
图2为本公开的一个实施例的移位寄存器的示意图；
图3为本公开的一个实施例的移位寄存器的驱动方法中正向扫描的时序图；
图4为本公开的一个实施例的移位寄存器的驱动方法中反向扫描的时序图；
图5a是根据本实施例的移位寄存器的示例性的驱动方法的流程图；
图5b是根据本实施例的移位寄存器的示例性的驱动方法的流程图；以及
图6示出了根据本公开的实施例的示例性的显示装置。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极在一定条件下是可以互换的，所以其源极、漏极从连接关系的描述上是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以晶体管为N型晶体管进行说明的。当采用N型晶体管时，第一极为N型晶体管的漏极，第二极为N型晶体管的源极，栅极输入 高电平时，源漏极导通，P型相反。可以想到的是采用晶体管为P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本公开实施例的保护范围内的。
在本公开提供的实施例中所述的工作电平是指高电平信号，非工作电平是指低电平信号。本领域技术人员可以理解，当采用不同类型的晶体管实现本公开描述的实施例时，可以根据实际情况改变晶体管的驱动时序以实现本公开提供的原理。
图1示出了一种现有的移位寄存器的结构示意图，该移位寄存器由10个晶体管和1个输出电容构成，发明人发现该种移位寄存器在正向扫描和反向扫描切换时控制信号输入端和复位信号端所输入的两个信号的晶体管中的电流方向会发生变化，从而导致在高温条件下，长时间正向扫描后切换反向扫描会发生移位寄存器信赖性横纹不良。
图2为本公开的一个实施例的移位寄存器的示意图。如图2所示，本公开提供一种移位寄存器，包括：正向扫描输入子电路1、反向扫描输入子电路2以及输出子电路5。
其中，正向扫描输入子电路1的第一端连接到正向扫描控制端VDS，第二端连接正向扫描输入端INPUT1，第三端连接上拉节点PU。反向扫描输入子电路2的第一端连接到反向扫描控制端VSD，第二端连接反向扫描输入端INPUT2，第三端连接上拉节点PU。
其中，在移位寄存器单元进行正向扫描的工作期间，正向扫描模输入块1在正向扫描控制端的控制下将正向输入信号输入到上拉节点PU。同时，在正向扫描工作期间，反向扫描输入子电路2配置成在反向扫描控制端VSD输入的反向扫描控制信号的控制下处于非工作状态。
在移位寄存器单元进行反向扫描的工作期间，反向扫描输入子电路2在反向扫描控制端的控制下将反向输入信号输入到上拉节点PU。同时，在反向扫描工作期间，正向扫描输入子电路1配置成在正向扫描控制端VDS输入的正向扫描控制信号的控制下处于非工作状态。
输出子电路5用于在上拉节点PU的电位控制下，将第一时钟信号端CLK 输入的时钟信号通过信号输出端OUTPUT进行输出。
在一些实施例中，正向扫描输入子电路1包括第一正向扫描输入晶体管M12和第二正向扫描输入晶体管M1。其中，第一正向扫描输入晶体管M12的控制极与第一极相连，并连接到正向扫描控制端VDS。第二正向扫描输入晶体管M1的控制极连接正向扫描输入端INPUT1，第一极连接第一正向扫描输入晶体管M12的第二极，第二极连接上拉节点PU。
在一些实施例中，反向扫描输入子电路2包括第一反向扫描输入晶体管M4和第二反向扫描输入晶体管M2。其中，第一反向扫描输入晶体管M4的控制极与第一极相连，并连接到反向扫描控制端VSD。第二反向扫描输入晶体管M2的控制极连接反向扫描输入端INPUT2，第一极连接第一反向扫描输入晶体管M12的第二极，第二极连接上拉节点PU。
在一些实施例中，输出子电路5包括输出晶体管M3和输出电容C1。其中，输出晶体管M3的控制极连接上拉节点PU，第一端连接第一时钟信号端CLK，第二端连接输出端OUTPUT。输出电容C1的第一端连接上拉节点PU，第二端连接输出端OUTPUT。
如图2所示出的，在一些实施例中，移位寄存器单元可以进一步包括：正向扫描复位子电路3、反向扫描复位子电路4、下拉控制子电路6、下拉子电路7、降噪子电路8。
其中，正向扫描复位子电路3用于正向扫描时，在正向复位信号和正向扫描信号的控制下，通过非工作电平信号对上拉节点PU进行复位。
在一些实施例中，正向扫描复位子电路3可以包括：第一正向扫描复位晶体管M15和第二正向扫描复位晶体管M16。其中，第一正向扫描复位晶体管M15的第一极连接上拉节点PU，第二极连接第二正向扫描复位晶体管M16的第一极，控制极连接反向扫描输入端INPUT2。第二正向扫描复位晶体管M16的第一极连接第一正向扫描复位晶体管M15的第二极，第二极连接反向扫描控制端VSD，控制极连接正向扫描控制端VDS。
反向扫描复位子电路4用于反向扫描时，在反向复位信号和反向扫描信号的控制下，通过非工作电平信号对上拉节点PU进行复位。
在一些实施例中，反向扫描复位子电路4可以包括：第一反向扫描复位晶体管M13和第二反向扫描复位晶体管M14。其中，第一反向扫描复位晶体管M13的第一极连接第二反向扫描复位晶体管M14的第二极，第二极连接上拉节点PU，控制极连接正向扫描输入端INPUT1。第二反向扫描复位晶体管M14的第一极连接正向扫描控制端VDS，第二极连接第一反向扫描复位晶体管M13的第一极，控制极连接反向扫描控制端VSD。
下拉控制子电路6用于在工作电平和上拉节点PU的电位的控制下，控制下拉节点PD的电位。下拉节点PD为下拉控制子电路6、下拉子电路7、降噪子电路8之间的连接节点。
在一些实施例中，下拉控制子电路6包括第一下拉控制晶体管M5和第二下拉控制晶体管M9。其中，第一下拉控制晶体管M5的第一极连接第二下拉控制晶体管M9的第一极，第二极连接所述下拉节点PD，控制极连接所述第二下拉控制晶体管M9的第二极。第二下拉控制晶体管M9的第一极和控制极均连接第一控制信号端GCH，第二极连接第一下拉控制晶体管M5的控制极和下拉子电路7。在一些实施例中，第一控制信号端GCH可以输入高电平的信号。
下拉子电路7用于在上拉节点PU的电位的控制下，通过非工作电平信号对下拉节点PD的电位进行下拉。
在一些实施例中，下拉子电路7包括：第一下拉晶体管M6和第二下拉晶体管M8。其中，第一下拉晶体管M6的第一极连接所述下拉节点PD，第二极连接低电平端，控制极连接所述上拉节点PU。第二下拉晶体管M8的第一极连接下拉控制子电路6，第二极连接低电平端，控制极连接上拉节点PU。
降噪子电路8用于在下拉节点PD的控制下，通过非工作电平信号降低上拉节点PU和信号输出端OUTPUT的输出噪声。
在一些实施例中，降噪子电路8包括：第一降噪晶体管M10和第二降噪晶体管M11。其中，第一降噪晶体管M10的第一极连接上拉节点PU，第二极连接第二控制信号端VGL，控制极连接下拉节点PD。第二降噪晶体管M11的第一极连接上拉节点PU，第二极连接第二控制信号端VGL，控制极连接所 述下拉节点PD。在一些实施例中，第二控制信号端VGL可以输入低电平的信号。
在一些实施例中，如图2所示的移位寄存器单元还可以包括输出重置子电路9，用于在每一帧画面扫描结束后，在第二控制信号的控制下，通过非工作电平信号对所述信号输出端OUTPUT所输出的信号重置。
例如，输出重置子电路9可以包括：输出重置晶体管M7。其中，输出重置晶体管M7的第一极连接所述信号输出端OUTPUT，第二极连接低电平信号端，控制极连接第二控制信号端GCL。
由于本公开提供的移位寄存器包括用于正向扫描时用的正向扫描输入子电路1和正向扫描复位子电路3，以及用于反向扫描时用的反向扫描输入子电路2和反向扫描复位子电路4，也即在对显示面板正向扫描和反向扫描分别用不同输入子电路和复位子电路，以使输入信号和复位信号在正向扫描和反向扫描时被切换成不同的回路，从而保证正向扫描输入子电路1和正向扫描复位子电路3，以及用于反向扫描时用的反向扫描输入子电路2和反向扫描复位子电路4在工作状态下的电流方向不变，进而解决现有移位寄存器中信赖性横纹不良的问题。
图3示出了根据本公开的实施例的移位寄存器在正向扫描期间的时序图。
在正向扫描期间，正向扫描控制端VDS所输入的信号为常高信号，反向扫描控制端VSD所输入的信号为常低信号。在正向扫描的预充阶段，正向扫描输入端INPUT1输入高电平信号，因此，第二正向扫描输入晶体管M1和第一正向扫描输入晶体管M12被导通，并通过正向扫描控制端VDS所输入的高电平为上拉节点PU进行预充电。此时，第一反向扫描输入晶体管M4在反向扫描控制端VSD的控制下关断，使得反向扫描输入子电路2在正向扫描期间处于非工作状态。
在上拉节点PU被预充至高电平后，输出晶体管M3在上拉节点PU的控制下导通。与此同时，第一时钟信号端CLK被写入高电平信号，信号输出端OUTPUT则输出高电平信号。
在正向扫描的复位阶段，反向扫描输入端INPUT2输入高电平信号，正 向扫描控制端VDS所输入的信号为常高信号，反向扫描控制端VSD所输入的信号为常低信号。因此，第一正向扫描复位晶体管M15和第二正向扫描复位晶体管M16被导通，并通过反向扫描控制端VSD所输入的低电平信号，拉低上拉节点PU的电位，以完成上拉节点PU的复位。
图4示出了根据本公开的实施例的移位寄存器在反向扫描期间的时序图。
在反向扫描期间，反向扫描控制端VSD所输入的信号为常高信号，正向扫描控制端VDS所输入的信号为常低信号。在反向扫描的预充阶段，反向扫描输入端INPUT2输入高电平信号，因此，第二反向扫描输入晶体管M2和第一反向扫描输入晶体管M4被导通，并通过反向扫描控制端所输入的高电平信号为上拉节点PU进行预充电。此时，第一正向扫描输入晶体管M12在正向扫描控制端VDS的控制下关断，使得正向扫描输入子电路1在反向扫描期间处于非工作状态。
在上拉节点PU被预充至高电平后，输出晶体管M3在上拉节点PU的控制下导通。与此同时，第一时钟信号端CLK被写入高电平信号，信号输出端OUTPUT则输出高电平信号。
在反向扫描的复位阶段，正向扫描输入端INPUT1输入高电平信号，同时在反向扫描时，正向扫描控制端VDS所输入的信号为常低信号，反向扫描控制端VSD所输入的信号为常高信号。因此，第一反向扫描复位晶体管M13和第二反向扫描复位晶体管M14被导通，通过正向扫描控制端VDS所输入的低电平信号，拉低上拉节点PU的电位，以完成上拉节点PU的复位。
在上述实施例中，以第一控制信号端GCH被输入一常高信号为例进行说明，第一下拉控制晶体管M5和第二下拉控制晶体管M9被导通，下拉节点PD的电位被拉至高电位。当然，第一控制信号端所输入的信号也可以为时钟信号，只要该时钟信号与第一时钟信号端CLK所输入的信号相差半个周期。
当上拉节点PU处于高电位时，第一下拉晶体管M6和第二下拉晶体管M8被导通，下拉节点PD被低电平信号端所输入的低电平信号下拉至低电平，同时，下拉控制子电路6的输出也被下拉至低电平。
当下拉节点PD处于高电平时，第一降噪晶体管M10和第二降噪晶体管 M11在下拉节点PD的控制下导通，并通过低电平信号端所输入的低电平信号，降低上拉节点PU和信号输出端OUTPUT所输出信号的噪声。
在一帧画面扫描后，需要对各移位寄存器的输出进行重置，因此，在一帧画面扫描完成后，给第二控制信号端GCL输入高电平信号，以使输出重置晶体管M7导通，通过低电平信号端所输入的低电平信号拉低信号输出端OUTPUT的输出。此时可以将第一控制信号端GCH所输入的高电平信号反转至低电平。
图5a和图5b是根据本实施例的移位寄存器的示例性的驱动方法的流程图。该方法能够用于驱动前述实施例中的移位寄存器工作。图5a示出的是移位寄存器在正向扫描期间的驱动方法的流程图，图5b示出的是移位寄存器在反向扫描期间的驱动方法的反向扫描。
例如，在正向扫描的预充阶段，采用正向扫描输入子电路1，对上拉节点PU进行预充电。在反向扫描的预充阶段，采用反向扫描输入子电路2，对上拉节点PU进行预充电。
例如，在正向扫描预充阶段，驱动方法可以包括：
通过正向扫描输入端所提供的正向输入信号和正向扫描控制端所提供的工作电平信号控制正向扫描输入子电路导通，并将正向扫描控制端所提供的工作电平信号，对上拉节点进行预充电。
在反向扫描预充阶段，驱动方法可以包括：
通过反向扫描输入端所提供反向输入信号和反向扫描控制端所提供的工作电平信号控制反向扫描输入子电路导通，并将反向扫描控制端所提供的工作电平信号，对上拉节点进行预充电。
在正向扫描的复位阶段，采用正向扫描复位阶段，对上拉节点PU进行复位。在反向扫描的复位阶段，采用反向扫描复位子电路4，对上拉节点PU进行复位。
在正向扫描复位阶段，驱动方法可以包括：
通过反向扫描输入端所提供正向复位信号和正向扫描控制端所提供的工作电平信号控制正向扫描复位子电路导通，并通过反向扫描控制端所提供的 非工作电平信号对上拉节点进行复位。
在反向扫描复位阶段，驱动方法可以包括：
通过正向扫描输入端所提供反向复位信号和反向扫描控制端所提供的工作电平信号控制反向扫描复位子电路导通，并通过正向扫描控制端所提供的非工作电平信号对上拉节点进行复位。
结合图2以及时序图3和4所示，以下对本实施例的移位寄存器的驱动方法进行说明。
其中，正向扫描输入端用于在正向扫描时提供正向输入信号，在反向扫描时提供反向复位信号。反向扫描输入端用于在正向扫描时提供正向复位信号，在反向扫描时提供反向输入信号。正向扫描控制端用于在正向扫描时提供工作电平信号，在反向扫描时提供非工作电平信号。反向扫描控制端用于在正向扫描时提供非工作电平信号，在反向扫描时提供工作电平信号。
正向扫描：正向扫描控制端VDS所输入的正向扫描控制信号为常高信号；反向扫描控制端VSD所输入的反向扫描控制信号为常低信号。
第一阶段(预充阶段)：正向扫描输入端INPUT1输入高电平信号，正向扫描控制端VDS输入高电平信号，第一正向扫描输入晶体管M1和第二正向扫描输入晶体管M12均被导通。此时通过正向扫描控制端所输入的高电平信号为上拉节点PU进行预充电，同时为输出电容C1进行充电。输出晶体管M3在上拉节点PU的高电平的控制下导通，此时第一时钟信号端CLK所输入的低电平信号通过信号输出端OUTPUT输出。
第二阶段(输出阶段)：正向扫描输入端INPUT1所输入的信号由高电平变为低电平，并控制第一正向扫描输入晶体管M1此时关断。此时上拉节点PU仍然处于高电平，输出晶体管M3保持开启。第一下拉晶体管M6在上拉节点PU的控制下导通，并控制下拉节点PD处于低电平。与此同时第一时钟信号端CLK所输入的信号为高电平信号，因此，信号输出端OUTPUT此刻输出高电平信号。
第三阶段(复位阶段)：反向扫描输入端INPUT2输入高电平信号，第一正向扫描复位晶体管M15、第二正向扫描复位晶体管M16分别在反向扫描 输入端输入的高电平信号以及正向扫描控制端输入的高电平信号的控制下导通。此时反向扫描控制端VSD所输入的低电平信号通过第一正向扫描复位晶体管M15和第二正向扫描复位晶体管M16拉低上拉节点PU的电位，以完成上拉节点PU的复位。同时，由于第一控制信号端GCH的信号处于高电平，第一下拉控制晶体管M5和第二下拉控制晶体管M9打开，下拉节点PD的电位被拉至高电平，并通过第一降噪晶体管M10和第二降噪晶体管M11加速对输出电容C1和信号输出端OUTPUT的放电。
第四阶段(降噪阶段)：下拉节点PD保持低电平，第一降噪晶体管M10和第二降噪晶体管M11保持导通，上拉节点PU和信号输出端OUTPUT保持低电平。
在一帧画面扫描结束后，将第二控制信号端GCL输入的低电平转为高电平，以使输出重置晶体管M7导通，以对信号输出端OUTPUT所输出的信号重置为低电平。
反向扫描：正向扫描控制端VDS所输入的正向扫描控制信号为低高信号；反向扫描控制端VSD所输入的反向扫描控制信号为常高信号。
第一阶段(预充阶段)：反向扫描输入端INPUT2输入高电平信号，反向扫描控制端VSD输入高电平信号，第二反向扫描输入晶体管M2和第一反向扫描输入晶体管M4均被打开，此时通过反向扫描控制端所输入的高电平信号为上拉节点PU进行预充电，同时为输出电容C1进行充电，输出晶体管M3被上拉节点PU的高电平打开，此时第一时钟信号端CLK所输入的低电平信号通过信号输出端OUTPUT输出。
第二阶段(输出阶段)：反向扫描输入端信号端INPUT2所输入的信号由高电平变为低电平，第二正向扫描输入晶体管M1此时关断，输出电容C1放电，上拉节点PU自举，仍然处于高电平，输出晶体管M3保持开启，第一下拉晶体管M6打开，下拉节点PD处于低电平；与此同时第一时钟信号端CLK所输入的信号为高电平信号，因此，信号输出端OUTPUT此刻输出高电平信号。
第三阶段(复位阶段)：正向扫描输入端INPUT1所输入的信号高电平 信号，第一反向扫描输入晶体管M13、第二反向扫描输入晶体管M14均被导通，此时正向扫描控制端VDS所输入的低电平信号通过第一反向扫描输入晶体管M13和第二反向扫描输入晶体管M14拉低上拉节点PU的电位，以完成上拉节点PU的复位。同时，第一控制信号端GCH的信号处于高电平，第一下拉控制晶体管M5和第二下拉控制晶体管M9打开，下拉节点PD的电位被拉至高电平，此时第一降噪晶体管M10和第二降噪晶体管M11加速对输出电容C1和信号输出端OUTPUT的放电。
第四阶段(降噪阶段)：下拉节点PD保持低电平，第一降噪晶体管M10和第二降噪晶体管M11保持开启，上拉节点PU和信号输出端OUTPUT保持低电平。
在一帧画面扫描结束，将第二控制信号端GCL输入低电平转为高电平，以使输出重置晶体管M7打开，以对信号输出端OUTPUT所输出的信号重置为低电平。
由于，本实施例的移位寄存器的驱动方法中，正向扫描的预充阶段所采用晶体管为第一正向扫描输入晶体管M1和第二正向扫描输入晶体管M12，反向扫描的预充阶段所采用的晶体管为第二反向扫描输入晶体管M2和第一反向扫描输入晶体管M4，正向扫描的复位阶段所采用的晶体管为第一正向扫描复位晶体管M15和第二正向扫描复位晶体管M16，反向扫描的复位阶段所采用的晶体管为第一反向扫描输入晶体管M13和第二反向扫描输入晶体管M14，以使输入信号和复位信号在正向扫描和反向扫描时被切换成不同的回路，从而保证用于反向扫描时用的晶体管在工作状态下的电流方向不变，进而解决现有移位寄存器中信赖性横纹不良的问题。
图6示出了根据本公开的实施例的示例性的显示装置。
如图6所示，本实施例提供了一种栅极驱动电路，其包括如前所述的移位寄存器单元。
相应的，本实施例中还公开了一种显示装置，其包括上述的栅极驱动电路。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
当然，本实施例的显示装置中还可以包括其他常规结构，如电源单元、显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (19)

  1. 一种移位寄存器，包括：
    正向扫描输入子电路，用于正向扫描时，在正向输入信号和正向扫描信号的控制下，通过工作电平信号对上拉节点的电位进行预充电；
    反向扫描输入子电路，用于反向扫描时，在反向输入信号和反向扫描信号的控制下，通过工作电平信号对上拉节点的电位进行预充电；
    输出子电路，用于在所述上拉节点的电位控制下，将时钟信号通过信号输出端进行输出；
    其中，所述上拉节点是所述正向扫描输入子电路、所述反向扫描输入子电路以及所述输出子电路的连接节点。
  2. 根据权利要求1所述的移位寄存器，还包括：
    正向扫描复位子电路，用于正向扫描时，在正向复位信号和所述正向扫描信号的控制下，通过非工作电平信号对所述上拉节点进行复位；
    反向扫描复位子电路，用于反向扫描时，在反向复位信号和所述反向扫描信号的控制下，通过非工作电平信号对所述上拉节点进行复位。
  3. 根据权利要求1-2中任一所述的移位寄存器，还包括：
    下拉控制子电路，用于在所述工作电平和所述上拉节点的电位的控制下，控制下拉节点的电位；
    下拉子电路，用于在所述上拉节点的电位的控制下，通过所述非工作电平信号对所述下拉节点的电位进行下拉；
    所述降噪子电路，用于在所述下拉节点的控制下，通过所述非工作电平信号降低所述上拉节点和所述信号输出端的输出噪声；
    其中，所述下拉节点是所述下拉控制子电路、所述下拉子电路和所述降噪子电路之间的连接节点。
  4. 根据权利要求1-3中任一所述的移位寄存器，其中，所述正向扫描输入子电路包括：第一正向扫描输入晶体管和第二正向扫描输入晶体管；其中，
    所述第二正向扫描输入晶体管的控制极连接正向扫描输入端，第一极连 接所述第一正向扫描输入晶体管的第二极，第二极连接所述上拉节点；
    所述第一正向扫描输入晶体管的控制极与第一极相连，并连接到正向扫描控制端。
  5. 根据权利要求1-4中任一所述的移位寄存器，其中，所述反向扫描输入子电路包括：第一反向扫描输入晶体管和第二反向扫描输入晶体管；其中，
    所述第一反向扫描输入晶体管的控制极与第一极相连，并连接到反向扫描控制端；
    所述第二反向扫描输入晶体管的控制极连接反向扫描输入端，第一极连接第一反向扫描输入晶体管的第二极，第二极连接所述上拉节点。
  6. 根据权利要求2-5中任一所述的移位寄存器，其中，所述正向扫描复位子电路包括：第一正向扫描复位晶体管和第二正向扫描复位晶体管；其中，
    所述第一正向扫描复位晶体管的第一极连接所述上拉节点，第二极连接所述第二正向扫描复位晶体管的第一极，控制极连接反向扫描输入端；
    所述第二正向扫描复位晶体管的第一极连接所述第一正向扫描复位晶体管的第二极，第二极连接反向扫描控制端，控制极连接正向扫描控制端。
  7. 根据权利要求2-6中任一所述的移位寄存器，其中，所述反向扫描复位子电路包括：第一反向扫描复位晶体管和第二反向扫描复位晶体管；其中，
    所述第一反向扫描复位晶体管的第一极连接所述第二反向扫描复位晶体管的第二极，第二极连接所述上拉节点，控制极连接正向扫描输入端；
    所述第二反向扫描复位晶体管的第一极连接正向扫描控制端，第二极连接第一反向扫描复位晶体管的第一极，控制极连接反向扫描控制端。
  8. 根据权利要求1-7中任一所述的移位寄存器，其中，所述输出子电路包括输出晶体管和输出电容；其中，
    所述输出晶体管的控制极连接上拉节点，第一端连接第一时钟信号端，第二端连接输出端；
    所述输出电容的第一端连接上拉节点，第二端连接输出端。
  9. 根据权利要求3-8中任一所述的移位寄存器，其中，所述下拉控制子电路包括第一下拉控制晶体管和第二下拉控制晶体管；其中，
    所述第一下拉控制晶体管的第一极连接第二下拉控制晶体管的第一极，第二极连接所述下拉节点，控制极连接所述第二下拉控制晶体管的第二极；
    所述第二下拉控制晶体管的第一极和控制极均连接第一控制信号端，第二极连接第一下拉控制晶体管的控制极和下拉子电路。
  10. 根据权利要求3-9中任一所述的移位寄存器，其中，所述下拉子电路包括：第一下拉晶体管和第二下拉晶体管；其中，
    所述第一下拉晶体管的第一极连接所述下拉节点，第二极连接低电平端，控制极连接所述上拉节点；
    所述第二下拉晶体管的第一极连接下拉控制子电路，第二极连接低电平端，控制极连接上拉节点。
  11. 根据权利要求3-10中任一所述的移位寄存器，其中，所述降噪子电路包括：第一降噪晶体管和第二降噪晶体管；其中，
    所述第一降噪晶体管的第一极连接上拉节点，第二极连接第二控制信号端，控制极连接下拉节点；
    所述第二降噪晶体管的第一极连接上拉节点，第二极连接第二控制信号端，控制极连接所述下拉节点。
  12. 根据权利要求1-11中任一所述的移位寄存器，其中，还包括：输出重置子电路，用于在每一帧画面扫描结束后，在第二控制信号的控制下，通过非工作电平信号对所述信号输出端所输出的信号重置。
  13. 根据权利要求12所述的移位寄存器，其中，所述输出重置子电路包括：输出重置晶体管；其中，
    所述输出重置晶体管的第一极连接所述信号输出端，第二极连接低电平信号端，控制极连接第二控制信号端。
  14. 一种如权利要求1-13中任一所述的移位寄存器的驱动方法，包括：
    在正向扫描的预充阶段，采用正向扫描输入子电路，对上拉节点进行预充电；
    在反向扫描的预充阶段，采用反向扫描输入子电路，对上拉节点进行预充电。
  15. 根据权利要求14所述的移位寄存器的驱动方法，还包括：
    在正向扫描的复位阶段，采用正向扫描复位子电路，对上拉节点进行复位；
    在反向扫描的复位阶段，采用反向扫描复位子电路，对上拉节点进行复位。
  16. 根据权利要求14所述的移位寄存器的驱动方法，其中，所述正向扫描预充阶段包括：
    通过第一信号端所提供正向输入信号和正向扫描控制端所提供的工作电平信号控制正向扫描输入子电路打开，并将正向扫描控制端所提供的工作电平信号，对上拉节点进行预充电；
    所述反向扫描预充阶段包括：
    通过第二信号所提供反向输入信号和反向扫描控制端所提供的工作电平信号控制反向扫描输入子电路打开，并将反向扫描控制端所提供的工作电平信号，对上拉节点进行预充电。
  17. 根据权利要求15所述的移位寄存器的驱动方法，其中，所述正向扫描复位阶段包括：
    通过第二信号端所提供正向复位信号和正向扫描控制端所提供的工作电平信号控制正向扫描复位子电路打开，并通过反向扫描控制端所提供的非工作电平信号对上拉节点进行复位；
    所述反向扫描复位阶段包括：
    通过第一信号端所提供反向复位信号和反向扫描控制端所提供的工作电平信号控制反向扫描复位子电路打开，并通过正向扫描控制端所提供的非工作电平信号对上拉节点进行复位。
  18. 一种栅极驱动电路，包括多个级联级的移位寄存器，所述移位寄存器单元为权利要求1-13中任一项所述的移位寄存器。
  19. 一种显示装置，包括权利要求18中所述的栅极驱动电路。
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