WO2016021397A1 - 貫通電極基板及びその製造方法、並びに貫通電極基板を用いた半導体装置 - Google Patents

貫通電極基板及びその製造方法、並びに貫通電極基板を用いた半導体装置 Download PDF

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WO2016021397A1
WO2016021397A1 PCT/JP2015/070636 JP2015070636W WO2016021397A1 WO 2016021397 A1 WO2016021397 A1 WO 2016021397A1 JP 2015070636 W JP2015070636 W JP 2015070636W WO 2016021397 A1 WO2016021397 A1 WO 2016021397A1
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electrode
substrate
electrode substrate
base
etching
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PCT/JP2015/070636
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English (en)
French (fr)
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浅野　雅朗
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大日本印刷株式会社
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Priority to CN201580040076.XA priority Critical patent/CN106664794B/zh
Publication of WO2016021397A1 publication Critical patent/WO2016021397A1/ja
Priority to US15/422,990 priority patent/US10008442B2/en

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    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
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    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
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    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed

Definitions

  • the present invention relates to a through electrode substrate, a manufacturing method thereof, and a semiconductor device using the through electrode substrate.
  • the through electrode is formed by filling the through hole with a conductive material by electrolytic plating or the like.
  • a through electrode substrate manufactured using an SOI wafer is disclosed (see Patent Document 1).
  • a blind via hole having a depth reaching the buried insulating layer is provided in the supporting substrate layer of the SOI wafer, and an inner wall insulating layer is applied to the inner wall of the via hole to provide the through electrode.
  • the buried insulating layer exposed by removing the silicon layer is provided with a contact hole in a portion corresponding to the through electrode.
  • the conventional through electrode substrate has a structure in which an insulating layer is provided on the surface, and the through electrode is exposed through a contact hole provided in the insulating layer so as to be conductive.
  • . 25 and 26 show the structure of such a through electrode substrate 800 in cross-sectional views.
  • the base 801 has a surface 801a and a surface 801b facing each other, and a through electrode 803 is disposed in a through-hole penetrating the surface 801a and the surface 801b.
  • a wiring 804 is disposed on the surface 801 b of the base 801 and the surface 803 b of the through electrode 803.
  • FIG. 26 is an enlarged view of the vicinity of the through electrode substrate 800 shown in FIG. 25 surrounded by a dotted line, and shows the vicinity of the periphery 803c on the surface 803b side of the through electrode 803.
  • a through electrode 803 is formed by filling a hole provided in the base body 801 by electrolytic plating. However, a minute space is formed between the side surface 803d of the through electrode 803 and the base body 801. May occur.
  • the through electrode 803 is arranged on the base 801, the surface 801b of the base 801 and the surface 803b of the through electrode 803 are polished by CMP or the like. In some cases, space is generated. If the space 881 generated by such a cause exists, the wiring 804 is disconnected, and a connection failure with the through electrode 803 occurs. Alternatively, when the space 881 is filled with gas, the connection reliability of the wiring 804 is reduced.
  • FIG. 27 and 28 are cross-sectional views of another form of the through electrode substrate 900.
  • FIG. FIG. 28 is a view showing a process of forming the through electrode substrate 900, and is an enlarged view of the vicinity surrounded by a dotted line in FIG.
  • a through electrode 903 that penetrates the surface 901a and the surface 901b of the base body 901 is disposed.
  • the through electrodes 903 exposed on the surface 901a side and the surface 901b side of the base 901 are referred to as a surface 903a and a surface 903b, respectively.
  • a surface of the through electrode 903 that is in contact with the base body 901 is a side surface 903d.
  • the insulating layer 930 is disposed on the surface 901 b of the base body 901 and a part on the surface 903 b of the through electrode 903 from the surface 901 b.
  • a wiring 904 is arranged on the insulating layer 930 and on the surface 903b of the through electrode 903 where the insulating layer 930 is not formed.
  • an insulating layer 930 is formed on a part of the surface 901b of the base 901 and part of the surface 903b of the through electrode 903. Since the insulating layer 930 is also formed in the vicinity of the peripheral edge 903c of the through electrode 903, the side surface 903d of the peripheral edge 903c is covered with the base 901 and the surface 903b side is covered with the insulating layer 930.
  • the peripheral edge 903c of the through electrode 903 is covered.
  • the insulating layer 930 is undercut during the manufacturing process, resulting in a gap. Then, the insulating layer 930 is structurally lacking in stability, which causes the wiring 904 to be disconnected.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a through-electrode substrate that is structurally stable by eliminating the problems caused by the structure occurring at the boundary between the through-electrode and the substrate. To do.
  • a base body having a first surface and a second surface facing each other, and a through electrode disposed in a through hole penetrating the first surface and the second surface of the base body,
  • the through electrode has an end surface on the first surface side and an end surface on the second surface side exposed from the base on the first surface and the second surface, and an end surface on the first surface side and an end surface on the second surface side.
  • the base body may be located at the periphery of the through electrode or outside the periphery, and may have an annular convex portion along the periphery.
  • the substrate may include glass.
  • the substrate may include silicon, and an insulating film may be disposed on the inner wall surface of the through hole.
  • a member made of the same material as that of the base may be disposed inside one or both of the end surface on the first surface side and the end surface on the second surface side whose peripheral edge is covered with the base material.
  • a plurality of wirings may be arranged on one or both of the end surface on the first surface side and the end surface on the second surface side whose peripheral edge is covered with the substrate.
  • an opening is formed in the first surface of the base body having the first surface and the second surface facing each other at a depth not reaching the second surface.
  • An electrode is formed by filling the substrate with a conductive material, and a mask is formed on the second surface of the base body, the mask having an opening in a part of the inner region of the electrode and covering the periphery of the electrode.
  • a method of manufacturing a through electrode substrate is provided, wherein the second surface of the substrate is etched to expose a part of the inner region of the electrode and to leave a part of the substrate at the periphery of the electrode. .
  • the mask may be formed in an annular shape.
  • the mask may include isotropic etching at least partially.
  • the etching mask may be removed as the etching progresses.
  • a semiconductor device having the above-described through electrode substrate is provided.
  • a through electrode penetrating through two opposite surfaces of a base is disposed, and the periphery of at least one surface of the through electrode is covered with the base, so that a structurally stable through electrode substrate is provided. be able to.
  • the manufacturing method of the penetration electrode substrate concerning a 1st embodiment of the present invention is a mimetic diagram showing a section of a substrate provided with a bottomed hole.
  • the manufacturing method of the penetration electrode substrate concerning a 1st embodiment of the present invention is a mimetic diagram showing the section of the substrate in which the penetration electrode was provided.
  • the manufacturing method of the penetration electrode substrate concerning a 1st embodiment of the present invention it is a mimetic diagram showing the section of the substrate in which the mask was formed.
  • the manufacturing method of the penetration electrode substrate concerning a 1st embodiment of the present invention it is a mimetic diagram showing the section of the substrate in the middle of etching.
  • the manufacturing method of the penetration electrode substrate concerning a 1st embodiment of the present invention is a mimetic diagram showing the section of the substrate in the middle of etching.
  • the top view and perspective view of a substrate which completed etching are shown.
  • the manufacturing method of the penetration electrode substrate concerning a 1st embodiment of the present invention it is a mimetic diagram showing the section of the substrate in which the wiring layer was formed.
  • the manufacturing method of the penetration electrode substrate concerning a 1st embodiment of the present invention it is a mimetic diagram showing the section of the substrate in which the insulating layer was formed.
  • the manufacturing method of the penetration electrode substrate concerning the modification of a 1st embodiment of the present invention it is a mimetic diagram showing the section of the substrate where etching was completed.
  • the manufacturing method of the penetration electrode substrate concerning the modification of a 1st embodiment of the present invention it is a mimetic diagram showing the state where the penetration electrode protruded from the convex part of the base.
  • the manufacturing method of the penetration electrode substrate concerning the modification of a 1st embodiment of the present invention it is a mimetic diagram showing the state where the penetration electrode which protruded from the convex part of the base was made flat.
  • the manufacturing method of the penetration electrode substrate concerning a 2nd embodiment of the present invention it is a mimetic diagram showing the section of the substrate in the middle of etching.
  • the manufacturing method of the penetration electrode substrate concerning a 2nd embodiment of the present invention it is a mimetic diagram showing the section of the substrate in which the mask was formed. In the manufacturing method of the penetration electrode substrate concerning a 2nd embodiment of the present invention, it is a mimetic diagram showing the section of the substrate where etching was completed. In the manufacturing method of the penetration electrode substrate concerning a 2nd embodiment of the present invention, it is a mimetic diagram showing the section of the substrate in which the wiring layer and the insulating layer were formed. It is a schematic diagram which shows the upper surface and cross section of the penetration electrode substrate which concern on 3rd Embodiment of this invention.
  • the through electrode substrate of the present invention is not limited to the following embodiments, and can be implemented with various modifications. In all the embodiments, the same components are described with the same reference numerals. In addition, the dimensional ratio in the drawing may be different from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.
  • FIG. 8 is a plan view and a perspective view of the through electrode substrate 100 according to the first embodiment of the present invention.
  • 8A is a plan view seen from the second surface 101b side of the base 101 constituting the through electrode substrate 100
  • FIG. 8B is a perspective view seen from an oblique direction on the second surface 101b side of the base 101.
  • FIG. FIG. FIG. 7 is a schematic diagram of a cross section when viewed in the AA ′ direction of FIG.
  • the through electrode substrate 100 has a through electrode 103 disposed on a base 101.
  • the base 101 has a first surface 101a and a second surface 101b that face each other.
  • the first surface 103 a is exposed from the first surface 101 a side of the base 101
  • the second surface 103 b is exposed from the second surface 101 b side of the base 101.
  • the side surface 103 d of the through electrode 103 is in contact with the base body 101.
  • the second surface 103 b of the through electrode 103 is covered with the base 101 at the periphery 103 c and the periphery thereof, and the other inner region is exposed from the base 101. That is, the peripheral edge 103c is covered with the base body 101 on both the side surface 103d side and the second surface 103b side.
  • the portion where the base 101 covers the peripheral edge 103c of the through electrode 103 and the second surface 103b in the vicinity thereof is thinner than the other portions, and the thin region (region where the thickness is reduced) 101e. Is formed.
  • FIG. 1 shows a cross section of a substrate in which a bottomed hole 102 is provided in a base 101 in the method of manufacturing a through electrode substrate 100.
  • the base 101 has an insulating property at least on the surface.
  • the substrate 101 for example, glass (blue plate glass, low expansion glass, non-alkali glass, etc.), sapphire, resin, or the like is used.
  • the thickness of the substrate 101 may be formed within a range of 100 ⁇ m to 1 mm.
  • the base 101 may be a base having an insulating surface provided with an insulating film on the surface of a conductive substrate.
  • an insulating film may be formed on the surface of a conductive substrate such as silicon.
  • the thickness of the insulating film may be formed within a range of 0.1 ⁇ m to 5 ⁇ m.
  • an insulating film be formed on the inner wall surface of the bottomed hole 102 to provide the insulating film on the inner wall surface of the final through hole.
  • an etching process for removing the insulating film is required in FIG. 7 described later.
  • the base 101 has a first surface 101a and a second surface 101b facing each other.
  • a mask (not shown) is formed on the first surface 101a side of the substrate 101, and the bottomed hole 102 is formed by etching.
  • Etching methods include second etching of the substrate 101 by dry etching processing such as RIE (Reactive Ion Etching) and DRIE (Deep RIE), wet etching processing, laser processing, and the like.
  • RIE Reactive Ion Etching
  • DRIE Deep RIE
  • wet etching processing laser processing, and the like.
  • a bottomed hole 102 that does not penetrate to the surface 101b side can be formed.
  • the depth of the bottomed hole 102 depends on the thickness of the substrate 101, but can be set to 100 ⁇ m to 500 ⁇ m, for example.
  • the size of the opening of the bottomed hole 102 is not particularly limited, and can be, for example, 10 ⁇ m to 100 ⁇ m.
  • the shape of the bottomed hole 102 typically shows a straight shape in the thickness direction of the base 101 as shown in each drawing, but is not limited thereto.
  • the opening on the first surface 101a side may be wide, and the bottom on the second surface 101b side may be narrowed to have a tapered shape.
  • the shape of the bottomed hole 102 on the plan view is not particularly limited and is typically a circle, but may be a rectangle or a polygon other than a circle.
  • FIG. 2 is a cross-sectional view showing a state in which the through electrode 103 is formed in the bottomed hole 102.
  • the through electrode 103 is formed by providing a conductive material so as to fill the bottomed hole 102.
  • a metal such as Cu is used as the conductive material.
  • an electrolytic plating filling method can be used.
  • electrolytic plating is performed, electrolytic plating is performed after forming a seed layer, that is, a base layer for plating formation (not shown).
  • a portion to be plated is exposed with a resist prepared by a lithography method.
  • the first surface 101a of the base 101 and the first surface 103a of the through electrode 103 are planarized by CMP (Chemical Mechanical Polishing) or the like.
  • the opening side (the first surface 101a side of the base body 101) of the through-hole electrode 103 disposed in the bottomed hole 102 is defined as the first surface 103a
  • the bottom side (base body 101) of the bottomed hole 102 is provided.
  • the second surface 101b side) is defined as a second surface 103b.
  • the surface in contact with the base 101 is referred to as a side surface 103d.
  • FIG. 3 is a cross-sectional view showing a state in which a mask 130 for etching is formed on the second surface 101b side of the base 101.
  • the mask 130 is disposed in the vicinity of the peripheral edge 103 c of the second surface 103 b of the through electrode 103 when seen through the second surface 101 b of the base 101 from the second surface 101 b side. At this time, it arrange
  • the mask 130 is arranged in this way because when the second surface 101b of the substrate 101 is isotropically etched after the mask 130 is arranged, the etching in the vicinity of the peripheral edge 103c of the second surface 103b of the through electrode 103 is delayed. This is to prevent the peripheral edge 103c of the second surface 103b of 103 from being exposed.
  • the mask 130 is arranged on the second surface 101 b of the base 101 in a ring shape following the peripheral edge 103 c of the through electrode 103.
  • the mask 130 is disposed along the shape on the plane of the second surface 103 b of the through electrode 103.
  • isotropic etching is performed from the opposite side of the first surface 101a of the base 101 in which the bottomed hole 102 is formed, that is, from the second surface 101b side of the base 101 that is the bottom of the bottomed hole 102. I do.
  • isotropic etching a wet etching process will be described.
  • the substrate 101 is glass
  • hydrofluoric acid is used as the etchant.
  • the mask 130 is made of a material resistant to hydrofluoric acid, and is formed by patterning, for example, chromium, copper, or the like by a resist plate making etching process. Note that a protective layer is formed before wet etching so that the first surface 101a side of the substrate 101 is not etched.
  • FIG. 7 is a cross-sectional view showing a state in which isotropic etching is completed, and shows the through electrode substrate 100 according to the first embodiment of the present invention.
  • FIG. 6 shows a state where the mask 130 and the portion where the second surface 101b of the base body 101 is in contact are all etched and the mask 130 is peeled off.
  • Etching is further advanced from FIG. 6, and etching is finally performed to the state shown in FIG. Referring to FIG. 7, the base body 101 is not completely etched in the vicinity of the periphery 103c of the second surface 103b of the through electrode 103, and a part of the base body 101 remains as a thin region 101e.
  • the second surface 103 b other than the vicinity of the peripheral edge 103 c of the through electrode 103 is exposed from the base body 101 as etching progresses. That is, the through electrode 103 is disposed in a through hole that penetrates between the first surface 101 a and the second surface 103 b of the base 101.
  • the periphery 103c of the through electrode 103 and the second surface 103b in the vicinity thereof are covered with the base 101. .
  • FIG. 8A is a plan view of the base 101 viewed from the second surface 101b side.
  • the second surface 103 b of the through electrode 103 is covered with a part of the second surface 101 b of the base 101 at the periphery 103 c and the vicinity thereof.
  • a region inside the second surface 103 b of the through electrode 103 is exposed from the second surface 101 b of the base 101.
  • FIG. 8B is a perspective view of the base 101 viewed from an oblique direction on the second surface 101b side.
  • an annular convex portion 101c is formed from a portion where the peripheral edge 103c of the penetrating electrode 103 formed in a circle is disposed and a portion located outside the portion.
  • the convex portion 101c is formed because the portion where the mask 130 is disposed is slower in etching than the portion where the mask 130 is not disposed.
  • the peripheral edge 103c of the through electrode 103 has a structure in which the side surface 103d side and the second surface 101b side are both covered with the base body 101.
  • FIG. 9 is a cross-sectional view of the through electrode substrate 110 in which the wiring layer 104 is formed on the second surface 101 b of the base body 101 and the second surface 103 b of the through electrode 103.
  • a conductive material is used for the wiring layer 104.
  • the conductive material for example, a metal material is applied to the second surface 101b side of the substrate 101, and is formed by a patterning method using photolithography.
  • an electronic component or the like may be mounted in addition to the wiring layer 104.
  • FIG. 10 shows a cross section of the through electrode substrate 120 in which the insulating layer 105 is further formed from FIG. 9, and is a cross sectional view seen from the B-B ′ direction of FIG.
  • a photosensitive resin is used for the insulating layer 105.
  • patterning by photolithography is performed and baking is performed, whereby the insulating layer 105 is formed.
  • an opening 106 reaching the wiring layer 104 is formed in the insulating layer 105.
  • FIG. 11 is a top view of the through electrode substrate 120 as viewed from the insulating layer 105 side.
  • the wiring layer 104 is formed so as to surround the peripheral edge 103 c of the circular through electrode 103.
  • the wiring layer 104 is further extended from the through electrode 103 in the direction of the opening 106 so as to surround the region where the opening 106 is formed in a rectangular shape.
  • a circle shown inside the circle indicating the peripheral edge 103 c of the through electrode 103 indicates a region exposed from the second surface 101 b side of the base 101 on the second surface 103 b of the through electrode 103.
  • the through electrode substrate 100 As described above, in the formation of the through electrode substrate 100 according to the first embodiment, there is a step of leaving the base body 101 near the periphery 103c of the through electrode 103, but the second surface 103b of the through electrode 103 and the base body 101 are left. There is no step of polishing the second surface 101b. Therefore, as described with reference to FIGS.
  • the substrate 801 is broken due to the polishing of the surface 803b of the through electrode 803 and the surface 801b of the substrate 801, the wiring 804 is disconnected due to the defect of the substrate 801, the substrate 801 and Problems such as a decrease in reliability of the connection of the wiring 804 due to the generation of a space between the through electrode 103 do not occur in the through electrode substrate 100 according to the first embodiment.
  • the periphery 103c of the second surface 103b of the through electrode 103 is covered with the base body 101 on both the side surface 103d side and the second surface 103b side.
  • the peripheral edge 903c of the through electrode 903 is covered with the base body 901 and the upper surface is covered with the insulating layer 930.
  • the insulating layer 930 is undercut to form a gap and structurally lack stability.
  • the through electrode substrate 100 according to the first embodiment does not have a structure corresponding to the insulating layer 930 in the conventional through electrode substrate, and there is no formation process thereof, and thus occurs in the formation process of the insulating layer 930.
  • the above problem does not occur.
  • the through electrode substrate 100 according to the first embodiment and the manufacturing method thereof can provide a structurally stable through electrode substrate.
  • a bottomed hole 102 is formed on the first surface 101a side of the base 101 having the first surface 101a and the second surface 101b facing each other, and the bottomed hole 102 is filled with the through electrode 103. Etching was performed from the second surface 101b side of the base 101 to expose the through electrode 103. In the modification, after the bottomed hole 102 is formed on the first surface 101 a side of the base 101, the through electrode 103 is not formed in the bottomed hole 102, and etching is first performed from the second surface 101 b side of the base 101. .
  • FIG. 12 shows a state in which a bottomed hole 102 is formed in the base 101 and etching is performed from the second surface 101b side of the base 101 to penetrate the bottomed hole 102.
  • the etching performed in the first modification is the same as the method described in the first embodiment. That is, FIG. 12 can be said to be a state in which the formation process of the through electrode 103 shown in FIG. 2 is omitted and the etching process shown in FIGS.
  • the through electrode 103 is formed by filling the metal from the original opening side of the bottomed hole 102. Since the metal is filled after passing through the bottomed hole 102, unnecessary gas is easily released when the metal is filled, and bubbles are hardly generated in the through electrode 103.
  • the through electrode substrate 100 similar to that described in FIG. 7 in the first embodiment is formed.
  • FIG. 14 is a diagram illustrating a state in which the second surface 103b is flattened and a through electrode substrate 100a according to a modification of the first embodiment is formed.
  • FIG. 18 is a schematic diagram of a cross section when viewed in the AA ′ direction in FIG.
  • the through electrode 103 is disposed on the base 101.
  • the base 101 has a first surface 101a and a second surface 101b that face each other.
  • the first surface 103 a is exposed from the first surface 101 a side of the base 101
  • the second surface 103 b is exposed from the second surface 101 b side of the base 101.
  • the side surface 103 d of the through electrode 103 is in contact with the base body 101.
  • the peripheral edge 103c of the through electrode 103 is covered with the base body 101 on both the side surface 103d side and the second surface 103b side.
  • the base body 101 has a constant thickness over almost the whole, but the thickness of the portion covering the second surface of the through electrode 103 is thin to form a thin area (area where the thickness is reduced) 101e. is doing.
  • the manufacturing method for forming the bottomed hole 102 in the base 101 and filling the through electrode 103 in the second embodiment is the same as the manufacturing method of the through electrode substrate 100 in the first embodiment described with reference to FIGS. 1 and 2. It is the same.
  • FIG. 15 is a diagram showing a state where etching has been performed over the entire surface of the second surface 101b from the second surface 101b side of the base 101 from the state of FIG.
  • Etching may be performed by wet etching, dry etching, laser processing, or the like.
  • a dotted line 101b ' indicates the position of the second surface 101b of the base 101 before etching. Etching is not performed until the second surface 103 b of the through electrode 103 is exposed, and a thickness a is left between the second surface 101 b of the base 101 and the second surface 103 b of the through electrode 103.
  • the etching process is performed by isotropic wet etching, for example, hydrofluoric acid is used as an etchant, and a protective layer is formed so that the first surface 101a side of the substrate 101 is not etched.
  • the etching is performed so that the thickness a is, for example, 30 ⁇ m or less. This is because, in the etching process after masking, which will be described later, if the thickness a is increased, the influence of the progress of the etching in the lateral direction in addition to the etching in the thickness direction of the substrate 101 cannot be ignored.
  • etching is performed by wet etching, uneven etching occurs, so that the thickness a is desirably 1 ⁇ m or more.
  • the thickness a is preferably 1 ⁇ m or more.
  • FIG. 16 is a cross-sectional view showing a state where the mask 131 is formed on the second surface 101 b of the base 101.
  • the mask arrangement shown in FIG. 16 shows mask formation when the etching process after mask formation is performed by anisotropic etching.
  • the mask 131 in order to expose the second surface 103b of the through electrode 103 from the base 101, the mask 131 is not formed in the region of the second surface 103b of the through electrode 103 to be exposed, and the mask is formed in the other portions. 131 is formed. More specifically, the mask 131 is formed from the side where the through electrode 103 does not exist to the portion beyond the peripheral edge 103c of the through electrode 103 when seen through the second surface 101b side of the base 101, It forms so that the periphery 103c may overlap.
  • the mask 131 is performed by, for example, resist patterning.
  • FIG. 17 is a view showing a state after anisotropic etching is performed from the state shown in FIG. 16 and showing a cross-sectional view of the through electrode substrate 200 according to the second embodiment of the present invention. .
  • the substrate 101 on which the mask 131 is not arranged is etched by anisotropic etching.
  • the mask 131 since the mask 131 is formed so as to overlap with the peripheral edge 103c, the second surface 103b of the through electrode 103 is exposed from the base body 101 leaving a portion near the peripheral edge 103c. Since the mask 131 is disposed up to the portion beyond the periphery 103c of the through electrode 103, the base 101 is not etched in the vicinity of the periphery 103c on the side surface 103d side and the second surface 103b side. A portion where the mask 131 is disposed is indicated by 131 'in the drawing. After the anisotropic etching step is completed, the mask 131 is peeled off.
  • FIG. 18 shows a cross-sectional view of the through electrode substrate 220 in which the wiring layer 104 is formed on the through electrode substrate 200 shown in FIG. 17 and the insulating layer 105 is further formed.
  • a method of forming the wiring layer 104 and forming the insulating layer 105 after the etching is completed is the same as that of the first embodiment.
  • the peripheral edge 103c of the second surface 103b of the through electrode 103 is covered by the base 101 on both the side surface 103d side and the second surface 103b side. Is called.
  • the manufacturing method of the through electrode substrate 200 in the second embodiment does not cause a problem in the manufacturing process in the prior art described with reference to FIGS. 25 to 28, similarly to the manufacturing method of the through electrode substrate 200 in the first embodiment. . Therefore, the through electrode substrate 200 can provide a structurally stable through electrode substrate as in the first embodiment.
  • the second surface 103b of the through electrode 103 is entirely exposed from the base body 101 except for the vicinity of the peripheral edge 103c.
  • the present invention is not limited to this.
  • a part of the substrate 101 may be left without being removed by resist processing.
  • FIG. 19 shows a plan view and a cross-sectional view of a through electrode substrate 300 according to the third embodiment.
  • a circular island-shaped substrate 101 d is arranged near the center of the through electrode 103.
  • the second surface 103b of the through electrode 103 has an opening formed in a ring shape.
  • FIG. 20 shows a plan view and a cross-sectional view of the through electrode substrate 400 according to the third embodiment.
  • the ring-shaped substrate 101 f is disposed near the center of the through electrode 103.
  • the second surface 103b of the through electrode 103 includes a ring-shaped opening located outside the base 101f remaining in a ring shape and a circular opening positioned inside the base 101f remaining in a ring shape. Is formed.
  • the opening of the second surface 103b of the through electrode 103 is formed in a predetermined shape by appropriately selecting a pattern for masking the second surface 101b of the substrate 101 with a resist. You can do it.
  • the area of the second surface 103b of the through electrode 103 is smaller than that of the first and second embodiments in order to facilitate the formation of the opening of the second surface 103b of the through electrode 103. It can be widely taken.
  • the third embodiment by appropriately setting the shape and the width of the opening of the second surface 103b of the through electrode 103, the through electrode 103, the second surface 103b of the through electrode 103, and the base 101 are formed. It becomes possible to adjust the resistance value between the wiring layer (not shown) arranged on the second surface 101b.
  • a wiring layer is arranged or another insulating layer is laminated. Adhesiveness is improved when it is turned into a solid.
  • the base 101 and the through electrode 103 are formed up to the state shown in FIG. 8 in the first embodiment.
  • the first wiring 505 is formed on the second surface 101b of the left base 101 in FIG. 21 and part of the second surface 103b of the adjacent through electrode 103.
  • the insulating layer 507 is formed on a part of the first wiring 505 and the second surface 103b of the through-electrode 103 adjacent thereto.
  • the second wiring 506 is formed on the insulating layer 507, the second surface 103b of the through electrode 103, and the second surface 101b of the right base 101.
  • the first wiring 505 and the second wiring 506 are electrically connected to each other through the through electrode 103, but are formed through the insulating layer 507, so that the other parts are electrically connected to each other. Not connected.
  • the manufacturing method of the through electrode substrate 500 according to the fourth embodiment is not limited to the manufacturing method described above.
  • the first wiring 505, the insulating layer 507, and the second wiring 506 may be similarly formed on the through electrode substrate 200 described in the second embodiment.
  • two openings are formed on the second surface 103b of the through electrode 103 so that the first wiring 505 and the second wiring 506 are connected to the formed openings, respectively. It may be formed.
  • a wiring layer and an insulating layer may be formed on the second surface 103b of the through electrode 103 so that three or more wirings are connected.
  • the through electrode substrate 500 according to the fourth embodiment since a plurality of wirings are connected via the through electrodes 103, it is possible to realize branching of the wirings on the through electrodes 103.
  • FIG. 22 is a diagram showing a semiconductor device 1000 according to the fifth embodiment of the present invention.
  • the through electrode substrate 610 is formed with a semiconductor element such as a DRAM, for example, and has connection terminals 611 and 612 formed of a wiring layer 104 (not shown) or the like.
  • One or more of the three through electrode substrates 610, 620, and 630 may be a through electrode substrate formed of a substrate formed of glass, sapphire, or the like.
  • the connection terminal 612 is connected to the connection terminal 701 of the LSI substrate 700 by the bump 751.
  • connection terminal 611 is connected to the connection terminal 622 of the through electrode substrate 620 by the bump 752.
  • the connection terminal 621 of the through electrode substrate 620 is connected to the connection terminal 632 of the through electrode substrate 630 by the bump 753.
  • a metal such as indium, copper, or gold is used for the bumps 751, 752, and 753, for example.
  • connection between the through-electrode substrate and another substrate is not limited to using bumps, and other bonding techniques such as eutectic bonding may be used.
  • polyimide, epoxy resin, or the like may be applied and baked to bond the through electrode substrate and another substrate.
  • FIG. 23 is a diagram showing another example of the semiconductor device according to the fifth embodiment of the present invention.
  • semiconductor chips (LSI chips) 710 and 720 such as a MEMS device, a CPU, and a memory, and a through electrode substrate 600 are stacked and connected to the LSI substrate 700.
  • the through electrode substrate 600 is disposed between the semiconductor chip 710 and the semiconductor chip 720 and connected by bumps 754 and 755.
  • a semiconductor chip 710 is placed on the LSI substrate 700, and the LSI substrate 700 and the semiconductor chip 720 are connected by a wire 705.
  • the through electrode substrate 600 is used as an interposer for stacking a plurality of semiconductor chips and three-dimensionally mounting them, and manufacturing a multi-functional semiconductor device by stacking a plurality of semiconductor chips having different functions. can do.
  • the semiconductor chip 710 as a three-axis acceleration sensor and the semiconductor chip 720 as a two-axis magnetic sensor, a semiconductor device in which a five-axis motion sensor is realized with one module can be manufactured.
  • the sensing result may be output as an analog signal.
  • a low-pass filter, an amplifier, and the like may also be formed on the semiconductor chip or the through electrode substrate 600.
  • FIG. 24 is a diagram showing another example of the semiconductor device according to the fifth embodiment of the present invention.
  • the above two examples (FIGS. 22 and 23) are three-dimensional mounting, but this example is an example applied to the combined mounting of two dimensions and three dimensions.
  • six through electrode substrates 610, 620, 630, 640, 650, and 660 are stacked and connected to the LSI substrate 700.
  • all the through electrode substrates are not only stacked and arranged, but also arranged in the in-plane direction of the LSI substrate 700.
  • One or more of these through electrode substrates 610, 620, 630, 640, 650, and 660 may be a through electrode substrate made of a substrate formed of glass, sapphire, or the like.
  • the through electrode substrates 610 and 650 are connected to the LSI substrate 700, the through electrode substrates 620 and 640 are connected to the through electrode substrate 610, and the through electrode substrate 630 is connected to the through electrode substrate 620.
  • the through electrode substrate 660 is connected to the through electrode substrate 650.
  • the through electrode substrates 630, 640, 660, etc. may be replaced with semiconductor chips.
  • Semiconductor devices 1000, 1000a, and 1000b manufactured as described above include, for example, mobile terminals (mobile phones, smartphones, notebook personal computers, and the like), information processing devices (desktop personal computers, servers, car navigation systems, and the like), home appliances, and the like. And so on. These electrical devices have a control unit configured by a CPU or the like that executes various applications to realize various functions, and various functions include a function that uses an output signal from the semiconductor device 1000.

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Abstract

　貫通電極の周縁付近に配置された絶縁部分に境界があることに伴う不具合を解消し、構造的に安定した貫通電極基板及びその製造方法を提供することを目的とする。貫通電極基板は、互いに対向する第１面と第２面とを有する基体と、前記基体の前記第１面から前記第２面を貫通する貫通孔に配置された貫通電極と、を有し、前記貫通電極は、前記第１面及び前記第２面において前記基体から露出される第１面側の端面及び第２面側の端面を有し、前記第１面側の端面及び前記第２面側の端面の一方又は双方は、周縁が前記基体で覆われていることを特徴とする。

Description

貫通電極基板及びその製造方法、並びに貫通電極基板を用いた半導体装置
　本発明は貫通電極基板及びその製造方法、並びに貫通電極基板を用いた半導体装置に関する。
　近年、ＬＳＩチップ間のインターポーザとして基板の表面と裏面を導通する導通部を備えた貫通電極基板の開発が進んできている。このような貫通電極基板では、貫通孔内部に電解めっきなどによって導電材を充填することで貫通電極が形成されている。貫通電極基板の従来技術としては、例えば、ＳＯＩウエハを用いて作製された貫通電極基板が開示されている（特許文献１参照。）。この貫通電極基板は、ＳＯＩウエハの支持基板層に、埋め込み絶縁層に達する深さを有するブラインドビアホールを設け、そのビアホールの内壁に内壁絶縁層を施して貫通電極が設けられている。また、シリコン層が除去されて露出した埋め込み絶縁層には、貫通電極に対応する部分にコンタクトホールが設けられている。
特開２００５－３８９４２号公報
　特許文献１に記載されているように、従来の貫通電極基板は、表面に絶縁層が設けられ、その絶縁層に設けられたコンタクトホールによって貫通電極が露出され導通がとれる構造を有している。図２５及び図２６は、このような貫通電極基板８００の構造を断面図で示したものである。基体８０１は互いに対向する表面８０１ａと表面８０１ｂを有し、表面８０１ａと表面８０１ｂを貫通する貫通孔に、貫通電極８０３が配置される。ここで、基体８０１の表面８０１ｂと、貫通電極８０３の表面８０３ｂは、同一面を形成していることがわかる。基体８０１の表面８０１ｂ及び貫通電極８０３の表面８０３ｂ上には、配線８０４が配置されている。
　図２６は、図２５で示した貫通電極基板８００の点線で囲んだ付近の拡大図であり、貫通電極８０３の表面８０３ｂ側の、周縁８０３ｃ付近を示している。貫通電極基板８００の形成においては、基体８０１に設けられた穴に電解めっきにより充填された貫通電極８０３が形成されるが、貫通電極８０３の側面８０３ｄと基体８０１との間に、微小の空間が発生する場合がある。また、基体８０１に貫通電極８０３が配置された後に、基体８０１の表面８０１ｂ及び貫通電極８０３の表面８０３ｂはＣＭＰなどによって研磨されるが、その際、表面８０３ｂ側の周縁８０３ｃ付近の基体８０１が削られてしまい、空間が発生する場合もある。このような原因によって生じた空間８８１が存在すると、配線８０４が断線してしまい、貫通電極８０３と接続不良が発生してしまう。あるいは、空間８８１にガスが充満することによって、配線８０４の接続の信頼性が低下してしまう。
　図２７及図２８は、別形態の貫通電極基板９００の断面図である。図２８は、貫通電極基板９００の形成過程を示した図であり、図２７の点線で囲んだ付近の拡大図である。図２７を参照すると、基体９０１の表面９０１ａと表面９０１ｂを貫通する貫通電極９０３が配置されている。ここで、基体９０１の表面９０１ａ側と表面９０１ｂ側に露出する貫通電極９０３を、それぞれ表面９０３ａと表面９０３ｂとする。また、貫通電極９０３の基体９０１と接する面を、側面９０３ｄとする。絶縁層９３０は、基体９０１の表面９０１ｂ上と、表面９０１ｂから貫通電極９０３の表面９０３ｂ上の一部にかけて配置される。絶縁層９３０上と、絶縁層９３０が形成されていない貫通電極９０３の表面９０３ｂ上に、配線９０４が配置されている。
　図２７では基体９０１の表面９０１ｂ上及び貫通電極９０３の表面９０３ｂ上の一部に絶縁層９３０が形成されている。絶縁層９３０が貫通電極９０３の周縁９０３ｃ付近にも形成されているので、周縁９０３ｃは、側面９０３ｄ側は基体９０１に覆われ、表面９０３ｂ側は絶縁層９３０で覆われている。
　絶縁層９３０を形成することによって貫通電極９０３の周縁９０３ｃは被覆される。しかし絶縁層９３０と貫通電極９０３との密着性が悪いと、製造工程の途中で絶縁層９３０がアンダーカットされて隙間が生じてしまう。そうすると、絶縁層９３０は構造的に安定性を欠くことになるので、配線９０４が断線する原因となる。
　本発明は、上述の課題に鑑みてなされたものであり、貫通電極と基体との境界部で発生する構造起因の不具合を解消し、構造的に安定した貫通電極基板を提供することを目的とする。
　本発明の一実施形態によると、互いに対向する第１面と第２面とを有する基体と、基体の前記第１面と第２面とを貫通する貫通孔に配置された貫通電極と、を有し、貫通電極は、第１面及び第２面において基体から露出される第１面側の端面及び第２面側の端面を有し、第１面側の端面及び第２面側の端面の一方又は双方は、周縁が基体で覆われていることを特徴とする、貫通電極基板が提供される。
　また、基体は貫通電極の周縁又は周縁の外側に位置し、前記周縁に沿う環状の凸部を有してもよい。
　また、基体はガラスを含んでもよい。
　また、基体はシリコンを含み、貫通孔の内壁面に絶縁膜が配置されてもよい。
　また、周縁が基体で覆われた第１面側の端面及び第２面側の端面の一方又は双方の内側に、基体と同じ材質の部材が配置されてもよい。
　また、周縁が基体で覆われた第１面側の端面及び第２面側の端面の一方又は双方に、複数の配線が配置されてもよい。
　また、本発明の別の一実施形態によると、互いに対向する第１面と第２面とを有する基体の第１面に、第２面に至らない深さで開口部を形成し、開口部を導電性材料で充填して電極を形成し、基体の第２面に、電極の内側領域の一部に開口を有し、電極の周縁を覆うマスクを形成し、マスクが設けられた状態で基体の第２面をエッチングし、電極の内側領域の一部を露出させ、かつ前記電極の周縁に前記基体の一部を残存させることを特徴とする、貫通電極基板の製造方法が提供される。
　また、マスクは環状に形成されてもよい。
　また、マスクは少なくとも一部に等方性エッチングを含んでもよい。
　また、エッチングマスクはエッチングが進行するにつれて取り除かれてもよい。
　また、本発明の別の一実施形態によると、上述の貫通電極基板を有する半導体装置が提供される。
　本発明によると、基体の互いに対向する２面を貫通する貫通電極が配置され、貫通電極の少なくとも一方の面の周縁が基体で覆われているので、構造的に安定した貫通電極基板を提供することができる。
本発明の第１実施形態に係る貫通電極基板の製造方法において、有底孔が設けられた基板の断面を示す模式図である。 本発明の第１実施形態に係る貫通電極基板の製造方法において、貫通電極が設けられた基板の断面を示す模式図である。 本発明の第１実施形態に係る貫通電極基板の製造方法において、マスクが形成された基板の断面を示す模式図である。 本発明の第１実施形態に係る貫通電極基板の製造方法において、エッチング途中の基板の断面を示す模式図である。 本発明の第１実施形態に係る貫通電極基板の製造方法において、エッチング途中の基板の断面を示す模式図である。 本発明の第１実施形態に係る貫通電極基板の製造方法において、エッチング途中の基板の断面を示す模式図である。 本発明の第１実施形態に係る貫通電極基板の製造方法において、エッチングが完了した基板の断面を示す模式図である。 本発明の第１実施形態に係る貫通電極基板の製造方法において、エッチングが完了した基板の平面図及び斜視図を示したものである。 本発明の第１実施形態に係る貫通電極基板の製造方法において、配線層が形成された基板の断面を示す模式図である。 本発明の第１実施形態に係る貫通電極基板の製造方法において、絶縁層が形成された基板の断面を示す模式図である。 本発明の第１実施形態に係る貫通電極基板の貫通電極を説明する上面図である。 本発明の第１実施形態の変形例に係る貫通電極基板の製造方法において、エッチングが完了した基板の断面を示す模式図である。 本発明の第１実施形態の変形例に係る貫通電極基板の製造方法において、貫通電極が基体の凸部よりもせり出した状態を示した模式図である。 本発明の第１実施形態の変形例に係る貫通電極基板の製造方法において、基体の凸部よりもせり出した貫通電極を平坦化した状態を示した模式図である。 本発明の第２実施形態に係る貫通電極基板の製造方法において、エッチング途中の基板の断面を示す模式図である。 本発明の第２実施形態に係る貫通電極基板の製造方法において、マスクが形成された基板の断面を示す模式図である。 本発明の第２実施形態に係る貫通電極基板の製造方法において、エッチングが完了した基板の断面を示す模式図である。 本発明の第２実施形態に係る貫通電極基板の製造方法において、配線層及び絶縁層が形成された基板の断面を示す模式図である。 本発明の第３実施形態に係る貫通電極基板の上面及び断面を示す模式図である。 本発明の第３実施形態に係る貫通電極基板の上面及び断面を示す模式図である。 本発明の第４実施形態に係る貫通電極基板の断面を示す模式図である。 本発明の第５実施形態に係る半導体装置を示す図である。 本発明の第５実施形態に係る半導体装置の別の例を示す図である。 本発明の第５実施形態に係る半導体装置のさらに別の例を示す図である。 従来技術に係る貫通電極基板の断面を示す模式図である。 従来技術に係る貫通電極基板の断面を示す模式図である。 従来技術に係る貫通電極基板の断面を示す模式図である。 従来技術に係る貫通電極基板の断面を示す模式図である。
　以下、図面を参照して、本発明の貫通電極基板を詳細に説明する。なお、本発明の貫通電極基板は以下の実施形態に限定されることはなく、種々の変形を行ない実施することが可能である。全ての実施形態においては、同じ構成要素には同一符号を付して説明する。また、図面の寸法比率は説明の都合上実際の比率とは異なったり、構成の一部が図面から省略されたりする場合がある。
＜第１実施形態＞
　以下、図１乃至図１１を参照して、本発明の第１実施形態に係る貫通電極基板１００の構成及び製造方法について説明する。
（全体構成）
　はじめに、貫通電極基板１００の構成の概要について、図７及び図８を用いて説明する。図８は、本発明の第１実施形態に係る貫通電極基板１００の平面図及び斜視図である。図８（ａ）は貫通電極基板１００を構成する基体１０１の第２面１０１ｂ側から見た平面図であり、図８（ｂ）は基体１０１の第２面１０１ｂ側の斜め方向から見た斜視図である。また、図７は、図８（ａ）のＡ－Ａ’方向に見た場合の断面の模式図を示している。
　貫通電極基板１００は、基体１０１に貫通電極１０３が配置される。基体１０１は、互いに対向する第１面１０１ａと第２面１０１ｂを有する。貫通電極１０３は、基体１０１の第１面１０１ａ側からは第１面１０３ａが露出し、基体１０１の第２面１０１ｂ側からは第２面１０３ｂが露出する。また、貫通電極１０３の側面１０３ｄは、基体１０１と接している。
　貫通電極１０３の第２面１０３ｂは、周縁１０３ｃ及びその周辺が基体１０１で覆われ、それ以外の内側の領域が基体１０１から露出する。すなわち、周縁１０３ｃは、側面１０３ｄ側及び第２面１０３ｂ側が、いずれも基体１０１によって覆われている。基体１０１が貫通電極１０３の周縁１０３ｃ及びその周辺の第２面１０３ｂを覆う部分は、その他の部分と比較して、厚さが薄くなっており、薄肉領域（厚さが薄くなった領域）１０１ｅが形成されている。
（貫通電極基板１００の製造方法）
　次に、図１乃至８を用いて、本発明の第１実施形態に係る貫通電極基板１００の製造方法を説明する。
　図１は、貫通電極基板１００の製造方法において、基体１０１に有底孔１０２が設けられた基板の断面を示している。基体１０１は、少なくとも表面が絶縁性を有する。基体１０１としては、例えばガラス（青板ガラス、低膨張ガラス、無アルカリガラス等）、サファイア、樹脂などが用いられる。この場合、基体１０１の厚さを１００μｍ～１ｍｍの範囲内で形成してもよい。
　また、基体１０１として、導電性を有する基板の表面に絶縁膜が設けられた、表面が絶縁性を有する基体であってもよい。例えば、シリコン等の導電性を有する基板の表面に、絶縁膜を形成してもよい。この場合、絶縁膜の厚さを０．１μｍ～５μｍの範囲内で形成してもよい。なお、基体１０１としてシリコンを含む基板を用いる場合、有底孔１０２の内壁面に絶縁膜を形成することにより、最終的な貫通孔の内壁面に絶縁膜を設ける構成とすることが好ましい。ただし、その場合、後述する図７において絶縁膜を除去するためのエッチングプロセスが必要となる。
　基体１０１は、互いに対向する第１面１０１ａと第２面１０１ｂを有する。基体１０１の第１面１０１ａ側にマスク（図示せず）を形成し、エッチングにより有底孔１０２を形成する。エッチングの方法としては、ＲＩＥ（Ｒｅａｃｔｉｖｅ　Ｉｏｎ　Ｅｔｃｈｉｎｇ：反応性イオンエッチング）、ＤＲＩＥ（Ｄｅｅｐ　ＲＩＥ：深掘り反応性イオンエッチング）等のドライエッチング加工、ウェットエッチング加工、レーザー加工等によって、基体１０１の第２面１０１ｂ側に貫通しない、有底孔１０２を形成することができる。
　有底孔１０２の深さは、基体１０１の厚さにもよるが、例えば１００μｍ～５００μｍとすることができる。有底孔１０２の開口の大きさは特に制限はなく、例えば１０μｍ～１００μｍとすることができる。また、有底孔１０２の形状は、典型的には各図に示すように基体１０１の厚さ方向にストレートな形状を示すが、これに限られない。例えば、第１面１０１ａ側の開口部を広く、第２面１０１ｂ側の底部を狭く、テーパ形状にしてもよい。また、有底孔１０２の中央部を凸状、凹状、またはこれらを組み合わせた形状にしてもよい。なお、有底孔１０２の平面図上での形状についても特に制限はなく、典型的には円形であるが、円形以外にも矩形や多角形であってもよい。
　次に、貫通電極１０３の形成について説明する。図２は、有底孔１０２に貫通電極１０３が形成された状態を示した断面図である。貫通電極１０３は、有底孔１０２を埋め込むように導電性材料を設けることで形成される。導電性の材料としては、例えばＣｕなどの金属が用いられる。貫通電極１０３としてＣｕなどの金属を用いる場合は、電解めっき充填法を用いることができる。電解めっきする場合は、シード層すなわちめっき形成の下地層を形成した後に電解めっきを施す（図示せず）。また、該電解めっきをパターン形成する場合は、リソグラフィー法で作製したレジストで、めっき形成する部分を露出させる。貫通電極１０３を充填した後に、基体１０１の第１面１０１ａ及び貫通電極１０３の第１面１０３ａを、ＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）等によって平坦化する。
　ここで、有底孔１０２に配置された貫通電極１０３の、有底孔１０２の開口側（基体１０１の第１面１０１ａ側）を第１面１０３ａとし、有底孔１０２の底側（基体１０１の第２面１０１ｂ側）を第２面１０３ｂとする。第２面１０３ｂの端部を、周縁１０３ｃとする。また、第１面１０３ａと第２面１０３ｂ以外で、基体１０１と接する面を側面１０３ｄとする。
　次に、マスク１３０の形成について説明する。図３は、基体１０１の第２面１０１ｂ側に、エッチングのためのマスク１３０が形成された状態を示した断面図である。マスク１３０は、基体１０１の第２面１０１ｂに、第２面１０１ｂ側から透視したときに、貫通電極１０３の第２面１０３ｂの周縁１０３ｃ付近に配置される。このとき、マスク１３０の少なくとも一部が周縁１０３ｃよりも内側に位置するように配置される。このようにマスク１３０を配置するのは、マスク１３０配置後に基体１０１の第２面１０１ｂを等方性エッチングしたときに、貫通電極１０３の第２面１０３ｂの周縁１０３ｃ付近のエッチングを遅らせ、貫通電極１０３の第２面１０３ｂの周縁１０３ｃが露出されないようにするためである。
　貫通電極１０３が円柱状の形状を有する場合、マスク１３０は基体１０１の第２面１０１ｂ上に、貫通電極１０３の周縁１０３ｃに倣ってリング状に配置される。貫通電極１０３が円柱以外の形状を有する場合、貫通電極１０３の第２面１０３ｂの平面上の形状に沿ってマスク１３０が配置される。
　マスク１３０を設けた後、有底孔１０２を形成した基体１０１の第１面１０１ａの反対側、すなわち有底孔１０２の底側である基体１０１の第２面１０１ｂ側から、等方性のエッチングを行う。等方性エッチングの一例として、ウェットエッチングの工程について説明する。基体１０１がガラスである場合、エッチング液には、例えばフッ酸が用いられる。この場合、マスク１３０には、フッ酸に耐性のある材料が用いられ、例えばクロム、銅等を、レジスト製版エッチング工程により、パターニングして形成する。なお、ウェットエッチングを行う前に、基体１０１の第１面１０１ａ側がエッチングされないように、保護層を形成しておく。
　図４乃至図７は、等方性エッチングが進行する状態を示した断面図である。特に、図７は等方性エッチングが完了した状態を示した断面図であり、本発明の第１実施形態に係る貫通電極基板１００を示している。
　図４及び図５を参照すると、初期の等方性エッチング時においては、基体１０１の第２面１０１ｂでマスク１３０が配置されている部分は、エッチングされていないことがわかる。ただし、等方性のウェットエッチングが進行するにつれて、マスク１３０が配置されていない部分から、横方向にエッチングが入り込むので、マスク１３０が配置されている部分も徐々にエッチングが進行する。図６は、マスク１３０と、基体１０１の第２面１０１ｂとが接する部分が、全てエッチングされて、マスク１３０が剥離した状態を示している。
　図６からさらにエッチングを進行させ、最終的に図７に示す状態までエッチングを行う。図７を参照すると、貫通電極１０３の第２面１０３ｂの周縁１０３ｃ付近には基体１０１が完全にエッチングされず、薄肉領域１０１ｅとして基体１０１の一部が残っている。一方、貫通電極１０３の周縁１０３ｃ付近以外の第２面１０３ｂは、エッチングが進み、基体１０１から露出している。すなわち、貫通電極１０３は、基体１０１の第１面１０１ａと第２面１０３ｂとの間を貫通する貫通孔に配置された状態となる。このように、貫通電極１０３の周縁１０３ｃ付近の基体１０１の一部が完全にエッチングされないことによって、貫通電極１０３の周縁１０３ｃ及びその付近の第２面１０３ｂは、基体１０１に覆われた構造となる。
　ここで、再度図８を用いて、図７で示した等方性エッチングが完了した基板の状態を説明する。図８（ａ）は、基体１０１の第２面１０１ｂ側から見た平面図である。貫通電極１０３の第２面１０３ｂは、周縁１０３ｃ及びその付近が、基体１０１の第２面１０１ｂの一部によって覆われている。一方、貫通電極１０３の第２面１０３ｂの内側の領域は、基体１０１の第２面１０１ｂから露出している。
　図８（ｂ）は、基体１０１の第２面１０１ｂ側の斜め方向から見た斜視図である。図８（ｂ）を参照すると、円形に形成された貫通電極１０３の周縁１０３ｃの配置された部分と、その外側に位置する部位にかけて、環状の凸部１０１ｃが形成されていることがわかる。凸部１０１ｃは、マスク１３０が配置された部分が、マスク１３０の配置されない部分と比較してエッチングの進行が遅くなったために、形成されたものである。凸部１０１ｃが形成されることによって、貫通電極１０３の周縁１０３ｃは、その側面１０３ｄ側及び第２面１０１ｂ側が、いずれも基体１０１に覆われた構造となる。
　次に、貫通電極基板１００に配線層１０４及び絶縁層１０５を形成する方法について、図９乃至図１１を用いて説明する。
　図９は、基体１０１の第２面１０１ｂ上及び貫通電極１０３の第２面１０３ｂ上に、配線層１０４が形成された貫通電極基板１１０の断面図である。配線層１０４は、導電性材料が用いられる。導電性材料としては、例えば金属材料を基体１０１の第２面１０１ｂ側に塗布し、フォトリソグラフィによるパターニングを行う方法などによって形成される。なお、図９では図示しないが、配線層１０４の他に電子部品等を搭載してもよい。
　次に、絶縁層１０５の形成について、図１０を用いて説明する。図１０は、図９からさらに絶縁層１０５が形成された貫通電極基板１２０の断面を示しており、図１１のＢ－Ｂ’方向から見た断面図である。絶縁層１０５には、例えば感光性樹脂が用いられる。この場合、感光性樹脂を基体１０１の第２面１０１ｂ及び配線層１０４上に形成した後に、フォトリソグラフィによるパターニングが行われ、焼成されることによって絶縁層１０５が形成される。また、絶縁層１０５には、配線層１０４に至る開口部１０６が形成される。
　図１１は、貫通電極基板１２０の絶縁層１０５側から見た上面図である。配線層１０４は、円形の貫通電極１０３の周縁１０３ｃを囲むように形成されている。配線層１０４はさらに、貫通電極１０３から開口部１０６の方向にかけて延線し、開口部１０６が形成された領域を矩形状に取り囲むよう形成されている。なお、貫通電極１０３の周縁１０３ｃを示す円の内側に示した円は、貫通電極１０３の第２面１０３ｂにおいて、基体１０１の第２面１０１ｂ側から露出している領域を示している。
　以上説明したように、第１実施形態に係る貫通電極基板１００の形成においては、貫通電極１０３の周縁１０３ｃ付近の基体１０１を残存させる工程があるが、貫通電極１０３の第２面１０３ｂと基体１０１の第２面１０１ｂを研磨する工程は存在しない。したがって、図２５及び図２６で説明したような、貫通電極８０３の表面８０３ｂと基体８０１の表面８０１ｂの研磨によって発生する基体８０１の欠損や、基体８０１の欠損に伴う配線８０４の断線、基体８０１と貫通電極１０３との間の空間の発生による配線８０４の接続についての信頼性の低下等の問題は、第１実施形態係る貫通電極基板１００では発生しない。
　さらに、第１実施形態に係る貫通電極基板１００では、貫通電極１０３の第２面１０３ｂの周縁１０３ｃが、側面１０３ｄ側も、第２面１０３ｂ側も、基体１０１によって覆われている。一方、図２７及び図２８で説明した別の従来の貫通電極基板では、貫通電極９０３の周縁９０３ｃは、側部が基体９０１で覆われ、上面が絶縁層９３０で覆われているが、絶縁層９３０の形成過程において絶縁層９３０がアンダーカットされて隙間が生じ、構造的に安定性を欠くことがあった。したがって、第１実施形態に係る貫通電極基板１００では、従来の貫通電極基板における絶縁層９３０に相当する構造を有しておらず、その形成過程も存在しないので、絶縁層９３０の形成過程に発生する上記問題は発生しない。
　したがって、第１実施形態に係る貫通電極基板１００及びその製造方法によって、構造的に安定した貫通電極基板を提供することが可能となる。
（変形例）
　次に、図１２乃至１４を用いて、本発明の第１実施形態における変形例を説明する。
　実施形態１では、互いに対向する第１面１０１ａと第２面１０１ｂを有する基体１０１の、第１面１０１ａ側に有底孔１０２を形成し、有底孔１０２に貫通電極１０３を充填してから、基体１０１の第２面１０１ｂ側からエッチングを行い、貫通電極１０３を露出させた。変形例では、基体１０１の第１面１０１ａ側に有底孔１０２を形成した後、有底孔１０２に貫通電極１０３は形成せずに、先に基体１０１の第２面１０１ｂ側からエッチングを行う。
　図１２は、基体１０１に有底孔１０２を形成し、基体１０１の第２面１０１ｂ側からエッチングを行い、有底孔１０２を貫通させた状態を示している。変形例１で実施するエッチングは、実施形態１で説明した方法と同様である。すなわち図１２は、実施形態１において、図２で示す貫通電極１０３の形成過程を省略し、図３乃至７で示したエッチング工程を行った状態といえる。
　エッチングによって有底孔１０２を貫通させてから、有底孔１０２の当初の開口側から金属を充填することによって、貫通電極１０３を形成する。有底孔１０２を貫通させてから金属を充填するので、金属充填時に不要な気体が抜けやすくなり、貫通電極１０３に気泡が発生しにくくなる。貫通電極１０３が形成されると、実施形態１における図７で説明したのと同様な貫通電極基板１００が形成される。
　ただし、変形例１においては、図１３に示すように、貫通電極１０３を形成したときに貫通電極１０３の第２面１０３ｂが凸部１０１ｃよりもせり出す場合がある（図１３の１０３ｆ参照）。このような場合、貫通電極１０３を形成した後に、第２面１０３ｂをＣＭＰ等によって平坦化する。図１４は、第２面１０３ｂを平坦化し、第１実施形態の変形例に係る貫通電極基板１００ａが形成された状態を示した図である。ＣＭＰを実施すると、ディシング現象によって貫通電極基板１００ａの第２面１０３ｂの中央部分がへこむので、過度に中央部分にへこみが発生しないように適宜調整する。
＜実施形態２＞
　次に、図１、図２、図８（ａ）、並びに図１５乃至１８を用いて、本発明の第２実施形態に係る貫通電極基板２００の構成及び製造方法について説明する。
（全体構成）
　第２実施形態に係る貫通電極基板２００の上面図は、第１実施形態の説明で用いた図８（ａ）と同様である。また、図１８は、図８（ａ）のＡ－Ａ’方向に見た場合の断面の模式図を示している。
　貫通電極基板２００は、基体１０１に貫通電極１０３が配置される。基体１０１は、互いに対向する第１面１０１ａと第２面１０１ｂを有する。貫通電極１０３は、基体１０１の第１面１０１ａ側からは第１面１０３ａが露出し、基体１０１の第２面１０１ｂ側からは第２面１０３ｂが露出する。また、貫通電極１０３の側面１０３ｄは、基体１０１と接している。
　貫通電極１０３の周縁１０３ｃは、側面１０３ｄ側及び第２面１０３ｂ側が、いずれも基体１０１によって覆われている。基体１０１はほぼ全体にわたって一定の厚さを有しているが、貫通電極１０３の第２面を覆う部分の厚さが薄くなっており、薄肉領域（厚さが薄くなった領域）１０１ｅを形成している。
（貫通電極基板２００の製造方法）
　第２実施形態における基体１０１に有底孔１０２を形成し、貫通電極１０３を充填するまでの製造方法は、図１及び図２を用いて説明した実施形態１における貫通電極基板１００の製造方法と同様である。
　図１５は、図２の状態から、基体１０１の第２面１０１ｂ側から、第２面１０１ｂの全面にわたってエッチングを行った状態を示した図である。エッチングの方法としては、ウェットエッチング加工、ドライエッチング加工、レーザー加工等によって行ってよい。なお、点線１０１ｂ’は、エッチングを行う前の、基体１０１の第２面１０１ｂの位置を示している。エッチングは、貫通電極１０３の第２面１０３ｂが露出するまでは行わず、基体１０１の第２面１０１ｂと貫通電極１０３の第２面１０３ｂとの間に、厚さａを残すようにする。
　エッチング工程を等方性ウェットエッチングで行う場合、エッチング液には、例えばフッ酸が用いられ、基体１０１の第１面１０１ａ側がエッチングされないように、保護層を形成しておく。この場合は、厚さａは、例えば３０μｍ以下になるようにエッチングを行う。これは、後述するマスキング後のエッチング過程において、厚さａが大きくなると、基体１０１の厚さ方向のエッチングに加え、横方向のエッチングの進行による影響が無視できなくなるためである。また、ウェットエッチングでエッチングを行った際に、エッチングのむらが発生することから、厚さａは１μｍ以上であることが望ましい。
　また、エッチング工程をＲＩＥやＤ－ＲＩＥ等の、異方性のドライエッチングで行った場合には、厚さａの上限は特にない。ただし、厚さａは１μｍ以上であることが望ましい。
　次に、貫通電極１０３を基体１０１の第２面１０１ｂから露出させるための、マスク形成について説明する。図１６は、基体１０１の第２面１０１ｂにマスク１３１を形成した状態を示した断面図である。なお、図１６で示すマスク配置は、マスク形成後のエッチング工程が異方性エッチングで行う場合のマスク形成を示したものである。
　第２実施形態では、貫通電極１０３の第２面１０３ｂを基体１０１から露出させるために、露出させる貫通電極１０３の第２面１０３ｂの領域にはマスク１３１を形成せず、それ以外の部分にマスク１３１を形成する。より詳細に言うと、マスク１３１は、基体１０１の第２面１０１ｂ側から透視したときに、貫通電極１０３が存在しない側から、貫通電極１０３の周縁１０３ｃを越える部分までにかけて形成し、マスク１３１と周縁１０３ｃが重畳するように形成する。マスク１３１は、例えばレジストのパターニングによって行われる。
　次に、貫通電極１０３を基体１０１の第２面１０１ｂから露出させるための、エッチングについて説明する。図１７は、図１６に示した状態から異方性エッチングを行った後の状態を示した図であり、本発明の第２実施形態に係る貫通電極基板２００の断面図を示したものである。
　異方性エッチングによって、マスク１３１の配置されていない基体１０１がエッチングされる。上述のように、マスク１３１は周縁１０３ｃと重畳するように形成されているので、貫通電極１０３の第２面１０３ｂが、周縁１０３ｃ付近の部分を残して基体１０１から露出される。マスク１３１は貫通電極１０３の周縁１０３ｃを越える部分まで配置されていたので、周縁１０３ｃの付近はその側面１０３ｄ側及び第２面１０３ｂ側も、基体１０１がエッチングされずに残っている。マスク１３１が配置されていた箇所を、図中の１３１’で示している。異方性エッチングの工程が終了した後に、マスク１３１を剥離させる。
　図１８は、図１７に示した貫通電極基板２００に配線層１０４が形成され、さらに絶縁層１０５が形成された貫通電極基板２２０の断面図を示したものである。エッチングが完了した後に、配線層１０４を形成し、絶縁層１０５を形成する方法は、実施形態１と同様である。
　以上説明したように、第２実施形態に係る貫通電極基板２００においても、貫通電極１０３の第２面１０３ｂの周縁１０３ｃが、側面１０３ｄ側も、第２面１０３ｂ側も、いずれも基体１０１によって覆われる。また、第２実施形態における貫通電極基板２００の製造方法は、第１実施形態における貫通電極基板２００の製造方法と同様に、図２５乃至図２８で説明した従来技術における製造過程における問題は発生しない。したがって、貫通電極基板２００は、第１実施形態と同様に構造的に安定した貫通電極基板を提供することができる。
＜第３実施形態＞
　次に、図１９及び図２０を参照して、本発明の第３実施形態に係る貫通電極基板３００及び４００の構成について説明する。
　第１実施形態及び第２実施形態においては、貫通電極１０３の第２面１０３ｂは、周縁１０３ｃの付近を残して基体１０１から全て露出していたが、本発明はこれに限られない。貫通電極１０３の周縁１０３ｃ付近以外でも、基体１０１の一部をレジスト処理で取り除かずに残存させてもよい。
　図１９は、第３実施形態に係る貫通電極基板３００の平面図及び断面図を示したものである。図１９（ａ）及び図１９（ｂ）を参照すると、円形をした島状の基体１０１ｄが、貫通電極１０３の中央付近に配置されていることがわかる。ここでは、貫通電極１０３の第２面１０３ｂは、リング状に開口部が形成される。
　図２０は、第３実施形態に係る貫通電極基板４００の平面図及び断面図を示したものである。図２０（ａ）及び図２０（ｂ）を参照すると、リング状の基体１０１ｆが、貫通電極１０３の中央付近に配置されていることがわかる。ここでは、貫通電極１０３の第２面１０３ｂは、リング状に残存させた基体１０１ｆの外側に位置するリング状の開口部と、リング状に残存させた基体１０１ｆの内側に位置する円形の開口部が形成される。
　図１９及び図２０に示した形状以外にも、基体１０１の第２面１０１ｂをレジストによりマスクするパターンを適宜選択することによって、貫通電極１０３の第２面１０３ｂの開口部を所定の形状に形成してよい。なお、第３実施形態では、貫通電極１０３の第２面１０３ｂの開口部の形成を容易にするために、第１実施形態及び第２実施形態よりも貫通電極１０３の第２面１０３ｂの面積を広くとってもよい。
　このように、第３実施形態では、貫通電極１０３の第２面１０３ｂの開口部の形状及び広さを適宜設定することによって、貫通電極１０３と、貫通電極１０３の第２面１０３ｂ及び基体１０１の第２面１０１ｂ上に配置される配線層（図示せず）との間の、抵抗値を調整することが可能となる。
　また、第３実施形態では、第１実施形態及び第２実施形態と比較して、貫通電極１０３の第２面１０３ｂ側の凹凸が増えるため、配線層を配置したり、他の絶縁層を積層化したりする際の、密着性が向上する。
＜実施形態４＞
　次に、図２１を参照して、本発明の第４実施形態に係る貫通電極基板５００の構成について説明する。第４実施形態では、貫通電極１０３の第２面１０３ｂに接続される、第１配線５０５及び第２配線５０６が形成されている。
　第４実施形態に係る貫通電極基板５００の製造方法の一例を説明する。まず、第１実施形態における図８で示した状態まで、基体１０１及び貫通電極１０３を形成する。次に、図２１の左側の基体１０１の第２面１０１ｂ上と、隣接する貫通電極１０３の第２面１０３ｂ上の一部に、第１配線５０５を形成する。次に、絶縁層５０７を、第１配線５０５及びこれに隣接する貫通電極１０３の第２面１０３ｂ上の一部に形成する。最後に、第２配線５０６を、絶縁層５０７、貫通電極１０３の第２面１０３ｂ及び右側の基体１０１の第２面１０１ｂ上に形成する。ここで、第１配線５０５と第２配線５０６とは、貫通電極１０３を介して相互に電気的に接続されるが、絶縁層５０７を介して形成されるため、それ以外の部分では電気的に接続されない。
　第４実施形態に係る貫通電極基板５００の製造方法は、上述した製造方法に限られない。例えば、第２実施形態で説明した貫通電極基板２００上に、同様に第１配線５０５、絶縁層５０７及び第２配線５０６を形成してもよい。また、第３実施形態で説明したように、貫通電極１０３の第２面１０３ｂ上に開口部を２つ形成し、形成した開口部にそれぞれ第１配線５０５、第２配線５０６が接続されるよう形成してもよい。
　また、貫通電極１０３の第２面１０３ｂ上に、３つ以上の配線が接続されるように、配線層及び絶縁層を形成してもよい。
　第４実施形態に係る貫通電極基板５００によると、貫通電極１０３を介して複数の配線が接続されるので、貫通電極１０３上で配線の分岐を実現することが可能となる。
＜第５実施形態＞
　第５実施形態においては、第１乃至第４実施形態における貫通電極基板を用いて製造される半導体装置１０００について説明する。
　図２２は、本発明の第５実施形態に係る半導体装置１０００を示す図である。半導体装置１０００は、３つの貫通電極基板６１０、６２０、６３０が積層され、ＬＳＩ基板７００に接続されている。貫通電極基板６１０は、例えば、ＤＲＡＭ等の半導体素子が形成され、配線層１０４（図示せず）等で形成された接続端子６１１、６１２を有している。これら３つの貫通電極基板６１０、６２０、６３０の１つ以上がガラス、サファイアなどで形成された基板からなる貫通電極基板であってもよい。接続端子６１２は、ＬＳＩ基板７００の接続端子７０１とバンプ７５１により接続されている。接続端子６１１は、貫通電極基板６２０の接続端子６２２とバンプ７５２により接続されている。貫通電極基板６２０の接続端子６２１は、貫通電極基板６３０の接続端子６３２とバンプ７５３により接続されている。バンプ７５１、７５２、７５３は、例えば、インジウム、銅、金等の金属を用いる。
　なお、貫通電極基板を積層する場合には、３層に限らず、２層であってもよいし、さらに４層以上であってもよい。また、貫通電極基板と他の基板との接続においては、バンプによるものに限らず、共晶接合など、他の接合技術を用いてもよい。また、ポリイミド、エポキシ樹脂等を塗布、焼成して、貫通電極基板と他の基板とを接着してもよい。
　図２３は、本発明の第５実施形態に係る半導体装置の別の例を示す図である。図２３に示す半導体装置１０００ａは、ＭＥＭＳデバイス、ＣＰＵ、メモリ等の半導体チップ（ＬＳＩチップ）７１０、７２０、および貫通電極基板６００が積層され、ＬＳＩ基板７００に接続されている。
　半導体チップ７１０と半導体チップ７２０との間に貫通電極基板６００が配置され、バンプ７５４、７５５により接続されている。ＬＳＩ基板７００上に半導体チップ７１０が載置され、ＬＳＩ基板７００と半導体チップ７２０とはワイヤ７０５により接続されている。この例では、貫通電極基板６００は、複数の半導体チップを積層して３次元実装するためのインターポーザとして用いられ、それぞれ機能の異なる複数の半導体チップを積層することで、多機能の半導体装置を製造することができる。例えば、半導体チップ７１０を３軸加速度センサとし、半導体チップ７２０を２軸磁気センサとすることによって、５軸モーションセンサを１つのモジュールで実現した半導体装置を製造することができる。
　半導体チップがＭＥＭＳデバイスにより形成されたセンサなどである場合には、センシング結果がアナログ信号により出力されるようなときがある。この場合には、ローパスフィルタ、アンプ等についても半導体チップまたは貫通電極基板６００に形成してもよい。
　図２４は、本発明の第５実施形態に係る半導体装置の別の例を示す図である。上記２つの例（図２２、図２３）は、３次元実装であったが、この例は、２次元と３次元との併用実装に適用した例である。図２４に示す半導体装置１０００ｂでは、ＬＳＩ基板７００には、６つの貫通電極基板６１０、６２０、６３０、６４０、６５０、６６０が積層されて接続されている。ただし、全ての貫通電極基板が積層して配置されているだけでなく、ＬＳＩ基板７００の面内方向にも並んで配置されている。これらの貫通電極基板６１０、６２０、６３０、６４０、６５０、６６０の１つ以上がガラス、サファイアなどで形成された基板からなる貫通電極基板であってもよい。
　図２４の例では、ＬＳＩ基板７００上に貫通電極基板６１０、６５０が接続され、貫通電極基板６１０上に貫通電極基板６２０、６４０が接続され、貫通電極基板６２０上に貫通電極基板６３０が接続され、貫通電極基板６５０上に貫通電極基板６６０が接続されている。なお、図２３に示す例のように、貫通電極基板を複数の半導体チップを接続するためのインターポーザとして用いても、このような２次元と３次元との併用実装が可能である。例えば、貫通電極基板６３０、６４０、６６０などが半導体チップに置き換えられてもよい。
　上記のように製造された半導体装置１０００、１０００ａ、１０００ｂは、例えば、携帯端末（携帯電話、スマートフォンおよびノート型パーソナルコンピュータ等）、情報処理装置（デスクトップ型パーソナルコンピュータ、サーバ、カーナビゲーション等）、家電等、様々な電気機器に搭載される。これらの電気機器は、アプリケーションを実行して各種機能を実現するＣＰＵ等で構成される制御部を有し、各種機能には半導体装置１０００からの出力信号を用いる機能が含まれる。
１００、２００、３００、４００、５００：貫通電極基板、１０１：基体、１０２：有底孔、１０３：貫通電極、１０４：配線層、１０５：絶縁層、１０６：開口部、１３０、１３１：マスク

Claims (11)

  1. 　第１面と、前記第１面に対向する第２面とを有する基体と、
    　前記基体の前記第１面と前記第２面とを貫通する貫通孔に配置された貫通電極と、を有し、
    　前記貫通電極における前記第１面側の端面および前記第２面側の端面の一方又は双方は、周縁が前記基体の一部で覆われていることを特徴とする貫通電極基板。
  2. 　前記基体は前記貫通電極の前記周縁又は前記周縁の外側に位置し、前記周縁に沿う環状の凸部を有することを特徴とする請求項１に記載の貫通電極基板。
  3. 　前記基体はガラスを含むことを特徴とする請求項１に記載の貫通電極基板。
  4. 　前記基体はシリコンを含み、前記貫通孔の内壁面に絶縁膜が配置されることを特徴とする請求項１に記載の貫通電極基板。
  5. 　前記周縁が前記基体の一部で覆われた前記第１面側の端面及び前記第２面側の端面の一方又は双方の内側に、前記基体と同じ材質の部材が配置されることを特徴とする請求項１に記載の貫通電極基板。
  6. 　前記周縁が前記基体の一部で覆われた前記第１面側の端面及び前記第２面側の端面の一方又は双方に、複数の配線が配置されることを特徴とする請求項１に記載の貫通電極基板。
  7. 　互いに対向する第１面と第２面とを有する基体の前記第１面に、前記第２面に至らない深さで開口部を形成し、
    　前記開口部を導電性材料で充填して電極を形成し、
    　前記基体の前記第２面に、前記電極の内側領域の一部に開口を有し、前記電極の周縁を覆うマスクを形成し、
    　前記マスクが設けられた状態で前記基体の前記第２面をエッチングし、前記電極の内側領域の一部を露出させ、かつ前記電極の周縁に前記基体の一部を残存させること
    を特徴とする貫通電極基板の製造方法。
  8. 　前記マスクは環状に形成されることを特徴とする請求項７に記載の貫通電極基板の製造方法。
  9. 　前記エッチングは少なくとも一部に等方性エッチングを含むことを特徴とする請求項７に記載の貫通電極基板の製造方法。
  10. 　前記マスクは前記エッチングが進行するにつれて取り除かれることを特徴とする請求項７に記載の貫通電極基板の製造方法。
  11. 　請求項１に記載の貫通電極基板を有する半導体装置。
     
     
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