CN106664794A - 贯通电极基板及其制造方法以及使用贯通电极基板的半导体装置 - Google Patents

贯通电极基板及其制造方法以及使用贯通电极基板的半导体装置 Download PDF

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CN106664794A
CN106664794A CN201580040076.XA CN201580040076A CN106664794A CN 106664794 A CN106664794 A CN 106664794A CN 201580040076 A CN201580040076 A CN 201580040076A CN 106664794 A CN106664794 A CN 106664794A
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electrode
matrix
electrode substrate
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CN106664794B (zh
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浅野雅朗
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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Abstract

本发明的目的在于提供一种消除因在贯通电极的周缘附近配置的绝缘部分具有边界所带来的缺陷而使得结构稳定的贯通电极基板及其制造方法。贯通电极基板的特征在于，具有：基体，具有相互对置的第一面和第二面；以及贯通电极，配置于贯通孔，所述贯通孔从所述基体的所述第一面至所述第二面贯通，所述贯通电极具有在所述第一面及所述第二面上从所述基体露出的第一面侧的端面和第二面侧的端面，所述第一面侧的端面和所述第二面侧的端面中的一方或双方的周缘被所述基体覆盖。

Description

贯通电极基板及其制造方法以及使用贯通电极基板的半导体 装置
技术领域
本发明涉及贯通电极基板及其制造方法以及
使用贯通电极基板的半导体装置。
背景技术
近年来，作为大规模集成电路(LSI，large-scale integrated)芯片之间的插入件(interposer)，开发了具有用于使基板的正面和背面导通的导通部的贯通电极基板。这种贯通电极基板通过电解镀敷等向贯通孔内部填充导电材料来形成贯通电极。作为贯通电极基板的现有技术，已公开了例如利用绝缘体上硅(SOI，Silicon-On-Insulator)晶片制成的贯通电极基板(参照专利文献1)。该贯通电极基板在SOI晶片的支持基板层设置有盲孔，该盲孔具有达到埋入绝缘层的深度，并且通过在所述通孔的内壁形成内壁绝缘层而设置了贯通电极。另外，在去除了硅层而露出的埋入绝缘层中，在与贯通电极相应的部分设置有接触孔。
(现有技术文献)
(专利文献)
专利文献1：日本特开2005-38942号公报
发明内容
(发明所要解决的问题)
如专利文献1记载，现有的贯通电极基板具有如下的结构：在表面上设置有绝缘层，贯通电极通过设置于该绝缘层的接触孔而露出，从而可导通。在图25及图26中，通过剖视图示出了这种贯通电极基板800的结构。基体801具有相互对置的表面801a和表面801b，在贯通表面801a和表面801b的贯通孔中可配置贯通电极803。在此，可知基体801的表面801b和贯通电极803的表面803b形成为同一面。在基体801的表面801b及贯通电极803的表面803b上配置有布线804。
图26为在图25中示出的贯通电极基板800的被虚线所包围的附近的放大图，示出了贯通电极803的表面803b侧的、周缘803c附近。就贯通电极基板800的形成而言，在设置于基体801的孔中，可形成通过电解镀敷而填充的贯通电极803，但是存在在贯通电极803的侧面803d和基体801之间产生微小的空间的情况。另外，在基体801中配置了贯通电极803之后，基体801的表面801b和贯通电极803的表面803b可利用化学机械抛光(CMP，ChemicalMechanical Polishing)等而被研磨，但是此时也存在表面803b侧的周缘803c附近的基体801被去除而产生空间的情况。若存在因这种原因而产生的空间881，则布线804会发生断线，从而发生与贯通电极803连接故障的情况。或者，会因空间881中充满气体而导致布线804的连接可靠性下降。
图27及图28为另一方式的贯通电极基板900的剖视图。图28为示出贯通电极基板900的形成过程的图，为图27中的由虚线包围的附近的放大图。参照图27，配置有贯通基体901的表面901a和表面901b的贯通电极903。在此，将从基体901的表面901a侧和表面901b侧露出的贯通电极903分别作为表面903a和表面903b。另外，与贯通电极903的与基体901相接的面作为侧面903d。绝缘层930针对于基体901的表面901b上以及从表面901b到贯通电极903的表面903b上的一部分而配置。在绝缘层930上和未形成绝缘层930的贯通电极903的表面903b上配置有布线904。
在图27中，针对基体901的表面901b上及贯通电极903的表面903b上的一部分形成有绝缘层930。由于在贯通电极903的周缘903c附近也形成有绝缘层930，因此，周缘903c的侧面903d侧被基体901覆盖，而表面903b侧被绝缘层930覆盖。
通过形成绝缘层930，来覆盖贯通电极903的周缘903c。然而，若绝缘层930与贯通电极903之间的紧贴性不好，则在制造工序的过程中绝缘层930会因底切(undercut)而产生间隙。这样会使绝缘层930在结构上欠缺稳定性，因而会成为布线904断线的原因。
本发明是鉴于上述问题而提出的，其目的在于提供一种消除了在贯通电极与基体之间的边界部发生的由结构所引起的缺陷而使得结构稳定的贯通电极基板。
(解决问题的方案)
根据本发明的一个实施方式，提供一种贯通电极基板，其特征在于，具有：基体，具有相互对置的第一面和第二面；以及贯通电极，配置于贯通孔，所述贯通孔贯通基体的所述第一面和第二面，其中，贯通电极具有在第一面及第二面上从基体露出的第一面侧的端面和第二面侧的端面，第一面侧的端面和第二面侧的端面中的一方或双方的周缘被基体覆盖。
另外，基体可以具有位于贯通电极的周缘或周缘的外侧且沿着所述周缘的环状的凸部。
另外，基体可以包括玻璃。
另外，基体包括硅，可以在贯通孔的内壁面上配置有绝缘膜。
另外，在周缘被基体覆盖的第一面侧的端面和第二面侧的端面中的一方或双方的内侧，可以配置与基体相同材质的部件。
另外，在周缘被基体覆盖的第一面侧的端面和第二面侧的端面中的一方或双方，可以配置多个布线。
另外，根据本发明的另一实施方式，提供一种贯通电极基板的制造方法，其特征在于包括以下步骤：在具有相互对置的第一面和第二面的基体的第一面上形成开口部，该开口部的深度未达到第二面；利用导电性材料填充开口部来形成电极；在基体的第二面上，形成在电极的内侧区域的一部分具有开口，并覆盖电极的周缘的掩模；在设置有掩模的状态下，对基体的第二面进行蚀刻，使电极的内侧区域的一部分露出，且使所述基体的一部分残存在所述电极的周缘。
另外，掩模可以形成为环状。
另外，掩模可以至少一部分地包含各向同性蚀刻。
另外，随着蚀刻的进行，蚀刻掩模可以被去除。
另外，根据本发明的又一实施方式，提供一种具有上述贯通电极基板的半导体装置。
(发明的效果)
根据本发明，配置有贯通基体的相互对置的两个面的贯通电极，贯通电极的至少一个面的周缘被基体覆盖，因此能够提供结构稳定的贯通电极基板。
附图说明
图1为示出在本发明的第一实施方式的贯通电极基板的制造方法中，设置有盲孔(有底孔)的基板的截面的示意图。
图2为示出在本发明的第一实施方式的贯通电极基板的制造方法中，设置有贯通电极的基板的截面的示意图。
图3为示出在本发明的第一实施方式的贯通电极基板的制造方法中，形成有掩模的基板的截面的示意图。
图4为示出在本发明的第一实施方式的贯通电极基板的制造方法中，蚀刻过程中的基板的截面的示意图。
图5为示出在本发明的第一实施方式的贯通电极基板的制造方法中，蚀刻过程中的基板的截面的示意图。
图6为示出在本发明的第一实施方式的贯通电极基板的制造方法中，蚀刻过程中的基板的截面的示意图。
图7为示出在本发明的第一实施方式的贯通电极基板的制造方法中，完成了蚀刻的基板的截面的示意图。
图8为示出在本发明的第一实施方式的贯通电极基板的制造方法中，完成了蚀刻的基板的俯视图及立体图。
图9为示出在本发明的第一实施方式的贯通电极基板的制造方法中，形成了布线层的基板的截面的示意图。
图10为示出在本发明的第一实施方式的贯通电极基板的制造方法中，形成了绝缘层的基板的截面的示意图。
图11为用于说明本发明的第一实施方式的贯通电极基板的贯通电极的俯视图。
图12为示出在本发明的第一实施方式的变型例的贯通电极基板的制造方法中，完成了蚀刻的基板的截面的示意图。
图13为示出在本发明的第一实施方式的变型例的贯通电极基板的制造方法中，贯通电极比基体的凸部更加突出的状态的示意图。
图14为示出在本发明的第一实施方式的变型例的贯通电极基板的制造方法中，将比基体的凸部更加突出的贯通电极平坦化了的状态的示意图。
图15为示出在本发明的第二实施方式的贯通电极基板的制造方法中，蚀刻过程中的基板的截面的示意图。
图16为示出在本发明的第二实施方式的贯通电极基板的制造方法中，形成了掩模的基板的截面的示意图。
图17为示出在本发明的第二实施方式的贯通电极基板的制造方法中，完成了蚀刻的基板的截面的示意图。
图18为示出在本发明的第二实施方式的贯通电极基板的制造方法中，形成了布线层及绝缘层的基板的截面的示意图。
图19为示出本发明的第三实施方式的贯通电极基板的上部面及截面的示意图。
图20为示出本发明的第三实施方式的贯通电极基板的上部面及截面的示意图。
图21为示出本发明的第四实施方式的贯通电极基板的截面的示意图。
图22为示出本发明的第五实施方式的半导体装置的图。
图23为示出本发明的第五实施方式的半导体装置的另一示例的图。
图24为示出本发明的第五实施方式的半导体装置的又一示例的图。
图25为示出现有技术的贯通电极基板的截面的示意图。
图26为示出现有技术的贯通电极基板的截面的示意图。
图27为示出现有技术的贯通电极基板的截面的示意图。
图28为示出现有技术的贯通电极基板的截面的示意图。
具体实施方式
以下，参照附图，对本发明的贯通电极基板进行详细的说明。此外，本发明的贯通电极基板不限定于以下的实施方式，可进行各种变形来实施。在所有的实施方式中，对相同的结构要素赋予同一附图标记来进行说明。另外，为了便于说明，存在附图的尺寸比例与实际比例不同，或在附图中省略了结构的一部分的情况。
<第一实施方式>
以下，参照图1至图11，对本发明的第一实施方式的贯通电极基板100的结构及制造方法进行说明。
(整体结构)
首先，利用图7及图8对贯通电极基板100的结构的概况进行说明。图8为本发明的第一实施方式的贯通电极基板100的俯视图及立体图。图8的(a)部分为从构成贯通电极基板100的基体101的第二面101b侧观察的俯视图，图8的(b)部分为从基体101的第二面101b侧的斜向观察的立体图。另外，图7示出从图8的(a)部分的A-A’方向观察的截面的示意图。
关于贯通电极基板100，贯通电极103配置于基体101中。基体101具有相互对置的第一面101a和第二面101b。贯通电极103的第一面103a从基体101的第一面101a侧露出，第二面103b从基体101的第二面101b侧露出。另外，贯通电极103的侧面103d与基体101相接。
贯通电极103的第二面103b的周缘103c及其周边被基体101覆盖，除此之外的内侧的区域从基体101露出。即，周缘103c的侧面103d侧及第二面103b侧均被基体101覆盖。基体101覆盖贯通电极103的周缘103c及其周边的第二面103b的部分与其余部分相比厚度更薄，形成了薄壁区域(厚度薄的区域)101e。
(贯通电极基板100的制造方法)
接下来，利用图1至图8，对根据本发明的第一实施方式的贯通电极基板100的制造方法进行说明。
在图1中示出在贯通电极基板100的制造方法中，在基体101中设置有盲孔102的基板的截面。基体101的至少表面具有绝缘性。作为基体101，可使用例如玻璃(钠钙玻璃、低膨胀玻璃、无碱玻璃等)、蓝宝石、树脂等。在这种情况下，基体101的厚度可以形成在100μm～1mm的范围内。
另外，作为基体101，可以是在具有导电性的基板的表面上设置有绝缘膜的、表面具有绝缘性的基体。例如，可以在硅等的具有导电性的基板的表面形成绝缘膜。在这种情况下，绝缘膜的厚度可在0.1μm～5μm的范围内。此外，优选地，在使用包含硅的基板作为基体101的情况下，优选如下的结构：通过在盲孔102的内壁面上形成绝缘膜，而在最终的贯通孔的内壁面上设置绝缘膜。然而，在这种情况下，需要进行在如下所述的图7中的用于去除绝缘膜的蚀刻工序。
基体101具有相互对置的第一面101a和第二面101b。在基体101的第一面101a侧形成掩模(未图示)，通过蚀刻而形成盲孔102。可利用反应离子蚀刻(RIE，Reactive IonEtching)、深反应离子蚀刻(DRIE，Deep RIE)等的干法蚀刻加工、湿法蚀刻加工、激光加工等作为蚀刻的方法，来形成不贯通基体101的第二面101b侧的盲孔102。
盲孔102的深度可依据基体101的厚度而不同，但可以为例如100μm～500μm。盲孔102的开口的大小无特别限定，可以为例如10μm～100μm。另外，如各图所示，盲孔102的形状典型的为在基体101的厚度方向上呈直线状，但不限于此。例如，也可以为第一面101a侧的开口部宽、第二面101b侧的底部窄的锥形。另外，盲孔102的中央部可以为凸状、凹状或它们的组合形状。此外，对于盲孔102在俯视图上的形状也无特别限定，典型的为圆形，但除圆形以外还可以为矩形或多边形。
接下来，对贯通电极103的形成进行说明。图2为示出在盲孔102中形成了贯通电极103的状态的剖视图。通过以填埋盲孔102的方式设置导电性材料来形成贯通电极103。作为导电性材料，可以使用例如Cu(铜)等的金属。在使用Cu等的金属作为贯通电极103的情况下，可使用电解镀敷填充法。在进行电解镀敷的情况下，在形成种子层、即用于形成镀层的基底层之后，实施电解镀敷(未图示)。另外，在将该电解镀敷图案用于图案形成的情况下，利用由光刻法制成的阻挡层，使要形成镀层的部分露出。在填充了贯通电极103之后，利用化学机械抛光(CMP，Chemical Mechanical Polishing)等来使基体101的第一面101a和贯通电极103的第一面103a平坦化。
在此，将配置在盲孔102中的贯通电极103的、盲孔102的开口侧(基体101的第一面101a侧)作为第一面103a，将盲孔102的底侧(基体101的第二面101b侧)作为第二面103b。将第二面103b的端部作为周缘103c。另外，将除了第一面103a和第二面103b之外的、与基体101相接的面作为侧面103d。
接下来，对掩模130的形成进行说明。图3为示出在基体101的第二面101b侧形成了用于蚀刻的掩模130的状态的剖视图。在基体101的第二面101b中，当从第二面101b侧透视观察时，掩模130配置于贯通电极103的第二面103b的周缘103c附近。此时，掩模130的至少一部分配置为位置比周缘103c更靠内侧。如此配置掩模130的原因是，在配置了掩模130之后对基体101的第二面101b进行了各向同性蚀刻时，使贯通电极103的第二面103b的周缘103c附近的蚀刻迟缓，使贯通电极103的第二面103b的周缘103c不会露出。
在贯通电极103呈圆柱形的情况下，在基体101的第二面101b上，掩模130可仿照贯通电极103的周缘103c而配置为环状。在贯通电极103呈除圆柱之外的形状的情况下，可沿着贯通电极103的第二面103b的俯视的形状来配置掩模130。
在设置了掩模130之后，从形成了盲孔102的基体101的第一面101a的相反侧、即从作为盲孔102的底侧的基体101的第二面101b侧进行各向同性的蚀刻。作为各向同性蚀刻的一个示例，对湿法蚀刻的工序进行说明。在基体101为玻璃的情况下，使用例如氢氟酸作为蚀刻液。在这种情况下，对于掩模130可使用耐氢氟酸的材料，并利用阻挡层制版蚀刻工序将例如铬、铜等图案化来形成。此外，在进行湿法蚀刻之前形成保护层，使得基体101的第一面101a侧不被蚀刻。
图4至图7为示出进行各向同性蚀刻的状态的剖视图。尤其是，图7为示出完成了各向同性蚀刻的状态的剖视图，示出了本发明的第一实施方式的贯通电极基板100。
参照图4及图5，可知在初始的各向同性蚀刻时，在基体101的第二面101b配置有掩模130的部分未被蚀刻。但是，随着各向同性的湿法蚀刻的推进，蚀刻会从未配置掩模130的部分在横向上侵入，因此未配置掩模130的部分也渐渐发生蚀刻。图6为示出掩模130与基体101的第二面101b相接的部分被完全蚀刻，掩模130剥离的状态。
从图6的状态进一步蚀刻，最终蚀刻进行至图7中示出的状态。参照图7，在贯通电极103的第二面103b的周缘103c附近，基体101不是被完全地蚀刻，而是基体101的一部分残存下来作为薄壁区域101e。另一方面，除了贯通电极103的周缘103c附近之外的第二面103b也进行蚀刻而从基体101露出。即，贯通电极103呈配置于贯通基体101的第一面101a与第二面103b之间的贯通孔中的状态。像这样，通过使贯通电极103的周缘103c附近的基体101的一部分不被完全蚀刻，成为使贯通电极103的周缘103c及其附近的第二面103b被基体101覆盖的结构。
在此，再次利用图8，来说明完成了图7中示出的各向同性蚀刻的基板的状态。图8的(a)部分为从基体101的第二面101b侧观察的俯视图。关于贯通电极103的第二面103b，周缘103c及其附近被基体101的第二面101b的一部分所覆盖。另一方面，贯通电极103的第二面103b的内侧的区域从基体101的第二面101b露出。
图8的(b)部分为从基体101的第二面101b侧的斜向观察的立体图。参照图8的(b)部分，可知在配置有形成为圆形的贯通电极103的周缘103c的部分以及直至位于其外侧的部位形成了环状的凸部101c。由于配置了掩模130的部分与未配置掩模130的部分相比，蚀刻的推进变得迟缓，从而可形成凸部101c。通过形成凸部101c，贯通电极103的周缘103c变为其侧面103d侧及第二面101b侧均被基体101覆盖的结构。
接下来，利用图9至图11来对在贯通电极基板100上形成布线层104及绝缘层105的方法进行说明。
图9为在基体101的第二面101b上及贯通电极103的第二面103b上形成了布线层104的贯通电极基板110的剖视图。布线层104可使用导电性材料。作为导电性材料，例如，可通过将金属材料涂敷于基体101的第二面101b侧，并利用光刻进行图案化的方法等来形成。此外，虽然在图9中未图示，但是除了布线层104之外，还可以搭载其他的电子部件等。
接下来，利用图10对绝缘层105的形成进行说明。图10为示出从图9中示出的情况进一步形成了绝缘层105的贯通电极基板120的截面，并且为从图11的B-B’方向观察的剖视图。绝缘层105可使用例如感光性树脂。在这种情况下，在基体101的第二面101b及布线层104上形成感光性树脂之后，利用光刻进行图案化，并利用烘焙而形成绝缘层105。另外，在绝缘层105中形成达到布线层104的开口部106。
图11为从贯通电极基板120的绝缘层105侧观察的俯视图。布线层104形成为包围圆形的贯通电极103的周缘103c。布线层104进一步形成为在从贯通电极103到开口部106的方向上延伸，并以矩形状包围形成有开口部106的区域。此外，在表示贯通电极103的周缘103c的圆内侧所示出的圆表示在贯通电极103的第二面103b中，从基体101的第二面101b侧露出的区域。
如上所述，就第一实施方式的贯通电极基板100的形成而言，存在使贯通电极103的周缘103c附近的基体101残存的工序，但不存在对贯通电极103的第二面103b和基体101的第二面101b进行研磨的工序。因此，第一实施方式的贯通电极基板100不会发生如图25及图26所说明的以下问题：由于对贯通电极803的表面803b和基体801的表面801b的研磨而发生的基体801的缺损或基体801的缺损所伴随的布线804的断线、因基体801与贯通电极103之间的空间的产生而引起的关于布线804的连接的可靠性降低等问题。
进而，在第一实施方式的贯通电极基板100中，贯通电极103的第二面103b的周缘103c的侧面103d侧、第二面103b侧均被基体101覆盖。另一方面，在图27及图28中说明的另一现有的贯通电极基板中，贯通电极903的周缘903c侧部被基体901覆盖，上部面被绝缘层930覆盖，但在绝缘层930的形成过程中，绝缘层930会因底切而产生间隙，因此结构上欠缺稳定性。因此，在第一实施方式的贯通电极基板100中，不具有相当于现有的贯通电极基板中的绝缘层930的结构，也不存在其形成过程，因而不会发生在绝缘层930的形成过程中发生的上述问题。
因此，通过第一实施方式的贯通电极基板100及其制造方法，可提供在结构上稳定的贯通电极基板。
(变型例)
接下来，利用图12至14对本发明的第一实施方式的变型例进行说明。
在实施方式1中，在具有相互对置的第一面101a和第二面101b的基体101的第一面101a侧形成盲孔102，在盲孔102填充中贯通电极103，并基体101的第二面101b侧进行蚀刻，使贯通电极103露出。在变型例中，在基体101的第一面101a侧形成盲孔102之后，不是在盲孔102中形成贯通电极103，而是先从基体101的第二面101b侧进行蚀刻。
图12示出了在基体101中形成盲孔102，从基体101的第二面101b侧进行蚀刻，使盲孔102贯通的状态。变型例1实施的蚀刻与实施方式1中说明的方法相同。即，图12可以说是在实施方式1中，省略图2所示的贯通电极103的形成过程，而进行了图3至7中示出的蚀刻工序的状态。
在利用蚀刻使盲孔102贯通之后，从盲孔102的当初的开口侧填充金属，由此形成贯通电极103。由于在使盲孔102贯通之后填充金属，因而在填充金属时易于排出不需要的气体，不易在贯通电极103中产生气泡。若形成贯通电极103，则可形成与实施方式1中的图7所说明的相同的贯通电极基板100。
但是，在变型例1中，如图13所示，当形成贯通电极103时，存在贯通电极103的第二面103b比凸部101c更加突出的情况(参照图13的103f)。在这种情况下，在形成贯通电极103之后，可利用CMP等来使第二面103b平坦化。图14为示出使第二面103b平坦化，并形成了第一实施方式的变型例的贯通电极基板100a的状态的图。若实施CMP，则会因碟形凹陷(dishing)现象而使得贯通电极基板100a的第二面103b的中央部分凹陷，因此需要进行适当调节以便在中央部分不会发生过度的凹陷。
<实施方式2>
接下来，利用图1、图2、图8的(a)部分、以及图15至图18，对本发明的第二实施方式的贯通电极基板200的结构及制造方法进行说明。
(整体结构)
第二实施方式的贯通电极基板200的俯视图与在第一实施方式的说明中使用的图8的(a)部分相同。另外，图18示出从图8的(a)部分的A-A’方向观察的截面的示意图。
关于贯通电极基板200，可在基体101中配置贯通电极103。基体101具有相互对置的第一面101a和第二面101b。贯通电极103的第一面103a从基体101的第一面101a侧露出，第二面103b从基体101的第二面101b侧露出。另外，贯通电极103的侧面103d与基体101相接。
贯通电极103的周缘103c的侧面103d侧及第二面103b侧均被基体101覆盖。基体101基本上在整体上具有恒定的厚度，但覆盖贯通电极103的第二面的部分的厚度薄，形成了薄壁区域(厚度薄的区域)101e。
(贯通电极基板200的制造方法)
在第二实施方式中，直至在基体101中形成盲孔102、并且填充贯通电极103的制造方法与使用图1及图2说明的实施方式1的贯通电极基板100的制造方法相同。
图15为示出从图2的状态开始从基体101的第二面101b侧开始遍及第二面101b全体地进行了蚀刻的状态的图。作为蚀刻的方法，可通过湿法蚀刻加工、干法蚀刻加工、激光加工等来进行。此外，虚线101b’示出进行蚀刻之前的、基体101的第二面101b的位置。关于蚀刻，并不是进行蚀刻直至贯通电极103的第二面103b露出，而是在基体101的第二面101b与贯通电极103的第二面103b之间留有厚度a。
在利用各向同性湿法蚀刻进行蚀刻工序的情况下，例如，可使用氢氟酸作为蚀刻液，并以使得基体101的第一面101a侧不被蚀刻的方式形成保护层。在这种情况下，进行蚀刻以使厚度a为例如30μm以下。这是因为，在后述的掩模之后的蚀刻过程中，若厚度a大，则除了在基体101的厚度方向上的蚀刻之外，蚀刻在横向上的发展所引起的影响也不容忽视。另外，在利用湿法蚀刻进行蚀刻时，由于会发生蚀刻的不均匀，因而优选厚度a为1μm以上。
另外，在利用RIE或DRIE等的各向异性干法蚀刻来进行蚀刻工序的情况下，不特别限定厚度a的上限。但是，优选厚度a为1μm以上。
接下来，对用于使贯通电极103从基体101的第二面101b露出的掩模的形成进行说明。图16为示出在基体101的第二面101b上形成了掩模131的状态的剖视图。此外，在图16中示出的掩模配置示出了利用各向异性蚀刻来进行掩模形成之后的蚀刻工序的情况下的掩模的形成。
在第二实施方式中，为了使贯通电极103的第二面103b从基体101露出，在要露出的贯通电极103的第二面103b的区域中不形成掩模131，而在除此之外的部分中形成掩模131。更详细的说明如下：当从基体101的第二面101b侧透视观察时，从不存在贯通电极103的一侧直至越过贯通电极103的周缘103c的部分形成掩模131，使得掩模131与周缘103c重叠。掩模131可利用例如阻挡层的图案化来进行。
接下来，对用于使贯通电极103从基体101的第二面101b露出的蚀刻进行说明。图17为从图16所示的状态进行了各向异性蚀刻之后的状态的图，为本发明的第二实施方式的贯通电极基板200的剖视图。
利用各向异性蚀刻，未配置掩模131的基体101会受到蚀刻。如上所述，掩模131形成为与周缘103c重叠，因此贯通电极103的第二面103b除了周缘103c附近的部分之外从基体101露出。掩模131配置至越过贯通电极103的周缘103c的部分，因而在周缘103c的附近，在其侧面103d侧及第二面103b侧，基体101均未蚀刻而残存。图中的131’示出了配置了掩模131的部位。各向异性蚀刻的工序完成之后，可使掩模131剥离。
图18为示出在图17所示的贯通电极基板200中形成布线层104，进而形成了绝缘层105的贯通电极基板220的剖视图。在完成了蚀刻之后，形成布线层104、并形成绝缘层105的方法与实施方式1相同。
如上所述，在第二实施方式的贯通电极基板200中，贯通电极103的第二面103b的周缘103c的侧面103d侧和第二面103b侧也均被基体101覆盖。另外，第二实施方式中的贯通电极基板200的制造方法与第一实施方式的贯通电极基板200的制造方法同样，不会发生在图25至图28中说明的现有技术中的制造过程中的问题。因此，关于贯通电极基板200，可提供与第一实施方式中同样的结构稳定的贯通电极基板。
<第三实施方式>
接下来，参照图19及图20，对本发明的第三实施方式的贯通电极基板300及400的结构进行说明。
在第一实施方式及第二实施方式中，贯通电极103的第二面103b的除周缘103c的附近外全都从基体101露出，但本发明不限于此。在除贯通电极103的周缘103c附近之外的部位，也可以使基体101的一部分在阻挡剂处理中不被去除而是残存。
图19为示出第三实施方式的贯通电极基板300的俯视图及剖视图。若参照图19的(a)部分及图19的(b)部分，可知呈圆形的岛状的基体101d配置于贯通电极103的中央附近。在此，贯通电极103的第二面103b形成有呈环状的开口部。
图20为示出第三实施方式的贯通电极基板400的俯视图及剖视图。参照图20的(a)部分及图20的(b)部分可知，环状的基体101f配置于贯通电极103的中央附近。在此，贯通电极103的第二面103b包括：环状的开口部，位于以环状残存的基体101f的外侧；以及圆形的开口部，位于以环状残存的基体101f的内侧。
除了图19及图20示出的形状之外，还可以通过对于基体101的第二面101b适当地选择利用阻挡剂进行掩模的图案，使贯通电极103的第二面103b的开口部形成规定的形状。此外，在第三实施方式中，为了易于进行贯通电极103的第二面103b的开口部的形成，也可以使贯通电极103的第二面103b的面积大于第一实施方式及第二实施方式的情况。
像这样，在第三实施方式中，通过适当地设定贯通电极103的第二面103b的开口部的形状及宽阔度，能够调节贯通电极103与在贯通电极103的第二面103b及基体101的第二面101b上配置的布线层(未图示)之间的电阻值。
另外，在第三实施方式中，与第一实施方式及第二实施方式相比，贯通电极103的第二面103b侧的凹凸增加，因而提高了当配置布线层或使其他绝缘层层叠化时的紧贴性。
<实施方式4>
接下来，参照图21，对本发明的第四实施方式的贯通电极基板500的结构进行说明。在第四实施方式中，形成有与贯通电极103的第二面103b相连接的第一布线505及第二布线506。
对第四实施方式的贯通电极基板500的制造方法的一个示例进行说明。首先，直至第一实施方式中的图8中示出的状态，形成基体101及贯通电极103。接下来，在图21的左侧的基体101的第二面101b上和相邻的贯通电极103的第二面103b上的一部分上形成第一布线505。接下来，在第一布线505及与其相邻的贯通电极103的第二面103b上的一部分上形成绝缘层507。最后，在绝缘层507、贯通电极103的第二面103b及右侧的基体101的第二面101b上形成第二布线506。在此，第一布线505与第二布线506经由贯通电极103而相互电连接，然而由于可隔着绝缘层507而形成，因此除此之外的部分不电连接。
第四实施方式的贯通电极基板500的制造方法不限于上述制造方法。例如，也可以在第二实施方式中说明的贯通电极基板200上，同样地形成第一布线505、绝缘层507及第二布线506。另外，如在第三实施方式中所说明的，也可以在贯通电极103的第二面103b上形成两个开口部，形成的开口部分别与第一布线505、第二布线506相连接。
另外，在贯通电极103的第二面103b上，还可以形成布线层及绝缘层，以便使三个以上的布线相连接。
根据第四实施方式的贯通电极基板500，由于经由贯通电极103连接多个布线，因此能够在贯通电极103上实现布线的分支。
<第五实施方式>
在第五实施方式中，对使用第一至第四实施方式中的贯通电极基板制造的半导体装置1000进行说明。
图22为示出本发明的第五实施方式的半导体装置1000的图。半导体装置1000由三个贯通电极基板610、620、630层叠而成，并与LSI基板700相连接。贯通电极基板610形成有例如动态随机存取存储器(DRAM，Dynamic Random Access Memory)等的半导体元件，并且具有由布线层104(未图示)等形成的连接端子611、612。这三个贯通电极基板610、620、630的一个以上可以为由玻璃、蓝宝石等形成的基板构成的贯通电极基板。连接端子612经由凸块(bump)751与LSI基板700的连接端子701相连接。连接端子611经由凸块752与贯通电极基板620的连接端子622相连接。贯通电极基板620的连接端子621与贯通电极基板630的连接端子632经由凸块753相连接。凸块751、752、753可使用例如铟、铜、金等的金属。
此外，在层叠贯通电极基板的情况下，不限于三层，也可以为两层，还可以为四层以上。另外，在贯通电极基板与其他基板之间的连接中，不限于利用凸块的技术，还可使用共晶接合等其他接合技术。另外，还可进行聚酰亚胺、环氧树脂等的涂敷、烘焙，将贯通电极基板与其他基板粘接起来。
图23为示出本发明的第五实施方式的半导体装置的另一示例的图。图23所示的半导体装置1000a由微机电系统(MEMS，Micro-Electro-Mechanical System)器件、中央处理器(CPU，Central Processing Unit)、存储器等的半导体芯片(LSI芯片)710、720及贯通电极基板600层叠而成，并与LSI基板700相连接。
在半导体芯片710与半导体芯片720之间配置有贯通电极基板600，并经由凸块754、755相连接。在LSI基板700上放置半导体芯片710，LSI基板700与半导体芯片720通过导线705相连接。在该示例中，贯通电极基板600可用作将多个半导体芯片层叠来进行三维安装的插入件，并且能够通过层叠功能各自不同的多个半导体芯片，来制造多功能的半导体装置。例如，可通过将半导体芯片710用作三轴加速度传感器，将半导体芯片720用作二轴磁传感器，来制造出用一个模块实现五轴运动传感器的半导体装置。
在半导体芯片为由MEMS器件形成的传感器等的情况下，存在传感结果利用模拟信号来输出的情况。在这种情况下，还可以将低通滤波器、放大器等形成于半导体芯片或贯通电极基板600。
图24为示出本发明的第五实施方式的半导体装置的又一示例的图。上述两个示例(图22、图23)为三维安装，而此示例为适用于二维和三维的合并安装的例子。在图24所示的半导体装置1000b中，LSI基板700与六个贯通电极基板610、620、630、640、650、660层叠并相连接。但是，并不是所有贯通电极基板都层叠配置，也并排配置在LSI基板700的面内方向上。这些贯通电极基板610、620、630、640、650、660中的一个以上也可以为由玻璃、蓝宝石等形成的基板构成的贯通电极基板。
在图24的示例中，在LSI基板700上连接有贯通电极基板610、650，在贯通电极基板610上连接有贯通电极基板620、640，在贯通电极基板620上连接有贯通电极基板630，在贯通电极基板650上连接有贯通电极基板660。此外，如图23所示的示例，即使将贯通电极基板用作用于连接多个半导体芯片的插入件，也可采用这种二维与三维的合并安装。例如，贯通电极基板630、640、660等还可以置换为半导体芯片。
通过如上所述的方法制造的半导体装置1000、1000a、1000b可搭载于例如便携式终端(移动电话、智能电话及笔记本式个人计算机等)、信息处理装置(台式个人计算机、服务器、汽车导航系统等)、家电等各种电子设备。这些电子设备具有由用于通过执行应用程序来实现各种功能的CPU等形成的控制部，各种功能包括使用来自半导体装置1000的输出信号的功能。
(附图标记的说明)
100、200、300、400、500：贯通电极基板；101：基体；102：盲孔；
103：贯通电极；104：布线层；105：绝缘层；106：开口部；130、131：掩模。

Claims (11)

1.一种贯通电极基板，其特征在于，具有：
基体，具有第一面和第二面，所述第二面与所述第一面对置；以及
贯通电极，配置于贯通孔，所述贯通孔贯通所述基体的所述第一面和所述第二面，
所述贯通电极的所述第一面侧的端面和所述第二面侧的端面中的一方或双方的周缘被所述基体的一部分覆盖。
2.根据权利要求1所述的贯通电极基板，其特征在于，所述基体具有位于所述贯通电极的所述周缘或所述周缘的外侧并沿着所述周缘的环状的凸部。
3.根据权利要求1所述的贯通电极基板，其特征在于，所述基体包括玻璃。
4.根据权利要求1所述的贯通电极基板，其特征在于，所述基体包括硅，在所述贯通孔的内壁面上配置有绝缘膜。
5.根据权利要求1所述的贯通电极基板，其特征在于，在所述周缘被所述基体的一部分覆盖的所述第一面侧的端面和所述第二面侧的端面中的一方或双方的内侧，配置有与所述基体相同材质的部件。
6.根据权利要求1所述的贯通电极基板，其特征在于，在所述周缘被所述基体的一部分覆盖的所述第一面侧的端面和所述第二面侧的端面中的一方或双方配置有多个布线。
7.一种贯通电极基板的制造方法，其特征在于，包括以下步骤：
在具有相互对置的第一面和第二面的基体的所述第一面上形成开口部，所述开口部的深度未达到所述第二面；
利用导电性材料填充所述开口部来形成电极；
在所述基体的所述第二面上，形成在所述电极的内侧区域的一部分具有开口，并覆盖所述电极的周缘的掩模；以及
在设置有所述掩模的状态下，对所述基体的所述第二面进行蚀刻，使所述电极的内侧区域的一部分露出，并且使所述基体的一部分残存于所述电极的周缘。
8.根据权利要求7所述的贯通电极基板的制造方法，其特征在于，所述掩模形成为环状。
9.根据权利要求7所述的贯通电极基板的制造方法，其特征在于，所述蚀刻至少一部分地包含各向同性蚀刻。
10.根据权利要求7所述的贯通电极基板的制造方法，其特征在于，所述掩模随着所述蚀刻的进行而被去除。
11.一种半导体装置，其具有根据权利要求1所述的贯通电极基板。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007184314A (ja) * 2005-12-30 2007-07-19 Murata Mfg Co Ltd セラミック多層基板の製造方法およびセラミック多層基板
US20120327626A1 (en) * 2011-06-27 2012-12-27 Shinko Electric Industries Co., Ltd. Wiring substrate, its manufacturing method, and semiconductor device
US20130333934A1 (en) * 2012-06-14 2013-12-19 Dror Hurwitz Multilayer electronic structure with stepped holes
WO2016021397A1 (ja) * 2014-08-06 2016-02-11 大日本印刷株式会社 貫通電極基板及びその製造方法、並びに貫通電極基板を用いた半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0493096A (ja) * 1990-08-08 1992-03-25 Shinko Electric Ind Co Ltd 多層セラミック基板
JP4069028B2 (ja) 2003-07-16 2008-03-26 株式会社フジクラ 貫通電極付き基板、その製造方法及び電子デバイス
JP2008066601A (ja) 2006-09-08 2008-03-21 Ebara Corp 基板処理方法、基板処理装置及び半導体装置
JP2011228495A (ja) 2010-04-20 2011-11-10 Asahi Glass Co Ltd 半導体デバイス貫通電極形成用のガラス基板の製造方法および半導体デバイス貫通電極形成用のガラス基板
CN103329637B (zh) * 2011-02-08 2016-04-13 株式会社村田制作所 树脂多层基板及其制造方法
US8853072B2 (en) 2011-06-06 2014-10-07 Micron Technology, Inc. Methods of forming through-substrate interconnects

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007184314A (ja) * 2005-12-30 2007-07-19 Murata Mfg Co Ltd セラミック多層基板の製造方法およびセラミック多層基板
US20120327626A1 (en) * 2011-06-27 2012-12-27 Shinko Electric Industries Co., Ltd. Wiring substrate, its manufacturing method, and semiconductor device
US20130333934A1 (en) * 2012-06-14 2013-12-19 Dror Hurwitz Multilayer electronic structure with stepped holes
WO2016021397A1 (ja) * 2014-08-06 2016-02-11 大日本印刷株式会社 貫通電極基板及びその製造方法、並びに貫通電極基板を用いた半導体装置

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