JP5241219B2 - 電子部品パッケージの製造方法、電子部品パッケージ用ウェハの製造方法ならびに電子部品パッケージ用基礎構造物の製造方法 - Google Patents
電子部品パッケージの製造方法、電子部品パッケージ用ウェハの製造方法ならびに電子部品パッケージ用基礎構造物の製造方法 Download PDFInfo
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- Condensed Matter Physics & Semiconductors (AREA)
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- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
以下、本発明の実施の形態について図面を参照して詳細に説明する。始めに、図1ないし図4を参照して、本発明の第1の実施の形態に係る電子部品パッケージの製造方法の概略について説明する。
次に、本発明の第2の実施の形態について説明する。本実施の形態に係る電子部品パッケージの製造方法の概略は、図1ないし図4を参照して説明した第1の実施の形態に係る電子部品パッケージの製造方法の概略と同様である。本実施の形態では、特にウェハ1を作製する工程が第1の実施の形態とは異なっている。以下、図23ないし図30を参照して、本実施の形態に係る電子部品パッケージの製造方法について詳しく説明する。図23は、本実施の形態における基板の一部を示す断面図である。図24ないし図29は、本実施の形態に係る電子部品パッケージの製造方法における各工程で作製される積層体の一部を示す断面図である。図30は、図29に示した工程に続く工程において作製される電子部品パッケージを示す断面図である。
Claims (13)
- 複数の外部接続端子を有する基体と、前記基体に接合され且つ前記複数の外部接続端子の少なくとも1つに電気的に接続された少なくとも1つの電子部品チップとを備えた電子部品パッケージの製造方法であって、
前記電子部品チップは複数の電極を有し、
前記電子部品パッケージは、それぞれ少なくとも1つの前記電極と少なくとも1つの前記外部接続端子とを電気的に接続する複数の端子用接続部を備え、
電子部品パッケージの製造方法は、
上面を有する基板と、前記基板の上面上に設けられた、複数の電子部品パッケージに対応した複数組の外部接続端子と、前記基板の上面上に設けられ、各々に前記少なくとも1つの電子部品チップが接合される複数のチップ接合用導体層とを有し、それぞれ後に互いに分離されることによって基体となる複数の基体予定部を含むウェハを作製する工程と、
前記ウェハの各基体予定部における前記チップ接合用導体層の上にそれぞれ少なくとも1つの電子部品チップを接合する工程と、
前記チップ接合用導体層の上に電子部品チップを接合する工程の後で、前記端子用接続部を形成する工程と、
前記端子用接続部を形成する工程の後で、各基体予定部が互いに分離されて複数の基体が形成されるように、前記ウェハを切断する工程とを備え、
前記ウェハを作製する工程は、前記基板の上面上に、めっき法を用いて前記複数組の外部接続端子を形成する工程を含み、
前記端子用接続部を形成する工程は、前記ウェハおよび電子部品チップを覆い、平坦化された上面を有する絶縁層を形成する工程と、前記絶縁層に、前記外部接続端子および電極を露出させるための複数の開口部を形成する工程と、その一部が前記開口部に挿入されるように、めっき法によって前記端子用接続部を形成する工程とを含むことを特徴とする電子部品パッケージの製造方法。 - 前記複数組の外部接続端子を形成する工程は、めっき法によって、それぞれ外部接続端子の一部となる複数の第1のめっき層を形成する工程と、めっき法によって、それぞれ前記複数の第1のめっき層の上に配置されるように前記複数の第2のめっき層を形成する工程とを含み、
前記複数の第1のめっき層を形成する工程は、同時に、前記複数のチップ接合用導体層を構成する複数のチップ接合用めっき層を形成することを特徴とする請求項1記載の電子部品パッケージの製造方法。 - 前記基板の上面は、前記複数のチップ接合用導体層が配置される複数の凹部を有し、
前記複数組の外部接続端子を形成する工程は、同時に、前記複数の凹部内に配置されるように前記複数のチップ接合用導体層を形成することを特徴とする請求項1記載の電子部品パッケージの製造方法。 - 前記電子部品パッケージは、複数の前記電子部品チップを備え、更に、前記複数の電子部品チップの電極同士を電気的に接続する少なくとも1つのチップ間接続部を備え、
前記チップ間接続部は、前記端子用接続部が形成される際に同時に形成されることを特徴とする請求項1記載の電子部品パッケージの製造方法。 - 更に、前記端子用接続部を形成する工程と前記ウェハを切断する工程との間において、前記電子部品チップを封止する封止部材を形成する工程を備えたことを特徴とする請求項1記載の電子部品パッケージの製造方法。
- 前記基体は側面を有し、前記側面において前記複数の外部接続端子の端面が露出していることを特徴とする請求項1記載の電子部品パッケージの製造方法。
- 電子部品パッケージは、更に、前記基体の側面に配置され、それぞれ外部接続端子の端面に接続された複数の端子用めっき膜を備え、
電子部品パッケージの製造方法は、更に、前記ウェハを切断する工程の後で、前記複数の端子用めっき膜を形成する工程を備えたことを特徴とする請求項6記載の電子部品パッケージの製造方法。 - 電子部品パッケージは、更に、それぞれ外部接続端子に接続された複数の端子用ピンを備え、
電子部品パッケージの製造方法は、更に、前記ウェハを切断する工程の後で、前記外部接続端子の端面に前記端子用ピンを接続する工程を備えたことを特徴とする請求項6記載の電子部品パッケージの製造方法。 - それぞれ、複数の外部接続端子を有する基体と、前記基体に接合され且つ前記複数の外部接続端子の少なくとも1つに電気的に接続された少なくとも1つの電子部品チップとを備えた複数の電子部品パッケージを製造するために用いられる電子部品パッケージ用基礎構造物の製造方法であって、
前記電子部品チップは複数の電極を有し、
前記電子部品パッケージは、それぞれ少なくとも1つの前記電極と少なくとも1つの前記外部接続端子とを電気的に接続する複数の端子用接続部を備え、
前記電子部品パッケージ用基礎構造物は、上面を有する基板と、基板の上面上に設けられた、複数の電子部品パッケージに対応した複数組の外部接続端子と、前記基板の上面上に設けられ、各々に前記少なくとも1つの電子部品チップが接合される複数のチップ接合用導体層とを有し、それぞれ後に互いに分離されることによって基体となる複数の基体予定部を含むウェハと、前記ウェハの各基体予定部における前記チップ接合用導体層の上に接合された複数の電子部品チップとを備え、
電子部品パッケージ用基礎構造物の製造方法は、
前記ウェハを作製する工程と、
前記ウェハの各基体予定部における前記チップ接合用導体層の上にそれぞれ少なくとも1つの電子部品チップを接合する工程と、
前記チップ接合用導体層の上に電子部品チップを接合する工程の後で、前記端子用接続部を形成する工程とを備え、
前記ウェハを作製する工程は、前記基板の上面上に、めっき法を用いて前記複数組の外部接続端子を形成する工程を含み、
前記端子用接続部を形成する工程は、前記ウェハおよび電子部品チップを覆い、平坦化された上面を有する絶縁層を形成する工程と、前記絶縁層に、前記外部接続端子および電極を露出させるための複数の開口部を形成する工程と、その一部が前記開口部に挿入されるように、めっき法によって前記端子用接続部を形成する工程とを含むことを特徴とする電子部品パッケージ用基礎構造物の製造方法。 - 前記複数組の外部接続端子を形成する工程は、めっき法によって、それぞれ外部接続端子の一部となる複数の第1のめっき層を形成する工程と、めっき法によって、それぞれ前記複数の第1のめっき層の上に配置されるように前記複数の第2のめっき層を形成する工程とを含み、
前記複数の第1のめっき層を形成する工程は、同時に、前記複数のチップ接合用導体層を構成する複数のチップ接合用めっき層を形成することを特徴とする請求項9記載の電子部品パッケージ用基礎構造物の製造方法。 - 前記基板の上面は、前記複数のチップ接合用導体層が配置される複数の凹部を有し、
前記複数組の外部接続端子を形成する工程は、同時に、前記複数の凹部内に配置されるように前記複数のチップ接合用導体層を形成することを特徴とする請求項9記載の電子部品パッケージ用基礎構造物の製造方法。 - 前記電子部品パッケージは、複数の前記電子部品チップを備え、更に、前記複数の電子部品チップの電極同士を電気的に接続する少なくとも1つのチップ間接続部を備え、
前記チップ間接続部は、前記端子用接続部が形成される際に同時に形成されることを特徴とする請求項9記載の電子部品パッケージ用基礎構造物の製造方法。 - 更に、前記端子用接続部を形成する工程の後で前記電子部品チップを封止する封止部材を形成する工程を備えたことを特徴とする請求項9記載の電子部品パッケージ用基礎構造物の製造方法。
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