JP5241219B2 - 電子部品パッケージの製造方法、電子部品パッケージ用ウェハの製造方法ならびに電子部品パッケージ用基礎構造物の製造方法 - Google Patents
電子部品パッケージの製造方法、電子部品パッケージ用ウェハの製造方法ならびに電子部品パッケージ用基礎構造物の製造方法 Download PDFInfo
- Publication number
- JP5241219B2 JP5241219B2 JP2007322711A JP2007322711A JP5241219B2 JP 5241219 B2 JP5241219 B2 JP 5241219B2 JP 2007322711 A JP2007322711 A JP 2007322711A JP 2007322711 A JP2007322711 A JP 2007322711A JP 5241219 B2 JP5241219 B2 JP 5241219B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- chip
- forming
- manufacturing
- component package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01044—Ruthenium [Ru]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15798—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49133—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting
- Y10T29/49135—Assembling to base an electrical component, e.g., capacitor, etc. with component orienting and shaping, e.g., cutting or bending, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
以下、本発明の実施の形態について図面を参照して詳細に説明する。始めに、図1ないし図4を参照して、本発明の第1の実施の形態に係る電子部品パッケージの製造方法の概略について説明する。
次に、本発明の第2の実施の形態について説明する。本実施の形態に係る電子部品パッケージの製造方法の概略は、図1ないし図4を参照して説明した第1の実施の形態に係る電子部品パッケージの製造方法の概略と同様である。本実施の形態では、特にウェハ1を作製する工程が第1の実施の形態とは異なっている。以下、図23ないし図30を参照して、本実施の形態に係る電子部品パッケージの製造方法について詳しく説明する。図23は、本実施の形態における基板の一部を示す断面図である。図24ないし図29は、本実施の形態に係る電子部品パッケージの製造方法における各工程で作製される積層体の一部を示す断面図である。図30は、図29に示した工程に続く工程において作製される電子部品パッケージを示す断面図である。
Claims (13)
- 複数の外部接続端子を有する基体と、前記基体に接合され且つ前記複数の外部接続端子の少なくとも1つに電気的に接続された少なくとも1つの電子部品チップとを備えた電子部品パッケージの製造方法であって、
前記電子部品チップは複数の電極を有し、
前記電子部品パッケージは、それぞれ少なくとも1つの前記電極と少なくとも1つの前記外部接続端子とを電気的に接続する複数の端子用接続部を備え、
電子部品パッケージの製造方法は、
上面を有する基板と、前記基板の上面上に設けられた、複数の電子部品パッケージに対応した複数組の外部接続端子と、前記基板の上面上に設けられ、各々に前記少なくとも1つの電子部品チップが接合される複数のチップ接合用導体層とを有し、それぞれ後に互いに分離されることによって基体となる複数の基体予定部を含むウェハを作製する工程と、
前記ウェハの各基体予定部における前記チップ接合用導体層の上にそれぞれ少なくとも1つの電子部品チップを接合する工程と、
前記チップ接合用導体層の上に電子部品チップを接合する工程の後で、前記端子用接続部を形成する工程と、
前記端子用接続部を形成する工程の後で、各基体予定部が互いに分離されて複数の基体が形成されるように、前記ウェハを切断する工程とを備え、
前記ウェハを作製する工程は、前記基板の上面上に、めっき法を用いて前記複数組の外部接続端子を形成する工程を含み、
前記端子用接続部を形成する工程は、前記ウェハおよび電子部品チップを覆い、平坦化された上面を有する絶縁層を形成する工程と、前記絶縁層に、前記外部接続端子および電極を露出させるための複数の開口部を形成する工程と、その一部が前記開口部に挿入されるように、めっき法によって前記端子用接続部を形成する工程とを含むことを特徴とする電子部品パッケージの製造方法。 - 前記複数組の外部接続端子を形成する工程は、めっき法によって、それぞれ外部接続端子の一部となる複数の第1のめっき層を形成する工程と、めっき法によって、それぞれ前記複数の第1のめっき層の上に配置されるように前記複数の第2のめっき層を形成する工程とを含み、
前記複数の第1のめっき層を形成する工程は、同時に、前記複数のチップ接合用導体層を構成する複数のチップ接合用めっき層を形成することを特徴とする請求項1記載の電子部品パッケージの製造方法。 - 前記基板の上面は、前記複数のチップ接合用導体層が配置される複数の凹部を有し、
前記複数組の外部接続端子を形成する工程は、同時に、前記複数の凹部内に配置されるように前記複数のチップ接合用導体層を形成することを特徴とする請求項1記載の電子部品パッケージの製造方法。 - 前記電子部品パッケージは、複数の前記電子部品チップを備え、更に、前記複数の電子部品チップの電極同士を電気的に接続する少なくとも1つのチップ間接続部を備え、
前記チップ間接続部は、前記端子用接続部が形成される際に同時に形成されることを特徴とする請求項1記載の電子部品パッケージの製造方法。 - 更に、前記端子用接続部を形成する工程と前記ウェハを切断する工程との間において、前記電子部品チップを封止する封止部材を形成する工程を備えたことを特徴とする請求項1記載の電子部品パッケージの製造方法。
- 前記基体は側面を有し、前記側面において前記複数の外部接続端子の端面が露出していることを特徴とする請求項1記載の電子部品パッケージの製造方法。
- 電子部品パッケージは、更に、前記基体の側面に配置され、それぞれ外部接続端子の端面に接続された複数の端子用めっき膜を備え、
電子部品パッケージの製造方法は、更に、前記ウェハを切断する工程の後で、前記複数の端子用めっき膜を形成する工程を備えたことを特徴とする請求項6記載の電子部品パッケージの製造方法。 - 電子部品パッケージは、更に、それぞれ外部接続端子に接続された複数の端子用ピンを備え、
電子部品パッケージの製造方法は、更に、前記ウェハを切断する工程の後で、前記外部接続端子の端面に前記端子用ピンを接続する工程を備えたことを特徴とする請求項6記載の電子部品パッケージの製造方法。 - それぞれ、複数の外部接続端子を有する基体と、前記基体に接合され且つ前記複数の外部接続端子の少なくとも1つに電気的に接続された少なくとも1つの電子部品チップとを備えた複数の電子部品パッケージを製造するために用いられる電子部品パッケージ用基礎構造物の製造方法であって、
前記電子部品チップは複数の電極を有し、
前記電子部品パッケージは、それぞれ少なくとも1つの前記電極と少なくとも1つの前記外部接続端子とを電気的に接続する複数の端子用接続部を備え、
前記電子部品パッケージ用基礎構造物は、上面を有する基板と、基板の上面上に設けられた、複数の電子部品パッケージに対応した複数組の外部接続端子と、前記基板の上面上に設けられ、各々に前記少なくとも1つの電子部品チップが接合される複数のチップ接合用導体層とを有し、それぞれ後に互いに分離されることによって基体となる複数の基体予定部を含むウェハと、前記ウェハの各基体予定部における前記チップ接合用導体層の上に接合された複数の電子部品チップとを備え、
電子部品パッケージ用基礎構造物の製造方法は、
前記ウェハを作製する工程と、
前記ウェハの各基体予定部における前記チップ接合用導体層の上にそれぞれ少なくとも1つの電子部品チップを接合する工程と、
前記チップ接合用導体層の上に電子部品チップを接合する工程の後で、前記端子用接続部を形成する工程とを備え、
前記ウェハを作製する工程は、前記基板の上面上に、めっき法を用いて前記複数組の外部接続端子を形成する工程を含み、
前記端子用接続部を形成する工程は、前記ウェハおよび電子部品チップを覆い、平坦化された上面を有する絶縁層を形成する工程と、前記絶縁層に、前記外部接続端子および電極を露出させるための複数の開口部を形成する工程と、その一部が前記開口部に挿入されるように、めっき法によって前記端子用接続部を形成する工程とを含むことを特徴とする電子部品パッケージ用基礎構造物の製造方法。 - 前記複数組の外部接続端子を形成する工程は、めっき法によって、それぞれ外部接続端子の一部となる複数の第1のめっき層を形成する工程と、めっき法によって、それぞれ前記複数の第1のめっき層の上に配置されるように前記複数の第2のめっき層を形成する工程とを含み、
前記複数の第1のめっき層を形成する工程は、同時に、前記複数のチップ接合用導体層を構成する複数のチップ接合用めっき層を形成することを特徴とする請求項9記載の電子部品パッケージ用基礎構造物の製造方法。 - 前記基板の上面は、前記複数のチップ接合用導体層が配置される複数の凹部を有し、
前記複数組の外部接続端子を形成する工程は、同時に、前記複数の凹部内に配置されるように前記複数のチップ接合用導体層を形成することを特徴とする請求項9記載の電子部品パッケージ用基礎構造物の製造方法。 - 前記電子部品パッケージは、複数の前記電子部品チップを備え、更に、前記複数の電子部品チップの電極同士を電気的に接続する少なくとも1つのチップ間接続部を備え、
前記チップ間接続部は、前記端子用接続部が形成される際に同時に形成されることを特徴とする請求項9記載の電子部品パッケージ用基礎構造物の製造方法。 - 更に、前記端子用接続部を形成する工程の後で前記電子部品チップを封止する封止部材を形成する工程を備えたことを特徴とする請求項9記載の電子部品パッケージ用基礎構造物の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/806,047 | 2007-05-29 | ||
US11/806,047 US7816176B2 (en) | 2007-05-29 | 2007-05-29 | Method of manufacturing electronic component package |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008300817A JP2008300817A (ja) | 2008-12-11 |
JP5241219B2 true JP5241219B2 (ja) | 2013-07-17 |
Family
ID=40086542
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007322711A Active JP5241219B2 (ja) | 2007-05-29 | 2007-12-14 | 電子部品パッケージの製造方法、電子部品パッケージ用ウェハの製造方法ならびに電子部品パッケージ用基礎構造物の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7816176B2 (ja) |
JP (1) | JP5241219B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9504162B2 (en) * | 2011-05-20 | 2016-11-22 | Pepex Biomedical, Inc. | Manufacturing electrochemical sensor modules |
US8552534B2 (en) | 2011-11-01 | 2013-10-08 | Headway Technologies, Inc. | Laminated semiconductor substrate, semiconductor substrate, laminated chip package and method of manufacturing the same |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3489952A (en) * | 1967-05-15 | 1970-01-13 | Singer Co | Encapsulated microelectronic devices |
KR100437437B1 (ko) * | 1994-03-18 | 2004-06-25 | 히다치 가세고교 가부시끼가이샤 | 반도체 패키지의 제조법 및 반도체 패키지 |
KR0179920B1 (ko) * | 1996-05-17 | 1999-03-20 | 문정환 | 칩 사이즈 패키지의 제조방법 |
US5899705A (en) * | 1997-11-20 | 1999-05-04 | Akram; Salman | Stacked leads-over chip multi-chip module |
JP2001035993A (ja) | 1999-07-19 | 2001-02-09 | Sony Corp | マルチチップモジュールおよびその製造方法 |
JP3833859B2 (ja) * | 1999-10-14 | 2006-10-18 | ローム株式会社 | 半導体装置およびその製造方法 |
JP2001094006A (ja) * | 1999-09-22 | 2001-04-06 | Hitachi Cable Ltd | 半導体素子搭載用基板及び半導体装置 |
JP2001244403A (ja) | 2000-02-29 | 2001-09-07 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP3772066B2 (ja) * | 2000-03-09 | 2006-05-10 | 沖電気工業株式会社 | 半導体装置 |
JP4659488B2 (ja) * | 2005-03-02 | 2011-03-30 | Okiセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
JP4777692B2 (ja) * | 2005-06-06 | 2011-09-21 | ローム株式会社 | 半導体装置 |
JP2008218926A (ja) * | 2007-03-07 | 2008-09-18 | Spansion Llc | 半導体装置及びその製造方法 |
-
2007
- 2007-05-29 US US11/806,047 patent/US7816176B2/en not_active Expired - Fee Related
- 2007-12-14 JP JP2007322711A patent/JP5241219B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
US7816176B2 (en) | 2010-10-19 |
US20080295328A1 (en) | 2008-12-04 |
JP2008300817A (ja) | 2008-12-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4994274B2 (ja) | 電子部品パッケージの製造方法 | |
CN101681886B (zh) | 半导体组合件、堆叠式半导体装置及制造半导体组合件及堆叠式半导体装置的方法 | |
JP5536973B2 (ja) | 貫通接続構造物を高密度に備えた積層可能な層構造体及び積層体 | |
KR101734882B1 (ko) | 영역 어레이 유닛 컨넥터를 갖는 적층 가능한 몰딩된 마이크로전자 패키지 | |
US8174109B2 (en) | Electronic device and method of manufacturing same | |
CN104025285B (zh) | 多管芯封装结构 | |
JP5004311B2 (ja) | 積層チップパッケージおよびその製造方法 | |
JP5154667B2 (ja) | 積層チップパッケージおよびその製造方法 | |
JP2002353402A (ja) | 半導体装置およびその製造方法 | |
JP5769293B2 (ja) | 積層チップパッケージの製造方法 | |
US10651150B2 (en) | Multichip module including surface mounting part embedded therein | |
JP5228068B2 (ja) | 積層チップパッケージおよびその製造方法 | |
JP5154253B2 (ja) | 電子部品パッケージ | |
JP5389752B2 (ja) | 電子部品パッケージの製造方法 | |
CN101477980A (zh) | 具有减小尺寸的堆叠晶片水平封装 | |
JP4675945B2 (ja) | 半導体装置 | |
JP5241219B2 (ja) | 電子部品パッケージの製造方法、電子部品パッケージ用ウェハの製造方法ならびに電子部品パッケージ用基礎構造物の製造方法 | |
US10651374B2 (en) | Semiconductor device, and method for manufacturing the same | |
KR100743653B1 (ko) | 적층 반도체 패키지 및 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20091209 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120316 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120411 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120629 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130319 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130402 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160412 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |