CN105428340A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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Publication number
CN105428340A
CN105428340A CN201510147871.0A CN201510147871A CN105428340A CN 105428340 A CN105428340 A CN 105428340A CN 201510147871 A CN201510147871 A CN 201510147871A CN 105428340 A CN105428340 A CN 105428340A
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China
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mentioned
semiconductor chip
semiconductor
chip
wiring
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CN201510147871.0A
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细美英一
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Toshiba Corp
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Toshiba Corp
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

根据实施方式，提供一种具有第1半导体芯片和第2半导体芯片的半导体装置。第2半导体芯片搭载在第1半导体芯片的背面。第1半导体芯片具有基板、背面布线、多层布线、贯通电极和表面电极。背面布线设在基板的背面上。背面布线电连接着第2半导体芯片的端子。多层布线设在基板的表面上。贯通电极经由基板将背面布线及多层布线电连接。表面电极设在多层布线之上。表面电极电连接在多层布线上。

Description

半导体装置及半导体装置的制造方法
本申请基于2014年9月11日提出的日本专利申请第2014－185365号主张优先权，这里引用其全部内容。
技术领域
本发明涉及半导体装置及半导体装置的制造方法。
背景技术
在半导体装置中，为了提高安装密度，使多个半导体芯片层叠。即，将支撑基板贴合在半导体基板上而使半导体基板薄化，然后使支撑基板从半导体基板剥离。并且，使半导体基板单片化而成为半导体芯片，使多个半导体芯片层叠，得到半导体装置。此时，希望降低半导体装置的制造成本。
发明内容
本发明的目的是提供一种例如适合于降低半导体装置的制造成本的半导体装置及半导体装置的制造方法。
技术方案提供一种半导体装置，具备：第1半导体芯片；第2半导体芯片，搭载在上述第1半导体芯片的背面；上述第1半导体芯片具有：基板；背面布线，设在上述基板的背面，电连接着上述第2半导体芯片的端子；多层布线，设在上述基板的表面；贯通电极，经由上述基板将上述背面布线及上述多层布线电连接；以及表面电极，设在上述多层布线之上，电连接于上述多层布线。
此外，技术方案提供一种半导体装置的制造方法，具备如下步骤：在半导体基板的表面上形成多层布线；在上述多层布线之上形成电连接于上述多层布线的表面电极；使支撑基板贴合到上述半导体基板的表面侧，以将上述多层布线及上述表面电极覆盖；在贴合着上述支撑基板的状态下将上述半导体基板从背面侧进行薄化；从薄化后的上述半导体基板的背面贯通到表面地形成与上述多层布线电连接的贯通电极；在薄化后的上述半导体基板的上述背面形成背面布线，以与上述贯通电极电连接；在薄化后的上述半导体基板的背面搭载第1半导体芯片，以将上述第1半导体芯片的端子电连接于上述背面布线；从薄化后的上述半导体基板将上述支撑基板剥离；以及对薄化后的上述半导体基板进行单片化，得到在背面搭载有上述第1半导体芯片的第2半导体芯片。
根据技术方案，能够提供一种例如适合于降低半导体装置的制造成本的半导体装置及半导体装置的制造方法。
附图说明
图1是表示有关第1实施方式的半导体装置的结构的剖视图。
图2是表示有关第1实施方式的半导体装置的结构的框图。
图3是表示有关第1实施方式的半导体装置的制造方法的剖视图。
图4是表示有关第1实施方式的半导体装置的制造方法的剖视图。
图5是表示有关第1实施方式的半导体装置的制造方法的剖视图。
图6是表示有关第1实施方式的半导体装置的制造方法的剖视图。
图7是表示有关第2实施方式的半导体装置的结构的剖视图。
图8是表示有关第2实施方式的半导体装置的制造方法的剖视图。
图9是表示有关第2实施方式的半导体装置的制造方法的剖视图。
图10是表示有关第3实施方式的半导体装置的结构的剖视图。
图11是表示有关第3实施方式的半导体装置的结构的框图。
图12是表示有关第3实施方式的半导体装置的制造方法的剖视图。
图13是表示有关第3实施方式的半导体装置的制造方法的剖视图。
具体实施方式
根据实施方式，提供一种具有第1半导体芯片和第2半导体芯片的半导体装置。第2半导体芯片搭载在第1半导体芯片的背面上。第1半导体芯片具有基板、背面布线、多层布线、贯通电极和表面电极。背面布线设在基板的背面上。背面布线与第2半导体芯片的端子电连接。多层布线，设在基板的表面上。贯通电极经由基板将背面布线及多层布线电连接。表面电极设在多层布线之上。表面电极与多层布线电连接。
以下，参照附图，详细地说明有关实施方式的半导体装置。另外，并不通过这些实施方式限定本发明。
(第1实施方式)
使用图1及图2对有关第1实施方式的半导体装置100进行说明。图1是表示半导体装置100的结构的剖视图。图2是表示半导体装置100的结构的框图。
对于半导体装置100有时要求高密度安装。例如，将加速度传感器或地磁传感器等的传感器芯片搭载在便携设备中，其市场扩大。为了在便携设备的有限的空间中装入功能，对于包括传感器芯片等的半导体芯片在内的半导体装置的高密度安装的要求非常强。
在半导体装置100中，为了使安装密度提高而使多个半导体芯片层叠。此外，在半导体装置100中，作为实现高密度安装的手段，进行通过贯通电极(TSV：ThroughSiliconVia)的三维安装。
具体而言，半导体装置100如图1所示，具备半导体芯片10、半导体芯片20、金属线40、导体球50及模制树脂60。
半导体芯片10具有基板11、背面布线13、多层布线12、贯通电极14及表面电极15。基板11可以由半导体形成，例如可以由以硅为主成分的材料形成。
背面布线13配设在基板11的背面11b上。背面布线13与贯通电极14电连接，被从贯通电极14的上方引绕到背面11b上的规定的位置。例如，在从与背面11b垂直的方向透视时、在与半导体芯片20重叠的位置上配设有贯通电极14的情况下，背面布线13被引绕到不与半导体芯片20重叠的位置。在背面布线13上接合金属线40，经由金属线40电连接于半导体芯片20的端子22。背面布线13由例如以铜为主成分的材料形成。另外，虽然没有图示，但基板11的背面11b被用绝缘层覆盖，背面布线13配设在基板11的背面11b的绝缘层上。由此，背面布线13和基板11被电绝缘。
绝缘膜16将背面布线13部分地覆盖，并且将背面布线13中的要接合金属线40的区域的附近露出。例如，绝缘膜16在平面观察中将配设有半导体芯片20的区域覆盖。
多层布线12设在基板11的表面11a上。多层布线12包括多个布线层M1～M3和将它们联络的插头布线(未图示)。此外，在基板11的表面11a上，交替地反复层叠绝缘层DF1～DF4和布线层M1～M3而形成多层布线构造。各布线层M1～M3例如由以铝为主成分的材料形成。各绝缘层DF1～DF4由例如以氧化硅为主成分的材料形成。
贯通电极14从背面11b到表面11a地将基板11贯通。贯通电极14将背面布线13及多层布线12电连接。贯通电极14例如由以铜为主成分的材料形成。贯通电极14上的基板11的表面11a侧的端部能够连接到多层布线12的最下方的布线层M1上。另外，虽然没有图示，但在贯通电极14与基板11之间夹着绝缘层。由此，将贯通电极14和基板11电绝缘。
表面电极15设在多层布线12之上，电连接于多层布线12。例如，表面电极15可以配置到多层布线12的最上方的布线层(最上方的布线)M3之上。表面电极15可以由与多层布线12中的各布线层M1～M3的材料(例如铝)相比、与导体球50的材料(例如焊料)的接合性更好的材料形成。表面电极15例如也可以由以铜为主成分的材料形成，也可以由以镍/金合金为主成分的材料形成。
表面电极15具有与导体球50对应的平面尺寸及形状。表面电极15例如在平面观察中可以是圆形状(例如直径0.2mm的圆形状)，也可以是矩形状(例如包含在直径0.2mm的圆中的矩形状)。此外，表面电极15以考虑导体球50的尺寸而决定的配置间隔被配置。表面电极15例如以间距0.4mm的配置间隔被配置。
半导体芯片20搭载在半导体芯片10的背面10b上。例如，半导体芯片20以其表面20a朝向与半导体芯片10相反侧的朝向搭载在半导体芯片10的背面10b上。半导体芯片20的背面20b通过贴装树脂30粘接在半导体芯片10的背面10b(绝缘膜16的表面)上。半导体芯片20的平面尺寸比半导体芯片10的平面尺寸小。半导体芯片20在从与背面10b垂直的方向透视的情况下包含在半导体芯片10中。由此，在半导体芯片10中，能够将背面布线13引绕到在从与背面10b垂直的方向透视时不与半导体芯片20重叠的位置。即，能够经由金属线40将半导体芯片20的端子22电连接到背面布线13上。半导体芯片20具有例如包括基板及多层布线的芯片主体21。多层布线可以相对于基板设在表面20a侧。半导体芯片20的端子22可以为在多层布线的最上方的布线层形成的电极焊盘。
金属线40将半导体芯片20的端子22和半导体芯片10的背面布线13电连接。金属线40例如由以铜或金为主成分的材料形成。
导体球50接合在表面电极15上，作为外部电极发挥功能。例如当将半导体装置100安装到设置基板上时，导体球50作为与设置基板连接的电极而发挥功能。导体球50例如由焊料形成。
模制树脂60将半导体芯片10的背面10b侧的空间封闭。由此，模制树脂60将半导体芯片20及金属线40覆盖。模制树脂60例如由环氧类的树脂形成。
另外，半导体装置100也可以是省略了导体球50的结构。在此情况下，可以使表面电极15作为外部电极发挥功能。
在半导体装置100中，半导体芯片10及半导体芯片20可以为相互具有同样的功能的芯片。或者，半导体芯片10及半导体芯片20可以为具有相互不同且相互关联的功能的芯片。半导体芯片20例如是存储器芯片、逻辑芯片或传感器芯片。作为传感器，可以考虑加速度传感器、磁传感器、光传感器等。
在半导体芯片20是存储器芯片的情况下，半导体芯片10可以为包含控制存储器芯片的存储器控制器在内的控制器芯片。
在半导体芯片20是逻辑芯片的情况下，半导体芯片10可以为包括与逻辑芯片进行协调控制的协调控制处理器的控制器芯片。
在半导体芯片20是传感器芯片20i的情况下，半导体芯片10可以为包含将传感器芯片20i的信号进行处理的信号处理电路的控制器芯片10i。在此情况下，可以如图2所示那样构成半导体装置100。
传感器芯片20i包括例如加速度传感器或地磁传感器等。传感器芯片20i具有传感器模组20i1及端子22。传感器模组20i1构成为，检测规定的物理量。例如在传感器芯片20i是加速度传感器的情况下，传感器模组20i1包括膜片及压电电阻元件，将膜片的位置变化用压电电阻元件检测，将检测出的信号向端子22输出。例如在传感器芯片20i是地磁传感器的情况下，传感器模组20i1包括电流源及霍尔元件，在被从电流源供给了电流的状态下霍尔元件检测地磁的大小及朝向，将检测出的信号向端子22输出。
向端子22输出的信号经由金属线40被向控制器芯片10i的背面布线13传递。向背面布线13传递的信号经由贯通电极14被向多层布线12传递。被向多层布线12传递的信号经由多层布线12内的规定的布线被向多层布线12内的信号处理电路121传递。信号处理电路121将信号处理，变换为能够由外部(例如，连接半导体装置100的主机装置)识别的信号，向表面电极15传递。向表面电极15传递的信号经由导体球50被向外部输出。
接着，使用图3A～图6B对半导体装置100的制造方法进行说明。图3A～图3C、图4A～图4C、图5A～图5C、图6A、图6B是表示半导体装置100的制造方法的工序剖视图。
在图3A所示的工序中，准备半导体基板11i。半导体基板11i可以使用例如由以硅为主成分的材料形成的基板。在半导体基板11i的表面11ia上，形成包括多层布线12的多层布线构造。即，一边将绝缘层DF1～DF4和布线层M1～M3交替地反复层叠一边进行规定的图案化(参照图1)。此时，将具有与要形成表面电极15的区域对应的开口图案的抗蚀剂图案RP1作为掩模，进行蚀刻，直到最上方的布线层M3露出。由此，在最上方的绝缘层DF4上形成开口17，以使最上方的布线层M3上的要形成表面电极15的区域露出。各绝缘层DF1～DF4例如由以氧化硅为主成分的材料形成。各布线层M1～M3例如由以铝为主成分的材料形成。开口17在平面观察中，能够以与要形成的表面电极15对应的形状形成。开口17例如在平面观察可以做成包含表面电极15的形状。
在图3B所示的工序中，在多层布线12之上形成表面电极15。此时，形成表面电极15以使其与多层布线12电连接。例如，表面电极15形成在通过最上方的布线层M3中的开口17而露出的区域之上(参照图1)。表面电极15由与导体球50的材料(例如焊料)的接合性良好的材料形成。表面电极15例如由以铜为主成分的材料或以镍/金合金为主成分的材料形成。例如，以抗蚀剂图案RP1为掩模进行镀层，形成表面电极15。并且，将抗蚀剂图案RP1除去。
表面电极15由与导体球50对应的平面尺寸及形状形成。表面电极15例如在平面观察中既可以以圆形状(例如直径0.2mm的圆形状)形成，也可以以矩形状(例如包含在直径0.2mm的圆中的矩形状)形成。此外，表面电极15以考虑导体球50的尺寸而决定的配置间隔形成。表面电极15例如以间距0.4mm的配置间隔形成。
在图3C所示的工序中，在半导体基板11i的表面11ia侧贴合支撑基板92，以将多层布线12及表面电极15覆盖。例如，在多层布线12及表面电极15之上涂敷粘接剂91，在粘接剂91之上配置支撑基板92。支撑基板92可以使用例如由以玻璃或硅为主成分的材料形成的基板。支撑基板92具有与稳定地支承半导体基板11i所需要的支承刚性相对应的厚度。
在图4A所示的工序中，在贴合着支撑基板92的状态下将半导体基板11i从背面11ib侧进行薄化。例如，将使背面11ib为下侧的半导体基板11i(参照图3C)配置到研磨垫板上，将半导体基板11i从上侧推压，用旋转的研磨垫板将半导体基板11i研磨。由此，能够得到薄化的半导体基板11j。
在图4B所示的工序中，将用来埋入贯通电极14的孔14a形成在半导体基板11j的要形成贯通电极14的区域中。例如，使半导体基板11j反转，使用具有与要形成贯通电极14的区域对应的开口图案的抗蚀剂图案RP2作为掩模，通过RIE等对半导体基板11j进行蚀刻，在半导体基板11j上形成孔14a。并且，将抗蚀剂图案RP2除去。
在图4C所示的工序中，为了将之后要形成的贯通电极14及背面布线13从半导体基板11k进行电绝缘，在孔14a及半导体基板11k的背面11kb上形成绝缘层(未图示)。然后，形成贯通电极14及背面布线13。例如，使用具有与要形成背面布线13的区域对应的开口图案的抗蚀剂图案RP3作为掩模进行镀层，在孔14a内形成贯通电极14，在半导体基板11k的背面11kb上形成背面布线13。此外，在半导体基板11k的背面11kb及背面布线13之上堆积绝缘膜16，将具有与要接合金属线40的区域对应的开口图案的抗蚀剂图案RP4作为掩模，对绝缘膜16i进行蚀刻。由此，能够形成将背面布线13部分地覆盖并具有使背面布线13的表面上的要接合金属线40的区域有选择地露出的开口的绝缘膜16(例如阻焊剂)。也可以对背面布线13的表面实施Ni/Au或Ni/Pd/Au等的表面处理。由此，能够实现下个工序中的连接性提高。
在图5A所示的工序中，在薄化的半导体基板11k的背面11kb上搭载半导体芯片20，进行引线接合连接。例如，在绝缘膜16的表面上的要配设半导体芯片20的区域涂敷贴装树脂30，在贴装树脂30之上配置半导体芯片20。并且，将金属线40的一端接合到背面布线13上，将金属线40的另一端接合到半导体芯片20的端子22上。半导体芯片20例如是存储器芯片、逻辑芯片或传感器芯片。半导体芯片20例如具有基板及多层布线，半导体芯片20的端子22可以为形成在最上方的布线层的电极焊盘。
另外，半导体基板11k的背面11kb包括要在后述的图6B的工序中将半导体基板11k单片化时分别要成为半导体芯片10的多个区域R1、R2。因此，在图5A所示的工序中，能够将半导体芯片20按照要成为半导体芯片10的各区域R1、R2搭载。此时，可以按照要成为半导体芯片10的各区域R1、R2，使作为半导体芯片20而具有不同功能者混合存在。
在图5B所示的工序中，将半导体基板11k的背面11kb侧用模制树脂60封固。在模制树脂60中，例如能够使用环氧类树脂等的绝缘性的热固化性树脂。
在图5C所示的工序中，将支撑基板92从半导体基板11k剥离。此时，也可以在多层布线12及/或表面电极15上附着粘接剂91后，用有机溶剂通过湿式蚀刻除去。由此，使表面电极15的表面露出。
在图6A所示的工序中，在表面电极15上接合导体球50。导体球50例如可以使用由焊料形成的结构。
在图6B所示的工序中，通过切割道将在图6A中用虚线表示的部分除去，将半导体基板11k单片化。由此，得到在背面10b上分别搭载有半导体芯片20的多个半导体芯片10。
另外，在半导体装置100中使表面电极15作为外部电极发挥功能的情况下，不再需要导体球50。在此情况下，图6A所示的工序也可以省略。
这里，考虑假设在半导体装置100中、不是在半导体芯片10的背面10b而是在表面10a侧(即，多层布线12的最上方的布线层M3中的焊盘)上搭载半导体芯片20的情况。在此情况下，在半导体装置100的制造方法中，在图4C所示的工序完成后，为了使包括多层布线12在内的多层布线构造的表面(即，最上方的绝缘层DF4的表面)露出而需要将支撑基板92从半导体基板11j剥离。并且，需要在使薄化的半导体基板11j反转而使支撑基板92粘接在半导体基板11j的背面上之后进行与图5A～图5B对应的工序，用与图5C的工序对应的工序将支撑基板92从半导体基板11k再次剥离。由此，需要进行多次花费工夫的支撑基板92的贴合、剥离，为了制造半导体装置100而需要的工序数增加，所以半导体装置100的制造成本有可能增大。此外，由于需要使薄化的半导体基板11j以不被支撑基板92支承的状态反转并对支撑基板92再次粘接，所以需要用来操作薄化后的半导体基板11j的特殊的设备。从该观点看，半导体装置100的制造成本也有可能增大。
相对于此，在第1实施方式中，在半导体装置100中，半导体芯片20的端子22经由金属线40而与背面布线13电连接。背面布线13经由贯通电极14而与多层布线12电连接。多层布线12与表面电极15电连接。使表面电极15或连接在表面电极15上的导体球50作为外部电极发挥功能。由此，能够在实现半导体芯片20用于与外部进行信号的交换的结构的同时将半导体芯片20搭载到半导体芯片10的背面上。因此，在半导体装置100的制造方法中能够将支撑基板92的贴合、剥离的次数抑制为1次，也不再需要用来将薄化的半导体基板11j操作的特殊的设备，所以能够降低半导体装置100的制造成本。即，根据第1实施方式，能够提供适合于降低半导体装置100的制造成本的半导体装置100。
此外，在第1实施方式中，在半导体装置100中，半导体芯片20的平面尺寸比半导体芯片10的平面尺寸小。半导体芯片2在从垂直于背面10b的方向透视的情况下包含在半导体芯片10中。由此，在半导体芯片10中，能够将背面布线13引绕到当从垂直于背面10b的方向透视时不与半导体芯片20重叠的位置。即，能够经由金属线40将半导体芯片20的端子22与背面布线13电连接。
此外，在第1实施方式中，在半导体装置100的制造方法中，贯通电极14的形成、背面布线13的形成及半导体芯片20的搭载是一边维持将支撑基板92贴合在半导体基板11k的表面11ka上的状态一边进行的。由此，在半导体装置100的制造方法中能够将支撑基板92的贴合、剥离的次数抑制为1次，也不再需要用来将薄化的半导体基板11j操作的特殊的设备，所以能够降低半导体装置100的制造成本。此外，由于能够缩短半导体装置100的制造所需要的时间，能够削减粘接剂及支撑基板的材料费，所以从该观点看，也能够降低半导体装置100的制造成本。
此外，在第1实施方式中，在半导体装置100的制造方法中，将导体球50接合到表面电极15上。表面电极15能够通过与多层布线12中的各布线层M1～M3的材料(例如铝)相比、与导体球50的材料(例如焊料)的接合性更好的材料(例如铜)形成。由此，能够使半导体装置100向设置基板的安装容易化。
此外，在半导体装置100中，在不是半导体芯片10的背面10b而是表面10a上搭载半导体芯片20的情况下，难以对相同的半导体基板11k按照作为半导体芯片10的区域而搭载具有不同功能的半导体芯片20。即，如果想要搭载具有不同的功能的半导体芯片20，则需要进行多层布线12的再设计，所以半导体装置100的制造成本有可能增大。
相对于此，在第1实施方式中，在半导体装置100的制造方法中，对于相同的半导体基板11k，能够按照作为半导体芯片10的区域而搭载具有不同功能的半导体芯片20。例如，在将多层布线12的布局图案变更的情况下，必须将相邻的电路的布局图案也变更等，产生进行多层布线12中的电路的再设计的需要。与此相比，在将背面布线13的布局图案变更的情况下，不需要多层布线12中的电路的布局图案的变更，不需要多层布线12中的电路的再设计。即，由于能够通过背面布线13采用适合于不同功能的布局图案，所以能够不进行多层布线12的再设计而实现与具有不同功能的半导体芯片20对应的布局结构的变更。结果，能够降低半导体装置100的制造成本。
另外，虽然没有图示，但在半导体装置100中，半导体芯片10也可以是将多层布线12省略的结构。在此情况下，表面电极15也可以连接在贯通电极14的表面11a侧的端部上。此外，在半导体装置100的制造方法中，也可以省略用图3A所示的工序形成多层布线12的处理，用图3B所示的工序在要形成贯通电极14的区域形成表面电极15。
(第2实施方式)
接着，对有关第2实施方式的半导体装置200进行说明。以下，以与第1实施方式不同的部分为中心进行说明。
在第1实施方式中，将半导体芯片20引线接合连接在半导体芯片10的背面10b上，而在第2实施方式中，将半导体芯片220倒装片连接到半导体芯片10的背面10b上。
具体而言，半导体装置200如图7所示，代替半导体芯片20及金属线40(参照图1)而具备半导体芯片220及导体凸块240。
半导体芯片220搭载在半导体芯片10的背面10b上。例如，半导体芯片220以其表面20a朝向半导体芯片10的朝向搭载在半导体芯片10的背面10b上。
半导体芯片220的端子222可以为形成在多层布线中的最上方的布线层中的电极焊盘。半导体芯片220的端子222可以具有与导体凸块240对应的大小及形状。半导体芯片220的端子222可以分配到表面20a上的周边区域中。此时，半导体芯片220的平面尺寸比半导体芯片10的平面尺寸小。半导体芯片220在从垂直于背面10b的方向透视的情况下包含在半导体芯片10中。由此，在半导体芯片10中，当从垂直于背面10b的方向透视时，能够将背面布线13延伸到半导体芯片220的表面20a上的与周边区域对应的位置(即，在图7中是与接合着导体凸块240的端子222对应的位置)。即，能够经由导体凸块240、将半导体芯片220的端子222电连接到背面布线13上。
导体凸块240将半导体芯片220的端子222和半导体芯片10的背面布线13电连接。导体凸块240例如由焊料形成。
此外，半导体装置200的制造方法如图8A～图9B所示，在以下的方面与第1实施方式不同。图8A～图8C、图9A、图9B是表示半导体装置200的制造方法的工序剖视图。
在半导体装置200的制造方法中，在进行了图3A～图3C、图4A～图4C所示的工序后，进行图8A～图8C、图9A、图9B所示的工序。
在图8A所示的工序中，在薄化的半导体基板11k的背面11kb上搭载半导体芯片220，进行倒装片连接。例如，在背面布线13的表面上的要配设半导体芯片220的端子222的区域，将导体凸块240接合，在导体凸块240之上配置半导体芯片220。导体凸块240例如使用通过焊料形成的结构。
此时，将半导体芯片220及导体凸块240的位置匹配，将半导体芯片220的端子222接合到导体凸块240。半导体芯片220例如是存储器芯片、逻辑芯片或传感器芯片。
另外，半导体芯片220可以按照半导体基板11k的背面11kb上的要成为半导体芯片10的区域R1、R2进行搭载。此时，可以按照要成为半导体芯片10的区域R1、R2，使作为半导体芯片220而具备不同功能者混合存在。
在图8B所示的工序中，将半导体基板11k的背面11kb侧用模制树脂60封固。在模制树脂60中，例如可以使用环氧类树脂等的绝缘性的热固化性树脂。此时，半导体芯片220和绝缘膜16的间隙也被用模制树脂60封固。
在图8C所示的工序中，将支撑基板92从半导体基板11k剥离。此时，若粘接剂91附着在多层布线12及表面电极15上，则可以用有机溶剂通过湿式蚀刻除去。由此，使表面电极15的表面露出。
在图9A所示的工序中，在表面电极15上接合导体球50。导体球50例如可以使用由焊料形成的结构。
在图9B所示的工序中，通过切割道将在图6A中用虚线表示的部分除去而将半导体基板11k单片化。由此，得到在背面10b上分别搭载有半导体芯片220的多个半导体芯片10。
如以上那样，在第2实施方式中，在半导体装置200中，半导体芯片220的端子222经由导体凸块240而与背面布线13电连接。背面布线13经由贯通电极14而与多层布线12电连接。多层布线12与表面电极15电连接。使表面电极15或连接在表面电极15上的导体球50作为外部电极发挥功能。由此，能够在实现半导体芯片220用来与外部进行信号的交换的结构的同时将半导体芯片220搭载到半导体芯片10的背面。因此，在半导体装置200的制造方法中，能够将支撑基板92的贴合、剥离的次数抑制为1次，不需要用来操作薄化的半导体基板11j的特殊的设备，所以能够减少半导体装置200的制造成本。即，通过第2实施方式，也能够提供适合于降低半导体装置200的制造成本的半导体装置200。
(第3实施方式)
接着，对有关第3实施方式的半导体装置300进行说明。以下，以与第1实施方式不同的部分为中心进行说明。
在第1实施方式中，将1个半导体芯片20搭载在半导体芯片10的背面10b上，而在第3实施方式中，将多个半导体芯片20、320搭载到半导体芯片310的背面10b上。
具体而言，半导体装置300如图10所示，代替半导体芯片10(参照图1)而具备半导体芯片310，还具备半导体芯片320、金属线340及导体球350。
半导体芯片310代替多层布线12(参照图1)而具有多层布线312，还具有背面布线313、贯通电极314及表面电极315。
背面布线313配置在基板11的背面11b上的与半导体芯片320对应的位置。背面布线313与贯通电极314电连接，被从贯通电极314之上引绕到背面11b上的规定的位置。例如，当从垂直于背面11b的方向透视时在与半导体芯片320重叠的位置配设有贯通电极314的情况下，背面布线313被引绕到不与半导体芯片320重叠的位置。在背面布线313上接合金属线340。经由金属线340将半导体芯片320的端子322电连接在背面布线313上。背面布线313例如由以铜为主成分的材料形成。
多层布线312设在基板11的表面11a上。多层布线312包括多个布线层M1～M3和将它们联络的插头布线(未图示)。此时，多层布线312除了与半导体芯片20对应的布线以外，还包括与半导体芯片320对应的布线。此外，在基板11的表面11a上，交替地反复层叠绝缘层DF1～DF4和布线层M1～M3而形成多层布线构造。各布线层M1～M3例如由以铝为主成分的材料形成。各绝缘层DF1～DF4例如由以氧化硅为主成分的材料形成。
贯通电极314将基板11从背面11b贯通到表面11a。贯通电极314将背面布线313及多层布线312电连接。贯通电极314由例如以铜为主成分的材料形成。贯通电极314的基板11的表面11a侧的端部能够连接到多层布线312中的最下方的布线层M1。
表面电极315设在多层布线312之上，与多层布线312电连接。例如，表面电极315能够配置到多层布线312中的最上方的布线层M3之上。表面电极315能够由与多层布线312中的各布线层M1～M3的材料(例如铝)相比、与导体球350的材料(例如焊料)的接合性更好的材料形成。表面电极315例如既可以由以铜为主成分的材料形成，也可以由以镍/金合金为主成分的材料形成。
表面电极315具有与导体球350对应的平面尺寸及形状。表面电极315例如在平面观察中可以是圆形状(例如直径0.2mm的圆形状)，也可以是矩形状(例如包含在直径0.2mm的圆中的矩形状)。此外，表面电极315以考虑导体球350的尺寸而决定的配置间隔配置。表面电极315例如以间距0.4mm的配置间隔配置。
半导体芯片320沿着半导体芯片310的背面10b而与半导体芯片20排列而配设，并且搭载在半导体芯片310的背面10b上。例如，半导体芯片320以其表面320a朝向与半导体芯片310相反侧的朝向、搭载在半导体芯片310的背面10b上。半导体芯片20的背面20b通过贴装树脂30粘接在半导体芯片310的背面10b(绝缘膜16的表面)上。半导体芯片320的平面尺寸比半导体芯片310的平面尺寸小。半导体芯片320在从垂直于背面10b的方向透视的情况下包含在半导体芯片310中。由此，在半导体芯片310中，能够将背面布线313引绕到当从垂直于背面10b的方向透视时不与半导体芯片320重叠的位置。即，能够经由金属线340将半导体芯片320的端子322电连接到背面布线313。半导体芯片320例如具有包括基板及多层布线的芯片主体321。多层布线能够相对于基板设在表面320a侧。半导体芯片320的端子322可以为形成在多层布线中的最上方的布线层中的电极焊盘。
金属线340将半导体芯片320的端子322与半导体芯片310的背面布线313电连接。金属线340例如由以铜或金为主成分的材料形成。
导体球350接合在表面电极315上，作为外部电极发挥功能。例如，当半导体装置300被安装到设置基板上时，导体球350作为连接到设置基板上的电极发挥功能。导体球350例如由焊料形成。
在半导体装置300中，半导体芯片310、半导体芯片20及半导体芯片320可以具有相互同样的功能。或者，半导体芯片310、半导体芯片20及半导体芯片320可以为一部分具有同样的功能，另一部分具有不同的功能。或者，半导体芯片310、半导体芯片20及半导体芯片320可以具有相互不同且相互关联的功能。半导体芯片20及半导体芯片320分别例如是存储器芯片、逻辑芯片或传感器芯片。作为传感器，可以考虑加速度传感器、磁传感器、光传感器等。
在半导体芯片20是传感器芯片20i、半导体芯片320是存储器芯片320i的情况下，半导体芯片310可以为包括对传感器芯片20i的信号进行处理的信号处理电路和控制存储器芯片320i的存储器控制器的控制器芯片310i。在此情况下，可以如图11所示那样构成半导体装置300。
传感器芯片20i包括例如加速度传感器或地磁传感器等。传感器芯片20i具有传感器模组20i1及端子22。传感器模组20i1构成为，检测规定的物理量。例如在传感器芯片20i是加速度传感器的情况下，传感器模组20i1包括膜片及压电电阻元件，将膜片的位置变化用压电电阻元件检测，将检测出的信号向端子22输出。例如在传感器芯片20i是地磁传感器的情况下，传感器模组20i1包括电流源及霍尔元件，在被从电流源供给了电流的状态下霍尔元件检测地磁的大小及朝向，将检测出的信号向端子22输出。
向端子22输出的信号经由金属线40被向控制器芯片310i的背面布线13传递。向背面布线13传递的信号经由贯通电极14被向多层布线312传递。向多层布线312传递的信号经由多层布线312内的规定的布线被向多层布线312内的信号处理电路121传递。信号处理电路121将信号处理，变换为能够由外部(例如连接半导体装置100的主机装置)识别的信号，向主控制器323供给。
主控制器323在判断为应将由传感器芯片20i检测出的物理量的当前值输出的情况下，将从信号处理电路121接受到的信号向表面电极15传递。向表面电极15传递的信号经由导体球50被向外部输出。
主控制器323在判断为应将由传感器芯片20i检测出的物理量的当前值作为履历信息储存的情况下，将从信号处理电路121接受到的信号向存储器控制器322供给。存储器控制器322将与表示物理量的当前值的信号对应的数据经由贯通电极314、背面布线313、金属线340及端子322向存储器模组320i1的存储单元写入。
主控制器323在判断为应对储存的履历信息进行处理而求出例如物理量的趋势信息的情况下，将指示该消息的指令向存储器控制器322供给。存储器控制器322按照该指令，将履历信息的数据从存储器模组320i1经由端子322、金属线340、背面布线313、贯通电极314读出，将读出的履历信息的数据向主控制器323供给。存储器控制器322基于履历信息的数据，求出物理量的趋势信息，将与求出的趋势信息对应的信号向表面电极315传递。向表面电极315传递的信号经由导体球350被向外部输出。
此外，半导体装置300的制造方法如图12A～图13B所示，在以下的方面与第1实施方式不同。图12A～图12C、图13A、图13B是表示半导体装置300的制造方法的工序剖视图。
在半导体装置300的制造方法中，在进行图3A～图3C、图4A～图4C所示的工序后，进行图12A～图12C、图13A、图13B所示的工序。
在图12A所示的工序中，在薄化的半导体基板11k的背面11kb上搭载半导体芯片20及半导体芯片320，分别进行引线接合连接。
例如，在绝缘膜16的表面上的要配设半导体芯片20的区域涂敷贴装树脂30，在贴装树脂30之上配置半导体芯片20。接着，将金属线40的一端接合到背面布线13上，将金属线40的另一端接合到半导体芯片20的端子22上。半导体芯片20例如是存储器芯片、逻辑芯片或传感器芯片。半导体芯片20例如具有基板及多层布线，半导体芯片20的端子22可以为形成在最上方的布线层中的电极焊盘。
此外，在绝缘膜16的表面中的要配设半导体芯片320的区域涂敷贴装树脂30，在贴装树脂30之上配置半导体芯片320。并且，将金属线340的一端接合到背面布线313上，将金属线340的另一端接合到半导体芯片320的端子322上。半导体芯片320例如是存储器芯片、逻辑芯片或传感器芯片。半导体芯片320例如具有基板及多层布线，半导体芯片320的端子322可以为形成在最上方的布线层中的电极焊盘。
另外，半导体芯片20及半导体芯片320可以按照半导体基板11k的背面11kb上的要成为半导体芯片310的区域R301、R302进行搭载。此时，可以按照要成为半导体芯片310的区域R301、R302，使对于半导体芯片20及半导体芯片320而言分别具有不同功能者混合存在。
在图12B所示的工序中，将半导体基板11k的背面11kb侧用模制树脂60封固。在模制树脂60中，例如可以使用环氧类树脂等的绝缘性的热固化性树脂。
在图12C所示的工序中，将支撑基板92从半导体基板11k剥离。此时，若在多层布线12及表面电极15、315上附着粘接剂91，则可以通过有机溶剂以湿式蚀刻除去。由此，使表面电极15及表面电极315各自的表面露出。
在图13A所示的工序中，在表面电极15上接合导体球50，在表面电极315上接合导体球350。导体球50及导体球350分别例如能够使用由焊料形成的结构。
在图13B所示的工序中，通过切割道将在图13A中用虚线表示的部分除去，使半导体基板11k单片化。由此，得到在背面10b上分别搭载有半导体芯片20及半导体芯片320的多个半导体芯片310。
如以上这样，在第3实施方式中，在半导体装置300中，在半导体芯片310的背面10b上搭载有多个半导体芯片20、320。由此，半导体芯片310、半导体芯片20及半导体芯片320可以具有相互不同且相互关联的功能。由此，能够容易地实现半导体装置300的高性能化。
另外，多个半导体芯片20、320的向半导体芯片310的背面10b的搭载也可以代替引线接合连接而通过倒装片连接进行。例如，半导体芯片20的端子22也可以经由导体凸块而电连接在背面布线13上。半导体芯片320的端子322也可以经由导体凸块而电连接在背面布线313上。
说明了本发明的一些实施方式，但这些实施方式是作为例子提示的，并不是要限定发明的范围。这些新的实施方式能够以其他各种各样的形态实施，在不脱离发明的主旨的范围内能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围及主旨中，并且包含在权利要求书所记载的发明和其等价的范围中。

Claims (20)

1.一种半导体装置，其特征在于，
具备：
第1半导体芯片；以及
第2半导体芯片，搭载在上述第1半导体芯片的背面；
上述第1半导体芯片具有：
基板；
背面布线，设在上述基板的背面，电连接着上述第2半导体芯片的端子；
多层布线，设在上述基板的表面；
贯通电极，经由上述基板将上述背面布线及上述多层布线电连接；以及
表面电极，设在上述多层布线之上，电连接于上述多层布线。
2.如权利要求1所述的半导体装置，其特征在于，
上述第2半导体芯片以设有多层布线的表面朝向与上述第1半导体芯片相反侧的朝向、搭载在上述第1半导体芯片的背面。
3.如权利要求1所述的半导体装置，其特征在于，
上述第2半导体芯片的端子经由金属线电连接于上述第1半导体芯片的上述背面布线。
4.如权利要求1所述的半导体装置，其特征在于，
上述第2半导体芯片的端子经由导体凸块电连接于上述第1半导体芯片的上述背面布线。
5.如权利要求1所述的半导体装置，其特征在于，
还具备接合于上述表面电极的导体球。
6.如权利要求1所述的半导体装置，其特征在于，
上述第2半导体芯片在从垂直于上述背面的方向进行透视的情况下包含在上述第1半导体芯片中。
7.如权利要求1所述的半导体装置，其特征在于，
上述第1半导体芯片及上述第2半导体芯片具有相互关联的功能。
8.如权利要求7所述的半导体装置，其特征在于，
上述第2半导体芯片是传感器芯片；
上述第1半导体芯片是包括对上述传感器芯片的信号进行处理的信号处理电路的控制器芯片。
9.如权利要求1所述的半导体装置，其特征在于，
还具备搭载在上述第1半导体芯片的上述背面并具有与上述第2半导体芯片不同的功能的第3半导体芯片。
10.如权利要求9所述的半导体装置，其特征在于，
上述第2半导体芯片及上述第3半导体芯片分别以设有多层布线的表面朝向与上述第1半导体芯片相反侧的朝向、搭载在上述第1半导体芯片的背面。
11.如权利要求9所述的半导体装置，其特征在于，
上述第2半导体芯片的端子和上述第3半导体芯片的端子分别经由金属线电连接于上述第1半导体芯片的上述背面布线。
12.如权利要求9所述的半导体装置，其特征在于，
上述第2半导体芯片的端子和上述第3半导体芯片的端子分别经由导体凸块电连接于上述第1半导体芯片的上述背面布线。
13.如权利要求9所述的半导体装置，其特征在于，
上述第2半导体芯片及上述第3半导体芯片分别在从垂直于上述背面的方向进行透视的情况下包含在上述第1半导体芯片中。
14.如权利要求9所述的半导体装置，其特征在于，
上述第1半导体芯片、上述第2半导体芯片及上述第3半导体芯片具有相互关联的功能。
15.如权利要求14所述的半导体装置，其特征在于，
上述第2半导体芯片是传感器芯片；
上述第3半导体芯片是存储器芯片；
上述第1半导体芯片是包括对上述传感器芯片的信号进行处理的信号处理电路和控制上述存储器芯片的存储器控制器的控制器芯片。
16.一种半导体装置的制造方法，其特征在于，具备如下步骤：
在半导体基板的表面上形成多层布线；
在上述多层布线之上形成电连接于上述多层布线的表面电极；
使支撑基板贴合到上述半导体基板的表面侧，以将上述多层布线及上述表面电极覆盖；
在贴合着上述支撑基板的状态下将上述半导体基板从背面侧进行薄化；
从薄化后的上述半导体基板的背面贯通到表面地形成与上述多层布线电连接的贯通电极；
在薄化后的上述半导体基板的上述背面形成背面布线，以与上述贯通电极电连接；
在薄化后的上述半导体基板的背面搭载第1半导体芯片，以将上述第1半导体芯片的端子电连接于上述背面布线；
从薄化后的上述半导体基板将上述支撑基板剥离；以及
对薄化后的上述半导体基板进行单片化，得到在背面搭载有上述第1半导体芯片的第2半导体芯片。
17.如权利要求16所述的半导体装置的制造方法，其特征在于，
上述多层布线的形成包括：形成将上述多层布线中的最上方的布线露出的开口的步骤；
上述表面电极的形成包括：在上述最上方的布线的从上述开口露出的区域之上形成上述表面电极的步骤。
18.如权利要求16所述的半导体装置的制造方法，其特征在于，
上述贯通电极的形成、上述背面布线的形成及上述第1半导体芯片的搭载是在维持在上述半导体基板的表面上贴合着上述支撑基板的状态的同时进行的。
19.如权利要求16所述的半导体装置的制造方法，其特征在于，
还具备在上述表面电极上接合导体球的步骤。
20.如权利要求16所述的半导体装置的制造方法，其特征在于，
还具备：将第3半导体芯片搭载到薄化后的上述半导体基板的背面的步骤，上述第3半导体芯片具有电连接于上述背面布线的端子，并且上述第3半导体芯片具有与上述第1半导体芯片不同的功能。
CN201510147871.0A 2014-09-11 2015-03-31 半导体装置及半导体装置的制造方法 Pending CN105428340A (zh)

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