TW201611219A - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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Publication number
TW201611219A
TW201611219A TW104107049A TW104107049A TW201611219A TW 201611219 A TW201611219 A TW 201611219A TW 104107049 A TW104107049 A TW 104107049A TW 104107049 A TW104107049 A TW 104107049A TW 201611219 A TW201611219 A TW 201611219A
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Taiwan
Prior art keywords
semiconductor wafer
semiconductor
back surface
wiring
substrate
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TW104107049A
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English (en)
Inventor
Eiichi Hosomi
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Toshiba Kk
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Publication of TW201611219A publication Critical patent/TW201611219A/zh

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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

本發明係一種半導體裝置及半導體裝置之製造方法，如根據實施形態，加以提供具有第1半導體晶片與第2半導體晶片之半導體裝置。第2半導體晶片係加以搭載於第1半導體晶片之背面。第1半導體晶片係具有基板與背面配線與多層配線與貫通電極與表面電極。背面配線係加以設置於基板的背面。背面配線係加以電性連接第2半導體晶片之端子。多層配線係加以設置於基板的表面。貫通電極係藉由基板，而電性連接背面配線及多層配線。表面電極加以設置於多層配線上。表面電極係加以電性連接於多層配線。

Description

半導體裝置及半導體裝置之製造方法 關連申請之引用
本申請係對於經由在2014年9月11日所申請之日本國專利申請第2014-185365號之優先權的利益為基礎，且尋求其利益，而其內容全體則經由引用而加以包含於此。
本實施形態係總體關於半導體裝置及半導體裝置之製造方法。
在半導體裝置中，為了使安裝密度提升，而使複數之半導體晶片層積。即，使支持基板貼合於半導體基板，將半導體基板薄化，之後，從半導體基板，使支持基板剝離。並且，使半導體基板個片化而作為半導體晶片，使複數之半導體晶片層積而得到半導體裝置。此時，降低半導體裝置之製造成本者為佳。
實施形態係例如，其目的為提供：適合於降低半導體 裝置之製造成本之半導體裝置，及半導體裝置之製造方法者。
實施形態係提供：具備第1半導體晶片，和加以搭載於前述第1半導體晶片的背面之第2半導體晶片；前述第1半導體晶片係具有：基板，和加以設置於前述基板的背面，加以電性連接前述第2半導體晶片的端子之背面配線，和加以設置於前述基板的表面之多層配線，和藉由前述基板，電性連接前述背面配線及前述多層配線之貫通電極，和加以設置於前述多層配線上，加以電性連接於前述多層配線之表面電極之半導體裝置。
另外，實施形態係提供：具備形成多層配線於半導體基板表面者，和將加以電性連接於前述多層配線之表面電極，形成於前述多層配線上者，和呈被覆前述多層配線及前述表面電極地，貼合支持基板於前述半導體基板之表面側者，和在加以貼合有前述支持基板之狀態，從背面側薄化前述半導體基板者，和從前述加以薄化之半導體基板之背面貫通至表面， 而形成加以電性連接於前述多層配線之貫通電極者，和呈加以電性連接於前述貫通電極地，形成背面配線於前述加以薄化之半導體基板之前述背面者，和第1半導體晶片之端子則呈加以電性連接於前述背面配線地，搭載前述第1半導體晶片於前述加以薄化之半導體基板之背面者，和從前述加以薄化之半導體基板，剝離前述支持基板者，和個片化前述加以薄化之半導體基板，前述第1半導體晶片則加以搭載於背面而得到第2半導體晶片者之半導體裝置之製造方法。
如根據實施形態，例如，可提供：適合於降低半導體裝置之製造成本之半導體裝置，及半導體裝置之製造方法者。
10，20，220，310，320‧‧‧半導體晶片
10i‧‧‧控制器晶片
11‧‧‧基板
11i，11k‧‧‧半導體基板
12，312‧‧‧多層配線
13，313‧‧‧背面配線
14，314‧‧‧貫通電極
15，315‧‧‧表面電極
16‧‧‧絕緣膜
20i‧‧‧感測器晶片
20i1‧‧‧感測器模組
40，340‧‧‧金屬導線
50，350‧‧‧導體球
60‧‧‧塑模樹脂
91‧‧‧接著劑
92‧‧‧支持基板
121‧‧‧信號處理電路
100，200，300‧‧‧半導體裝置
DF1~DF4‧‧‧絕緣層
M1~M3‧‧‧配線層
圖1係顯示有關第1實施形態之半導體裝置之構成的剖面圖。
圖2係顯示有關第1實施形態之半導體裝置之構成的方塊圖。
圖3係顯示有關第1實施形態之半導體裝置之製造方法的剖面圖。
圖4係顯示有關第1實施形態之半導體裝置之製造方法的剖面圖。
圖5係顯示有關第1實施形態之半導體裝置之製造方法的剖面圖。
圖6係顯示有關第1實施形態之半導體裝置之製造方法的剖面圖。
圖7係顯示有關第2實施形態之半導體裝置之構成的剖面圖。
圖8係顯示有關第2實施形態之半導體裝置之製造方法的剖面圖。
圖9係顯示有關第2實施形態之半導體裝置之製造方法的剖面圖。
圖10係顯示有關第3實施形態之半導體裝置之構成的剖面圖。
圖11係顯示有關第3實施形態之半導體裝置之構成的方塊圖。
圖12係顯示有關第3實施形態之半導體裝置之製造方法的剖面圖。
圖13係顯示有關第3實施形態之半導體裝置之製造方法的剖面圖。
實施例
如根據實施形態，加以提供具有第1半導體晶片與第2半導體晶片之半導體裝置。第2半導體晶片係加以搭載於第1半導體晶片之背面。第1半導體晶片係具有基板與 背面配線與多層配線與貫通電極與表面電極。背面配線係加以設置於基板的背面。背面配線係加以電性連接第2半導體晶片之端子。多層配線係加以設置於基板的表面。貫通電極係藉由基板，而電性連接背面配線及多層配線。表面電極係加以設置於多層配線上。表面電極係加以電性連接於多層配線。
於以下，參照添加圖面，詳細地說明有關實施形態之半導體裝置。然而，並非經由此等之實施形態而加以限定本發明者。
(第1實施形態)
對於有關第1實施形態之半導體裝置100，使用圖1及圖2而加以說明。圖1係顯示半導體裝置100之構成的剖面圖。圖2係顯示半導體裝置100之構成的方塊圖。
對於半導體裝置100係有要求高密度安裝者。例如，加速度感測器或磁場感測器等之感測器晶片則成為呈加以搭載於攜帶機器，而其市場則擴大。為了放入機能於攜帶機器之所限制之空間，對於包含感測器晶片等之半導體晶片的半導體裝置之高密度安裝之要求係非常強。
在半導體裝置100中，為了使安裝密度提升，而使複數之半導體晶片層積。另外，在半導體裝置100中，作為實現高密度安裝之手段，進行經由貫通電極(TSV：Through Silicon Via)之三維安裝。
具體而言，半導體裝置100係如圖1所示，具備半導 體晶片10，半導體晶片20，金屬導線40，導體球50，及塑模樹脂60。
半導體晶片10係具有基板11，背面配線13，多層配線12，貫通電極14，及表面電極15。基板11係未由半導體加以形成亦可，例如，可由將矽作為主成分之材料而形成者。
背面配線13係加以配置於基板11之背面11b上。背面配線13係加以電性連接於貫通電極14，從貫通電極14上加以導引至在背面11b之特定的位置。例如，從垂直於背面11b之方向透視時，加以配置貫通電極14於與半導體晶片20重疊之位置的情況，背面配線13係導引至未與半導體晶片20重疊之位置。對於背面配線13係加以接合有金屬導線40，藉由金屬導線40而加以電性連接半導體晶片20之端子22。背面配線13係例如，由將銅作為主成分之材料而加以形成。然而，雖未圖示，但由絕緣層而加以被覆基板11之背面11b，而背面配線13係加以配置於基板11之背面11b的絕緣層上。經由此等，加以電性絕緣背面配線13與基板11。
絕緣膜16係部分性地被覆背面配線13之同時，露出欲加以接合在背面配線13之金屬導線40之範圍的附近。例如，絕緣膜16係在平面視中，被覆加以配置有半導體晶片20之範圍。
多層配線12係加以設置於基板11的表面11a。多層配線12係包含複數之配線層M1~M3與連絡此等之插塞 配線(未圖示)。另外，對於基板11的表面11a，交互反覆加以層積絕緣層DF1~DF4與配線層M1~M3而加以形成多層配線構造。各配線層M1~M3係例如，由將鋁作為主成分之材料而加以形成。各絕緣層DF1~DF4係例如，由將氧化矽作為主成分之材料而加以形成。
貫通電極14係從背面11b貫通基板11至表面11a。貫通電極14係電性連接背面配線13及多層配線12。貫通電極14係例如，由將銅作為主成分之材料而加以形成。在貫通電極14之基板11的表面11a側的端部係可連接於在多層配線12之最下的配線層M1者。然而，雖未圖示，但對於貫通電極14與基板11之間係介入存在有絕緣層。經由此等，加以電性絕緣貫通電極14與基板11。
表面電極15係加以設置於多層配線12上，加以電性連接於多層配線12。例如，表面電極15係可配置於在多層配線12之最上的配線層(最上的配線)M3上者。表面電極15係可由較在多層配線12之各配線層M1~M3的材料(例如，鋁)，與導體球50之材料(例如，焊錫)的接合性為良好之材料而形成者。表面電極15係例如，由將銅作為主成分之材料而加以形成亦可，而亦可由將鎳/金合金作為主成分之材料而加以形成。
表面電極15係具有對應於導體球50之平面尺寸及形狀。表面電極15係例如，在平面視中，亦可為圓形狀(例如，直徑0.2mm之圓形狀)，而為矩形狀(例如，包含於直徑0.2mm的圓之矩形狀)。另外，表面電極15 係以考慮導體球50之尺寸所決定之配置間隔而加以配置。表面電極15係例如，由間隙0.4mm之配置間隔而加以配置。
半導體晶片20係加以搭載於半導體晶片10之背面10b。例如，半導體晶片20係在其表面20a則朝向與半導體晶片10之相反側的方向，加以搭載於半導體晶片10之背面10b。半導體晶片20之背面20b係經由安裝樹脂30而加以接著於半導體晶片10之背面10b(絕緣膜16之表面)。半導體晶片20之平面尺寸係較半導體晶片10之平面尺寸為小。半導體晶片20係在從垂直於背面10b之方向透視之情況，包含於半導體晶片10。經由此，在半導體晶片10中，在從垂直於背面10b之方向透視時，至未與半導體晶片20重疊之位置，可導引背面配線13者。即，可藉由金屬導線40而將半導體晶片20的端子22，電性連接於背面配線13者。半導體晶片20係例如，具有包含基板及多層配線之晶片主體21。多層配線係對於基板而言可設置於表面20a側者。半導體晶片20之端子22係可作為加以形成於在多層配線之最上的配線層之電極墊片者。
金屬導線40係電性連接半導體晶片20之端子22與半導體晶片10之背面配線13。金屬導線40係例如，由將銅或金作為主成分之材料而加以形成。
導體球50係加以接合於表面電極15，而作為外部電極而發揮機能。例如，半導體裝置100則在加以安裝於安 裝基板時，導體球50係作為加以連接於安裝基板之電極而發揮機能。導體球50係例如，由焊錫而加以形成。
塑模樹脂60係封閉半導體晶片10之背面10b側的空間。經由此，塑模樹脂60係被覆半導體晶片20及金屬導線40。塑模樹脂60係例如，由環氧系樹脂加以形成。
然而，半導體裝置100係亦可為省略導體球50之構成。此情況，可使表面電極15作為外部電極而發揮機能者。
在半導體裝置100中，半導體晶片10及半導體晶片20係可作為具有相互同樣的機能者。或者，半導體晶片10及半導體晶片20係可作為具有相互不同，且相互關連之機能者。半導體晶片20係例如，為記憶體晶片，邏輯晶片，或者感測器晶片。作為感測器，係考量有加速器感測器，磁性感測器，光感測器等。
半導體晶片20為記憶體晶片之情況，半導體晶片10係可作為包含控制記憶體晶片之記憶體控制器之控制器晶片者。
半導體晶片20為邏輯晶片之情況，半導體晶片10係可作為包含與邏輯晶片進行協調控制之協調控制處理器之控制器晶片者。
半導體晶片20為感測器晶片20i之情況，半導體晶片10係可作為包含處理感測器晶片20i之信號的信號處理電路之控制器晶片10i。此情況，如圖2所示，可加以構成半導體裝置100。
感測器晶片20i係例如，包含加速度感測器或磁場感測器等。感測器晶片20i係具有感測器模組20i1及端子22。感測器模組20i1係呈檢測特定之物理量地加以構成。例如，感測器晶片20i為加速度感測器之情況，感測器模組20i1係包含隔膜及壓電電阻，由壓電電阻而檢測隔膜的位置變化，將所檢測到之信號輸出至端子22。例如，感測器晶片20i為磁場感測器之情況，感測器模組20i1係包含電流源及電洞元件，在自電流源加以供給電流之狀態，電洞元件則檢測磁場之大小或方向，將所檢測到之信號輸出至端子22。
加以輸出至端子22之信號係經由金屬導線40而加以傳達至控制器晶片10i之背面配線13。加以傳達至背面配線13之信號係經由貫通電極14而加以傳達至多層配線12。加以傳達至多層配線12之信號係經由多層配線12內之特定的配線而加以傳達至多層配線12內之信號處理電路121。信號處理電路121係處理信號而變換為可在外部(例如，加以連接有半導體裝置100之主機裝置)辨識之信號，而傳達至表面電極15。加以傳達至表面電極15之信號係藉由導體球50而輸出至外部。
接著，對於半導體裝置100之製造方法，使用圖3A~圖6B而加以說明。圖3A~圖3C、圖4A~圖4C、圖5A~圖5C、圖6A、圖6B係顯示半導體裝置100之製造方法的工程剖面圖。
在圖3A所示之工程中，準備半導體基板11i。半導 體基板11i係例如，可使用由將矽作為主成分的材料加以形成之構成者。於半導體基板11i之表面11ia，形成包含多層配線12之多層配線構造。即，交互反覆層積、絕緣層DF1~DF4與配線層M1~M3之同時，進行特定的圖案化(參照圖1)。此時，將具有對應於欲形成表面電極15之範圍的開口圖案之光阻劑圖案RP1作為光罩，至最上的配線層M3露出為止，進行蝕刻。經由此，呈加以露出欲形成在最上的配線層M3之表面電極15之範圍地，形成開口17於最上的絕緣層DF4。各絕緣層DF1~DF4係例如，由將氧化矽作為主成分之材料而形成。各配線層M1~M3係例如，由將鋁作為主成分之材料而形成。開口17係在平面視中，可以對應於欲加以形成之表面電極15之形狀而形成者。開口17係例如，在平面視中，可作為包含表面電極15之形狀者。
在圖3B所示之工程中，於多層配線12上形成表面電極15。此時，呈加以電性連接於多層配線12地，形成表面電極15。例如，表面電極15係加以形成於經由最上的配線層M3之開口17所露出之範圍上(參照圖1)。表面電極15係由與導體球50之材料(例如，焊錫)之接合性良好的材料而形成。表面電極15係例如，由將銅作為主成分之材料，或由將鎳/金合金作為主成分之材料而加以形成。例如，將光阻劑圖案RP1作為光罩而進行電鍍，形成表面電極15。並且，除去光阻劑圖案RP1。
表面電極15係由對應於導體球50之平面尺寸及形狀 而形成。表面電極15係例如，在平面視中，亦可為圓形狀(例如，直徑0.2mm之圓形狀)，而為矩形狀(例如，包含於直徑0.2mm的圓之矩形狀)亦可。另外，表面電極15係以考慮導體球50之尺寸所決定之配置間隔而形成。表面電極15係例如，由間隙0.4mm之配置間隔而形成。
在圖3C之工程中，呈被覆多層配線12及表面電極15地，於半導體基板11i的表面11ia側，貼合支持基板92。例如，塗上接著劑91於多層配線12及表面電極15上，再配置支持基板92於接著劑91上。支持基板92係例如，可使用由將玻璃或矽作為主成分的材料加以形成之構成者。支持基板92係具有對應對於安定地支持半導體基板11i必要之支持剛性的厚度。
在圖4A所示之工程中，在加以貼合支持基板92之狀態，從背面11ib側薄化半導體基板11i。例如，將背面11ib作為於下側之半導體基板11i(參照圖3C)，配置於研磨墊上，從上側壓住半導體基板11i，以旋轉之研磨墊而研磨半導體基板11i。經由此而得到加以薄化之半導體基板11j。
在圖4B的工程中，將為了埋入貫通電極14的孔14a，形成於欲加以形成在半導體基板11j之貫通電極14的範圍。例如，反轉半導體基板11j，將具有對應於加以形成貫通電極14之範圍的開口圖案的光阻劑圖案RP2，使用於光罩，經由RIE等而對於半導體基板11j而言進行 蝕刻，於半導體基板11j形成孔14a。並且，除去光阻劑圖案RP2。
在圖4C所示的工程中，為了從半導體基板11k電性絕緣之後欲形成之貫通電極14及背面配線13，於孔14a及半導體基板11k的背面11kb，形成絕緣層(未圖示)。之後，形成貫通電極14及背面配線13。例如，將具有對應於加以形成背面配線13之範圍的開口圖案的光阻劑圖案RP3，使用於光罩，進行電鍍，於孔14a內形成貫通電極14，於半導體基板11k之背面11kb上形成背面配線13。另外，於半導體基板11k之背面11kb及背面配線13上，堆積絕緣膜16，將具有對應於欲加以接合金屬導線40之範圍的開口圖案之光阻劑圖案RP4，作為光罩而對於絕緣膜16i而言，進行蝕刻。經由此，部分地被覆背面配線13之同時，可形成具有選擇性地露出欲加以接合在背面配線13表面之金屬導線40之範圍的開口之絕緣膜16(例如，抗焊劑)者。對於背面配線13表面，係施以Ni/Au或Ni/Pd/Au等之表面處理亦可。經由此，加以謀求在接下來的工程之連接性提升。
在圖5A所示之工程中，搭載半導體晶片20於加以薄化之半導體基板11k之背面11kb，進行導線接合連接。例如，於欲配置在絕緣膜16表面之半導體晶片20的範圍，塗上安裝樹脂30，於安裝樹脂30上配置半導體晶片20。並且，將金屬導線40之一端接合於背面配線13，將金屬導線40之另一端接合於半導體晶片20之端子22。 半導體晶片20係例如，為記憶體晶片，邏輯晶片，或者感測器晶片。半導體晶片20係例如，具有基板及多層配線，半導體晶片20之端子22係可作為加以形成於最上之配線層之電極墊片者。
然而，半導體基板11k之背面11kb係在後述之圖6B的工程中，將半導體基板11k加以個片化時，包含各欲成為半導體晶片10之複數的範圍R1，R2。因此，在圖5A所示之工程中，可將半導體晶片20，搭載於欲成為半導體晶片10之各範圍R1，R2者。此時，於欲成為半導體晶片10之各範圍R1，R2，可使作為半導體晶片20而具有不同機能之構成混入存在者。
在圖5B所示之工程中，以塑模樹脂60而封閉半導體基板11k之背面11kb側。對於塑模樹脂60係例如，可使用環氧系樹脂等之絕緣性的熱硬化性樹脂者。
在圖5C之工程中，從半導體基板11k剝離支持基板92。此時，如於多層配線12及/或表面電極15附著有接著劑91時，由有機溶劑，以濕蝕刻而除去亦可。經由此，加以露出有表面電極15的表面。
在圖6A所示之工程中，於表面電極15上結合導體球50。導體球50係例如，可使用由焊錫而加以形成之構成者。
在圖6B所示之工程中，經由切割而除去以虛線示於圖6A之部分，將半導體基板11k個片化。經由此，得到各加以搭載半導體晶片20於背面10b之複數之半導體晶 片10。
然而，在半導體裝置100中，使表面電極15作為外部電極而發揮機能之情況，導體球50係成為不需要。此情況，亦可省略圖6A所示之工程。
在此，假設在半導體裝置100中，對於並非在半導體晶片10之背面10b，而於表面10a側(即，在多層配線12之最上的配線層M3的墊片)，加以搭載半導體晶片20而考量。此情況，在半導體裝置100之製造方法中，在圖4C所示之工程結束之後，為了使包含多層配線12之多層配線構造表面(即，最上之絕緣層DF4表面)露出，而必須從半導體基板11j剝離支持基板92。並且，使加以薄化之半導體基板11j反轉，而使支持基板92接著於半導體基板11j之背面之後，進行相當於圖5A~圖5B之工程，必須在相當於圖5C之工程的工程，從半導體基板11k再次剝離支持基板92。經由此，必須複數次進行繁雜之支持基板92的貼合‧剝離，而為了製造半導體裝置100所需之工程數則增加之故，有著半導體裝置100之製造成本增大之可能性。另外，因必須使加以薄化之半導體基板11j，在未加以支持於支持基板92之狀態而反轉，再次接著於支持基板92之故，為了裝卸加以薄化之半導體基板11j之特殊的設備則成為必要。從此觀點，亦有半導體裝置100之製造成本增大之可能性。
對於此，在第1實施形態中，在半導體裝置100中，半導體晶片20的端子22係藉由金屬導線40而加以電性 連接於背面配線13。背面配線13係經由貫通電極14而加以電性連接於多層配線12。多層配線12係加以電性連接於表面電極15。使表面電極15或加以連接於表面電極15之導體球50，作為外部電極而發揮機能。經由此等，半導體晶片20則實現為了進行與外部信號之交換之構成同時，可將半導體晶片20搭載於半導體晶片10之背面者。因此，在半導體裝置100之製造方法中，可將支持基板92之貼合‧剝離的次數抑制為1次，而成為亦無須為了裝卸加以薄化之半導體基板11j之特殊的設備之故，可降低半導體裝置100之製造成本。即，如根據第1實施形態，可提供適合降低半導體裝置100之製造成本的半導體裝置100。
另外，在第1實施形態中，在半導體裝置100中，半導體晶片20之平面尺寸係較半導體晶片10之平面尺寸為小。半導體晶片20係在從垂直於背面10b之方向透視之情況，包含於半導體晶片10。經由此，在半導體晶片10中，在從垂直於背面10b之方向透視時，至未與半導體晶片20重疊之位置，可導引背面配線13者。即，可藉由金屬導線40而將半導體晶片20的端子22，電性連接於背面配線13者。
另外，在第1實施形態中，在半導體裝置100之製造方法中，貫通電極14之形成，背面配線13之形成，及半導體晶片20之搭載係維持加以貼合支持基板92於半導體基板11k之表面11ka之狀態同時而加以進行。經由此， 在半導體裝置100之製造方法中，可將支持基板92之貼合‧剝離的次數抑制為1次，而成為亦無須為了裝卸加以薄化之半導體基板11j之特殊的設備之故，可降低半導體裝置100之製造成本。另外，可縮短對於半導體裝置100之製造所需之時間，而可削減接著劑及支持基板之材料費之故，從此觀點，亦可降低半導體裝置100之製造成本。
另外，在第1實施形態中，在半導體裝置100之製造方法中，於表面電極15上接合導體球50。表面電極15係可由較在多層配線12之各配線層M1~M3的材料(例如，鋁)，與導體球50之材料(例如，焊錫)的接合性為良好之材料(例如，銅)而形成者。經由此，可容易化對於半導體裝置100之安置基板的安裝。
另外，在半導體裝置100中，並非在半導體晶片10之背面10b而於表面10a，加以搭載半導體晶片20之情況，對於相同的半導體基板11k而言，於各成為半導體晶片10之範圍，搭載具有不同機能之半導體晶片20之情況則為困難。即，當作為欲搭載具有不同機能之半導體晶片20時，多層配線12之再設計則成為必要之故，半導體裝置100之製造成本則有增大之可能性。
對於此，在第1實施形態中，在半導體裝置100之製造方法中，對於相同的半導體基板11k而言，於各成為半導體晶片10之範圍，可搭載具有不同機能之半導體晶片20者。例如，變更多層配線12之佈局圖案之情況，產生有亦必須變更鄰接電路之佈局圖案等，進行在多層配線 12之電路的再設計之必要。比較於此，變更背面配線13之佈局圖案之情況，無須在多層配線12之電路的佈局圖案變更，而無須在多層配線12之電路的再設計。即，可在背面配線13取得適合不同機能之佈局圖案之故，而無須進行多層配線12之再設計而實現對應於具有不同機能之半導體晶片20的佈局構成之變更。此結果，可降低半導體裝置100之製造成本。
然而，雖無圖示，但在半導體裝置100中，半導體晶片10係亦可為省略多層配線12之構成。此情況，表面電極15則亦可加以連接於在貫通電極14之表面11a側的端部。另外，在半導體裝置100之製造方法中，在圖3A所示之工程，加以省略形成多層配線12之處理，而在圖3B所示之工程，於欲加以形成貫通電極14之範圍，加以形成表面電極15亦可。
(第2實施形態)
接著，對於有關第2實施形態之半導體裝置200加以說明。在以下，將與第1實施形態不同的部分為中心加以說明。
在第1實施形態中，將半導體晶片20，導線接合連接於半導體晶片10之背面10b，但在第2實施形態中，將半導體晶片220，覆晶連接於半導體晶片10之背面10b。
具體而言，半導體裝置200係如圖7所示，取代於半 導體晶片20及金屬導線40(參照圖1)而具備半導體晶片220及導體凸塊240。
半導體晶片220係加以搭載於半導體晶片10之背面10b。例如，半導體晶片220係在其表面20a則朝向半導體晶片10之方向，加以搭載於半導體晶片10之背面10b。
半導體晶片220之端子222係可作為加以形成於在多層配線之最上的配線層之電極墊片者。半導體晶片220之端子222係可作為具有對應於導體凸塊240之尺寸及形狀之構成者。半導體晶片220之端子222係可加以配置於在表面20a之周邊範圍。此時，半導體晶片220之平面尺寸係較半導體晶片10之平面尺寸為小。半導體晶片220係在從垂直於背面10b之方向透視之情況，包含於半導體晶片10。經由此，在半導體晶片10中，從垂直於背面10b之方向透視時，至對應於在半導體晶片220之表面20a之周邊範圍的位置(即，在圖7為對應於於加以接合導體凸塊240之端子222之位置)為止，可延伸背面配線13者。即，可藉由導體凸塊240而將半導體晶片220的端子222，電性連接於背面配線13者。
導體凸塊240係電性連接半導體晶片220之端子222與半導體晶片10之背面配線13。導體凸塊240係例如，由焊錫而加以形成。
另外，半導體裝置200之製造方法則如圖8A~圖9B所示地，在接下來的點與第1實施形態不同。圖8A~圖 8C，圖9A，圖9B係顯示半導體裝置200之製造方法的工程剖面圖。
在半導體裝置200之製造方法中，在進行圖3A~圖3C，圖4A~圖4C所示之工程之後，進行圖8A~圖8C，圖9A，圖9B所示之工程。
在圖8A所示之工程中，搭載半導體晶片220於加以薄化之半導體基板11k之背面11kb，進行覆晶連接。例如，於欲配置在背面配線13表面之半導體晶片220的端子222之範圍，接合導體凸塊240，再於導體凸塊240上配置半導體晶片220。導體凸塊240係例如，可使用由焊錫而加以形成之構成者。
此時，配合半導體晶片220及導體凸塊240之位置，將半導體晶片220的端子222接合於導體凸塊240。半導體晶片220係例如，為記憶體晶片，邏輯晶片，或者感測器晶片。
然而，半導體晶片220係可搭載於欲成為在半導體基板11k之背面11kb之半導體晶片10之各範圍R1，R2者。此時，於欲成為半導體晶片10之各範圍R1，R2，可使作為半導體晶片220而具有不同機能之構成混入存在者。
在圖8B所示之工程中，以塑模樹脂60而封閉半導體基板11k之背面11kb側。對於塑模樹脂60係例如，可使用環氧系樹脂等之絕緣性的熱硬化性樹脂者。此時，半導體晶片220與絕緣膜16之間隙亦由塑模樹脂60加以封 閉。
在圖8C之工程中，從半導體基板11k剝離支持基板92。此時，如於多層配線12及表面電極15附著有接著劑91時，由有機溶劑，以濕蝕刻而除去亦可。經由此，加以露出有表面電極15的表面。
在圖9A所示之工程中，於表面電極15上接合導體球50。導體球50係例如，可使用由焊錫而加以形成之構成者。
在圖9B所示之工程中，經由切割而除去以虛線示於圖6A之部分，將半導體基板11k個片化。經由此，得到各加以搭載半導體晶片220於背面10b之複數之半導體晶片10。
如以上，在第2實施形態中，在半導體裝置200中，半導體晶片220的端子222係藉由導體凸塊240而加以電性連接於背面配線13。背面配線13係經由貫通電極14而加以電性連接於多層配線12。多層配線12係加以電性連接於表面電極15。使表面電極15或加以連接於表面電極15之導體球50，作為外部電極而發揮機能。經由此等，半導體晶片220則實現為了進行與外部信號之交換之構成同時，可將半導體晶片220搭載於半導體晶片10之背面者。因此，在半導體裝置200之製造方法中，可將支持基板92之貼合‧剝離的次數抑制為1次，而成為亦無須為了裝卸加以薄化之半導體基板11j之特殊的設備之故，可降低半導體裝置200之製造成本。即，如根據第2 實施形態，亦可提供適合降低半導體裝置200之製造成本的半導體裝置200。
(第3實施形態)
接著，對於有關第3實施形態之半導體裝置300加以說明。在以下，將與第1實施形態不同的部分為中心加以說明。
在第1實施形態中，將1個半導體晶片20，搭載於半導體晶片10之背面10b，但在第3實施形態中，將複數之半導體晶片20，320，搭載於半導體晶片310之背面10b。
具體而言，半導體裝置300係如圖10所示，取代於半導體晶片10(參照圖1)而具備半導體晶片310，而更具備半導體晶片320，金屬導線340，及導體球350。
半導體晶片310係取代於多層配線12(參照圖1)而具有多層配線312，而更具有背面配線313，貫通電極314，及表面電極315。
背面配線313係加以配置於在基板11之背面11b上的半導體晶片320之位置。背面配線313係加以電性連接於貫通電極314，從貫通電極314上加以導引至在背面11b之特定的位置。例如，從垂直於背面11b之方向透視時，加以配置貫通電極314於與半導體晶片320重疊之位置的情況，背面配線313係導引至未與半導體晶片320重疊之位置。對於背面配線313係加以接合金屬導線340。 藉由金屬導線340而加以電性連接半導體晶片320之端子322於背面配線313。背面配線313係例如，由將銅作為主成分之材料而加以形成。
多層配線312係加以設置於基板11的表面11a。多層配線312係包含複數之配線層M1~M3與連絡此等之插塞配線(未圖示)。此時，多層配線312係加上於對應於半導體晶片20之配線而包含對應於半導體晶片320之配線。另外，對於基板11的表面11a上，交互反覆加以層積絕緣層DF1~DF4與配線層M1~M3而加以形成多層配線構造。各配線層M1~M3係例如，由將鋁作為主成分之材料而加以形成。各絕緣層DF1~DF4係例如，由將氧化矽作為主成分之材料而加以形成。
貫通電極314係從背面11b貫通基板11至表面11a。貫通電極314係電性連接背面配線313及多層配線312。貫通電極314係例如，由將銅作為主成分之材料而加以形成。在貫通電極314之基板11的表面11a側的端部係可連接於在多層配線312之最下的配線層M1者。
表面電極315係加以設置於多層配線312上，加以電性連接於多層配線312。例如，表面電極315係可配置於在多層配線312之最上的配線層M3上者。表面電極315係可由較在多層配線312之各配線層M1~M3的材料(例如，鋁)，與導體球350之材料(例如，焊錫)的接合性為良好之材料而形成者。表面電極315係例如，由將銅作為主成分之材料而加以形成亦可，而亦可由將鎳/金合金 作為主成分之材料而加以形成。
表面電極315係具有對應於導體球350之平面尺寸及形狀。表面電極315係例如，在平面視中，亦可為圓形狀(例如，直徑0.2mm之圓形狀)，而為矩形狀(例如，包含於直徑0.2mm的圓之矩形狀)。另外，表面電極315係以考慮導體球350之尺寸所決定之配置間隔而加以配置。表面電極315係例如，由間隙0.4mm之配置間隔而加以配置。
半導體晶片320係沿著半導體晶片310之背面10b而呈與半導體晶片20排列地加以配置之同時，加以搭載於半導體晶片310之背面10b。例如，半導體晶片320係在其表面320a則朝向與半導體晶片310之相反側的方向，加以搭載於半導體晶片310之背面10b。半導體晶片20之背面20b係經由安裝樹脂30而加以接著於半導體晶片310之背面10b(絕緣膜16之表面)。半導體晶片320之平面尺寸係較半導體晶片310之平面尺寸為小。半導體晶片320係在從垂直於背面10b之方向透視之情況，包含於半導體晶片310。經由此，在半導體晶片310中，在從垂直於背面10b之方向透視時，至未與半導體晶片320重疊之位置，可導引背面配線313者。即，可藉由金屬導線340而將半導體晶片320的端子322，電性連接於背面配線313者。半導體晶片320係例如，具有包含基板及多層配線之晶片主體321。多層配線係對於基板而言可設置於表面320a側者。半導體晶片320之端子322係可作為加 以形成於在多層配線之最上的配線層之電極墊片者。
金屬導線340係電性連接半導體晶片320之端子322與半導體晶片310之背面配線313。金屬導線340係例如，由將銅或金作為主成分之材料而加以形成。
導體球350係加以接合於表面電極315，而作為外部電極而發揮機能。例如，半導體裝置300則在加以安裝於安置基板時，導體球350係作為加以連接於安置基板之電極而發揮機能。導體球350係例如，由焊錫而加以形成。
在半導體裝置300中，半導體晶片310，半導體晶片20及半導體晶片320係可作為具有相互同樣的機能者。或者，半導體晶片310，半導體晶片20及半導體晶片320係可作為一部分具有同樣機能，而其他一部分作為具有不同機能之構成者。或者，半導體晶片310，半導體晶片20，及半導體晶片320係可作為具有相互不同，且相互關連之機能之構成者。各半導體晶片20及半導體晶片320係例如，為記憶體晶片，邏輯晶片，或者感測器晶片。作為感測器，係考量有加速器感測器，磁性感測器，光感測器等。
半導體晶片20則為感測器晶片20i，而半導體晶片320則為記憶體晶片320i之情況，半導體晶片310係可作為包含處理感測器晶片20i之信號的信號處理電路與控制記憶體晶片320i之記憶體控制器之控制器晶片310i者。此情況，如圖11所示，可加以構成半導體裝置300。
感測器晶片20i係例如，包含加速度感測器或磁場感 測器等。感測器晶片20i係具有感測器模組20i1及端子22。感測器模組20i1係呈檢測特定之物理量地加以構成。例如，感測器晶片20i為加速度感測器之情況，感測器模組20i1係包含隔膜及壓電電阻，由壓電電阻而檢測隔膜的位置變化，將所檢測到之信號輸出至端子22。例如，感測器晶片20i為磁場感測器之情況，感測器模組20i1係包含電流源及電洞元件，在自電流源加以供給電流之狀態，電洞元件則檢測磁場之大小或方向，將所檢測到之信號輸出至端子22。
加以輸出至端子22之信號係經由金屬導線40而加以傳達至控制器晶片310i之背面配線13。加以傳達至背面配線13之信號係經由貫通電極14而加以傳達至多層配線312。加以傳達至多層配線312之信號係經由多層配線312內之特定的配線而加以傳達至多層配線312內之信號處理電路121。信號處理電路121係處理信號而變換為可在外部(例如，加以連接有半導體裝置100之主機裝置)辨識之信號，而傳達至主控制器323。
主控制器323係判斷為欲輸出由感測器晶片20i所檢測之物理量的現在值之情況，將自信號處理電路121接受到之信號，傳達至表面電極15。加以傳達至表面電極15之信號係藉由導體球50而輸出至外部。
主控制器323係判斷為將由感測器晶片20i所檢測之物理量的現在值作為履歷資訊而欲蓄積之情況，將自信號處理電路121接受到之信號，傳達至記憶體控制器322。 記憶體控制器322係將因應顯示物理量的現在值之信號的資料，經由貫通電極314，背面配線313，金屬導線340，及端子322而寫入至在記憶體模組320i1之記憶體單元。
記憶體控制器323係處理所蓄積之履歷資訊而例如，判斷為欲求得物理量之趨勢資訊之情況，將指示其內容之指令，供給至記憶體控制器322。記憶體控制器322係依照其指令，將履歷資訊的資料，從記憶體模組320i1，經由端子322，金屬導線340，背面配線313，貫通電極314而讀出，再將所讀出之履歷資訊的資料供給至主控制器323。記憶體控制器322係依據履歷資訊的資料而求得物理量之趨勢資訊，而將因應所求得之趨勢資訊的信號，傳達至表面電極315。加以傳達至表面電極315之信號係藉由導體球350而輸出至外部。
另外，半導體裝置300之製造方法則如圖12A~圖13B所示地，在接下來的點與第1實施形態不同。圖12A~圖12C，圖13A，圖13B係顯示半導體裝置300之製造方法的工程剖面圖。
在半導體裝置300之製造方法中，在進行圖3A~圖3C，圖4A~圖4C所示之工程之後，進行圖12A~圖12C，圖13A，圖13B所示之工程。
在圖12A所示之工程中，搭載半導體晶片20及半導體晶片320於加以薄化之半導體基板11k之背面11kb，各進行導線接合連接。
例如，於欲配置在絕緣膜16表面之半導體晶片20的範圍，塗上安裝樹脂30，於安裝樹脂30上配置半導體晶片20。並且，將金屬導線40之一端接合於背面配線13，將金屬導線40之另一端接合於半導體晶片20之端子22。半導體晶片20係例如，為記憶體晶片，邏輯晶片，或者感測器晶片。半導體晶片20係例如，具有基板及多層配線，半導體晶片20之端子22係可作為加以形成於最上之配線層之電極墊片者。
例如，於欲配置在絕緣膜16表面之半導體晶片320的範圍，塗上安裝樹脂30，於安裝樹脂30上配置半導體晶片320。並且，將金屬導線340之一端接合於背面配線313，將金屬導線340之另一端接合於半導體晶片320之端子322。半導體晶片320係例如，為記憶體晶片，邏輯晶片，或者感測器晶片。半導體晶片320係例如，具有基板及多層配線，半導體晶片320之端子322係可作為加以形成於最上之配線層之電極墊片者。
然而，半導體晶片20及半導體晶片320係可搭載於欲成為在半導體基板11k之背面11kb之半導體晶片310之各範圍R301，R302者。此時，於欲成為半導體晶片310之各範圍R301，R302，可使作為半導體晶片20及半導體晶片320而具有不同機能之構成混入存在者。
在圖12B所示之工程中，以塑模樹脂60而封閉半導體基板11k之背面11kb側。對於塑模樹脂60係例如，可使用環氧系樹脂等之絕緣性的熱硬化性樹脂者。
在圖12C之工程中，從半導體基板11k剝離支持基板92。此時，如於多層配線12及表面電極15，315附著有接著劑91時，由有機溶劑，以濕蝕刻而除去亦可。經由此，表面電極15及表面電極315之各表面則加以露出。
在圖13A所示之工程中，於表面電極15上接合導體球50，於表面電極315上接合導體球350。各導體球50及導體球350係例如，可使用由焊錫而加以形成之構成者。
在圖13B所示之工程中，經由切割而除去以虛線示於圖13A之部分，將半導體基板11k個片化。經由此，得到各加以搭載半導體晶片20及半導體晶片320於背面10b之複數之半導體晶片310。
如以上，在第3實施形態中，在半導體裝置300中，於半導體晶片310之背面10b，加以搭載複數之半導體晶片20，320。經由此，半導體晶片310，半導體晶片20，及半導體晶片320係可作為具有相互不同，且相互關連之機能之構成者。經由此，可容易地實現半導體裝置300之高機能化。
然而，對於複數之半導體晶片20，320之半導體晶片310之背面10b的搭載係取代導線接合連接，而由覆晶連接進行亦可。例如，半導體晶片20之端子22係藉由導體凸塊而加以電性連接於背面配線13亦可。半導體晶片320之端子322係藉由導體凸塊而加以電性連接於背面配線313亦可。
雖已說明過本發明之幾個實施形態，但此等實施形態係作為例而提示之構成，未特意限定發明之範圍者。此等新穎之實施形態係可由其他種種形態而加以實施，在不脫離發明的內容範圍，可進行種種省略，置換，變更者。此等實施形態或其變形係與包含於發明範圍或內容之同時，包含於記載於申請專利申請範圍之發明與其均等的範圍。
10，20‧‧‧半導體晶片
10a、11a、20a‧‧‧表面
10b、11b、20b‧‧‧背面
11‧‧‧基板
12‧‧‧多層配線
13‧‧‧背面配線
14‧‧‧貫通電極
15‧‧‧表面電極
16‧‧‧絕緣膜
21‧‧‧晶片主體
22‧‧‧端子
30‧‧‧安裝樹脂
40‧‧‧金屬導線
50‧‧‧導體球
60‧‧‧塑模樹脂
100‧‧‧半導體裝置
DF1~DF4‧‧‧絕緣層
M1~M3‧‧‧配線層

Claims (20)

  1. 一種半導體裝置，其特徵為具備：第1半導體晶片，和加以搭載於前述第1半導體晶片的背面之第2半導體晶片；前述第1半導體晶片係具有：基板，和加以設置於前述基板的背面，加以電性連接前述第2半導體晶片的端子之背面配線，和加以設置於前述基板的表面之多層配線，和藉由前述基板，電性連接前述背面配線及前述多層配線之貫通電極，和加以設置於前述多層配線上，加以電性連接於前述多層配線之表面電極者。
  2. 如申請專利範圍第1項記載之半導體裝置，其中，前述第2半導體晶片係設置有多層配線之表面則在朝向與前述第1半導體晶片相反側之方向，加以搭載於前述第1半導體晶片的背面者。
  3. 如申請專利範圍第1項記載之半導體裝置，其中，前述第2半導體晶片的端子係藉由金屬導線而加以電性連接於前述第1半導體晶片之前述背面配線者。
  4. 如申請專利範圍第1項記載之半導體裝置，其中，前述第2半導體晶片的端子係藉由導體凸塊而加以電性連接於前述第1半導體晶片之前述背面配線者。
  5. 如申請專利範圍第1項記載之半導體裝置，其中，更具備加以接合於前述表面電極之導體球者。
  6. 如申請專利範圍第1項記載之半導體裝置，其中，前述第2半導體晶片係於從垂直於前述背面之方向透視之情況，包含於前述第1半導體晶片。
  7. 如申請專利範圍第1項記載之半導體裝置，其中，前述第1半導體晶片及前述第2半導體晶片係具有相互關連之機能者。
  8. 如申請專利範圍第7項記載之半導體裝置，其中，前述第2半導體晶片係感測器晶片，前述第1半導體晶片係包含處理前述感測器晶片之信號的信號處理電路之控制器晶片。
  9. 如申請專利範圍第1項記載之半導體裝置，其中，更具備加以搭載於前述第1半導體晶片之前述背面，具有與前述第2半導體晶片不同機能之第3半導體晶片者。
  10. 如申請專利範圍第9項記載之半導體裝置，其中，前述第2半導體晶片及前述第3半導體晶片係各設置有多層配線之表面則在朝向與前述第1半導體晶片相反側之方向，加以搭載於前述第1半導體晶片的背面者。
  11. 如申請專利範圍第9項記載之半導體裝置，其中，前述第2半導體晶片之端子與前述第3半導體晶片之端子係各藉由金屬導線而加以電性連接於前述第1半導體晶片之前述背面配線者。
  12. 如申請專利範圍第9項記載之半導體裝置，其中，前述第2半導體晶片之端子與前述第3半導體晶片之端子係各藉由導體凸塊而加以電性連接於前述第1半導體晶片之前述背面配線者。
  13. 如申請專利範圍第9項記載之半導體裝置，其中，前述第2半導體晶片及前述第3半導體晶片係於各從垂直於前述背面之方向透視之情況，包含於前述第1半導體晶片者。
  14. 如申請專利範圍第9項記載之半導體裝置，其中，前述第1半導體晶片，前述第2半導體晶片及前述第3半導體晶片係具有相互關連之機能者。
  15. 如申請專利範圍第14項記載之半導體裝置，其中，前述第2半導體晶片係感測器晶片，前述第3半導體晶片係記憶體晶片，前述第1半導體晶片係包含處理前述感測器晶片之信號的信號處理電路與控制前述記憶體晶片之記憶體控制器之控制器晶片。
  16. 一種半導體裝置之製造方法，其特徵為具備：形成多層配線於半導體基板表面者，和將加以電性連接於前述多層配線之表面電極，形成於前述多層配線上者，和呈被覆前述多層配線及前述表面電極地，貼合支持基板於前述半導體基板之表面側者，和在加以貼合有前述支持基板之狀態，從背面側薄化 前述半導體基板者，和從前述加以薄化之半導體基板之背面貫通至表面，而形成加以電性連接於前述多層配線之貫通電極者，呈加以電性連接於前述貫通電極地，形成背面配線於前述加以薄化之半導體基板之前述背面者，和第1半導體晶片之端子則呈加以電性連接於前述背面配線地，搭載前述第1半導體晶片於前述加以薄化之半導體基板之背面者，和從前述加以薄化之半導體基板，剝離前述支持基板者，和個片化前述加以薄化之半導體基板，而得到前述第1半導體晶片則加以搭載於背面而得到第2半導體晶片者。
  17. 如申請專利範圍第16項記載之半導體裝置之製造方法，其中，前述多層配線的形成係包含形成露出前述多層配線之最上的配線之開口者，前述表面電極之形成係包含形成前述表面電極於經由在前述最上之配線的前述開口所露出之範圍上者。
  18. 如申請專利範圍第16項記載之半導體裝置之製造方法，其中，前述貫通電極之形成，前述背面配線之形成，及前第1半導體晶片之搭載係維持加以以貼合前述支持基板於前述半導體基板表面之狀態同時而進行者。
  19. 如申請專利範圍第16項記載之半導體裝置之製造方法，其中，更具備接合導體球於前述表面電極上者。
  20. 如申請專利範圍第16項記載之半導體裝置之製造方法，其中，更具備具有加以電性連接於前述背面配線之端子，將具有與前述第1半導體晶片不同機能之第3半導體晶片，搭載於前述加以薄化之半導體基板背面者。
TW104107049A 2014-09-11 2015-03-05 半導體裝置及半導體裝置之製造方法 TW201611219A (zh)

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