JP2006156436A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2006156436A JP2006156436A JP2004340041A JP2004340041A JP2006156436A JP 2006156436 A JP2006156436 A JP 2006156436A JP 2004340041 A JP2004340041 A JP 2004340041A JP 2004340041 A JP2004340041 A JP 2004340041A JP 2006156436 A JP2006156436 A JP 2006156436A
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Abstract
【解決手段】 機能素子が作り込まれた半導体基板11の一方の面に、絶縁層12を介して導体層13を形成した後、半導体基板11の所定の箇所にスルーホールTH1を形成する。さらに、半導体基板の他方の面に支持シートを張り付け、導体層13と支持シート上とをワイヤ14により接続し、導体層13、ワイヤ14及びスルーホールTH1が形成されている部分を樹脂16で封止した後、支持シートを除去する。さらに、半導体基板11の他方の面から露出しているワイヤ14の端部14a上に導体層15を形成する。
【選択図】 図1
Description
11…シリコン基板(半導体基板)、
12…パッシベーション膜(絶縁層/保護膜)、
13…パッド(導体層)、
13a…導体層、
14…ボンディングワイヤ、
14a…ボンディングワイヤの端部、
15…バリヤメタル層(導体層)、
16…封止樹脂、
17…ソルダレジスト層(絶縁層/保護膜)、
18…はんだボール(外部接続端子)、
20,20a,30,30a,40,40a,50…半導体装置、
BS…支持シート、
PR…レジスト層(マスク)、
TH1,TH2,TH3,TH4,TH5…スルーホール、
W…シリコンウエハ(半導体ウエハ)。
Claims (9)
- 半導体基板内に作り込まれた機能素子に電気的に接続されて該半導体基板の一方の面に形成された第1の導体層と、前記半導体基板の他方の面に形成された第2の導体層とが、前記半導体基板の所定の箇所に形成されたスルーホールを介してボンディングワイヤにより接続され、前記半導体基板の一方の面の、少なくとも前記第1の導体層、ボンディングワイヤ及びスルーホールが形成されている部分が、封止樹脂で覆われていることを特徴とする半導体装置。
- 前記半導体基板の他方の面に、前記第2の導体層を露出させて保護膜が形成され、該保護膜から露出している第2の導体層上に外部接続端子が接合されていることを特徴とする請求項1に記載の半導体装置。
- 請求項2に記載の半導体装置が、所要個数、前記第1の導体層及び前記外部接続端子を介して電気的に接続されて積層されていることを特徴とする半導体装置。
- 請求項2に記載の半導体装置に、チップ部品が前記第1の導体層に電気的に接続されて搭載されていることを特徴とする半導体装置。
- 請求項2に記載の半導体装置に、稼動部分を有する機械/電気信号変換機能付きチップ部品が搭載され、さらに該チップ部品の稼動部分を保護するためのキャップにより封止されていることを特徴とする半導体装置。
- 機能素子が作り込まれた半導体基板の一方の面に、絶縁層を介して、前記機能素子に電気的に接続される第1の導体層を形成する工程と、
前記半導体基板の所定の箇所にスルーホールを形成する工程と、
前記半導体基板の他方の面に支持シートを張り付ける工程と、
前記絶縁層上の前記第1の導体層と前記スルーホール内の前記支持シートとをボンディングワイヤにより接続する工程と、
前記半導体基板の一方の面の、少なくとも前記第1の導体層、ボンディングワイヤ及びスルーホールが形成されている部分を、樹脂により封止する工程と、
前記支持シートを除去する工程と、
前記半導体基板の他方の面から露出している前記ボンディングワイヤの端部上に第2の導体層を形成する工程とを含むことを特徴とする半導体装置の製造方法。 - 機能素子が作り込まれた半導体基板の一方の面に、前記機能素子に電気的に接続される第1の導体層を形成すると共に、前記半導体基板の他方の面に、絶縁層を介して、該絶縁層の所定の箇所に形成された開口部を覆うようにして導体パターンを形成する工程と、
前記半導体基板の、前記絶縁層の開口部の領域に対応する箇所に、スルーホールを形成する工程と、
前記半導体基板上の前記第1の導体層と前記スルーホール内の前記導体パターンとをボンディングワイヤにより接続する工程と、
前記半導体基板の一方の面の、少なくとも前記第1の導体層、ボンディングワイヤ及びスルーホールが形成されている部分を、樹脂により封止する工程と、
前記半導体基板の他方の面から露出している前記導体パターン上に第2の導体層を形成する工程とを含むことを特徴とする半導体装置の製造方法。 - さらに、前記半導体基板の他方の面に、前記第2の導体層を露出させて保護膜を形成する工程と、
前記保護膜から露出している第2の導体層上に外部接続端子を接合した後、個々のチップ単位に個片化する工程とを含むことを特徴とする請求項6又は請求項7に記載の半導体装置の製造方法。 - 前記スルーホールを形成する箇所は、前記半導体基板内で前記機能素子が形成されていない部分に選定されることを特徴とする請求項6又は請求項7に記載の半導体装置の製造方法。
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JP2008546174A (ja) * | 2005-05-19 | 2008-12-18 | マイクロン テクノロジー, インク. | 導電性相互接続体を用いて半導体装置を製造するための裏面処理方法及びそのシステム |
JP2009506539A (ja) * | 2005-08-24 | 2009-02-12 | マイクロン テクノロジー, インク. | マイクロ電子デバイスおよびマイクロ電子支持デバイスならびに関連するアセンブリおよび方法 |
JP2009135193A (ja) * | 2007-11-29 | 2009-06-18 | Powertech Technology Inc | シリコンスルーホールを有する半導体チップ装置及びその製造方法 |
JP2009135423A (ja) * | 2007-11-09 | 2009-06-18 | Denso Corp | 半導体装置 |
JP2010045131A (ja) * | 2008-08-11 | 2010-02-25 | Shinko Electric Ind Co Ltd | 配線基板の製造方法 |
JP2011096851A (ja) * | 2009-10-29 | 2011-05-12 | Sony Corp | 半導体装置とその製造方法、及び電子機器 |
US8053909B2 (en) | 2005-04-08 | 2011-11-08 | Micron Technology, Inc. | Semiconductor component having through wire interconnect with compressed bump |
US8120167B2 (en) | 2006-04-24 | 2012-02-21 | Micron Technology, Inc. | System with semiconductor components having encapsulated through wire interconnects (TWI) |
US8193646B2 (en) | 2005-12-07 | 2012-06-05 | Micron Technology, Inc. | Semiconductor component having through wire interconnect (TWI) with compressed wire |
JP2016174129A (ja) * | 2015-03-18 | 2016-09-29 | 浜松ホトニクス株式会社 | 光検出装置 |
JP2018074163A (ja) * | 2016-11-03 | 2018-05-10 | オプティツ インコーポレイテッド | スクリーン下のセンサ組立体 |
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Also Published As
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EP1662566A2 (en) | 2006-05-31 |
EP1662566A3 (en) | 2010-11-03 |
US20060108666A1 (en) | 2006-05-25 |
JP4528100B2 (ja) | 2010-08-18 |
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