JP4863214B2 - 薄膜化シリコンからなる電子チップの製造方法 - Google Patents
薄膜化シリコンからなる電子チップの製造方法 Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims description 30
- 239000010703 silicon Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title description 27
- 239000004065 semiconductor Substances 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
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- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 88
- 235000012431 wafers Nutrition 0.000 description 44
- 230000008021 deposition Effects 0.000 description 17
- 238000001259 photo etching Methods 0.000 description 7
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- 238000005516 engineering process Methods 0.000 description 5
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- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-NJFSPNSNSA-N silicon-30 atom Chemical compound [30Si] XUIMIQQOPSSXEZ-NJFSPNSNSA-N 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 206010011878 Deafness Diseases 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 231100000895 deafness Toxicity 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
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- 208000016354 hearing loss disease Diseases 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14645—Colour imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
−一方で、特に導電性のバイアホール22'及び24'の上端において、ウェーハの表面を覆い、接点の備えのために局部的に開口のある絶縁層31と、
−他方で、回路内において相互接続を確立し、特に絶縁層31を通じて導電性のバイアホール22'及び24'と接触するための、金属又は高度にドーピングされた多結晶シリコンの導電層32とが示され、
−最後に、センサー及びその関連する回路を形成するために、適切なパターンに従ってフォトエッチングされた絶縁性及び導電性の多層のスタックが、単一の層34の形で全般的に示されている。
Claims (9)
- 前面に半導体材料の薄い活性層(12)を備えた半導体ウェーハ(10)から電子チップを製作するための方法であって、活性層の前面上へ少なくとも一つの導電層(32)を形成するステップと、ウェーハを前面で支持基板(40)上へ結合するステップと、半導体ウェーハの背面を薄膜化するステップと、次にこのように薄膜化された背面へ少なくとも一つの金属層を堆積するステップと、前記チップの外部接続のための少なくとも一つの接触子を形成するために前記金属層をエッチングするステップとを含む、方法において、
複数の狭い垂直溝(20、22、24、26)がウェーハ内へ、その前面において前記結合作業前であり前記一つの導電層の形成作業前にエッチングされ、これらの狭い垂直溝が薄膜化作業の後に残る半導体ウェーハの残留厚さにほぼ等しい深さにわたってウェーハ内へと延び、該溝が活性層から絶縁された導電性材料で充填され、薄膜化された層の前面と背面の間に導電性のバイアホール(20′、22′、24′、26′)を形成し、前記溝は前記接触子の下に位置する一連の平行溝を含んでおり、前記接触子は前記一連の平行溝を介して前記導電層と電気的に接続することを特徴とする方法。 - カラーフィルターの層が、結合及び薄膜化の後にウェーハの背面へ堆積されることを特徴とする請求項1に記載の方法。
- カラーフィルターの堆積後、半導体ウェーハ及びその支持基板が別の透明な基板(60)上へ結合され、そして支持基板が除去されることを特徴とする請求項2に記載の方法。
- 溝が薄いシリコン酸化物(28)でコーティングされたそれらの内壁を有し、導電性となるように高度にドーピングされた多結晶シリコン(30)で充填されることを特徴とする請求項1〜3のいずれか一項に記載の方法。
- 少なくとも一つの接触子のために、前記狭い垂直溝を含む半導体領域を完全に囲む連続的な溝を形成し、前記半導体領域が前記活性層の残りから分離されるように、前記連続的な溝を前記活性層から分離された導電材料で充填することを特徴とする請求項1〜4のいずれか一項に記載の方法。
- 半導体ウェーハが厚さ5〜20μm程度の活性層を形成する、より軽くドーピングされたエピタキシャル層でコーティングされている高度にドーピングされたシリコン基板を含み、そして溝の深さが実質的にエピタキシャル層の厚さに等しいことを特徴とする請求項1〜5のいずれか一項に記載の方法。
- カラー画像センサーであって、
−支持基板(40、60)と、
−光電性領域のマトリックスがその中に形成された薄いシリコン層と、
−少なくとも一つのエッチングされた導電層を含み、前記薄いシリコン層の前面におけるエッチングされた層と、
−少なくとも一つの接触子を含み、前記薄いシリコン層の反対の面、すなわち背面の上へ堆積された少なくとも一つの金属層と、
−前記薄いシリコン層の反対の面、すなわち背面の上へ堆積されたカラーフィルターの層と、
−前記背面上の前記接触子と前記前面上の前記導電層との間に導電性のバイアホールを形成し、一つの前記接触子と接触する導電性材料で充填され、絶縁層でコーティングされた平行する垂直の側壁を有し、前記接触子の下の前記薄いシリコン層全体を横切っている一連の狭い垂直溝とを備えたカラー画像センサー。 - 少なくとも一つの狭い垂直溝が、前記導電層及び前記接触子と接続される狭い垂直溝を含む半導体領域を完全に囲む連続的な溝であり、前記半導体領域が前記活性層の残りから分離されるように、前記連続的な溝が前記活性層から分離された導電材料で充填されることを特徴とする請求項7に記載のカラー画像センサー。
- 半導体材料の薄い活性層(12)を前面に備えた半導体ウェーハ(10)を用いて電子チップを製作するための方法であって、
前記活性層をエッチングして、当該活性層の厚さと等しい深さであって互いに平行する一連の平行溝(20、22、24、26)を形成し、
前記一連の平行溝の内壁面に絶縁層(28)を形成し、
前記一連の平行溝に導電性材料(30)を充填することによって導電性のバイアホール(20′、22′、24′、26′)を形成し、
前記活性層の前面に前記複数のバイアホール(22′、24′)と電気的に接続される導電層(32)を形成し、
前記半導体ウェーハの背面を支持基板(40)の表面に結合し、
前記半導体ウェーハを除去し、
前記活性層の背面に前記複数のバイアホール(22′、24′)と電気的に接続される金属層(44′)を形成する方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR03/14595 | 2003-12-12 | ||
FR0314595A FR2863773B1 (fr) | 2003-12-12 | 2003-12-12 | Procede de fabrication de puces electroniques en silicium aminci |
PCT/EP2004/053003 WO2005067054A1 (fr) | 2003-12-12 | 2004-11-18 | Procede de fabrication de puces electroniques en silicium aminci |
Publications (2)
Publication Number | Publication Date |
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JP2007518253A JP2007518253A (ja) | 2007-07-05 |
JP4863214B2 true JP4863214B2 (ja) | 2012-01-25 |
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Application Number | Title | Priority Date | Filing Date |
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JP2006543528A Expired - Fee Related JP4863214B2 (ja) | 2003-12-12 | 2004-11-18 | 薄膜化シリコンからなる電子チップの製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US20070166956A1 (ja) |
EP (1) | EP1700343A1 (ja) |
JP (1) | JP4863214B2 (ja) |
CN (1) | CN1894797A (ja) |
CA (1) | CA2546310A1 (ja) |
FR (1) | FR2863773B1 (ja) |
WO (1) | WO2005067054A1 (ja) |
Families Citing this family (11)
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US7504277B2 (en) | 2005-10-12 | 2009-03-17 | Raytheon Company | Method for fabricating a high performance PIN focal plane structure using three handle wafers |
US7749799B2 (en) | 2005-11-15 | 2010-07-06 | California Institute Of Technology | Back-illuminated imager and method for making electrical and optical connections to same |
FR2910707B1 (fr) * | 2006-12-20 | 2009-06-12 | E2V Semiconductors Soc Par Act | Capteur d'image a haute densite d'integration |
FR2910705B1 (fr) * | 2006-12-20 | 2009-02-27 | E2V Semiconductors Soc Par Act | Structure de plots de connexion pour capteur d'image sur substrat aminci |
US7875948B2 (en) | 2008-10-21 | 2011-01-25 | Jaroslav Hynecek | Backside illuminated image sensor |
JP5682174B2 (ja) * | 2010-08-09 | 2015-03-11 | ソニー株式会社 | 固体撮像装置とその製造方法、並びに電子機器 |
KR20130119193A (ko) * | 2012-04-23 | 2013-10-31 | 주식회사 동부하이텍 | 후면 수광 이미지 센서와 그 제조방법 |
US9666523B2 (en) * | 2015-07-24 | 2017-05-30 | Nxp Usa, Inc. | Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof |
US10043676B2 (en) * | 2015-10-15 | 2018-08-07 | Vishay General Semiconductor Llc | Local semiconductor wafer thinning |
CN108321215B (zh) * | 2018-03-07 | 2024-09-13 | 苏州晶方半导体科技股份有限公司 | 光学指纹识别芯片的封装结构及其制作方法 |
US20230296994A1 (en) * | 2022-03-21 | 2023-09-21 | Infineon Technologies Ag | Back Side to Front Side Alignment on a Semiconductor Wafer with Special Structures |
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2003
- 2003-12-12 FR FR0314595A patent/FR2863773B1/fr not_active Expired - Fee Related
-
2004
- 2004-11-18 US US10/582,711 patent/US20070166956A1/en not_active Abandoned
- 2004-11-18 WO PCT/EP2004/053003 patent/WO2005067054A1/fr active Application Filing
- 2004-11-18 JP JP2006543528A patent/JP4863214B2/ja not_active Expired - Fee Related
- 2004-11-18 CA CA002546310A patent/CA2546310A1/fr not_active Abandoned
- 2004-11-18 CN CNA2004800370925A patent/CN1894797A/zh active Pending
- 2004-11-18 EP EP04820955A patent/EP1700343A1/fr not_active Withdrawn
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JPH0228335A (ja) * | 1988-07-18 | 1990-01-30 | Nec Corp | モノリシック集積回路素子の製造方法 |
JPH08236788A (ja) * | 1995-02-28 | 1996-09-13 | Nippon Motorola Ltd | 半導体センサの製造方法 |
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EP1369929A1 (en) * | 2002-05-27 | 2003-12-10 | STMicroelectronics S.r.l. | A process for manufacturing encapsulated optical sensors, and an encapsulated optical sensor manufactured using this process |
Also Published As
Publication number | Publication date |
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CA2546310A1 (fr) | 2005-07-21 |
FR2863773B1 (fr) | 2006-05-19 |
EP1700343A1 (fr) | 2006-09-13 |
FR2863773A1 (fr) | 2005-06-17 |
WO2005067054A1 (fr) | 2005-07-21 |
CN1894797A (zh) | 2007-01-10 |
US20070166956A1 (en) | 2007-07-19 |
JP2007518253A (ja) | 2007-07-05 |
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