WO2016009473A1 - 半導体装置の製造方法、及び、半導体装置 - Google Patents
半導体装置の製造方法、及び、半導体装置 Download PDFInfo
- Publication number
- WO2016009473A1 WO2016009473A1 PCT/JP2014/068707 JP2014068707W WO2016009473A1 WO 2016009473 A1 WO2016009473 A1 WO 2016009473A1 JP 2014068707 W JP2014068707 W JP 2014068707W WO 2016009473 A1 WO2016009473 A1 WO 2016009473A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- insulating film
- semiconductor layer
- conductivity type
- sectional
- taken along
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 188
- 238000004519 manufacturing process Methods 0.000 title claims description 76
- 210000000746 body region Anatomy 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 57
- 229910052710 silicon Inorganic materials 0.000 claims description 57
- 239000010703 silicon Substances 0.000 claims description 57
- 239000012535 impurity Substances 0.000 claims description 39
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 88
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 229910052785 arsenic Inorganic materials 0.000 description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Definitions
- the present invention relates to a semiconductor device manufacturing method and a semiconductor device.
- SGT Surrounding Gate Transistor
- one transistor is formed on one silicon column, and an nMOS transistor composed of one silicon column and a pMOS transistor composed of one silicon column are formed on a plane (for example, see Patent Document 4). Since at least two silicon pillars are formed on a plane, an area corresponding to at least two silicon pillars is required.
- a plurality of gates are formed on one silicon pillar (see, for example, Patent Document 5).
- a gate insulating film is formed on the side wall of the silicon pillar, and a source line and a bit line are connected to the upper end and the lower end of the silicon pillar.
- JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2008-300558 A JP 2014-57068 A
- an object is to provide an inverter circuit formed of a single semiconductor pillar.
- the semiconductor device of the present invention includes a third first conductive semiconductor layer formed on a semiconductor substrate, and a first columnar semiconductor layer formed on the semiconductor substrate, the first conductive semiconductor layer, 1st body region, 2nd 1st conductivity type semiconductor layer, 1st 2nd conductivity type semiconductor layer, 2nd body region, 2nd 2nd conductivity type semiconductor layer, 3rd 2nd conductivity type semiconductor
- a first columnar semiconductor layer formed in this order from the substrate side; a first gate insulating film formed around the first body region; and a periphery of the first gate insulating film.
- the first gate insulating film is further formed on the upper and lower surfaces of the first gate, and the second gate insulating film is further formed on the upper and lower surfaces of the second gate.
- the semiconductor device has a first connection region formed between the second first conductivity type semiconductor layer and the first second conductivity type semiconductor layer.
- the fourth conductive film has the same impurity as that of the second conductive semiconductor layer, and the fourth insulating film has the same impurity as that of the second second conductive semiconductor layer.
- a second insulating film that is an oxide film containing a first conductivity type impurity is deposited on a substrate, and a sixth insulating film that is a nitride film is deposited.
- Depositing a third insulating film that is an oxide film containing an impurity of a second conductivity type, which is a conductivity type different from the first conductivity type and depositing the second insulating film, the sixth insulating film, and the Etching the third insulating film to form a contact hole, forming a first columnar silicon layer in the contact hole by epitaxial growth, removing the sixth insulating film, and depositing metal to form an output terminal It is characterized by doing.
- a first columnar silicon layer is formed in the contact hole by epitaxial growth, and then heat treatment is performed, whereby a second first conductivity type semiconductor layer and a first second conductivity type semiconductor are formed on the first columnar silicon layer. A layer is formed.
- an inverter circuit formed of one semiconductor pillar can be provided.
- the region, the second first conductivity type semiconductor layer, the first second conductivity type semiconductor layer, the second body region, the second second conductivity type semiconductor layer, and the third second conductivity type semiconductor layer are on the substrate side.
- the first gate insulating film is further formed on the upper and lower surfaces of the first gate, and the second gate insulating film is further formed on the upper and lower surfaces of the second gate.
- the vertical insulation of the first gate and the vertical insulation of the second gate can be ensured.
- the first connection region formed between the second first conductivity type semiconductor layer and the first second conductivity type semiconductor layer includes the second first conductivity type semiconductor layer,
- the first second-conductivity-type semiconductor layer can be separated, and the second first-conductivity-type semiconductor layer, the first second-conductivity-type semiconductor layer, and the output terminal extending in the connection region can be connected. it can.
- the fourth conductive film has the same impurity as the impurity of the second conductive type semiconductor layer, and the fourth insulating film has the same impurity as the impurity of the second second conductive type semiconductor layer.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view concerning the manufacturing method of the semiconductor device concerning the present invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view concerning the manufacturing method of the semiconductor device concerning the present invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
- FIG. 4B is a sectional view taken along line xx ′ in FIG. (C) is a sectional view taken along line y-y ′ of (a).
- FIG. 1 A structure of a semiconductor device according to an embodiment of the present invention is shown in FIG.
- the semiconductor is silicon, but a semiconductor other than silicon may be used.
- the first gate 126 and the second gate 121 are preferably made of metal in order to adjust the threshold value of the transistor.
- the metal is preferably titanium nitride or aluminum titanium nitride.
- the first gate insulating film 125 and the second gate insulating film 120 are preferably an oxide film, an oxynitride film, or a high dielectric film.
- the first gate insulating film 125 is further formed on the upper and lower surfaces of the first gate 126, and the second gate insulating film 120 is further formed on the upper and lower surfaces of the second gate 121.
- first insulating film 103 surrounding the first first conductivity type silicon layer 131 and the second insulating film 105 surrounding the second first conductivity type silicon layer 130 are provided.
- the insulating film 103 has the same impurity as the impurity of the first first conductivity type silicon layer 131, and the second insulating film 105 is the same as the impurity of the second first conductivity type silicon layer 130.
- the third insulating film 109 has the same impurity as that of the first second conductive silicon layer 129, and the fourth insulating film 111 is formed of the second second conductive silicon layer 129. It has the same impurity as the impurity.
- the first insulating film 103 and the second insulating film 105 are preferably oxide films containing phosphorus or arsenic at a high concentration.
- the third insulating film 109 and the fourth insulating film 111 are preferably oxide films containing boron at a high concentration.
- the first insulating film 103 and the second insulating film 105 are preferably oxide films containing boron at a high concentration.
- the third insulating film 109 and the fourth insulating film 111 are preferably oxide films containing phosphorus or arsenic at a high concentration.
- FIGS. 1-10 A manufacturing process for forming an SGT structure according to an embodiment of the present invention will be described with reference to FIGS.
- silicon is used for the substrate, but other semiconductors may be used.
- the nMOS is formed below the columnar semiconductor layer and the pMOS is formed above, but the pMOS may be formed below and the nMOS may be formed above.
- impurities are introduced into the silicon substrate 101 to form a third first conductivity type silicon layer 102.
- a first insulating film 103 is formed.
- the first insulating film 103 is preferably an oxide film.
- An oxide film containing phosphorus or arsenic at a high concentration is preferable.
- an impurity may be implanted to form an oxide film containing phosphorus or arsenic at a high concentration.
- the fifth insulating film 104 is formed.
- the fifth insulating film 104 is preferably a nitride film.
- a second insulating film 105 is formed.
- the second insulating film 105 is preferably an oxide film.
- An oxide film containing phosphorus or arsenic at a high concentration is preferable.
- an impurity may be implanted to form an oxide film containing phosphorus or arsenic at a high concentration.
- a sixth insulating film 106 is formed.
- the sixth insulating film 106 is preferably a nitride film.
- a first resist 107 is formed.
- the sixth insulating film 106 is etched.
- the first resist 107 is removed.
- a seventh insulating film 108 is formed and planarized.
- the seventh insulating film 108 is preferably an oxide film.
- the seventh insulating film 108 is etched back to expose the sixth insulating film 106.
- a third insulating film 109 is formed.
- the third insulating film 109 is preferably an oxide film.
- An oxide film containing boron at a high concentration is preferable.
- an impurity may be implanted to form an oxide film containing boron at a high concentration.
- an eighth insulating film 110 is formed.
- the eighth insulating film 110 is preferably a nitride film.
- a fourth insulating film 111 is formed.
- the fourth insulating film 111 is preferably an oxide film.
- An oxide film containing boron at a high concentration is preferable.
- an impurity may be implanted to form an oxide film containing boron at a high concentration.
- a second resist 112 is formed.
- the fourth insulating film 111, the eighth insulating film 110, the third insulating film 109, the seventh insulating film 108, the sixth insulating film 106, the second insulating film 105, 5 insulating film 104 and first insulating film 103 are etched.
- the second resist 112 is removed.
- a ninth insulating film 113 is deposited and planarized.
- the ninth insulating film 113 is preferably an oxide film.
- the ninth insulating film 113 prevents the columnar semiconductor layer from being bent or collapsed when the eighth insulating film 110, the sixth insulating film 106, and the fifth insulating film 104 are removed later. Can do.
- a third resist 114 is formed.
- the ninth insulating film 113, the fourth insulating film 111, the eighth insulating film 110, the third insulating film 109, the sixth insulating film 106, the second insulating film 105, The insulating film 104 and the first insulating film 103 are etched to form contact holes 115.
- the third resist 114 is removed.
- the first columnar silicon layer 116 is formed by epitaxial growth. Polysilicon may be deposited.
- boron impurities are introduced to form a third second-conductivity-type silicon layer 117.
- polysilicon 118 is deposited. Although polysilicon is used, any material can be used as long as it becomes a hard mask.
- a fourth resist 119 is formed.
- the polysilicon 118, the ninth insulating film 113, and the fourth insulating film 111 are etched.
- the fourth resist 119 is removed.
- the eighth insulating film 110 is etched. Wet etching is preferred.
- the second gate insulating film 120 is preferably an oxide film, an oxynitride film, or a high dielectric film.
- a metal 121 to be the second gate 121 is formed.
- the metal 121 is preferably titanium nitride or aluminum titanium nitride.
- the metal 121 is etched to form the second gate 121.
- the exposed second gate insulating film 120 and third insulating film 109 are etched to expose the sixth insulating film 106.
- a tenth insulating film 122 is deposited.
- the tenth insulating film 122 is preferably an oxide film.
- the tenth insulating film 122 is etched and left in a sidewall shape.
- the sixth insulating film 106 is etched. Wet etching is preferred.
- a metal 123 to be the output terminal 123 is formed.
- the metal 123 is preferably titanium nitride, aluminum titanium nitride, or tungsten.
- the metal 123 is etched to form the output terminal 123.
- the second insulating film 105 is etched, and the fifth insulating film 104 is exposed.
- an eleventh insulating film 124 is deposited.
- the eleventh insulating film 124 is preferably an oxide film.
- the eleventh insulating film 124 is etched and left in a sidewall shape.
- the fifth insulating film 104 is etched. Wet etching is preferred.
- the first gate insulating film 125 is preferably an oxide film, an oxynitride film, or a high dielectric film.
- a metal 126 to be the first gate 126 is formed.
- the metal 126 is preferably titanium nitride or aluminum titanium nitride.
- the metal 126 is etched to form the first gate 126.
- the exposed first gate insulating film 125 is etched.
- a first interlayer insulating film 127 is deposited, planarized, and the polysilicon 118 is exposed.
- the polysilicon 118 is etched. At this time, a part of the third second conductivity type silicon layer 117 is etched.
- heat treatment is performed, and by solid phase diffusion, the first first conductivity type silicon layer 131, the second first conductivity type silicon layer 130, the first second conductivity type silicon layer 129, and the first Two second conductivity type silicon layers 128 are formed. Heat treatment may be performed before the second gate 121 is formed.
- a fifth resist 132 is formed.
- the ninth insulating film 113 and the second gate insulating film 120 are etched.
- the second gate 121 is etched.
- the second gate insulating film 120 is etched.
- the fifth resist 132 is removed.
- the second interlayer insulating film 133 is deposited and planarized.
- the second interlayer insulating film 133 is etched back to expose the third second conductivity type silicon layer 117.
- a sixth resist 134 is formed.
- the first interlayer insulating film 127 is etched to form a contact hole 135.
- the sixth resist 134 is removed.
- a seventh resist 136 is formed.
- the second interlayer insulating film 133 is etched to form a contact hole 137.
- the seventh resist 136 is removed.
- an eighth resist 138 is formed.
- the ninth insulating film 113 and the second gate insulating film 120 are etched.
- the second gate 121 is etched.
- the second gate insulating film 120, the third insulating film 109, the seventh insulating film 108, the second insulating film 105, and the first gate insulating film 125 are etched to form a contact hole 139. Form.
- the eighth resist 138 is removed.
- a metal 143 is deposited to form contacts 140 and 141 and a first contact 142.
- ninth resists 144, 145, 146, 147 are formed.
- the metal 143 is etched to form metal wirings 143a, 143b, 143c, and 143d.
- the ninth resists 144, 145, 146, 147 are removed.
- First gate metal 127. First interlayer insulating film 128. Second second conductivity type silicon layer 129. First second conductivity type silicon layer 130. Second first conductivity type silicon layer 131. First first conductivity type silicon layer 132. Fifth resist 133. Second interlayer insulating film 134. Sixth resist 135. Contact hole 136. Seventh resist 137. Contact hole 138. Eighth resist 139. Contact hole 140. Contact 141. Contact 142. First contact 143. Metal 143a. Metal wiring 143b. Metal wiring 143c. Metal wiring 143d. Metal wiring 144. Ninth resist 145. Ninth resist 146. Ninth resist 147. Ninth resist 201. Second body region 202. First body region 203. First connection area
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
Abstract
一本の半導体柱で形成されたインバータ回路を提供することを課題とする。半導体基板上に形成された第3の第1導電型半導体層と、前記半導体基板上に形成された第1の柱状半導体層と、前記第1の柱状半導体層に第1の第1導電型半導体層と第1のボディ領域と第2の第1導電型半導体層と第1の第2導電型半導体層と第2のボディ領域と第2の第2導電型半導体層と第3の第2導電型半導体層とが基板側からこの順に形成されるのであって、前記第1のボディ領域の周囲に形成された第1のゲート絶縁膜と、前記第1のゲート絶縁膜の周囲に形成された第1のゲートと、前記第2のボディ領域の周囲に形成された第2のゲート絶縁膜と、前記第2のゲート絶縁膜の周囲に形成された第2のゲートと、前記第2の第1導電型半導体層と前記第1の第2導電型半導体層とに接続する出力端子と、前記第1のゲートと前記第2のゲートとを接続する第1のコンタクトと、を有することを特徴とする半導体装置により、上記課題を解決する。
Description
本発明は半導体装置の製造方法、及び、半導体装置に関する。
半導体集積回路、特にMOSトランジスタを用いた集積回路は、高集積化の一途を辿っている。この高集積化に伴って、その中で用いられているMOSトランジスタはナノ領域まで微細化が進んでいる。このようなMOSトランジスタの微細化が進むと、リーク電流の抑制が困難であり、必要な電流量確保の要請から回路の占有面積をなかなか小さくできない、といった問題があった。このような問題を解決するために、基板に対してソース、ゲート、ドレインが垂直方向に配置され、ゲート電極が柱状半導体層を取り囲む構造のSurrounding Gate Transistor(以下、「SGT」という。)が提案されている(例えば、特許文献1、特許文献2、特許文献3を参照)。
従来のSGTを用いたインバータでは、一本のシリコン柱に一個のトランジスタが形成され、1本のシリコン柱からなるnMOSトランジスタと1本のシリコン柱からなるpMOSトランジスタが平面上に形成されている(例えば特許文献4を参照)。少なくとも2本のシリコン柱が平面上に形成されているため、少なくとも2本のシリコン柱分の面積が必要となる。
従来の不揮発性メモリにおいて、一本のシリコン柱に複数のゲートが形成されている(例えば特許文献5を参照)。シリコン柱の側壁にゲート絶縁膜が形成され、シリコン柱の上部端と下部端でソース線、ビット線が接続されている。
そこで、一本の半導体柱で形成されたインバータ回路を提供することを目的とする。
本発明の半導体装置は、半導体基板上に形成された第3の第1導電型半導体層と、前記半導体基板上に形成された第1の柱状半導体層であって、第1導電型半導体層、第1のボディ領域、第2の第1導電型半導体層、第1の第2導電型半導体層、第2のボディ領域、第2の第2導電型半導体層、第3の第2導電型半導体層が基板側からこの順に形成された第1の柱状半導体層と、前記第1のボディ領域の周囲に形成された第1のゲート絶縁膜と、前記第1のゲート絶縁膜の周囲に形成された第1のゲートと、前記第2のボディ領域の周囲に形成された第2のゲート絶縁膜と、前記第2のゲート絶縁膜の周囲に形成された第2のゲートと、前記第2の第1導電型半導体層と前記第1の第2導電型半導体層とに接続する出力端子と、前記第1のゲートと前記第2のゲートとを接続する第1のコンタクトと、
を有することを特徴とする。
を有することを特徴とする。
また、前記第1のゲート絶縁膜は前記第1のゲートの上面と下面にさらに形成され、前記第2のゲート絶縁膜は前記第2のゲートの上面と下面にさらに形成されていることを特徴とする。
また、前記第2の第1導電型半導体層と前記第1の第2導電型半導体層との間に形成された第1の接続領域を有することを特徴とする。
また、前記第1の第1導電型半導体層を取り囲む第1の絶縁膜と、前記第2の第1導電型半導体層を取り囲む第2の絶縁膜とを有し、前記第1の絶縁膜は、前記第1の第1導電型半導体層の不純物と同じ不純物を有し、前記第2の絶縁膜は、前記第2の第1導電型半導体層の不純物と同じ不純物を有し、前記第1の第2導電型半導体層を取り囲む第3の絶縁膜と、前記第2の第2導電型半導体層を取り囲む第4の絶縁膜とを有し、前記第3の絶縁膜は、前記第1の第2導電型半導体層の不純物と同じ不純物を有し、前記第4の絶縁膜は、前記第2の第2導電型半導体層の不純物と同じ不純物を有することを特徴とする。
また、本発明の半導体装置の製造方法は、基板上に、第1の導電型の不純物を含む酸化膜である第2の絶縁膜を堆積し、窒化膜である第6の絶縁膜を堆積し、第1の導電型とは異なる導電型である第2の導電型の不純物を含む酸化膜である第3の絶縁膜を堆積し、前記第2の絶縁膜と前記第6の絶縁膜と前記第3の絶縁膜をエッチングしコンタクト孔を形成し、前記コンタクト孔にエピタキシャル成長により第1の柱状シリコン層を形成し、前記第6の絶縁膜を除去し、金属を堆積することにより出力端子を形成することを特徴とする。
また、前記コンタクト孔にエピタキシャル成長により第1の柱状シリコン層を形成した後に、熱処理を行うことにより、第1の柱状シリコン層に第2の第1導電型半導体層と第1の第2導電型半導体層を形成することを特徴とする。
本発明によれば、一本の半導体柱で形成されたインバータ回路を提供することができる。
半導体基板上に形成された第3の第1導電型半導体層と、前記半導体基板上に形成された第1の柱状半導体層であって、第1の第1導電型半導体層、第1のボディ領域、第2の第1導電型半導体層、第1の第2導電型半導体層、第2のボディ領域、第2の第2導電型半導体層、第3の第2導電型半導体層が基板側からこの順に形成された第1の柱状半導体装置と、前記第1のボディ領域の周囲に形成された第1のゲート絶縁膜と、前記第1のゲート絶縁膜の周囲に形成された第1のゲートと、前記第2のボディ領域の周囲に形成された第2のゲート絶縁膜と、前記第2のゲート絶縁膜の周囲に形成された第2のゲートと、前記第2の第1導電型半導体層と前記第1の第2導電型半導体層とに接続する出力端子と、前記第1のゲートと前記第2のゲートとを接続する第1のコンタクトとにより、一本の半導体柱で形成されたインバータが形成されるため、1本の半導体柱分の面積でインバータを実現することができる。
また、前記第1のゲート絶縁膜は前記第1のゲートの上面と下面にさらに形成され、前記第2のゲート絶縁膜は前記第2のゲートの上面と下面にさらに形成されていることにより、第1のゲートの上下方向の絶縁と、第2のゲートの上下方向の絶縁を確かなものとすることができる。
また、前記第2の第1導電型半導体層と前記第1の第2導電型半導体層との間に形成された第1の接続領域を有することにより、第2の第1導電型半導体層と第1の第2導電型半導体層とを分離することができ、接続領域に延在する第2の第1導電型半導体層と第1の第2導電型半導体層と出力端子を接続することができる。
また、前記第1の第1導電型半導体層を取り囲む第1の絶縁膜と、前記第2の第1導電型半導体層を取り囲む第2の絶縁膜とを有し、前記第1の絶縁膜は、前記第1の第1導電型半導体層の不純物と同じ不純物を有し、前記第2の絶縁膜は、前記第2の第1導電型半導体層の不純物と同じ不純物を有し、前記第1の第2導電型半導体層を取り囲む第3の絶縁膜と、前記第2の第2導電型半導体層を取り囲む第4の絶縁膜とを有し、前記第3の絶縁膜は、前記第1の第2導電型半導体層の不純物と同じ不純物を有し、前記第4の絶縁膜は、前記第2の第2導電型半導体層の不純物と同じ不純物を有することを特徴とすることにより、固相拡散により、一本の柱状半導体層に異なる導電型の半導体層を形成することができる。
以下に、本発明の実施形態について説明する。本発明の実施形態に係る半導体装置の構造を図1に示す。本実施例では、半導体をシリコンとしたが、シリコン以外の半導体としてもよい。
シリコン基板101上に形成された第3の第1導電型シリコン層102と、前記シリコン基板101上に形成された第1の柱状シリコン層116とを有し、前記第1の柱状シリコン層116は、第1の第1導電型シリコン層131と第1のボディ領域202と第2の第1導電型シリコン層130と第1の第2導電型シリコン層129と第2のボディ領域201と第2の第2導電型シリコン層128と第3の第2導電型シリコン層117とが基板側からこの順に形成され、さらに、前記第1のボディ領域202の周囲に形成された第1のゲート絶縁膜125と、前記第1のゲート絶縁膜125の周囲に形成された第1のゲート126と、前記第2のボディ領域201の周囲に形成された第2のゲート絶縁膜120と、前記第2のゲート絶縁膜120の周囲に形成された第2のゲート121と、前記第2の第1導電型シリコン層130と前記第1の第2導電型シリコン層129とに接続する出力端子123と、前記第1のゲート126と前記第2のゲート121とを接続する第1のコンタクト142と、を有している。
第1のゲート126と第2のゲート121は、トランジスタのしきい値を調整するため、金属であることが好ましい。また、金属は、窒化チタン、窒化アルミチタンが好ましい。また、第1のゲート絶縁膜125と第2のゲート絶縁膜120は、酸化膜、酸窒化膜、高誘電体膜が好ましい。
前記第1のゲート絶縁膜125は前記第1のゲート126の上面と下面にさらに形成され、前記第2のゲート絶縁膜120は前記第2のゲート121の上面と下面にさらに形成されている。
前記第2の第1導電型シリコン層130と前記第1の第2導電型シリコン層129との間に形成された第1の接続領域203を有している。
また、前記第1の第1導電型シリコン層131を取り囲む第1の絶縁膜103と、前記第2の第1導電型シリコン層130を取り囲む第2の絶縁膜105とを有し、前記第1の絶縁膜103は、前記第1の第1導電型シリコン層131の不純物と同じ不純物を有し、前記第2の絶縁膜105は、前記第2の第1導電型シリコン層130の不純物と同じ不純物を有し、前記第1の第2導電型シリコン層129を取り囲む第3の絶縁膜109と、前記第2の第2導電型シリコン層128を取り囲む第4の絶縁膜111とを有し、前記第3の絶縁膜109は、前記第1の第2導電型シリコン層129の不純物と同じ不純物を有し、前記第4の絶縁膜111は、前記第2の第2導電型シリコン層129の不純物と同じ不純物を有する。
下部のトランジスタがnMOSの場合、第1の絶縁膜103と第2の絶縁膜105は、リンもしくは砒素を高濃度に含む酸化膜が好ましい。上部のトランジスタがpMOSの場合、第3の絶縁膜109と前記第4の絶縁膜111は、ボロンを高濃度に含む酸化膜が好ましい。下部のトランジスタがpMOSの場合、第1の絶縁膜103と第2の絶縁膜105は、ボロンを高濃度に含む酸化膜が好ましい。上部のトランジスタがnMOSの場合、第3の絶縁膜109と前記第4の絶縁膜111は、リンもしくは砒素を高濃度に含む酸化膜が好ましい。
本発明の実施形態に係るSGTの構造を形成するための製造工程を、図2~図70を参照して説明する。本実施例では、基板にシリコンを使用したが、他の半導体を用いてもよい。また、本実施例では、柱状半導体層の下部にnMOSを、上部にpMOSを形成する工程としたが、下部にpMOSを、上部にnMOSを形成してもよい。
図2に示すように、シリコン基板101に不純物を導入し、第3の第1導電型シリコン層102を形成する。
図3に示すように、第1の絶縁膜103を形成する。第1の絶縁膜103は、酸化膜が好ましい。リンもしくは砒素を高濃度に含む酸化膜が好ましい。また、第1の絶縁膜103を形成後、不純物を注入し、リンもしくは砒素を高濃度に含む酸化膜としてもよい。
図4に示すように、第5の絶縁膜104を形成する。第5の絶縁膜104は窒化膜が好ましい。
図5に示すように、第2の絶縁膜105を形成する。第2の絶縁膜105は、酸化膜が好ましい。リンもしくは砒素を高濃度に含む酸化膜が好ましい。また、第2の絶縁膜105を形成後、不純物を注入し、リンもしくは砒素を高濃度に含む酸化膜としてもよい。
図6に示すように、第6の絶縁膜106を形成する。第6の絶縁膜106は窒化膜が好ましい。
図7に示すように、第1のレジスト107を形成する。
図8に示すように、第6の絶縁膜106をエッチングする。
図9に示すように、第1のレジスト107を除去する。
図10に示すように、第7の絶縁膜108を形成し、平坦化する。第7の絶縁膜108は酸化膜が好ましい。
図11に示すように、第7の絶縁膜108をエッチバックし、第6の絶縁膜106を露出する。
図12に示すように、第3の絶縁膜109を形成する。第3の絶縁膜109は、酸化膜が好ましい。ボロンを高濃度に含む酸化膜が好ましい。また、第3の絶縁膜109を形成後、不純物を注入し、ボロンを高濃度に含む酸化膜としてもよい。
図13に示すように、第8の絶縁膜110を形成する。第8の絶縁膜110は窒化膜が好ましい。
図14に示すように、第4の絶縁膜111を形成する。第4の絶縁膜111は、酸化膜が好ましい。ボロンを高濃度に含む酸化膜が好ましい。また、第4の絶縁膜111を形成後、不純物を注入し、ボロンを高濃度に含む酸化膜としてもよい。
図15に示すように、第2のレジスト112を形成する。
図16に示すように、第4の絶縁膜111、第8の絶縁膜110、第3の絶縁膜109、第7の絶縁膜108、第6の絶縁膜106、第2の絶縁膜105、第5の絶縁膜104、第1の絶縁膜103をエッチングする。
図17に示すように、第2のレジスト112を剥離する。
図18に示すように、第9の絶縁膜113を堆積し、平坦化する。第9の絶縁膜113は酸化膜が好ましい。また、第9の絶縁膜113により、第8の絶縁膜110、第6の絶縁膜106、第5の絶縁膜104を、後に除去したとき、柱状半導体層が曲がることもしくは倒れることを回避することができる。
図19に示すように、第3のレジスト114を形成する。
図20に示すように、第9の絶縁膜113、第4の絶縁膜111、第8の絶縁膜110、第3の絶縁膜109、第6の絶縁膜106、第2の絶縁膜105、第5の絶縁膜104、第1の絶縁膜103をエッチングし、コンタクト孔115を形成する。
図21に示すように、第3のレジスト114を除去する。
図22に示すように、エピタキシャル成長を行い、第1の柱状シリコン層116を形成する。ポリシリコンを堆積してもよい。
図23に示すように、ボロンの不純物導入を行い、第3の第2導電型シリコン層117を形成する。
図24に示すように、ポリシリコン118を堆積する。ポリシリコンを用いたが、ハードマスクとなる材料であればよい。
図25に示すように、第4のレジスト119を形成する。
図26に示すように、ポリシリコン118、第9の絶縁膜113、第4の絶縁膜111をエッチングする。
図27に示すように、第4のレジスト119を除去する。
図28に示すように、第8の絶縁膜110をエッチングする。ウエットエッチングが好ましい。
図29に示すように、第2のゲート絶縁膜120を形成する。第2のゲート絶縁膜120は、酸化膜、酸窒化膜、高誘電体膜が好ましい。
図30に示すように、第2のゲート121となる金属121を形成する。金属121は、窒化チタン、窒化アルミチタンが好ましい。
図31に示すように、金属121をエッチングし、第2のゲート121を形成する。
図32に示すように、露出した第2のゲート絶縁膜120と第3の絶縁膜109をエッチングし、第6の絶縁膜106を露出する。
図33に示すように、第10の絶縁膜122を堆積する。第10の絶縁膜122は酸化膜が好ましい。
図34に示すように、第10の絶縁膜122をエッチングし、サイドウォール状に残存させる。
図35に示すように、第6の絶縁膜106をエッチングする。ウエットエッチングが好ましい。
図36に示すように、出力端子123となる金属123を形成する。金属123は、窒化チタン、窒化アルミチタン、タングステンが好ましい。
図37に示すように、金属123をエッチングし、出力端子123を形成する。
図38に示すように、第2の絶縁膜105をエッチングし、第5の絶縁膜104を露出する。
図39に示すように、第11の絶縁膜124を堆積する。第11の絶縁膜124は酸化膜が好ましい。
図40に示すように、第11の絶縁膜124をエッチングし、サイドウォール状に残存させる。
図41に示すように、第5の絶縁膜104をエッチングする。ウエットエッチングが好ましい。
図42に示すように、第1のゲート絶縁膜125を形成する。第1のゲート絶縁膜125は、酸化膜、酸窒化膜、高誘電体膜が好ましい。
図43に示すように、第1のゲート126となる金属126を形成する。金属126は、窒化チタン、窒化アルミチタンが好ましい。
図44に示すように、金属126をエッチングし、第1のゲート126を形成する。
図45に示すように、露出した第1のゲート絶縁膜125をエッチングする。
図46に示すように、第1の層間絶縁膜127を堆積し、平坦化し、ポリシリコン118を露出する。
図47に示すように、ポリシリコン118をエッチングする。このとき、第3の第2導電型シリコン層117の一部がエッチングされる。
図48に示すように、熱処理を行い、固相拡散により、第1の第1導電型シリコン層131と第2の第1導電型シリコン層130と第1の第2導電型シリコン層129と第2の第2導電型シリコン層128が形成される。第2のゲート121形成前に熱処理を行ってもよい。
図49に示すように、第5のレジスト132を形成する。
図50に示すように、第9の絶縁膜113、第2のゲート絶縁膜120、をエッチングする。
図51に示すように、第2のゲート121をエッチングする。
図52に示すように、第2のゲート絶縁膜120をエッチングする。
図53に示すように、第5のレジスト132を除去する。
図54に示すように、第2の層間絶縁膜133を堆積し、平坦化する。
図55に示すように、第2の層間絶縁膜133をエッチバックし、第3の第2導電型シリコン層117を露出する。
図56に示すように、第6のレジスト134を形成する。
図57に示すように、第1の層間絶縁膜127をエッチングし、コンタクト孔135を形成する。
図58に示すように、第6のレジスト134を除去する。
図59に示すように、第7のレジスト136を形成する。
図60に示すように、第2の層間絶縁膜133をエッチングし、コンタクト孔137を形成する。
図61に示すように、第7のレジスト136を除去する。
図62に示すように、第8のレジスト138を形成する。
図63に示すように、第9の絶縁膜113、第2のゲート絶縁膜120をエッチングする。
図64に示すように、第2のゲート121をエッチングする。
図65に示すように、第2のゲート絶縁膜120、第3の絶縁膜109、第7の絶縁膜108、第2の絶縁膜105、第1のゲート絶縁膜125をエッチングし、コンタクト孔139を形成する。
図66に示すように、第8のレジスト138を除去する。
図67に示すように、金属143を堆積し、コンタクト140、141、第1のコンタクト142を形成する。
図68に示すように、第9のレジスト144、145、146、147を形成する。
図69に示すように、金属143をエッチングし、金属配線143a、143b、143c、143dを形成する。
図70に示すように、第9のレジスト144、145、146、147を除去する。
以上により、本発明の半導体装置の製造方法が示された。
なお、本発明は、本発明の広義の精神と範囲を逸脱することなく、様々な実施形態及び変形が可能とされるものである。また、上述した実施形態は、本発明の一実施例を説明するためのものであり、本発明の範囲を限定するものではない。
例えば、上記実施例において、p型(p+型を含む。)とn型(n+型を含む。)とをそれぞれ反対の導電型とした半導体装置の製造方法、及び、それにより得られる半導体装置も当然に本発明の技術的範囲に含まれる。
101.シリコン基板
102.第3の第1導電型シリコン層
103.第1の絶縁膜
104.第5の絶縁膜
105.第2の絶縁膜
106.第6の絶縁膜
107.第1のレジスト
108.第7の絶縁膜
109.第3の絶縁膜
110.第8の絶縁膜
111.第4の絶縁膜
112.第2のレジスト
113.第9の絶縁膜
114.第3のレジスト
115.コンタクト孔
116.第1の柱状シリコン層
117.第3の第2導電型シリコン層
118.ポリシリコン
119.第4のレジスト
120.第2のゲート絶縁膜
121.第2のゲート、金属
122.第10の絶縁膜
123.出力端子、金属
124.第11の絶縁膜
125.第1のゲート絶縁膜
126.第1のゲート、金属
127.第1の層間絶縁膜
128.第2の第2導電型シリコン層
129.第1の第2導電型シリコン層
130.第2の第1導電型シリコン層
131.第1の第1導電型シリコン層
132.第5のレジスト
133.第2の層間絶縁膜
134.第6のレジスト
135.コンタクト孔
136.第7のレジスト
137.コンタクト孔
138.第8のレジスト
139.コンタクト孔
140.コンタクト
141.コンタクト
142.第1のコンタクト
143.金属
143a.金属配線
143b.金属配線
143c.金属配線
143d.金属配線
144.第9のレジスト
145.第9のレジスト
146.第9のレジスト
147.第9のレジスト
201.第2のボディ領域
202.第1のボディ領域
203.第1の接続領域
102.第3の第1導電型シリコン層
103.第1の絶縁膜
104.第5の絶縁膜
105.第2の絶縁膜
106.第6の絶縁膜
107.第1のレジスト
108.第7の絶縁膜
109.第3の絶縁膜
110.第8の絶縁膜
111.第4の絶縁膜
112.第2のレジスト
113.第9の絶縁膜
114.第3のレジスト
115.コンタクト孔
116.第1の柱状シリコン層
117.第3の第2導電型シリコン層
118.ポリシリコン
119.第4のレジスト
120.第2のゲート絶縁膜
121.第2のゲート、金属
122.第10の絶縁膜
123.出力端子、金属
124.第11の絶縁膜
125.第1のゲート絶縁膜
126.第1のゲート、金属
127.第1の層間絶縁膜
128.第2の第2導電型シリコン層
129.第1の第2導電型シリコン層
130.第2の第1導電型シリコン層
131.第1の第1導電型シリコン層
132.第5のレジスト
133.第2の層間絶縁膜
134.第6のレジスト
135.コンタクト孔
136.第7のレジスト
137.コンタクト孔
138.第8のレジスト
139.コンタクト孔
140.コンタクト
141.コンタクト
142.第1のコンタクト
143.金属
143a.金属配線
143b.金属配線
143c.金属配線
143d.金属配線
144.第9のレジスト
145.第9のレジスト
146.第9のレジスト
147.第9のレジスト
201.第2のボディ領域
202.第1のボディ領域
203.第1の接続領域
Claims (6)
- 半導体基板上に形成された第3の第1導電型半導体層と、
前記半導体基板上に形成された第1の柱状半導体層であって、第1導電型半導体層と第1のボディ領域、第2の第1導電型半導体層、第1の第2導電型半導体層、第2のボディ領域、第2の第2導電型半導体層、第3の第2導電型半導体層が基板側からこの順に形成された第1の柱状半導体層と、
前記第1のボディ領域の周囲に形成された第1のゲート絶縁膜と、
前記第1のゲート絶縁膜の周囲に形成された第1のゲートと、
前記第2のボディ領域の周囲に形成された第2のゲート絶縁膜と、
前記第2のゲート絶縁膜の周囲に形成された第2のゲートと、
前記第2の第1導電型半導体層と前記第1の第2導電型半導体層とに接続する出力端子と、
前記第1のゲートと前記第2のゲートとを接続する第1のコンタクトと、
を有することを特徴とする半導体装置。 - 前記第1のゲート絶縁膜は前記第1のゲートの上面と下面にさらに形成され、前記第2のゲート絶縁膜は前記第2のゲートの上面と下面にさらに形成されていることを特徴とする請求項1に記載の半導体装置。
- 前記第2の第1導電型半導体層と前記第1の第2導電型半導体層との間に形成された第1の接続領域を有することを特徴とする請求項1に記載の半導体装置。
- 前記第1の第1導電型半導体層を取り囲む第1の絶縁膜と、前記第2の第1導電型半導体層を取り囲む第2の絶縁膜とを有し、
前記第1の絶縁膜は、前記第1の第1導電型半導体層の不純物と同じ不純物を有し、
前記第2の絶縁膜は、前記第2の第1導電型半導体層の不純物と同じ不純物を有し、
前記第1の第2導電型半導体層を取り囲む第3の絶縁膜と、前記第2の第2導電型半導体層を取り囲む第4の絶縁膜とを有し、
前記第3の絶縁膜は、前記第1の第2導電型半導体層の不純物と同じ不純物を有し、
前記第4の絶縁膜は、前記第2の第2導電型半導体層の不純物と同じ不純物を有することを特徴とする請求項1に記載の半導体装置。 - 基板上に、第1の導電型の不純物を含む酸化膜である第2の絶縁膜を堆積し、窒化膜である第6の絶縁膜を堆積し、第1の導電型とは異なる導電型である第2の導電型の不純物を含む酸化膜である第3の絶縁膜を堆積し、前記第2の絶縁膜と前記第6の絶縁膜と前記第3の絶縁膜をエッチングしコンタクト孔を形成し、前記コンタクト孔にエピタキシャル成長により第1の柱状シリコン層を形成し、前記第6の絶縁膜を除去し、金属を堆積することにより出力端子を形成することを特徴とする半導体装置の製造方法。
- 前記コンタクト孔にエピタキシャル成長により第1の柱状シリコン層を形成した後に、熱処理を行うことにより、第1の柱状シリコン層に第2の第1導電型半導体層と第1の第2導電型半導体層を形成することを特徴とする請求項5に記載の半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2014/068707 WO2016009473A1 (ja) | 2014-07-14 | 2014-07-14 | 半導体装置の製造方法、及び、半導体装置 |
JP2015513918A JP5990843B2 (ja) | 2014-07-14 | 2014-07-14 | 半導体装置の製造方法、及び、半導体装置 |
US14/743,570 US9780179B2 (en) | 2014-07-14 | 2015-06-18 | Method for producing semiconductor device and semiconductor device |
US15/680,724 US10483366B2 (en) | 2014-07-14 | 2017-08-18 | Semiconductor device |
US15/680,631 US20170345908A1 (en) | 2014-07-14 | 2017-08-18 | Method for producing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2014/068707 WO2016009473A1 (ja) | 2014-07-14 | 2014-07-14 | 半導体装置の製造方法、及び、半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016009473A1 true WO2016009473A1 (ja) | 2016-01-21 |
Family
ID=55068213
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2014/068707 WO2016009473A1 (ja) | 2014-07-14 | 2014-07-14 | 半導体装置の製造方法、及び、半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (3) | US9780179B2 (ja) |
JP (1) | JP5990843B2 (ja) |
WO (1) | WO2016009473A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016009473A1 (ja) * | 2014-07-14 | 2016-01-21 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置の製造方法、及び、半導体装置 |
JP6122556B2 (ja) * | 2015-03-03 | 2017-04-26 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置 |
EP3295434A4 (en) * | 2015-05-12 | 2018-10-03 | A La Carte Media Inc. | Systems and methods for remote collection of electronic devices for value |
US10043796B2 (en) * | 2016-02-01 | 2018-08-07 | Qualcomm Incorporated | Vertically stacked nanowire field effect transistors |
US11081569B2 (en) * | 2017-12-15 | 2021-08-03 | International Business Machines Corporation | Resistor loaded inverter structures |
US11437376B2 (en) * | 2019-05-31 | 2022-09-06 | Tokyo Electron Limited | Compact 3D stacked-CFET architecture for complex logic cells |
US11094819B2 (en) * | 2019-12-06 | 2021-08-17 | International Business Machines Corporation | Stacked vertical tunnel FET devices |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0613623A (ja) * | 1992-03-02 | 1994-01-21 | Motorola Inc | 半導体装置 |
JPH10112543A (ja) * | 1996-10-04 | 1998-04-28 | Oki Electric Ind Co Ltd | 半導体素子および半導体素子の製造方法 |
JP2001028399A (ja) * | 1999-06-18 | 2001-01-30 | Lucent Technol Inc | 垂直方向トランジスタcmos集積回路の形成方法 |
JP2003163280A (ja) * | 2001-09-10 | 2003-06-06 | Agere Systems Guardian Corp | 垂直置換ゲート接合電界効果トランジスタ |
JP2007250652A (ja) * | 2006-03-14 | 2007-09-27 | Sharp Corp | 半導体装置 |
JP2011023543A (ja) * | 2009-07-15 | 2011-02-03 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US1804286A (en) * | 1928-06-07 | 1931-05-05 | Speno Frank | Conveyer |
JP2703970B2 (ja) | 1989-01-17 | 1998-01-26 | 株式会社東芝 | Mos型半導体装置 |
JP3057661B2 (ja) | 1988-09-06 | 2000-07-04 | 株式会社東芝 | 半導体装置 |
JP2950558B2 (ja) | 1989-11-01 | 1999-09-20 | 株式会社東芝 | 半導体装置 |
US5398200A (en) * | 1992-03-02 | 1995-03-14 | Motorola, Inc. | Vertically formed semiconductor random access memory device |
US5208172A (en) * | 1992-03-02 | 1993-05-04 | Motorola, Inc. | Method for forming a raised vertical transistor |
US5612563A (en) * | 1992-03-02 | 1997-03-18 | Motorola Inc. | Vertically stacked vertical transistors used to form vertical logic gate structures |
US5324673A (en) * | 1992-11-19 | 1994-06-28 | Motorola, Inc. | Method of formation of vertical transistor |
US5721168A (en) * | 1996-12-02 | 1998-02-24 | Powerchip Semiconductor Corp. | Method for forming a ring-shape capacitor |
US6670642B2 (en) * | 2002-01-22 | 2003-12-30 | Renesas Technology Corporation. | Semiconductor memory device using vertical-channel transistors |
JP2007059680A (ja) * | 2005-08-25 | 2007-03-08 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
EP1804286A1 (en) * | 2005-12-27 | 2007-07-04 | Interuniversitair Microelektronica Centrum | Elongate nanostructure semiconductor device |
JP5016832B2 (ja) * | 2006-03-27 | 2012-09-05 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
JP5130596B2 (ja) | 2007-05-30 | 2013-01-30 | 国立大学法人東北大学 | 半導体装置 |
JP5317343B2 (ja) * | 2009-04-28 | 2013-10-16 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置及びその製造方法 |
KR101539697B1 (ko) * | 2008-06-11 | 2015-07-27 | 삼성전자주식회사 | 수직형 필라를 활성영역으로 사용하는 3차원 메모리 장치,그 제조 방법 및 그 동작 방법 |
US8395206B2 (en) * | 2008-10-09 | 2013-03-12 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
JP5032532B2 (ja) * | 2009-06-05 | 2012-09-26 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置及びその製造方法 |
JP2011216657A (ja) * | 2010-03-31 | 2011-10-27 | Unisantis Electronics Japan Ltd | 半導体装置 |
DE102010064291B4 (de) * | 2010-12-28 | 2013-06-06 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verfahren zur Herstellung von Transistoren mit Metallgateelektrodenstrukturen mit großem ε mit einem polykristallinen Halbleitermaterial und eingebetteten verformungsinduzierenden Halbleiterlegierungen |
KR102015578B1 (ko) | 2012-09-11 | 2019-08-28 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그 형성방법 |
WO2016009473A1 (ja) * | 2014-07-14 | 2016-01-21 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置の製造方法、及び、半導体装置 |
JP5928658B1 (ja) * | 2014-08-07 | 2016-06-01 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
JP5989238B2 (ja) * | 2014-08-28 | 2016-09-07 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置、及び、半導体装置の製造方法 |
WO2016035213A1 (ja) * | 2014-09-05 | 2016-03-10 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置 |
WO2016110981A1 (ja) * | 2015-01-08 | 2016-07-14 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 柱状半導体装置と、その製造方法 |
JP6122556B2 (ja) * | 2015-03-03 | 2017-04-26 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置 |
-
2014
- 2014-07-14 WO PCT/JP2014/068707 patent/WO2016009473A1/ja active Application Filing
- 2014-07-14 JP JP2015513918A patent/JP5990843B2/ja active Active
-
2015
- 2015-06-18 US US14/743,570 patent/US9780179B2/en active Active
-
2017
- 2017-08-18 US US15/680,631 patent/US20170345908A1/en not_active Abandoned
- 2017-08-18 US US15/680,724 patent/US10483366B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0613623A (ja) * | 1992-03-02 | 1994-01-21 | Motorola Inc | 半導体装置 |
JPH10112543A (ja) * | 1996-10-04 | 1998-04-28 | Oki Electric Ind Co Ltd | 半導体素子および半導体素子の製造方法 |
JP2001028399A (ja) * | 1999-06-18 | 2001-01-30 | Lucent Technol Inc | 垂直方向トランジスタcmos集積回路の形成方法 |
JP2003163280A (ja) * | 2001-09-10 | 2003-06-06 | Agere Systems Guardian Corp | 垂直置換ゲート接合電界効果トランジスタ |
JP2007250652A (ja) * | 2006-03-14 | 2007-09-27 | Sharp Corp | 半導体装置 |
JP2011023543A (ja) * | 2009-07-15 | 2011-02-03 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPWO2016009473A1 (ja) | 2017-04-27 |
US20160013284A1 (en) | 2016-01-14 |
US20170345908A1 (en) | 2017-11-30 |
US10483366B2 (en) | 2019-11-19 |
JP5990843B2 (ja) | 2016-09-14 |
US9780179B2 (en) | 2017-10-03 |
US20170345909A1 (en) | 2017-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5990843B2 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP5731073B1 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP6065190B2 (ja) | 半導体装置 | |
JP5989238B2 (ja) | 半導体装置、及び、半導体装置の製造方法 | |
JP5928658B1 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP5902868B1 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP5654184B1 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
WO2016139755A1 (ja) | 半導体装置 | |
WO2014199433A1 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP6310500B2 (ja) | 半導体装置、及び、半導体装置の製造方法 | |
WO2015193939A1 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP5833214B2 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP5643900B2 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP6159777B2 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP6211637B2 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP6230648B2 (ja) | 半導体装置 | |
JP5869166B2 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP5926354B2 (ja) | 半導体装置 | |
JP6080989B2 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP6055883B2 (ja) | 半導体装置の製造方法、及び、半導体装置 | |
JP5980288B2 (ja) | 半導体装置 | |
JP2015233068A (ja) | 半導体装置 | |
JP2015233115A (ja) | 半導体装置 | |
JP2014207486A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ENP | Entry into the national phase |
Ref document number: 2015513918 Country of ref document: JP Kind code of ref document: A |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14897591 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 14897591 Country of ref document: EP Kind code of ref document: A1 |