WO2015199030A1 - 配線基板、半導体装置及び半導体装置の製造方法 - Google Patents

配線基板、半導体装置及び半導体装置の製造方法 Download PDF

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Publication number
WO2015199030A1
WO2015199030A1 PCT/JP2015/067892 JP2015067892W WO2015199030A1 WO 2015199030 A1 WO2015199030 A1 WO 2015199030A1 JP 2015067892 W JP2015067892 W JP 2015067892W WO 2015199030 A1 WO2015199030 A1 WO 2015199030A1
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Prior art keywords
layer
resin
support
semiconductor device
wiring board
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PCT/JP2015/067892
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English (en)
French (fr)
Inventor
小林　茜
泰人 芥川
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凸版印刷株式会社
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Application filed by 凸版印刷株式会社 filed Critical 凸版印刷株式会社
Priority to KR1020177001426A priority Critical patent/KR101995141B1/ko
Priority to EP15812648.2A priority patent/EP3163607A4/en
Priority to JP2016529572A priority patent/JPWO2015199030A1/ja
Priority to CN201580034451.XA priority patent/CN106463473A/zh
Publication of WO2015199030A1 publication Critical patent/WO2015199030A1/ja
Priority to US15/384,966 priority patent/US9735099B2/en

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Definitions

  • the present invention relates to a wiring board, a semiconductor device, and a method for manufacturing the semiconductor device.
  • Patent Document 1 describes a method of manufacturing a semiconductor device in which an external connection member having a rewiring layer and an external connection terminal is directly formed on a semiconductor chip. In this manufacturing method, an external connection member having a rewiring layer and external connection terminals is formed in the semiconductor chip region.
  • a semiconductor device provided by the manufacturing method is called a Fan-in type WLP (Wafer Level Package).
  • Patent Document 2 there is an external connection member that forms an insulating layer that covers the periphery of a semiconductor chip fixed to a support substrate, and that has a rewiring layer and an external connection terminal on the semiconductor chip and the insulating layer.
  • a method of manufacturing the semiconductor device to be formed is described. In this manufacturing method, the external connection member having the rewiring layer and the external connection terminals is also formed in the peripheral region outside the outer edge of the semiconductor chip.
  • a semiconductor device provided by the manufacturing method is called a fan-out type WLP.
  • a wiring board includes a support having transparency, an adhesive layer provided on a main surface of the support, a first resin layer, a second resin layer provided on the first resin layer, And a laminate provided at least between the first resin layer and the second resin layer and provided on the adhesive layer, and the adhesive layer is provided on the main surface of the support, It has a peeling layer containing a third resin that can be decomposed by light irradiation, and a protective layer that is provided on the peeling layer so as to protect the laminate from light and contains a fourth resin.
  • This wiring board is provided with a laminate functioning as an external connection member for connecting a semiconductor chip in a semiconductor device to an external device.
  • the semiconductor chip and the wiring substrate having the external connection member can be manufactured separately, which is used to improve the manufacturing efficiency of the semiconductor device.
  • the support has transparency. Thereby, by irradiating light to a peeling layer through a support body, 3rd resin decomposes
  • the protective layer between the release layer and the laminate it is possible to suppress the transmission of light energy to the laminate. Thereby, it can suppress that resin contained in the 1st resin layer and the 2nd resin layer of a layered product is decomposed. Therefore, since the support can be easily peeled off from the laminate after the semiconductor chip and the laminate of the wiring substrate are bonded, the semiconductor device manufactured using the wiring substrate can be thinned.
  • the linear expansion coefficient of the support may be ⁇ 1 ppm / ° C. or more and 10 ppm / ° C. or less.
  • the semiconductor chip is manufactured by a substrate mainly composed of an inorganic substance such as a silicon substrate, the linear expansion coefficient of the semiconductor chip and the linear expansion coefficient of the support are close to each other. Therefore, it is possible to suppress the positional deviation that occurs when the semiconductor chip is mounted on the wiring board.
  • the support may be a glass substrate.
  • the support is inexpensive and has high strength, and the support can be easily enlarged. Moreover, the roughness of the surface of a support body can be adjusted easily.
  • the maximum height roughness of the main surface of the support may be 0.01 ⁇ m or more and 5 ⁇ m or less. In this case, since the unevenness of the laminate provided on the support is reduced, disconnection and short circuit of the wiring pattern can be suppressed.
  • the protective layer may be a layer made of the fourth resin or a layer mainly composed of the fourth resin.
  • the protective layer can be removed with high selectivity with respect to the wiring pattern. As a result, etching of the wiring pattern and the like can be prevented, and good connection between the wiring pattern and the external device can be ensured. Therefore, the yield of semiconductor devices manufactured using the wiring board is improved.
  • the thickness of the laminated body may be 0.001 mm or more and 1 mm or less.
  • the wiring pattern in the laminate can be protected by the first resin layer and the second resin layer, and the warpage of the wiring board can be suppressed.
  • a semiconductor device includes any one of the wiring substrates described in the above paragraphs, in which a stacked body from which a support is removed and a protruding electrode is provided on one surface. And a semiconductor chip connected to the wiring pattern of the stacked body through the protruding electrodes.
  • the semiconductor chip and the laminated body as the external connection member are separately manufactured, the manufacturing efficiency of the semiconductor device is improved. Further, since the support in the wiring board is removed from the stacked body, the semiconductor device can be thinned.
  • the wiring pattern and the semiconductor chip may be connected to each other via a connection terminal containing solder.
  • the deviation can be filled by the connection terminals including the solder, and the connection failure generated between the semiconductor chip and the laminated body is eliminated. Can be suppressed.
  • connection terminal including gold.
  • the conductivity of the connection terminal is improved and corrosion of the connection terminal is suppressed.
  • a method for manufacturing a semiconductor device includes a step of preparing any of the wiring boards described in the above paragraph, a semiconductor chip mounted on a laminate of the wiring boards, and a wiring pattern. A step of bonding the semiconductor chip to the substrate, and a step of peeling the support from the laminate by irradiating the adhesive layer with light through the support.
  • the release layer is irradiated with light through the support, whereby the resin is decomposed and the adhesive strength of the release layer can be weakened. Therefore, since the support can be easily peeled off from the laminate after the semiconductor chip and the laminate of the wiring substrate are bonded, the semiconductor device manufactured using the wiring substrate can be thinned. Furthermore, handling can be facilitated by using a wiring substrate having a support when a semiconductor chip is mounted on the laminate.
  • the light may be laser light.
  • sufficient heat energy required for the resin in the release layer to decompose can be sufficiently applied, and the adhesive force of the release layer can be effectively weakened.
  • the semiconductor device manufacturing method may further include a step of covering the semiconductor chip bonded to the wiring pattern with a sealing resin.
  • the semiconductor chip can be protected by the sealing resin, and the detachment of the semiconductor chip from the stacked body can be suppressed.
  • the semiconductor device manufacturing method may further include a step of removing the adhesive layer from the laminated body after the step of peeling the support from the laminated body.
  • the method for manufacturing a semiconductor device may further include a step of providing an external connection terminal on the stacked body and a step of cutting the stacked body into pieces after the step of peeling the support from the stacked body. Good.
  • the wiring board used for the improvement of the manufacturing efficiency of the semiconductor device and the thinning of the semiconductor device can be reduced, and the manufacturing efficiency can be reduced.
  • a method of manufacturing the semiconductor device can be provided.
  • FIG. 1 is a diagram for explaining a semiconductor device manufactured using the wiring board of this embodiment.
  • FIG. 2 is a diagram illustrating the wiring board according to the present embodiment.
  • 3A to 3C are diagrams for explaining an example of a method of manufacturing a wiring board.
  • 4A to 4C are diagrams for explaining an example of a method of manufacturing a wiring board.
  • 5A to 5C are diagrams for explaining an example of a method for manufacturing a semiconductor device.
  • 6A to 6C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
  • 7A to 7C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
  • FIG. 8 is a diagram illustrating a part of a wiring board according to a modification.
  • 9A to 9C are views for explaining a method of manufacturing a wiring board according to the embodiment.
  • 10A to 10C are diagrams for explaining a method of manufacturing a wiring board according to the embodiment.
  • FIG. 1 is a diagram illustrating a semiconductor device manufactured using the wiring board of the present embodiment.
  • the semiconductor device 1 includes a stacked body 21, a semiconductor chip 22, an underfill 24, a mold resin 25, and a plurality of external connection terminals 31. Details of the laminated body 21 will be described later.
  • the semiconductor chip 22 is an integrated circuit (IC or LSI) having, for example, a transistor or a diode formed on the surface of a semiconductor substrate, and has a substantially rectangular parallelepiped shape.
  • a substrate mainly composed of an inorganic substance such as a silicon substrate (Si substrate), a gallium nitride substrate (GaN substrate), or a silicon carbide substrate (SiC substrate) is used.
  • a silicon substrate is used as the semiconductor substrate.
  • the linear expansion coefficient (CTE: Coefficient of Thermal Expansion) of the semiconductor chip 22 formed using the silicon substrate is about 2 to 4 ppm / ° C. (eg, 3 ppm / ° C.).
  • the linear expansion coefficient in the present embodiment is a length that changes in response to an increase in temperature within a temperature range of 20 ° C. to 260 ° C., for example.
  • Protruding electrodes (also referred to as bumps) 23 are provided on the surface 22 a of the semiconductor chip 22.
  • the semiconductor chip 22 is electrically connected to a wiring pattern (not shown) exposed on one main surface 21 a of the multilayer body 21 through the protruding electrodes 23.
  • the protruding electrode 23 is made of, for example, a metal such as Au, Ag, Cu, or Al or an alloy thereof, a metal composite obtained by applying Cu plating to Cu, or Sn, Sn—Pb, Sn—Ag, Sn—Cu, Sn. -Ag-Cu, Sn-Bi, or Au-based solder.
  • the protruding electrode 23 may be disposed in the entire region of the semiconductor chip 22 or may be disposed in the peripheral region of the semiconductor chip 22.
  • Examples of a method for connecting the wiring substrate 11 (not shown) and the semiconductor chip 22 to each other include a wire bonding method and a flip chip method.
  • the semiconductor chip 22 and the stacked body 21 are connected to each other by a flip chip method from the viewpoint of reducing the mounting area and improving the work efficiency.
  • the underfill 24 is an adhesive used for fixing and sealing the semiconductor chip 22 on the stacked body 21.
  • the underfill 24 for example, one of epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin or a mixture of two or more of these resins, silica as a filler, A material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added is used.
  • the underfill 24 may be liquid or film-shaped.
  • the mold resin 25 is a sealing resin used for covering and protecting the semiconductor chip 22.
  • the mold resin 25 for example, one of epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin or a mixture of two or more of these resins, silica as a filler, A material to which titanium oxide, aluminum oxide, magnesium oxide, zinc oxide, or the like is added is used.
  • the external connection terminal 31 is provided on the other main surface 21b of the multilayer body 21.
  • the external connection terminal 31 is electrically connected to the semiconductor chip 22 via a wiring pattern provided in the stacked body 21.
  • the external connection terminal 31 is formed of solder such as Sn, Sn—Pb, Sn—Ag, Sn—Cu, Sn—Ag—Cu, or Sn—Bi.
  • solder such as Sn, Sn—Pb, Sn—Ag, Sn—Cu, Sn—Ag—Cu, or Sn—Bi.
  • Ni plating, Au plating, or Sn plating is applied to a portion where the wiring pattern is exposed on the other main surface 21b of the multilayer body 21. May be applied, a pre-solder process may be applied, or an organic coating process such as OSP (Organic Solderability Preservative) may be applied.
  • OSP Organic Solderability Preservative
  • FIG. 2 is a diagram for explaining the wiring board of the present embodiment.
  • the wiring substrate 11 includes a support 12, an adhesive layer (adhesive layer) 13, and a laminate 21.
  • the stacked body 21 includes a first resin layer 14, connection pads 15, a wiring pattern 18, a second resin layer 19, and connection terminals 20.
  • the thickness of the laminated body 21 may be, for example, 0.001 mm or more and 1 mm or less, 0.01 mm or more and 0.8 mm or less, 0.03 mm or more and 0.5 mm or less, and 0 0.001 mm to 0.8 mm, 0.001 mm to 0.5 mm, 0.01 mm to 0.8 mm, 0.01 mm to 0.5 mm There may be.
  • the thickness of the laminated body 21 is 0.001 mm or more, the wiring pattern 18 provided in the laminated body 21 can be protected by the first resin layer 14 and the second resin layer 19.
  • the thickness of the laminated body 21 is 1 mm or less, the warp of the wiring board 11 due to the difference in the linear expansion coefficient between the support body 12 and the laminated body 21 can be suppressed.
  • the thickness of the laminated body 21 in this specification is the thickness direction from the upper surface of the adhesive layer 13 to the uppermost surface of the second resin layer 19 or the wiring pattern 18. That is, the “thickness” is a length along the direction perpendicular to the main surface of the wiring board 11.
  • the support 12 is a substrate made of a material having a property of transmitting light (transparency), for example.
  • the main surface 12a of the support 12 has, for example, a substantially rectangular shape, a substantially circular shape, or a substantially elliptical shape.
  • the range of the wavelength of light transmitted through the support 12 may be, for example, 300 nm or more and 2000 nm or less, or 300 nm or more and 1100 nm or less.
  • the support 12 may have a property of transmitting a specific wavelength such as laser light.
  • a glass substrate is used as the support 12, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, sapphire glass, or the like is used.
  • the linear expansion coefficient of glass is preferably close to the linear expansion coefficient of the semiconductor chip 22 described above, for example, ⁇ 1 ppm / ° C. or more and 10.0 ppm / ° C. or less (or 0.5 ppm / ° C. or more and 5.0 ppm / ° C.).
  • the maximum height roughness Rz on the main surface 12a of the support 12 based on JIS B 0601: 2013 may be, for example, 0.01 ⁇ m or more and 5 ⁇ m or less, or 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the maximum height roughness Rz of the main surface 12a of the support 12 is 0.01 ⁇ m or more, an increase in cost for preparing the support 12 can be suppressed.
  • the maximum height roughness Rz of the main surface 12a of the support 12 is 5 ⁇ m or less, disconnection, short circuit, and the like of the wiring pattern 18 due to the unevenness of the main surface 12a can be suppressed.
  • the adhesive layer 13 is a layer for adhering the support 12 and the laminate 21 to each other.
  • the adhesive layer 13 has a release layer 41 provided on the main surface 12 a of the support 12 and a protective layer 42 provided on the release layer 41.
  • the release layer 41 includes a resin (third resin) that can be decomposed by light irradiation. Since the light in this embodiment is laser light, a resin that can be thermally decomposed when irradiated with laser light is used as the resin included in the release layer 41.
  • the resin included in the release layer 41 include an epoxy resin, a polyurethane resin, a silicone resin, a polyester resin, an oxetane resin, and a resin in which two or more of these resins are mixed. It is done.
  • the thickness of the release layer 41 is, for example, 1 ⁇ m to 10 ⁇ m.
  • the protective layer 42 is configured to protect the laminate 21 from light irradiated through the support 12 from the outside.
  • the protective layer 42 for example, one of epoxy resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a resin (fourth resin) in which two or more of these resins are mixed is used. Used.
  • the protective layer 42 may be a layer made of the above resin or a layer containing the above resin as a main component.
  • the thickness of the protective layer 42 is sufficiently larger than the release layer 41 from the viewpoint of protecting the stacked body 21 from light, for example, 20 ⁇ m to 100 ⁇ m.
  • the first resin layer 14 is a resin layer provided on the adhesive layer 13 and has an opening 14a.
  • the first resin layer 14 includes, for example, a resin material such as epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer, or silicone, and a composite material thereof.
  • the first resin layer 14 may contain an inorganic filler or an organic filler.
  • the 1st resin layer 14 may also contain the material which the epoxy resin and glass fiber combined, for example.
  • a solder resist made of an epoxy insulating resin or the like may be used as the first resin layer 14, for example, a solder resist made of an epoxy insulating resin or the like may be used.
  • the thickness of the first resin layer 14 is, for example, 0.5 ⁇ m to 30 ⁇ m.
  • connection pad 15 is a conductive layer made of a metal such as Au, and is provided in the opening 14 a of the first resin layer 14.
  • the connection pad 15 may be in contact with the adhesive layer 13 in the opening 14a.
  • the thickness of the connection pad 15 is, for example, 0.001 ⁇ m to 3 ⁇ m.
  • the wiring pattern 18 is a conductive layer made of a metal such as Au, Cu, or Ni, and is provided on the first resin layer 14 and the connection pad 15.
  • the wiring pattern 18 is electrically connected to the connection pad 15 through the opening 14 a of the first resin layer 14.
  • the thickness of the wiring pattern 18 is, for example, 1 ⁇ m to 20 ⁇ m.
  • the second resin layer 19 is a resin layer provided on the first resin layer 14, the connection pads 15, and the wiring pattern 18, and has an opening 19a.
  • the second resin layer 19 includes, for example, a resin material such as epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer, or silicone, and a composite material thereof. Further, the second resin layer 19 may contain an inorganic filler or an organic filler.
  • the second resin layer 19 may include, for example, a material in which an epoxy resin and glass fiber are combined. As the second resin layer 19, for example, a solder resist made of an epoxy insulating resin or the like may be used.
  • the opening 19 a provided in the second resin layer 19 does not overlap the opening 14 a of the first resin layer 14 and is provided so as to expose a part of the wiring pattern 18.
  • the thickness of the second resin layer 19 is, for example, 0.5 ⁇ m to 30 ⁇ m.
  • connection terminal 20 is a terminal provided in the opening 19 a of the second resin layer 19, and is provided so that the wiring pattern 18 can be easily electrically connected to the protruding electrode 23 of the semiconductor chip 22.
  • the connection terminal 20 is formed of eutectic solder or lead-free solder (Sn—Ag, Sn—Cu, Sn—Ag—Cu, Sn—Bi, or the like), for example.
  • the connection terminal 20 may be a terminal in which eutectic solder or lead-free solder is provided on conductive layers made of various metals. Further, the connection terminal 20 may be formed by performing plating treatment of Ni, Au, Sn or the like on the opening 19a or organic coating treatment of OSP or the like.
  • connection terminal 20 may be formed by performing gold plating on the wiring pattern 18.
  • the conductivity of the connection terminal 20 is improved, and corrosion of the connection terminal 20 is suppressed.
  • the protruding electrode 23 of the semiconductor chip 22 is a gold ball bump (for example, a gold bump made of Au, an alloy containing Au, or a metal composite having a surface plated with Au, or a bump formed of Au-based solder). In this case, the bondability between the protruding electrode 23 and the connection terminal subjected to gold plating is improved.
  • FIGS. 3A to 3C and FIGS. 4A to 4C are diagrams for explaining an example of a method for manufacturing a wiring board.
  • the adhesive layer 13 including the peeling layer 41 and the protective layer 42 is formed on the main surface 12 a of the support 12.
  • the release layer 41 is formed by a known method such as a printing method, a vacuum press method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method.
  • the protective layer 42 is formed by a printing method, a vacuum press method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, a photolithography method, or a combination of these. Is done.
  • the first resin layer 14 is formed by a known method such as a printing method, a vacuum pressing method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. Is done.
  • the opening 14 a is formed by removing a part of the first resin layer 14 by, for example, performing laser irradiation or photolithography on the first resin layer 14.
  • the connection pad 15 is provided by plating, for example. The connection pad 15 is not necessarily provided.
  • a seed layer 16 is provided on the first resin layer 14 and the connection pad 15.
  • the seed layer 16 is connected to the connection pad 15 through the opening 14 a of the first resin layer 14.
  • the seed layer 16 is formed by, for example, an electroless plating method, a sputtering method, a CVD method, or the like.
  • the seed layer 16 may be formed by attaching a conductive foil made of Cu or the like to the first resin layer 14.
  • the seed layer 16 is formed of, for example, a Cu layer, a Cu layer plated with Ni, a Cu layer plated with Au, a Cu layer plated with solder, an Al layer, or an Ag / Pd alloy layer.
  • a Cu layer is used from the viewpoints of cost, electrical characteristics, and manufacturability.
  • a resist 17 having an opening 17 a is provided on the seed layer 16. Then, a part of the seed layer 16 exposed by the opening 17a is thickened by, for example, performing a plating process.
  • a thin region in the seed layer 16 is referred to as a first region 16a
  • a thick region is referred to as a second region 16b.
  • the first region 16 a is a region existing between the first resin layer 14 and the resist 17.
  • the second region 16b is formed of, for example, a Cu layer, a Cu layer plated with Ni, a Cu layer plated with Au, a Cu layer plated with solder, an Al layer, an Ag / Pd alloy layer, or the like.
  • a Cu layer is used from the viewpoints of cost, electrical characteristics, and manufacturability.
  • a negative type or positive type photoresist is used as the resist 17, for example.
  • the wiring pattern 18 is formed by removing the first region 16a in the resist 17 and the seed layer 16.
  • the resist 17 may be removed from the first resin layer 14 by, for example, lift-off, or may be removed by etching.
  • the first region 16a is removed by wet etching or dry etching, for example.
  • the second region 16 b becomes the wiring pattern 18.
  • a part of the second region 16b may be etched simultaneously with the first region 16a. That is, the wiring pattern 18 in the present embodiment is formed by a semi-additive method.
  • a seed layer such as a Cu layer is formed, a resist having a desired pattern is formed on the seed layer, and an exposed portion of the seed layer is thickened by an electrolytic plating method or the like to remove the resist. Thereafter, a thin seed layer is etched to obtain a wiring pattern.
  • the second resin layer 19 is formed on the first resin layer 14 and the wiring pattern 18, and an opening is formed in a part of the second resin layer 19.
  • a portion 19a is formed.
  • the second resin layer 19 is formed by a known method such as a printing method, a vacuum pressing method, a vacuum laminating method, a roll laminating method, a spin coating method, a die coating method, a curtain coating method, a roller coating method, or a photolithography method. Is done.
  • the opening 19a is formed by removing a part of the second resin layer 19 by performing laser irradiation or photolithography on the second resin layer 19, for example. A part of the wiring pattern 18 is exposed by forming the opening 19a.
  • connection terminal 20 is formed in the opening 19a.
  • the connection terminal 20 is provided by supplying eutectic solder or lead-free solder into the opening 19a, for example.
  • the wiring substrate 11 including the support 12, the adhesive layer 13, the first resin layer 14, the connection pad 15, the wiring pattern 18, the second resin layer 19, and the stacked body 21 including the connection terminals 20 is formed. .
  • FIGS. 5A to 5C, FIGS. 6A to 6C, and FIGS. 7A to 7C a semiconductor device using the wiring substrate according to the present embodiment is used. A method of manufacturing the will be described.
  • FIGS. 5A to 5C, FIGS. 6A to 6C, and FIGS. 7A to 7C are diagrams illustrating an example of a method for manufacturing a semiconductor device.
  • a wiring board 11 having a support 12, an adhesive layer 13, and a laminate 21 is prepared.
  • the wiring board 11 is equivalent to the wiring board 11 shown by FIG. 2 or FIG.
  • a plurality of semiconductor chips 22 are mounted on the wiring board 11.
  • the semiconductor chip 22 is mounted on one main surface 21a of the multilayer body 21 in the wiring board 11 by a flip chip method.
  • the protruding electrode 23 of the semiconductor chip 22 and the connection terminal 20 (see FIG. 2) of the wiring board 11 are connected to each other.
  • the semiconductor chip 22 and the wiring substrate 11 are fixed and sealed.
  • the underfill 24 may be supplied between the semiconductor chip 22 and the wiring substrate 11 after the semiconductor chip 22 is mounted on the wiring substrate 11.
  • the underfill 24 may be attached to the semiconductor chip 22 or the wiring board 11 in advance, and the sealing with the underfill 24 may be completed at the same time that the semiconductor chip 22 is mounted on the wiring board 11.
  • the semiconductor chip 22 and the wiring substrate 11 are fixed and sealed by the underfill 24 by applying a curing process to the underfill 24 by heating or light irradiation.
  • the underfill 24 is not necessarily provided.
  • a mold resin 25 is formed on one main surface 21 a of the laminate 21.
  • the semiconductor chip 22 is embedded with the mold resin 25.
  • the mold resin 25 is formed by a known method such as a transfer molding method or a potting method.
  • the semiconductor chip 22 may be covered so as to be sealed with the mold resin 25.
  • the adhesive layer 13 is irradiated with the laser light L through the support 12.
  • the laser beam L may be irradiated over the entire support 12, or the laser beam L may be irradiated to a desired position of the support 12.
  • the entire support 12 is irradiated with the laser light L while reciprocating linearly.
  • the laser beam L may have a wavelength of 300 nm to 2000 nm, may have a wavelength of 300 nm to 1500 nm, and may have a wavelength of 300 nm to 1100 nm.
  • a device that emits the laser light L there is a YAG laser device that emits light with a wavelength of 1064 nm, a second harmonic YAG laser device with a wavelength of 532 nm, or a semiconductor laser device that emits light with a wavelength of 780 to 1300 nm.
  • the support 12 has transparency and transmits the laser light L. Therefore, the energy of the laser beam L that has passed through the support 12 is absorbed by the adhesive layer 13. The absorbed energy of the laser beam L is converted into thermal energy in the adhesive layer 13. With this thermal energy, the resin of the release layer 41 reaches the thermal decomposition temperature and is thermally decomposed. As a result, the force with which the release layer 41 bonds the support 12 and the laminate 21 is weakened.
  • the support 12 is peeled from the laminate 21.
  • the method of peeling the support body 12 from the laminated body 21 may be performed manually or using a machine.
  • the adhesive layer 13 (more specifically, the protective layer 42) is removed from the laminate 21.
  • the peeling layer 41 remains, the adhesive layer 13 having the peeling layer 41 and the protective layer 42 is removed.
  • the adhesive layer 13 remaining on the other main surface 21 b is removed from the laminate 21 by peeling after sticking an adhesive tape to the other main surface 21 b of the laminate 21.
  • the other main surface 21b may be immersed in a mixed solution of an aqueous potassium permanganate solution and an aqueous sodium hydroxide solution to remove the adhesive layer 13, or the mixed solution may be sprayed on the other main surface 21b.
  • the adhesive layer 13 may be removed by Alternatively, the other main surface 21b may be immersed in an organic solvent such as acetone or methyl ethyl ketone to remove the adhesive layer 13, or the organic layer may be sprayed onto the other main surface 21b to remove the adhesive layer 13. May be.
  • the adhesive layer 13 may remain on the other main surface 21b, but in this case, it is necessary to form an opening for providing the external connection terminal 31 using a laser beam or the like. In this way, the support 12 and the adhesive layer 13 are removed from the laminate 21 as shown in FIG.
  • a plurality of external connection terminals 31 are formed on the other main surface 21 b of the stacked body 21.
  • the external connection terminals 31 are formed in portions corresponding to the connection pads 15 (see FIG. 2) of the multilayer body 21.
  • the external connection terminal 31 is formed by a solder ball mounting method or the like.
  • the laminate 21 and the mold resin 25 located in the region between the semiconductor chips 22 are cut and separated. Tidy up.
  • the laminate 21 and the mold resin 25 are cut using a dicing saw or a laser.
  • the semiconductor device 1 formed using the wiring substrate 11 is manufactured.
  • the semiconductor chip 22 in the semiconductor device 1 includes the stacked body 21 that functions as an external connection member for connecting to an external device.
  • the support 12 has transparency. Accordingly, the resin is decomposed by irradiating the release layer 41 with light through the support 12, and the adhesive force of the release layer 41 can be weakened. Therefore, after joining the semiconductor chip 22 and the laminated body 21 of the wiring board 11, the support 12 can be easily peeled from the laminated body 21, and the semiconductor device 1 manufactured using the wiring board 11 can be thin. Can be realized.
  • the adhesive layer 13 includes the release layer 41 and the protective layer 42, and the protective layer 42 is provided between the release layer 41 and the laminate 21, whereby light (for example, laser light) energy is applied to the laminate 21. Can be prevented from being transmitted. Therefore, the resin contained in the first resin layer 14 and the second resin layer 19 of the laminate 21 can be prevented from being decomposed. Further, by manufacturing the semiconductor device 1 using the wiring substrate 11 having the support 12, the wiring substrate 11 can be easily handled.
  • the linear expansion coefficient of the support 12 may be not less than ⁇ 1 ppm / ° C. and not more than 10 ppm / ° C.
  • the semiconductor chip 22 since the semiconductor chip 22 is manufactured from a substrate mainly composed of an inorganic substance such as a silicon substrate, the linear expansion coefficient of the semiconductor chip 22 and the linear expansion coefficient of the support 12 are close to each other. For this reason, it is possible to suppress the positional deviation that occurs when the semiconductor chip 22 is mounted on the wiring board 11. Therefore, it becomes possible to prevent the semiconductor chip 22 from being mounted on the wiring substrate 11 and to destroy the portion where the semiconductor chip 22 and the wiring substrate 11 are joined.
  • the support 12 may be a glass substrate.
  • the support 12 is inexpensive and high in strength, and the support 12 can be easily enlarged. Further, the roughness of the surface of the support 12 can be easily adjusted.
  • the maximum height roughness Rz of the main surface 12a of the support 12 may be not less than 0.01 ⁇ m and not more than 5 ⁇ m. In this case, since the unevenness of the stacked body 21 provided on the support 12 is reduced, disconnection and short circuit of the wiring pattern 18 can be suppressed.
  • the protective layer 42 may be a layer made of a resin or a layer mainly composed of a resin. In this case, the protective layer 42 can be removed with high selectivity with respect to the connection pad 15. Thereby, the etching of the connection pad 15 is prevented, and a good connection between the connection pad 15 and the external connection terminal 31 can be secured. Therefore, the yield of the semiconductor device 1 is improved.
  • the thickness of the laminated body 21 may be 0.001 mm or more and 1 mm or less.
  • the wiring pattern 18 in the laminate 21 can be protected by the first resin layer 14 and the second resin layer 19 and the warping of the wiring substrate 11 can be suppressed.
  • the light may be laser light L.
  • heat energy necessary for the resin in the release layer 41 to decompose can be sufficiently applied, and the adhesive force of the release layer 41 can be effectively weakened.
  • the adhesive force of the release layer 41 can be effectively weakened without damaging the semiconductor chip 22 with the laser beam L.
  • the semiconductor device 1 manufactured using the wiring substrate 11 according to the present embodiment includes the stacked body 21 from which the support 12 is removed, and the protruding electrode 23 on the surface 22a. And a semiconductor chip 22 connected to the wiring pattern 18 of the stacked body 21.
  • the semiconductor chip 22 and the stacked body 21 that is an external connection member are separately manufactured, the manufacturing efficiency of the semiconductor device 1 is improved.
  • the semiconductor device 1 can be thinned.
  • the wiring pattern 18 and the semiconductor chip 22 may be connected to each other via a connection terminal 20 containing solder.
  • the deviation can be filled with the solder included in the connection terminal 20, and the gap between the semiconductor chip 22 and the stacked body 21 can be filled. Connection failures that occur can be suppressed.
  • FIG. 8 is a diagram showing a part of connection wiring according to a modification.
  • the release layer 41 ⁇ / b> A of the adhesive layer 13 ⁇ / b> A may contain a metal such as copper, nickel, gold, silver, titanium, chromium, and aluminum and a metal oxide thereof.
  • This metal and metal oxide are, for example, particles 51 dispersed in the release layer 41A.
  • the particles 51 dispersed in the release layer 41A are more likely to absorb light energy such as laser light than the resin of the release layer 41A.
  • the light energy absorbed by the particles 51 is converted into thermal energy, and the thermal energy is transmitted into the release layer 41A, whereby the decomposition of the resin in the release layer 41A can be promoted.
  • the adhesive force of the release layer 41A can be sufficiently weakened, so that the transmission of light energy to the laminate 21 can be further suppressed. . Therefore, it can suppress suitably that resin contained in the 1st resin layer 14 and the 2nd resin layer 19 of layered product 21 is decomposed.
  • the metal or metal oxide contained in the release layer 41A may not be particles but may be fragments.
  • the wiring board, the semiconductor device, and the manufacturing method of the semiconductor device according to the present invention are not limited to the above-described embodiments, and various other modifications are possible. For example, you may combine the said embodiment and modification suitably. Further, a plurality of semiconductor chips 22 stacked on the stacked body 21 may be mounted in a region of the wiring board 11 to be separated. In addition, a member other than the semiconductor chip 22 (for example, a passive component such as a capacitor) may be mounted on the stacked body 21.
  • the opening 14a in the first resin layer 14 and the opening 19a in the second resin layer 19 may overlap each other.
  • the connection terminals 20 in the stacked body 21 are not necessarily provided.
  • the wiring pattern 18 on the wiring substrate 11 is formed not only by the semi-additive method but also by a known method such as a subtractive method or a full additive method.
  • the subtractive method is a method in which a resist having a desired pattern is formed on a conductor layer such as a Cu layer, an unnecessary conductor layer is etched, and then the resist is removed to obtain a wiring pattern.
  • the full additive method an electroless plating catalyst is first adsorbed on the resin layer, and a resist having a desired pattern is formed on the resin layer. Next, the catalyst is activated while leaving the resist as an insulating film, and a conductor such as Cu is deposited in the resist opening by electroless plating. Then, the resist is removed to obtain a desired wiring pattern.
  • a new wiring pattern and a third resin layer may be formed on the second resin layer 19. That is, the laminate 21 may have three resin layers. Furthermore, by repeating the formation of the wiring pattern and the resin layer described above, it is possible to form a laminate 21 in which a large number of wiring patterns and resin layers are stacked.
  • the release layer 41 and the protective layer 42 were formed in order on the main surface 12 a of the support 12.
  • glass OA-10G (manufactured by Nippon Electric Glass Co., Ltd.), 1.1 mm thickness) was used.
  • the linear expansion coefficient of the support 12 was about 4 ppm / ° C.
  • the release layer 41 on the main surface 12a of the support 12 was formed using 3M Light-To-Heat-Conversion (LTHC) Release Coating (Sumitomo 3M Limited).
  • the protective layer 42 was formed using 3M UV-Cable Adhesive LC-5200 (manufactured by Sumitomo 3M Limited).
  • the release layer 41 and the protective layer 42 were both formed by spin coating.
  • an opening 14 a was formed in the first resin layer 14.
  • the first resin layer 14 was formed on the protective layer 42 by a vacuum laminating method.
  • ABF-GX-T31 manufactured by Ajinomoto Fine Techno Co., Ltd.
  • the opening 14a was provided by laser irradiation.
  • the connection pad 15 was formed in the said opening part 14a by Au plating.
  • the wiring pattern 18 was formed by a semi-additive method.
  • the material of the wiring pattern 18 was Cu.
  • the second resin layer 19 was formed, and the opening 19 a was provided in the second resin layer 19.
  • the second resin layer 19 was formed on the first resin layer 14 and the wiring pattern 18 by a vacuum laminating method.
  • ABF-GX-T31 Alignment-GX-T31 (Ajinomoto Fine Techno Co., Ltd.) was used.
  • the opening 19a was provided by laser irradiation.
  • an OSP process is performed in the opening 19a to form a connection terminal 20A, thereby obtaining a wiring board 11A having a laminate 21.
  • the thickness of the laminate 21 composed of the first resin layer 14, the second resin layer 19, and the wiring pattern 18 was about 0.07 mm.
  • the semiconductor chip 22 was mounted on the obtained wiring board 11A.
  • a semiconductor chip 22 having a protruding electrode 23 having a Sn-3.5Ag solder layer formed on the tip of a Cu post was used. Further, the linear expansion coefficient of the semiconductor chip 22 was about 3 ppm / ° C.
  • An underfill 24 was previously supplied to the wiring board 11A. After aligning the protruding electrodes 23 of the semiconductor chip 22 and the connection terminals 20 of the wiring board 11A, the semiconductor chip 22 was pressure-bonded to the wiring board 11A and heated. Thereafter, the upper surface of the wiring substrate 11A including the semiconductor chip 22 was sealed with a molding resin 25 by a transfer molding method.
  • the support 12 was removed from the wiring substrate 11A by irradiating the entire support with a 1064 nm YAG laser while linearly reciprocating from the support 12 side of the wiring substrate 11A. Further, after the adhesive tape was applied to the laminate 21 and the protective layer 42, the protective layer 42 was removed from the wiring board 11 ⁇ / b> A by peeling the adhesive tape. Next, Sn-3Ag-0.5Cu solder balls were mounted on the laminate 21, and the external connection terminals 31 were formed. This structure was affixed to a dicing tape and diced to obtain the semiconductor device 1 shown in FIG.
  • the semiconductor device 1 produced as described above was observed with an X-ray fluoroscope (XVA-160 ⁇ , manufactured by Uniheight System Co., Ltd.).
  • XVA-160 ⁇ manufactured by Uniheight System Co., Ltd.
  • a positional deviation of about 2 ⁇ m from the design value occurred between the protruding electrode 23 of the semiconductor chip 22 and the connection terminal 20 of the wiring board 11 ⁇ / b> A.
  • a support made of polyimide having a relatively low linear expansion coefficient in the resin is used as a support for the wiring board used for forming the semiconductor device, the protruding electrode of the semiconductor chip and the connection terminal of the wiring board In general, a positional deviation of about 15 ⁇ m occurs from the design value.
  • the difference in displacement due to the material of the support is such that the linear expansion coefficient of the polyimide support is about 12 to 50 ppm / ° C., which is greatly different from the linear expansion coefficient of the semiconductor chip (about 2 to 4 ppm / ° C.). It is considered to be a body. Therefore, it was confirmed that the positional deviation generated between the semiconductor chip and the wiring board was smaller when the glass support was used for the wiring board than when the resin support was used.
  • the semiconductor device is used for improving the manufacturing efficiency of the semiconductor device and reducing the thickness of the semiconductor device, or reducing the thickness and manufacturing efficiency of the semiconductor device. Can be improved.
  • SYMBOLS 1 Semiconductor device 11, 11A ... Wiring board, 12 ... Support body, 13, 13A ... Adhesive layer, 14 ... 1st resin layer, 15 ... Connection pad, 16 ... Seed layer, 17 ... Resist, 18 ... Wiring pattern, DESCRIPTION OF SYMBOLS 19 ... 2nd resin layer, 20, 20A ... Connection terminal, 21 ... Laminated body, 22 ... Semiconductor chip, 23 ... Projection electrode, 24 ... Underfill, 25 ... Mold resin, 31 ... External connection terminal, 33 ... Dicing tape, 41 ... release layer, 42 ... protective layer, L ... laser beam.

Abstract

　半導体装置の製造効率の改善に供される配線基板１１は、透明性を有する支持体１２と、支持体１２の主面１２ａ上に設けられると共に、光の照射により分解可能な第３樹脂を含む剥離層４１、及び剥離層４１上に設けられると共に第４樹脂を含む保護層４２とを有する接着層１３と、第１樹脂層１４、第１樹脂層１４上に設けられる第２樹脂層１９、及び第１樹脂層１４及び第２樹脂層１９の間に少なくとも設けられる配線パターン１８を有し、接着層１３上に設けられる積層体２１と、を備える。これにより、半導体チップ２２と外部接続部材である配線基板１１とを別々に製造することができるため、半導体装置１の製造効率の改善に供される。

Description

配線基板、半導体装置及び半導体装置の製造方法
　本発明は、配線基板、半導体装置及び半導体装置の製造方法に関する。
　近年、半導体チップ及び外部接続部材を用いた半導体装置が、電子機器及び自動車等の様々な分野に用いられている。下記特許文献１には、半導体チップ上に再配線層及び外部接続端子を有する外部接続部材が直接形成される半導体装置の製造方法が記載されている。この製造方法では、再配線層及び外部接続端子を有する外部接続部材が半導体チップ領域内に形成される。当該製造方法によって設けられた半導体装置は、Ｆａｎ－ｉｎ型のＷＬＰ（Wafer　Level　Package：ウエハレベルパッケージ）と呼ばれている。
　また、下記特許文献２には、支持基板に固定された半導体チップの周囲を覆う絶縁層を形成し、当該半導体チップ上及び当該絶縁層上に再配線層及び外部接続端子を有する外部接続部材が形成される半導体装置の製造方法が記載されている。この製造方法では、半導体チップの外縁より外側の周辺領域にも再配線層及び外部接続端子を有する外部接続部材が形成される。当該製造方法によって設けられた半導体装置は、Ｆａｎ－ｏｕｔ型のＷＬＰと呼ばれている。
特開平１１－１１１８９６号公報 特開２０１１－１８７４７３号公報 特開２０１４－７３１５号公報
　上記特許文献１に記載される製造方法では、外部接続部材は半導体チップ領域内に形成されるため、外部接続端子の数及び位置が制限される。また、特許文献１，２に記載される製造方法では、個片化された半導体チップ上に直接外部接続部材を形成するので、半導体装置の製造効率が低くなる。
　本発明は、半導体装置の製造効率の改善に供される配線基板と、製造効率が改善された半導体装置と、当該半導体装置を製造する方法を提供することを目的とする。
　本発明の一態様に係る配線基板は、透明性を有する支持体と、支持体の主面上に設けられる接着層と、第１樹脂層、第１樹脂層上に設けられる第２樹脂層、及び第１樹脂層及び第２樹脂層の間に少なくとも設けられる配線パターンを有し、接着層上に設けられる積層体と、を備え、接着層は、支持体の主面上に設けられると共に、光の照射により分解可能な第３樹脂を含む剥離層と、光から積層体を保護するように剥離層上に設けられると共に第４樹脂を含む保護層とを有する。
　この配線基板では、半導体装置における半導体チップが外部装置と接続するための外部接続部材として機能する積層体が設けられている。これにより、半導体チップと外部接続部材を有する配線基板とを別々に製造することができるため、半導体装置の製造効率の改善に供される。また、この配線基板では支持体が透明性を有している。これにより、支持体を介して剥離層に光が照射されることによって第３樹脂が分解し、剥離層の接着力を弱めることができる。加えて、保護層が、剥離層と積層体との間に設けられることによって、積層体に光のエネルギーが伝達することを抑制できる。これにより、積層体の第１樹脂層及び第２樹脂層に含まれる樹脂が分解されることを抑制できる。したがって、半導体チップと配線基板の積層体とを接合した後に、容易に支持体を積層体から剥離することができるため、当該配線基板を用いて製造される半導体装置の薄型化が可能になる。
　また、支持体の線膨張係数は、－１ｐｐｍ／℃以上１０ｐｐｍ／℃以下であってもよい。この場合、半導体チップはシリコン基板等の無機物を主成分とした基板によって製造されているので、半導体チップの線膨張係数と支持体の線膨張係数とが互いに近い値となる。したがって、配線基板に半導体チップを搭載した際に発生する位置ずれを抑制することができる。
　また、支持体はガラス基板であってもよい。この場合、支持体を安価で強度を高くすると共に、支持体の大型化が容易となる。また、支持体の表面の粗さを容易に調整することができる。
　支持体の主面の最大高さ粗さは、０．０１μｍ以上５μｍ以下であってもよい。この場合、支持体上に設けられる積層体の凹凸が小さくなるため、配線パターンの断線及び短絡等を抑制できる。
　また、保護層が第４樹脂からなる層、または第４樹脂を主成分とした層であってもよい。この場合、配線パターンに対して選択性よく保護層を除去することができる。これにより、配線パターンのエッチング等を防ぎ、該配線パターンと外部装置との良好な接続が確保できる。したがって、配線基板を用いて製造される半導体装置の歩留まりが向上する。
　また、積層体の厚さは、０．００１ｍｍ以上１ｍｍ以下であってもよい。この場合、積層体における配線パターンを第１樹脂層及び第２樹脂層によって保護できると共に、配線基板の反りを抑制できる。
　また、本発明の他の一態様に係る半導体装置は、上記段落に記載されるいずれかの配線基板において、支持体が除去された積層体と、一表面に突起電極が設けられており、当該突起電極を介して積層体の配線パターンに接続される半導体チップと、を備える。この半導体装置では、半導体チップと外部接続部材である積層体とが別々に製造されているため、半導体装置の製造効率が改善される。また、配線基板における支持体が積層体から除去されていることによって、半導体装置の薄型化が可能になる。
　また、配線パターンと半導体チップとは、はんだを含む接続端子を介して互いに接続されていてもよい。この場合、配線パターンと半導体チップとの間に位置ずれが発生した場合であっても、はんだを含む接続端子によってずれを埋めることができ、半導体チップと積層体との間に発生する接続不良を抑制できる。
　また、配線パターンと半導体チップとは、金を含む接続端子を介して互いに接続されていてもよい。この場合、接続端子の導電性が向上すると共に、当該接続端子の腐食が抑制される。
　また、本発明の他の一態様に係る半導体装置の製造方法は、上記段落に記載されるいずれかの配線基板を準備する工程と、配線基板の積層体に半導体チップを搭載すると共に、配線パターンに半導体チップを接合する工程と、支持体を介して接着層に光を照射することによって、支持体を積層体から剥離する工程と、を備える。
　この半導体装置の製造方法によれば、支持体を介して剥離層に光が照射されることによって樹脂が分解し、剥離層の接着力を弱めることができる。したがって、半導体チップと配線基板の積層体とを接合した後に、容易に支持体を積層体から剥離することができるため、当該配線基板を用いて製造される半導体装置の薄型化が可能になる。さらに積層体に半導体チップを搭載する際に支持体を有する配線基板を用いることによって、ハンドリングを容易にすることができる。
　また、光はレーザー光であってもよい。この場合、剥離層内の樹脂が分解するために必要な熱エネルギーを十分に加えることができ、剥離層の接着力を効果的に弱めることができる。
　また、上記半導体装置の製造方法は、配線パターンに接合された半導体チップを封止樹脂で覆う工程を更に備えてもよい。この場合、半導体チップを封止樹脂によって保護することができると共に、半導体チップの積層体からの脱離を抑制できる。
　また、上記半導体装置の製造方法は、支持体を積層体から剥離した工程後、積層体から接着層を除去する工程を更に備えてもよい。
　また、上記半導体装置の製造方法は、支持体を積層体から剥離した工程後、積層体に外部接続端子を設ける工程と、積層体を切断して個片化する工程と、を更に備えてもよい。
　本発明の配線基板、半導体装置、及び当該半導体装置を製造する方法によれば、半導体装置の製造効率の改善及び当該半導体装置の薄型化に供される配線基板と、薄型化が可能となり製造効率が改善された半導体装置と、当該半導体装置を製造する方法を提供できる。
図１は、本実施形態の配線基板を用いて製造された半導体装置を説明する図である。 図２は、本実施形態の配線基板を説明する図である。 図３（ａ）～（ｃ）は、配線基板の製造方法の一例を説明する図である。 図４（ａ）～（ｃ）は、配線基板の製造方法の一例を説明する図である。 図５（ａ）～（ｃ）は、半導体装置の製造方法の一例を説明する図である。 図６（ａ）～（ｃ）は、半導体装置の製造方法の一例を説明する図である。 図７（ａ）～（ｃ）は、半導体装置の製造方法の一例を説明する図である。 図８は、変形例に係る配線基板の一部を示す図である。 図９（ａ）～（ｃ）は、実施例の配線基板の製造方法を説明する図である。 図１０（ａ）～（ｃ）は、実施例の配線基板の製造方法を説明する図である。
　以下、添付図面を参照して、本発明の好適な実施形態について詳細に説明する。なお、以下の説明において、同一要素又は同一機能を有する要素には、同一符号を用いることとし、重複する説明は省略する。
　図１は、本実施形態の配線基板を用いて製造された半導体装置を説明する図である。図１に示されるように、半導体装置１は、積層体２１と、半導体チップ２２と、アンダーフィル２４と、モールド樹脂２５と、複数の外部接続端子３１とを備えている。なお、積層体２１の詳細については後述する。
　半導体チップ２２は、例えば半導体基板表面に形成されるトランジスタ又はダイオード等を有する集積回路（ＩＣ又はＬＳＩ）であり、略直方体形状を有している。半導体チップ２２に用いられる半導体基板は、例えばシリコン基板（Ｓｉ基板）、窒化ガリウム基板（ＧａＮ基板）、又は炭化ケイ素基板（ＳｉＣ基板）等の無機物を主成分とした基板が用いられる。本実施形態では、半導体基板としてシリコン基板が用いられる。シリコン基板を用いて形成される半導体チップ２２の線膨張係数（ＣＴＥ：Coefficient　of　Thermal　Expansion）は、約２～４ｐｐｍ／℃（例えば３ｐｐｍ／℃）である。本実施形態における線膨張係数は、例えば２０℃～２６０℃の温度範囲内における温度の上昇に対応して変化する長さとする。
　半導体チップ２２の表面２２ａには、突起電極（バンプとも言う）２３が設けられている。半導体チップ２２は、この突起電極２３を介して積層体２１の一方の主面２１ａにて露出する配線パターン（図示せず）と電気的に接続している。突起電極２３は、例えばＡｕ、Ａｇ、Ｃｕ、Ａｌ等の金属もしくはこれらの合金、ＣｕにＡｕめっき等を施した金属複合体、又は、Ｓｎ、Ｓｎ－Ｐｂ、Ｓｎ－Ａｇ、Ｓｎ－Ｃｕ、Ｓｎ－Ａｇ－Ｃｕ、Ｓｎ－ＢｉもしくはＡｕ系等のはんだによって形成される。突起電極２３は、半導体チップ２２の領域内全体に配置されていてもよいし、半導体チップ２２の周辺領域に配置されていてもよい。配線基板１１（図示せず）と半導体チップ２２とを互いに接続する方式としては、例えばワイヤボンディング方式又はフリップチップ方式が挙げられる。本実施形態では、実装面積の縮小化及び作業の効率化の観点から、フリップチップ方式によって半導体チップ２２及び積層体２１が互いに接続されている。
　アンダーフィル２４は、半導体チップ２２を積層体２１上に固定及び封止するために用いられる接着剤である。アンダーフィル２４としては、例えば、エポキシ樹脂、ポリウレタン樹脂、シリコーン樹脂、ポリエステル樹脂、オキセタン樹脂、及びマレイミド樹脂の内の１種又はこれらの樹脂の２種類以上が混合された樹脂に、フィラーとしてシリカ、酸化チタン、酸化アルミニウム、酸化マグネシウム、又は酸化亜鉛等を加えた材料が用いられる。アンダーフィル２４は、液状であってもよいし、フィルム状であってもよい。
　モールド樹脂２５は、半導体チップ２２を覆って封止及び保護するために用いられる封止樹脂である。モールド樹脂２５としては、例えば、エポキシ樹脂、ポリウレタン樹脂、シリコーン樹脂、ポリエステル樹脂、オキセタン樹脂、及びマレイミド樹脂の内の１種又はこれらの樹脂の２種類以上が混合された樹脂に、フィラーとしてシリカ、酸化チタン、酸化アルミニウム、酸化マグネシウム、又は酸化亜鉛等を加えた材料が用いられる。
　外部接続端子３１は、積層体２１の他方の主面２１ｂ上に設けられている。外部接続端子３１は、積層体２１内に設けられている配線パターンを介して半導体チップ２２と電気的に接続している。外部接続端子３１は、例えばＳｎ、Ｓｎ－Ｐｂ、Ｓｎ－Ａｇ、Ｓｎ－Ｃｕ、Ｓｎ－Ａｇ－Ｃｕ、又はＳｎ－Ｂｉ等のはんだによって形成される。外部接続端子３１がはんだから形成される場合、外部接続端子３１を形成する前、積層体２１の他方の主面２１ｂにて配線パターンが露出した部分に、例えばＮｉめっき、Ａｕめっき、又はＳｎめっきが施されてもよく、プレソルダー処理が施されてもよく、ＯＳＰ（Ｏｒｇａｎｉｃ　Ｓｏｌｄｅｒａｂｉｌｉｔｙ　Ｐｒｅｓｅｒｖａｔｉｖｅ）等の有機被膜処理が施されてもよい。
　図２は、本実施形態の配線基板を説明する図である。図２に示されるように、配線基板１１は、支持体１２と、接着層（接着剤層）１３と、積層体２１とを備えている。積層体２１は、第１樹脂層１４、接続パッド１５、配線パターン１８、第２樹脂層１９、及び接続端子２０を有している。積層体２１の厚さは、例えば０．００１ｍｍ以上１ｍｍ以下であってもよく、０．０１ｍｍ以上０．８ｍｍ以下であってもよく、０．０３ｍｍ以上０．５ｍｍ以下であってもよく、０．００１ｍｍ以上０．８ｍｍ以下であってもよく、０．００１ｍｍ以上０．５ｍｍ以下であってもよく、０．０１ｍｍ以上０．８ｍｍ以下であってもよく、０．０１ｍｍ以上０．５ｍｍ以下であってもよい。積層体２１の厚さが０．００１ｍｍ以上であることによって、積層体２１に設けられる配線パターン１８を第１樹脂層１４及び第２樹脂層１９によって保護することができる。積層体２１の厚さが１ｍｍ以下であることによって、支持体１２と積層体２１との線膨張係数等の差に起因した配線基板１１の反りを抑制できる。なお、本明細書における積層体２１の厚さとは、接着層１３の上面から第２樹脂層１９又は配線パターン１８の最上面に至るまでの厚み方向である。つまり、「厚さ」とは、配線基板１１の主面に対する垂直方向に沿った長さとする。
　支持体１２は、例えば光を透過する性質（透明性）を有する材料から構成される基板である。支持体１２の主面１２ａは、例えば略矩形状、略円形状、又は略楕円形状等である。支持体１２が透過する光の波長の範囲は、例えば３００ｎｍ以上２０００ｎｍ以下でもよく、３００ｎｍ以上１１００ｎｍ以下でもよい。支持体１２は、例えばレーザー光のような特定の波長を透過する性質を有するものでもよい。支持体１２は、例えばガラス基板が用いられる。ガラスとしては、例えば石英ガラス、ホウケイ酸ガラス、無アルカリガラス、ソーダガラス、又はサファイアガラス等が用いられる。ガラスの線膨張係数は、上述した半導体チップ２２の線膨張係数と近い値であることが好ましく、例えば－１ｐｐｍ／℃以上１０．０ｐｐｍ／℃以下（又は０．５ｐｐｍ／℃以上５．０ｐｐｍ／℃以下）である。ＪＩＳ　Ｂ　０６０１：２０１３に基づいた支持体１２の主面１２ａにおける最大高さ粗さＲｚは、例えば０．０１μｍ以上５μｍ以下でもよく、０．１μｍ以上３μｍ以下でもよい。支持体１２の主面１２ａの最大高さ粗さＲｚが０．０１μｍ以上であることによって、支持体１２を準備するコストの増加を抑制することができる。支持体１２の主面１２ａの最大高さ粗さＲｚが５μｍ以下であることによって、主面１２ａの凹凸に起因した配線パターン１８の断線及び短絡等を抑制できる。
　接着層１３は、支持体１２と積層体２１とを互いに接着させるための層である。接着層１３は、支持体１２の主面１２ａ上に設けられる剥離層４１と、剥離層４１上に設けられる保護層４２とを有している。
　剥離層４１は、光の照射により分解可能な樹脂（第３樹脂）を含んでいる。本実施形態における光はレーザー光であるので、剥離層４１に含まれる樹脂として、レーザー光が照射されることによって熱分解可能な樹脂が用いられる。剥離層４１に含まれる樹脂としては、例えばエポキシ樹脂、ポリウレタン樹脂、シリコーン樹脂、ポリエステル樹脂、オキセタン樹脂、及びマレイミド樹脂の内の１種又はこれらの樹脂の２種類以上が混合された樹脂等が用いられる。剥離層４１の厚さは、例えば１μｍ～１０μｍである。
　保護層４２は、外部から支持体１２を介して照射される光から積層体２１を保護するように構成されている。保護層４２としては、例えばエポキシ樹脂、ポリウレタン樹脂、シリコーン樹脂、ポリエステル樹脂、オキセタン樹脂、及びマレイミド樹脂の内の１種又はこれらの樹脂の２種類以上が混合された樹脂（第４樹脂）等が用いられる。保護層４２が上記樹脂からなる層、または上記樹脂を主成分とした層にしてもよい。保護層４２の厚さは、積層体２１を光から保護する観点から、剥離層４１よりも十分に大きく、例えば２０μｍ～１００μｍである。
　第１樹脂層１４は、接着層１３上に設けられる樹脂層であり、開口部１４ａを有している。第１樹脂層１４は、例えばエポキシ樹脂、ポリイミド、マレイミド樹脂、ポリエチレンテレフタラート、ポリフェニレンオキシド、液晶ポリマー、又はシリコーン等の樹脂材料及びこれらの複合材料を含む。また、第１樹脂層１４には、無機フィラー又は有機フィラーが含まれていてもよい。第１樹脂層１４は、例えばエポキシ樹脂及びガラス繊維が組み合わせた材料を含んでもよい。第１樹脂層１４として、例えばエポキシ系の絶縁性樹脂等からなるソルダーレジストが用いられてもよい。第１樹脂層１４の厚さは、例えば０．５μｍ～３０μｍである。
　接続パッド１５は、例えばＡｕ等の金属から構成される導電層であり、第１樹脂層１４の開口部１４ａ内に設けられている。接続パッド１５は、開口部１４ａ内において接着層１３と接していてもよい。接続パッド１５の厚さは、例えば０．００１μｍ～３μｍである。
　配線パターン１８は、例えばＡｕ、Ｃｕ、Ｎｉ等の金属から構成される導電層であり、第１樹脂層１４及び接続パッド１５上に設けられている。配線パターン１８は、第１樹脂層１４の開口部１４ａを介して接続パッド１５に電気的に接続されている。配線パターン１８の厚さは、例えば１μｍ～２０μｍである。
　第２樹脂層１９は、第１樹脂層１４、接続パッド１５、及び配線パターン１８上に設けられる樹脂層であり、開口部１９ａを有している。第２樹脂層１９は、例えばエポキシ樹脂、ポリイミド、マレイミド樹脂、ポリエチレンテレフタラート、ポリフェニレンオキシド、液晶ポリマー、又はシリコーン等の樹脂材料及びこれらの複合材料を含む。また、第２樹脂層１９には、無機フィラー又は有機フィラーが含まれていてもよい。第２樹脂層１９は、例えばエポキシ樹脂及びガラス繊維が組み合わせた材料を含んでもよい。第２樹脂層１９として、例えばエポキシ系の絶縁性樹脂等からなるソルダーレジストが用いられてもよい。第２樹脂層１９に設けられている開口部１９ａは、第１樹脂層１４の開口部１４ａと重なっておらず、配線パターン１８の一部を露出するように設けられている。第２樹脂層１９の厚さは、例えば０．５μｍ～３０μｍである。
　接続端子２０は、第２樹脂層１９の開口部１９ａ内に設けられる端子であり、配線パターン１８が半導体チップ２２の突起電極２３と電気的接続しやすいように設けられている。接続端子２０は、例えば共晶はんだ又は鉛フリーはんだ（Ｓｎ－Ａｇ、Ｓｎ－Ｃｕ、Ｓｎ－Ａｇ－Ｃｕ、又はＳｎ－Ｂｉ等）によって形成される。接続端子２０は、種々の金属からなる導電層上に共晶はんだ又は鉛フリーはんだが設けられた端子でもよい。また、開口部１９ａに、Ｎｉ、Ａｕ、Ｓｎ等のめっき処理を施す、又はＯＳＰ等の有機被膜処理を施すことにより、接続端子２０を形成してもよい。また、接続端子２０は、配線パターン１８に金めっきを行うことにより形成してもよい。この場合、接続端子２０の導電性が向上すると共に、接続端子２０の腐食が抑制される。半導体チップ２２の突起電極２３が金ボールバンプ（例えば、Ａｕ、Ａｕを含む合金、もしくは表面にＡｕめっきを施した金属複合体による金バンプ、又は、Ａｕ系のはんだによって形成されたバンプ）である場合、当該突起電極２３と金めっきが施された接続端子との接合性が向上する。
　次に、図３（ａ）～（ｃ）及び図４（ａ）～（ｃ）を参照しながら、本実施形態に係る配線基板の製造方法を説明する。図３（ａ）～（ｃ）及び図４（ａ）～（ｃ）は、配線基板の製造方法の一例を説明する図である。
　まず、図３（ａ）に示されるように、支持体１２の主面１２ａ上に剥離層４１及び保護層４２を含む接着層１３を形成する。剥離層４１は、例えば印刷法、真空プレス法、真空ラミネート法、ロールラミネート法、スピンコート法、ダイコート法、カーテンコート法、ローラーコート法、又はフォトリソグラフィー法等の公知の方法にて形成される。また、保護層４２は、印刷法、真空プレス法、真空ラミネート法、ロールラミネート法、スピンコート法、ダイコート法、カーテンコート法、ローラーコート法、又はフォトリソグラフィー法等およびこれらを組み合わせた方法によって形成される。
　次に、図３（ｂ）に示されるように、接着層１３上に第１樹脂層１４を設けた後、当該第１樹脂層１４に開口部１４ａを形成する。そして、当該開口部１４ａ内に接続パッド１５を形成する。第１樹脂層１４は、例えば印刷法、真空プレス法、真空ラミネート法、ロールラミネート法、スピンコート法、ダイコート法、カーテンコート法、ローラーコート法、又はフォトリソグラフィー法等の公知の方法にて形成される。開口部１４ａは、例えば第１樹脂層１４に対してレーザーの照射、又はフォトリソグラフィーを行い、第１樹脂層１４の一部を除去することによって形成される。接続パッド１５は、例えばめっき処理によって設けられる。接続パッド１５は、必ずしも設けなくてもよい。
　次に、図３（ｃ）に示されるように、第１樹脂層１４及び接続パッド１５上にシード層１６を設ける。シード層１６は、第１樹脂層１４の開口部１４ａを介して接続パッド１５に接続されている。シード層１６は、例えば無電解めっき法、スパッタ法、又はＣＶＤ法等によって形成される。また、第１樹脂層１４にＣｕ等から構成される導体箔を貼り付けることによって、シード層１６を形成してもよい。シード層１６は、例えばＣｕ層、ＮｉめっきがなされたＣｕ層、ＡｕめっきがなされたＣｕ層、はんだめっきがなされたＣｕ層、Ａｌ層、又はＡｇ／Ｐｄ合金層等によって形成される。本実施形態では、コスト、電気特性、及び製造容易性の観点からＣｕ層が用いられる。
　次に、図４（ａ）に示されるように、シード層１６上に開口部１７ａを有するレジスト１７を設ける。そして、開口部１７ａによって露出されたシード層１６の一部に、例えばめっき処理を施すことによって当該一部を厚くする。ここで、シード層１６における薄い領域を第１領域１６ａとし、厚い領域を第２領域１６ｂとする。第１領域１６ａは、第１樹脂層１４及びレジスト１７の間に存在する領域である。第２領域１６ｂは、例えばＣｕ層、ＮｉめっきがなされたＣｕ層、ＡｕめっきがなされたＣｕ層、はんだめっきがなされたＣｕ層、Ａｌ層、又はＡｇ／Ｐｄ合金層等によって形成される。本実施形態では、コスト、電気特性、及び製造容易性の観点からＣｕ層が用いられる。また、レジスト１７としては、例えばネガ型又はポジ型のフォトレジストが用いられる。
　次に、図４（ｂ）に示されるように、レジスト１７及びシード層１６における第１領域１６ａを除去することによって配線パターン１８を形成する。レジスト１７は、例えばリフトオフによって第１樹脂層１４上から除去されてもよいし、エッチングによって除去されてもよい。第１領域１６ａは、例えばウェットエッチング又はドライエッチングによって除去される。第１領域１６ａが除去されることによって、第２領域１６ｂが配線パターン１８となる。第２領域１６ｂの一部は、第１領域１６ａと同時にエッチングされてもよい。すなわち、本実施形態における配線パターン１８は、セミアディティブ法によって形成される。セミアディティブ法とは、Ｃｕ層等のシード層を形成し、所望のパターンを有するレジストをシード層上に形成し、シード層における露出した部分を電解めっき法等により厚膜化し、レジストを除去した後、薄いシード層をエッチングして配線パターンを得る方法である。
　また、図４（ｂ）に示されるように、配線パターン１８の形成後、第２樹脂層１９を第１樹脂層１４及び配線パターン１８上に形成し、第２樹脂層１９の一部に開口部１９ａを形成する。第２樹脂層１９は、例えば印刷法、真空プレス法、真空ラミネート法、ロールラミネート法、スピンコート法、ダイコート法、カーテンコート法、ローラーコート法、又はフォトリソグラフィー法等の公知の方法にて形成される。開口部１９ａは、例えば第２樹脂層１９に対してレーザーの照射、又はフォトリソグラフィーを行い、第２樹脂層１９の一部を除去することによって形成される。開口部１９ａの形成によって、配線パターン１８の一部が露出される。
　最後に、図４（ｃ）に示されるように、開口部１９ａ内に接続端子２０を形成する。接続端子２０は、例えば共晶はんだ又は鉛フリーはんだを開口部１９ａ内に供給することによって設けられる。以上によって、支持体１２と、接着層１３と、第１樹脂層１４、接続パッド１５、配線パターン１８、第２樹脂層１９及び接続端子２０を含む積層体２１とを有する配線基板１１を形成する。
　次に、図５（ａ）～（ｃ）、図６（ａ）～（ｃ）、及び図７（ａ）～（ｃ）を参照しながら、本実施形態に係る配線基板を用いて半導体装置を製造する方法を説明する。図５（ａ）～（ｃ）、図６（ａ）～（ｃ）及び図７（ａ）～（ｃ）は、半導体装置の製造方法の一例を説明する図である。
　まず、図５（ａ）に示されるように、支持体１２、接着層１３、及び積層体２１を有する配線基板１１を準備する。配線基板１１は、図２又は図４（ｃ）によって示される配線基板１１と同等である。
　次に、図５（ｂ）に示されるように、配線基板１１に複数の半導体チップ２２を搭載する。具体的には、配線基板１１における積層体２１の一方の主面２１ａ上に、半導体チップ２２をフリップチップ方式にて搭載する。半導体チップ２２を配線基板１１に搭載する際、半導体チップ２２の突起電極２３と配線基板１１の接続端子２０（図２を参照）とが、互いに接続される。また、半導体チップ２２及び配線基板１１の間にアンダーフィル２４を設けておくことによって、半導体チップ２２及び配線基板１１を固定及び封止する。アンダーフィル２４は、半導体チップ２２を配線基板１１に搭載した後に、半導体チップ２２及び配線基板１１の間に供給してもよい。また、半導体チップ２２又は配線基板１１に予めアンダーフィル２４を付着しておき、半導体チップ２２を配線基板１１に搭載すると同時にアンダーフィル２４による封止を完了させてもよい。例えば、加熱又は光照射による硬化処理をアンダーフィル２４に施すことによって、アンダーフィル２４による半導体チップ２２及び配線基板１１の固定及び封止を行う。アンダーフィル２４は、必ずしも設けなくてもよい。
　次に、図５（ｃ）に示されるように、積層体２１の一方の主面２１ａ上にモールド樹脂２５を形成する。この際、モールド樹脂２５によって半導体チップ２２を埋設する。モールド樹脂２５は、例えばトランスファーモールド法又はポッティング法等の公知の方法にて形成される。半導体チップ２２は、モールド樹脂２５によって封止されるように覆われていてもよい。
　次に、図６（ａ）に示されるように、支持体１２を介して接着層１３にレーザー光Ｌを照射する。支持体１２全体に渡ってレーザー光Ｌを照射してもよいし、支持体１２の所望の位置にレーザー光Ｌを照射してもよい。本実施形態では、接着層１３内の剥離層４１の樹脂を確実に分解する観点から、直線的に往復させながら支持体１２全体にレーザー光Ｌを照射する。レーザー光Ｌは、例えば３００ｎｍ以上２０００ｎｍ以下の波長を有してもよく、３００ｎｍ以上１５００ｎｍ以下の波長を有していてもよく、３００ｎｍ以上１１００ｎｍ以下の波長を有していてもよい。レーザー光Ｌを出射する装置の一例として１０６４ｎｍの波長の光を出射するＹＡＧレーザー装置、５３２ｎｍの波長の２倍高調波ＹＡＧレーザー装置、又は７８０～１３００ｎｍの波長の光を出射する半導体レーザー装置等が挙げられる。支持体１２は透明性を有しており、レーザー光Ｌを透過する。よって、支持体１２を透過したレーザー光Ｌのエネルギーは、接着層１３に吸収される。吸収されたレーザー光Ｌのエネルギーは、接着層１３内にて熱エネルギーに変換される。この熱エネルギーによって、剥離層４１の樹脂は熱分解温度に達し、熱分解する。これによって、剥離層４１が支持体１２と積層体２１とを接着する力が弱まる。
　次に、図６（ｂ）に示されるように、積層体２１から支持体１２を剥離する。支持体１２を積層体２１から剥離する方法は、手動でもよいし機械を用いて行ってもよい。次に、積層体２１から接着層１３（より具体的には、保護層４２）を除去する。剥離層４１が残存している場合、剥離層４１及び保護層４２を有する接着層１３を除去する。例えば、積層体２１の他方の主面２１ｂに粘着テープを貼り付けた後ピールすることにより、他方の主面２１ｂ上に残存していた接着層１３を積層体２１から除去する。また、他方の主面２１ｂを過マンガン酸カリウム水溶液及び水酸化ナトリウム水溶液の混合溶液等に浸漬して接着層１３を除去してもよいし、当該混合溶液を他方の主面２１ｂにスプレーすることによって接着層１３を除去してもよい。また、他方の主面２１ｂをアセトン又はメチルエチルケトン等の有機溶剤に浸漬して接着層１３を除去してもよいし、当該有機溶剤を他方の主面２１ｂにスプレーすることによって接着層１３を除去してもよい。また、接着層１３を他方の主面２１ｂに残存したままでもよいが、この場合、レーザー光等を用いて外部接続端子３１を設けるための開口部を形成させる必要がある。以上により、図６（ｃ）に示されるように、積層体２１から支持体１２及び接着層１３を除去する。
　次に、図７（ａ）に示されるように、積層体２１の他方の主面２１ｂ上に複数の外部接続端子３１を形成する。具体的には、積層体２１の接続パッド１５（図２を参照）に相当する部分に、外部接続端子３１を形成する。例えばはんだボール搭載法等によって外部接続端子３１を形成する。
　次に、図７（ｂ）に示されるように、モールド樹脂２５にダイシングテープ３３を貼り付けた後、各半導体チップ２２の間の領域に位置する積層体２１及びモールド樹脂２５を切断し、個片化する。例えばダイシングソー又はレーザー等を用いて積層体２１及びモールド樹脂２５を切断する。以上により、図７（ｃ）に示されるように、配線基板１１を用いて形成された半導体装置１が製造される。
　以上に説明した本実施形態に係る配線基板１１では、半導体装置１における半導体チップ２２が外部装置と接続するための外部接続部材として機能する積層体２１を備えている。これにより、半導体チップ２２と外部接続部材を有する配線基板１１とを別々に製造することができるため、半導体装置１の製造効率の改善に供される。また、この配線基板１１では支持体１２が透明性を有している。これにより、支持体１２を介して剥離層４１に光が照射されることによって樹脂が分解し、剥離層４１の接着力を弱めることができる。したがって、半導体チップ２２と配線基板１１の積層体２１とを接合した後に、容易に支持体１２を積層体２１から剥離することができ、当該配線基板１１を用いて製造される半導体装置１の薄型化が可能になる。加えて、接着層１３が剥離層４１及び保護層４２を有すると共に、保護層４２が剥離層４１と積層体２１との間に設けられることによって、積層体２１に光（例えばレーザー光）のエネルギーが伝達することを抑制できる。したがって、積層体２１の第１樹脂層１４及び第２樹脂層１９に含まれる樹脂が分解されることを抑制できる。さらに支持体１２を有する配線基板１１を用いて半導体装置１を製造することによって、配線基板１１のハンドリングを容易にすることができる。
　また、支持体１２の線膨張係数は、－１ｐｐｍ／℃以上１０ｐｐｍ／℃以下であってもよい。この場合、半導体チップ２２はシリコン基板等の無機物を主成分とした基板によって製造されているので、半導体チップ２２の線膨張係数と支持体１２の線膨張係数とが互いに近い値となる。このため、配線基板１１に半導体チップ２２を搭載した際に発生する位置ずれを抑制することができる。したがって、半導体チップ２２が配線基板１１に搭載不可能となること、及び半導体チップ２２と配線基板１１とを接合する部分が破壊することが抑制される。
　また、支持体１２はガラス基板であってもよい。この場合、支持体１２を安価で強度を高くすると共に、支持体１２の大型化が容易にできる。また、支持体１２の表面の粗さを容易に調整することができる。
　支持体１２の主面１２ａの最大高さ粗さＲｚは、０．０１μｍ以上５μｍ以下であってもよい。この場合、支持体１２上に設けられる積層体２１の凹凸が小さくなるため、配線パターン１８の断線及び短絡等を抑制できる。
　また、保護層４２が樹脂からなる層、または樹脂を主成分とした層であってもよい。この場合、接続パッド１５に対して選択性よく保護層４２を除去することができる。これにより、接続パッド１５のエッチング等を防ぎ、該接続パッド１５と外部接続端子３１との良好な接続が確保できる。したがって、半導体装置１の歩留まりが向上する。
　また、積層体２１の厚さは、０．００１ｍｍ以上１ｍｍ以下であってもよい。この場合、積層体２１における配線パターン１８を第１樹脂層１４及び第２樹脂層１９によって保護できると共に、配線基板１１の反りを抑制できる。
　また、光はレーザー光Ｌであってもよい。この場合、剥離層４１内の樹脂が分解するために必要な熱エネルギーを十分に加えることができ、剥離層４１の接着力を効果的に弱めることができる。また、レーザー光Ｌは支持体１２を介して剥離層４１に照射されるため、半導体チップ２２にレーザー光Ｌによるダメージを与えずに剥離層４１の接着力を効果的に弱めることができる。
　また、本実施形態に係る配線基板１１を用いて製造される半導体装置１は、支持体１２が除去された積層体２１と、表面２２ａに突起電極２３が設けられており、当該突起電極２３を介して積層体２１の配線パターン１８に接続される半導体チップ２２と、を備えている。この半導体装置１では、半導体チップ２２と外部接続部材である積層体２１とが別々に製造されているため、半導体装置１の製造効率が改善される。また、配線基板１１における支持体１２が積層体２１から除去されていることによって、半導体装置１の薄型化が可能になる。
　また、配線パターン１８と半導体チップ２２とは、はんだを含む接続端子２０を介して互いに接続されていてもよい。この場合、配線パターン１８と半導体チップ２２との間に位置ずれが発生した場合であっても、接続端子２０が含むはんだによってずれを埋めることができ、半導体チップ２２と積層体２１との間に発生する接続不良を抑制できる。
　図８は、変形例に係る接続配線の一部を示す図である。図８に示されるように、接着層１３Ａの剥離層４１Ａは、銅、ニッケル、金、銀、チタン、クロム、アルミニウム等の金属およびこれらの金属酸化物を含んでいてもよい。この金属及び金属酸化物は、例えば剥離層４１Ａに分散する粒子５１である。剥離層４１Ａ内に分散した粒子５１は、剥離層４１Ａの樹脂よりもレーザー光等の光のエネルギーを吸収しやすい。粒子５１によって吸収された光エネルギーが熱エネルギーに変換され、該熱エネルギーが剥離層４１Ａ内に伝達することにより、剥離層４１Ａ内の樹脂の分解を促進できる。これにより、配線基板１１に照射される光のエネルギーの総量を低減しても剥離層４１Ａの接着力を十分に弱めることができるので、積層体２１に光のエネルギーが伝達することを一層抑制できる。したがって、積層体２１の第１樹脂層１４及び第２樹脂層１９に含まれる樹脂が分解されることを好適に抑制できる。なお、剥離層４１Ａ内に含まれる金属又は金属酸化物は、粒子ではなく破片等でもよい。
　本発明による配線基板、半導体装置及び半導体装置の製造方法は、上述した実施形態に限られるものではなく、他に様々な変形が可能である。例えば、上記実施形態及び変形例を適宜組み合わせてもよい。また、積層体２１に積層される半導体チップ２２は、個片化される配線基板１１の領域に複数搭載されてもよい。また、積層体２１には、半導体チップ２２以外の部材（例えばコンデンサ等の受動部品）が搭載されていてもよい。
　また、例えば第１樹脂層１４における開口部１４ａと第２樹脂層１９における開口部１９ａとは、互いに重なっていてもよい。さらに、例えば積層体２１における接続端子２０は、必ずしも設けられていなくてもよい。
　また、配線基板１１における配線パターン１８は、セミアディティブ法に限らず、例えばサブトラクティブ法又はフルアディティブ法等の公知の方法にて形成される。ここで、サブトラクティブ法とは、Ｃｕ層等の導体層上に所望のパターンを有するレジストを形成して不要な導体層をエッチングした後、レジストを剥離して配線パターンを得る方法である。また、フルアディティブ法は、まず樹脂層上に無電解めっき触媒を吸着させ、所望のパターンのレジストを樹脂層上に形成する。次に、このレジストを絶縁膜として残したまま触媒を活性化させ、無電解めっき法によりレジスト開口部内にＣｕ等の導体を析出させる。そして、レジストを除去して所望の配線パターンを得る方法である。
　また、第２樹脂層１９上に、新たな配線パターンと第３樹脂層とを形成してもよい。つまり、積層体２１は、樹脂層を３層有してもよい。さらに、上述した配線パターン及び樹脂層の形成を繰り返すことによって、配線パターン及び樹脂層が多数積層された積層体２１を形成することもできる。
　本発明を以下の実施例によりさらに詳細に説明するが、本発明はこれらの例に限定されるものではない。
（配線基板）
　実施例では、まず、図９（ａ）に示されるように、支持体１２の主面１２ａ上に剥離層４１及び保護層４２を順に形成した。支持体１２として、ガラス（ＯＡ－１０Ｇ（日本電気硝子株式会社製）、１．１ｍｍ厚）を使用した。支持体１２の線膨張係数は、約４ｐｐｍ／℃であった。支持体１２の主面１２ａ上の剥離層４１は、３Ｍ　Ｌｉｇｈｔ－Ｔｏ－Ｈｅａｔ－Ｃｏｎｖｅｒｓｉｏｎ（ＬＴＨＣ）Ｒｅｌｅａｓｅ　Ｃｏａｔｉｎｇ（住友スリーエム株式会社製）を用いて形成した。保護層４２は、３Ｍ　ＵＶ－Ｃｕｒａｂｌｅ　Ａｄｈｅｓｉｖｅ　ＬＣ－５２００（住友スリーエム株式会社製）を用いて形成した。剥離層４１及び保護層４２は、いずれもスピンコート法により形成した。
　次に、図９（ｂ）に示されるように、保護層４２上に第１樹脂層１４を設けた後、当該第１樹脂層１４に開口部１４ａを形成した。第１樹脂層１４は、真空ラミネート法によって保護層４２上に形成した。第１樹脂層１４として、ＡＢＦ－ＧＸ－Ｔ３１（味の素ファインテクノ株式会社製）を使用した。開口部１４ａは、レーザー照射により設けた。そして、当該開口部１４ａ内に接続パッド１５をＡｕめっきにより形成した。
　次に、図９（ｃ）～図１０（ｂ）に示されるように、接続パッド１５を形成した後、セミアディティブ法によって配線パターン１８を形成した。配線パターン１８の材料はＣｕとした。また、配線パターン１８を形成した後、第２樹脂層１９を形成し、開口部１９ａを第２樹脂層１９に設けた。第２樹脂層１９は、真空ラミネート法によって第１樹脂層１４及び配線パターン１８上に形成した。第２樹脂層１９として、ＡＢＦ－ＧＸ－Ｔ３１（味の素ファインテクノ株式会社製）を使用した。開口部１９ａは、レーザー照射により設けた。
　最後に、図１０（ｃ）に示されるように、開口部１９ａ内にＯＳＰ処理を施すことにより接続端子２０Ａを形成することによって、積層体２１を有する配線基板１１Ａを得た。第１樹脂層１４、第２樹脂層１９及び配線パターン１８からなる積層体２１の厚さは、約０．０７ｍｍだった。
（半導体装置）
　次に、得られた配線基板１１Ａに半導体チップ２２を搭載した。半導体チップ２２は、Ｃｕポストの先端にＳｎ－３．５Ａｇはんだ層を形成した突起電極２３を有しているものを用いた。また、半導体チップ２２の線膨張係数は、約３ｐｐｍ／℃であった。配線基板１１Ａには予めアンダーフィル２４を供給しておいた。半導体チップ２２の突起電極２３と配線基板１１Ａの接続端子２０との位置合わせを行った後、半導体チップ２２を配線基板１１Ａに圧着させ、加熱した。この後、半導体チップ２２を含む配線基板１１Ａの上面を、トランスファーモールド法により、モールド樹脂２５を用いて封止した。そして、配線基板１１Ａの支持体１２側より、直線的に往復させながら支持体全体に１０６４ｎｍのＹＡＧレーザーを照射し、支持体１２を配線基板１１Ａより取り除いた。さらに、積層体２１及び保護層４２に粘着テープを貼り付けた後に当該粘着テープをピールすることにより、保護層４２を配線基板１１Ａより除去した。次に、積層体２１にＳｎ－３Ａｇ－０．５Ｃｕはんだボールを搭載し、外部接続端子３１を形成した。この構成体をダイシングテープに貼り付け、ダイシングすることによって、図１に示される半導体装置１を得た。
（Ｘ線透視装置による観察）
　上記のようにして作成された半導体装置１について、Ｘ線透視装置（株式会社ユニハイトシステム製、ＸＶＡ－１６０α）にて観察を行った。半導体装置１を観察した結果、半導体チップ２２の突起電極２３と配線基板１１Ａの接続端子２０との間には、設計値から約２μｍの位置ずれが生じていた。ここで、半導体装置の形成に用いられる配線基板の支持体として、樹脂の中で線膨張係数が比較的低いポリイミド製の支持体を用いた場合、半導体チップの突起電極と当該配線基板の接続端子との間には、通常、設計値から約１５μｍの位置ずれが生じる。このような支持体の材質による位置ずれの違いは、ポリイミド製の支持体の線膨張係数は約１２～５０ｐｐｍ／℃であり、半導体チップの線膨張係数（約２～４ｐｐｍ／℃）と大きく異なるからだと考えられる。したがって、配線基板にガラス製の支持体を用いた方が、樹脂製の支持体を用いるよりも、半導体チップと配線基板との間に発生する位置ずれが小さくなっていることが確認できた。
　本発明の配線基板、半導体装置、及び当該半導体装置を製造する方法によれば、半導体装置の製造効率の改善及び当該半導体装置の薄型化に供される、又は半導体装置の薄型化及び製造効率を改善することができる。
　１…半導体装置、１１，１１Ａ…配線基板、１２…支持体、１３，１３Ａ…接着層、１４…第１樹脂層、１５…接続パッド、１６…シード層、１７…レジスト、１８…配線パターン、１９…第２樹脂層、２０，２０Ａ…接続端子、２１…積層体、２２…半導体チップ、２３…突起電極、２４…アンダーフィル、２５…モールド樹脂、３１…外部接続端子、３３…ダイシングテープ、４１…剥離層、４２…保護層、Ｌ…レーザー光。

Claims (14)

  1. 　透明性を有する支持体と、
    　前記支持体の主面上に設けられる接着層と、
    　第１樹脂層、前記第１樹脂層上に設けられる第２樹脂層、及び前記第１樹脂層及び第２樹脂層の間に少なくとも設けられる配線パターンを有し、前記接着層上に設けられる積層体と、
    を備え、
    　前記接着層は、前記支持体の前記主面上に設けられると共に光の照射により分解可能な第３樹脂を含む剥離層と、前記光から前記積層体を保護するように前記剥離層上に設けられると共に第４樹脂を含む保護層とを有する、
    配線基板。
  2. 　前記支持体の線膨張係数は、－１ｐｐｍ／℃以上１０ｐｐｍ／℃以下である、請求項１に記載の配線基板。
  3. 　前記支持体は、ガラス基板である、請求項１又は２に記載の配線基板。
  4. 　前記支持体の前記主面の最大高さ粗さは、０．０１μｍ以上５μｍ以下である、請求項１～３のいずれか一項に記載の配線基板。
  5. 　前記保護層が前記第４樹脂からなる層、または前記第４樹脂を主成分とした層である、請求項１～４のいずれか一項に記載の配線基板。
  6. 　前記積層体の厚さは、０．００１ｍｍ以上１ｍｍ以下である、請求項１～５のいずれか一項に記載の配線基板。
  7. 　請求項１～６のいずれか一項に記載される配線基板において、前記支持体が除去された前記積層体と、
    　表面に突起電極が設けられており、当該突起電極を介して前記積層体の前記配線パターンに接続される半導体チップと、
    を備える半導体装置。
  8. 　前記配線パターンと前記半導体チップとは、はんだを含む接続端子を介して互いに接続されている、請求項７に記載の半導体装置。
  9. 　前記配線パターンと前記半導体チップとは、金を含む接続端子を介して互いに接続されている、請求項７又は８に記載の半導体装置。
  10. 　請求項１～６のいずれか一項に記載される配線基板を準備する工程と、
    　前記配線基板の前記積層体に半導体チップを搭載すると共に、前記配線パターンに前記半導体チップを接合する工程と、
    　前記支持体を介して前記接着層に光を照射することによって、前記支持体を前記積層体から剥離する工程と、
    を備える半導体装置の製造方法。
  11. 　前記光は、レーザー光である、請求項１０に記載の半導体装置の製造方法。
  12. 　前記配線パターンに接合された前記半導体チップを封止樹脂で覆う工程を更に備える請求項１０又は１１に記載の半導体装置の製造方法。
  13. 　前記支持体を前記積層体から剥離した前記工程後、前記積層体から前記接着層を除去する工程を更に備える請求項１０～１２のいずれか一項に記載の半導体装置の製造方法。
  14. 　前記支持体を前記積層体から剥離した前記工程後、前記積層体に外部接続端子を設ける工程と、
    　前記積層体を切断して個片化する工程と、を更に備える請求項１０～１３のいずれか一項に記載の半導体装置の製造方法。
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