WO2015118721A1 - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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Publication number
WO2015118721A1
WO2015118721A1 PCT/JP2014/076722 JP2014076722W WO2015118721A1 WO 2015118721 A1 WO2015118721 A1 WO 2015118721A1 JP 2014076722 W JP2014076722 W JP 2014076722W WO 2015118721 A1 WO2015118721 A1 WO 2015118721A1
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Prior art keywords
region
type
outer peripheral
exposed
semiconductor device
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Ceased
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PCT/JP2014/076722
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English (en)
French (fr)
Japanese (ja)
Inventor
秀史 高谷
順 斎藤
明高 添野
濱田　公守
水野　祥司
佐智子 青井
渡辺　行彦
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Denso Corp
Toyota Motor Corp
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Denso Corp
Toyota Motor Corp
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Priority to CN201480075197.3A priority Critical patent/CN105981173B/zh
Priority to DE112014006350.9T priority patent/DE112014006350B4/de
Priority to US15/116,288 priority patent/US9640651B2/en
Publication of WO2015118721A1 publication Critical patent/WO2015118721A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/761—PN junctions
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    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
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    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • the technology disclosed in this specification relates to a semiconductor device.
  • the semiconductor device disclosed in Japanese Patent Laid-Open No. 2008-135522 has a MOSFET and a plurality of termination trenches formed around the MOSFET. Each termination trench extends in an annular shape so as to surround a region where the MOSFET is formed. An insulating layer is disposed in each termination trench. A p-type floating region is formed in the semiconductor layer in the range in contact with the bottom surface of each termination trench. When the MOSFET is turned off, a depletion layer extends from the body region of the MOSFET toward the outer peripheral side (region where the termination trench is formed). When the depletion layer extends to the p-type floating region below the innermost termination trench, the depletion layer further extends from the p-type floating toward the outer peripheral side.
  • the depletion layer when the depletion layer extends to the adjacent p-type floating region, the depletion layer extends further to the outer peripheral side from the p-type floating region. Thus, the depletion layer spreads widely around the region where the MOSFET is formed, passing through each p-type floating region. Thereby, the breakdown voltage of the semiconductor device is improved.
  • the p-type floating region described above is formed by forming a termination trench, implanting p-type impurities into the bottom surface of the termination trench, and then diffusing the implanted p-type impurities into the semiconductor layer.
  • the diffusion distance of the p-type impurity may be shortened, and the interval between the p-type floating regions may not be sufficiently narrowed. In such a case, it becomes difficult to sufficiently extend the depletion layer in the region of the interval.
  • the semiconductor device has a semiconductor substrate.
  • the semiconductor device includes an n-type first region exposed in the surface of the semiconductor substrate, a p-type second region disposed below the first region, and the second An n-type third region disposed below the region and separated from the first region by the second region, and formed on the surface and penetrating through the first region and the second region A plurality of gate trenches reaching the third region, a first insulating layer disposed in the gate trench, a second insulating layer disposed in the gate trench, and the second insulating layer interposed between the second insulating layer and the second insulating layer.
  • the plurality of gate trenches are formed when the surface is viewed in plan. Termination trench that goes around the area A second insulating layer disposed in the termination trench, a p-type lower end p-type region in contact with the lower end of the termination trench, and an outer peripheral side of the termination trench, and is in contact with the termination trench A p-type outer peripheral p-type region exposed on the surface, and a plurality of p-type guard ring regions formed on the outer peripheral side of the outer peripheral p-type region and exposed on the surface; The outer peripheral p-type region is separated from the plurality of guard ring regions, and the plurality of guard ring regions are separated from each other. The n-type peripheral n-type region is separated.
  • the outer peripheral side means a direction away from a region where a plurality of gate trenches are formed.
  • region mentioned above may be connected with the outer periphery p-type area
  • a switching element is formed by the first region, the second region, the third region, the fourth region, and the gate electrode.
  • a depletion layer spreads from the second region to the third region.
  • the depletion layer reaches the lower end of the gate trench.
  • the depletion layer reaches the fourth region.
  • a depletion layer also spreads from the fourth region into the third region.
  • a breakdown voltage in the region where the switching element is formed is ensured.
  • the depletion layer that extends from the second region to the third region reaches the lower end of the termination trench, the depletion layer reaches the lower end p-type region.
  • the depletion layer extends from the lower end p-type region and the outer peripheral p-type region into the outer peripheral n-type region.
  • the depletion layer extending from the outer peripheral p-type region reaches the guard ring region adjacent to the outer peripheral p-type region, the depletion layer further extends from the guard ring region toward the adjacent guard ring region.
  • the depletion layer extends toward the outer peripheral side via each guard ring region.
  • the depletion layer extends widely in the outer peripheral region, and a breakdown voltage is secured.
  • extension of the depletion layer can be promoted by the guard ring exposed on the surface of the semiconductor substrate.
  • the guard ring region is formed in a range exposed on the surface of the semiconductor substrate, it can be formed with high accuracy. For this reason, the space
  • the surface may have a first surface and a second surface protruding from the first surface by forming a stepped portion on the surface.
  • the termination trench may be formed in the second surface.
  • the outer peripheral p-type region may be exposed in a range extending from the second surface to the first surface.
  • the plurality of guard ring regions may be exposed on the first surface. In this case, an interval between the termination trench and the stepped portion may be 10 ⁇ m or more.
  • the end of the outer peripheral p-type region on the outer peripheral side and exposed to the surface is an Al high concentration region in which the Al concentration is higher than the B concentration.
  • the region adjacent to the Al high concentration region in the peripheral p-type region may be a B high concentration region in which the B concentration is higher than the Al concentration.
  • the width of the Al high concentration region may be wider than the width of each guard ring region.
  • variety means the dimension in the direction which goes to an outer peripheral side from an inner peripheral side.
  • leakage current in the outer peripheral p-type region can be suppressed.
  • a part of the lower end p-type region extends to the inner peripheral side from the termination trench, and the lower end p-type region extends to the inner peripheral side from the termination trench.
  • the part may not extend above the lower end of the termination trench.
  • the guard ring region may contain Al.
  • the guard ring region can be formed with higher accuracy.
  • the semiconductor device having the steps described above may be manufactured by the following method.
  • This method includes growing a p-type layer on the n-type layer, removing a part of the p-type layer, exposing the surface of the n-type layer, and exposing the p-type layer.
  • a step of forming a surface protruding from the surface where the n-type layer is exposed, and a range extending from the surface where the n-type layer is exposed to the surface where the p-type layer is exposed Forming the peripheral p-type region by implanting p-type impurities into the surface, and forming the guard ring region by implanting p-type impurities into the surface where the n-type layer is exposed. And forming a termination trench on the surface where the p-type layer is exposed.
  • FIG. 2 is a plan view of the semiconductor device 10.
  • FIG. 2 is a longitudinal sectional view taken along line II-II in FIG. The expanded sectional view of the outer periphery p-type area
  • FIG. 4 is a graph showing an impurity concentration distribution along the line AA in FIG. 3.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • FIG. 6 is an explanatory diagram of a manufacturing process of the semiconductor device 10.
  • the graph which shows the relationship between width W3 and DS pressure
  • the semiconductor device 10 includes a semiconductor substrate 12 made of SiC (silicon carbide).
  • the semiconductor substrate 12 has a MOSFET region 20 and an outer peripheral region 50.
  • a MOSFET is formed in the MOSFET region 20.
  • the outer peripheral region 50 is a region outside the MOSFET region 20.
  • the outer peripheral region 50 is a region between the MOSFET region 20 and the end face 12 a of the semiconductor substrate 12.
  • a breakdown voltage structure is formed in the outer peripheral region 50.
  • FIG. 1 only the termination trench 54, the boundary p-type region 59, and the guard ring region 64 are shown in the outer peripheral region 50 in consideration of easy viewing.
  • a source region 22, a body region 26, a drift region 28, a drain region 30, a p-type floating region 32, a gate trench 34, a source electrode 36, and a drain electrode 38 are formed in the MOSFET region 20. ing.
  • a plurality of source regions 22 are formed in the MOSFET region 20.
  • the source region 22 is an n-type region containing an n-type impurity at a high concentration.
  • the source region 22 is formed in a range exposed on the upper surface of the semiconductor substrate 12.
  • the body region 26 is formed on the side and the lower side of the source region 22 and is in contact with the source region 22.
  • Body region 26 is a p-type region.
  • the body region 26 is exposed on the upper surface of the semiconductor substrate 12 at a position where the source region 22 is not formed.
  • the drift region 28 is an n-type region containing n-type impurities at a low concentration.
  • the n-type impurity concentration of the drift region 28 is lower than the n-type impurity concentration of the source region 22.
  • the drift region 28 is formed below the body region 26. The drift region 28 is in contact with the body region 26 and is separated from the source region 22 by the body region 26.
  • the drain region 30 is an n-type region containing an n-type impurity at a high concentration.
  • the n-type impurity concentration of the drain region 30 is higher than the n-type impurity concentration of the drift region 28.
  • the drain region 30 is formed below the drift region 28. Drain region 30 is in contact with drift region 28 and is separated from body region 26 by drift region 28.
  • the drain region 30 is formed in a range exposed on the lower surface of the semiconductor substrate 12.
  • a plurality of gate trenches 34 are formed in the MOSFET region 20.
  • the gate trench 34 is a groove formed on the upper surface of the semiconductor substrate 12.
  • Each gate trench 34 is formed so as to penetrate the source region 22 and the body region 26 and reach the drift region 28.
  • the plurality of gate trenches 34 extend in parallel to each other.
  • a bottom insulating layer 34a, a gate insulating film 34b, and a gate electrode 34c are formed in each gate trench 34.
  • the bottom insulating layer 34 a is a thick insulating layer formed at the bottom of the gate trench 34.
  • a side surface of the gate trench 34 above the bottom insulating layer 34a is covered with a gate insulating film 34b.
  • a gate electrode 34c is formed in the gate trench 34 above the bottom insulating layer 34a.
  • the gate electrode 34c is opposed to the source region 22, the body region 26, and the drift region 28 through the gate insulating film 34b.
  • the gate electrode 34c is insulated from the semiconductor substrate 12 by the gate insulating film 34b and the bottom insulating layer 34a.
  • the upper surface of the gate electrode 34c is covered with an insulating layer 34d.
  • the p-type floating region 32 is formed in the semiconductor substrate 12 in a range in contact with the bottom surface (that is, the lower end) of each gate trench 34.
  • the periphery of the p-type floating region 32 is surrounded by the drift region 28.
  • the p-type floating regions 32 are separated from each other by the drift region 28.
  • Each p-type floating region 32 is separated from the body region 26 by the drift region 28.
  • the source electrode 36 is formed on the upper surface of the semiconductor substrate 12 in the MOSFET region 20.
  • the source electrode 36 is electrically connected to the source region 22 and the body region 26.
  • the drain electrode 38 is formed on the lower surface of the semiconductor substrate 12.
  • the drain electrode 38 is electrically connected to the drain region 30.
  • drift region 28 and drain region 30 extend to the outer peripheral region 50.
  • the drift region 28 and the drain region 30 extend to the end face 12 a of the semiconductor substrate 12.
  • the drain electrode 38 is formed on the entire lower surface of the semiconductor substrate 12 including the outer peripheral region 50. Further, the upper surface of the semiconductor substrate 12 in the outer peripheral region 50 is covered with an insulating layer 52.
  • the drift region 28 in the MOSFET region 20 may be referred to as an element portion drift region 28a
  • the drift region 28 in the outer periphery region 50 may be referred to as an outer periphery drift region 28b.
  • a stepped portion 70 is formed on the surface of the semiconductor substrate 12 in the outer peripheral region 50.
  • the stepped portion 70 divides the surface of the semiconductor substrate 12 into a surface 72 on the central portion side and a surface 74 on the end surface 12a side.
  • the surface 72 protrudes upward with respect to the surface 74.
  • the thickness of the semiconductor substrate 12 is thicker at the portion corresponding to the surface 72 than at the portion corresponding to the surface 74.
  • the MOSFET region 20 described above is formed in a portion corresponding to the surface 72 (a portion having a large thickness).
  • the height of the stepped portion 70 is larger than the thickness of the body region 26. Therefore, the front surface 74 is located on the lower side (back surface side) than the lower end of the body region 26.
  • a termination trench 54 is formed on the surface 72 of the semiconductor substrate 12 in the outer peripheral region 50.
  • An insulating layer 53 is formed in the termination trench 54.
  • the termination trench 54 is formed at a position adjacent to the body region 26.
  • the termination trench 54 has substantially the same depth as the gate trench 34. Therefore, the insulating layer 53 is in contact with the element portion drift region 28 a at a position deeper than the body region 26.
  • the termination trench 54 extends around the MOSFET region 20 when the surface of the semiconductor substrate 12 is viewed in plan. Therefore, body region 26 is separated from any p-type region in outer peripheral region 50 by insulating layer 53. That is, in this embodiment, the region surrounded by the termination trench 54 is the MOSFET region 20.
  • a lower end p-type region 60 is formed at a position in contact with the lower end (that is, the bottom surface) of the termination trench 54.
  • the lower end p-type region 60 is not formed in the MOSFET region 20.
  • an outer peripheral p-type region 62 is formed in a region on the outer peripheral side of the termination trench 54 and in a position in contact with the termination trench 54.
  • the outer peripheral p-type region 62 is formed from the position exposed at the surface 72 to the position exposed at the surface 74.
  • the outer peripheral p-type region 62 is exposed on the surface 72, the stepped portion 70 and the surface 74.
  • the outer peripheral p-type region 62 extends to a position deeper than the lower end of the termination trench 54. As shown in the drawing, in this embodiment, the lower end p-type region 60 and the outer peripheral p-type region 62 are connected. Since the lower end p-type region 60 and the outer peripheral p-type region 62 are one p-type region, hereinafter, these may be collectively referred to as a boundary portion p-type region 59. That is, the boundary p-type region 59 is a p-type region extending across the position exposed at the lower end of the termination trench 54, the position exposed at the surface 72, and the position exposed at the surface 74. As shown in FIG. 1, the boundary p-type region 59 is formed so as to go around the MOSFET region 20 along the termination trench 54. As shown in FIG. 2, an outer peripheral drift region 28 b is formed below the boundary p-type region 59.
  • FIG. 3 shows an enlarged cross-sectional view of the vicinity of the outer peripheral edge of the outer peripheral p-type region 62.
  • the outer peripheral p-type region 62 has an Al (aluminum) high concentration region 61 and a B (boron) high concentration region 63.
  • the Al high concentration region 61 is a p-type region having a higher Al concentration than B
  • the B high concentration region 63 is a p-type region having a higher B concentration than Al.
  • the outer peripheral p-type region 62 does not contain p-type impurities other than B and Al except for an uncontrollable error level.
  • the Al high concentration region 61 is formed at the outer peripheral end of the outer peripheral p-type region 62 in the range where the outer peripheral p-type region 62 is exposed on the surface 74.
  • the B high concentration region 63 is formed in the outer peripheral p-type region 62 other than the Al high concentration region 61. Most of the outer peripheral p-type region 62 is constituted by the B high concentration region 63.
  • FIG. 4 shows an impurity concentration distribution (impurity concentration distribution along the line AA in FIG. 3) in the vicinity of the outer peripheral edge of the outer peripheral p-type region 62. 3 and 4, a region 61 a is a region containing Al and not containing B.
  • the region 61b contains Al and B, and the concentration of Al is higher than the concentration of B.
  • the Al high concentration region 61 is composed of a region 61a and a region 61b.
  • the width W1 (that is, the dimension in the direction from the inner circumference side to the outer circumference side) of the Al high concentration region 61 shown in FIG. 3 is wider than each width W2 of the guard ring region 64 described later.
  • said width W1, W2 means the dimension in the direction which goes to an outer peripheral side from an inner peripheral side.
  • each guard ring region 64 is a p-type region and is formed in a range exposed to the surface 74. Each guard ring region 64 is formed only in a shallow range. Therefore, the lower end of each guard ring region 64 is located on the upper side (surface side) than the lower end of the outer peripheral p-type region 62.
  • An outer peripheral drift region 28 b is formed below each guard ring region 64. An outer peripheral drift region 28 b is formed between the guard ring region 64 on the innermost peripheral side (the MOSFET region 20 side) and the outer peripheral p-type region 62.
  • the innermost guard ring region 64 is separated from the outer peripheral p-type region 62 by the outer peripheral drift region 28 b. Further, an outer peripheral drift region 28 b is formed between the guard ring regions 64. The guard ring regions 64 are separated from each other by the outer peripheral drift region 28b.
  • Each guard ring region 64 contains Al as a p-type impurity. Each guard ring region 64 does not contain p-type impurities other than Al except for an uncontrollable error level.
  • the operation of the semiconductor device 10 will be described.
  • a voltage that makes the drain electrode 38 positive is applied between the drain electrode 38 and the source electrode 36.
  • the gate-on voltage is applied to the gate electrode 34c, whereby the MOSFET in the MOSFET region 20 is turned on. That is, a channel is formed in the body region 26 at a position facing the gate electrode 34 c, and from the source electrode 36 to the drain electrode 38 via the source region 22, the channel, the drift region 28, and the drain region 30. Current flows.
  • the application of the gate-on voltage to the gate electrode 34c is stopped, the channel disappears and the MOSFET is turned off.
  • the depletion layer extending from the above-described pn junction reaches the boundary p-type region 59 below the termination trench 54 as indicated by an arrow 82 in FIG. Then, a depletion layer spreads from the boundary p-type region 59 into the drift region 28.
  • the drift region 28 between the gate trench 34 and the termination trench 54 has a depletion layer extending from the p-type floating region 32 below the gate trench 34 and a boundary p-type region 59 below the termination trench 54 (that is, the lower end p). Depleted by the depletion layer extending from the mold region 60).
  • the depth of the gate trench 34 and the depth of the termination trench 54 are substantially equal (that is, the position in the depth direction of the p-type floating region 32 and the position in the depth direction of the lower end p-type region 60).
  • equipotential lines extend in the lateral direction (direction parallel to the surface 72). Thereby, electric field concentration in the vicinity of the termination trench 54 is suppressed.
  • the boundary p-type region 59 extends from a range in contact with the lower end of the termination trench 54 to a position in contact with the surface 74 of the semiconductor substrate 12. For this reason, in the vicinity of the surface 74, the depletion layer spreads from the boundary p-type region 59 toward the innermost guard ring region 64. When the depletion layer reaches the innermost guard ring region 64, the depletion layer extends from the guard ring region 64 to the adjacent guard ring region 64. In this way, the depletion layer spreads to the outer peripheral side via each guard ring region 64 sequentially. For this reason, the depletion layer extends widely in the outer peripheral region 50. Thereby, a high breakdown voltage in the outer peripheral region 50 is realized.
  • the lower boundary p-type region 59 of the termination trench 54 is provided at a deep position like the p-type floating region 32, so that the electric field in the vicinity of the outer peripheral end of the MOSFET region 20 is obtained. Concentration is suppressed. Further, since the boundary p-type region 59 extends from the bottom surface of the termination trench 54 to the surface 74 of the semiconductor substrate 12 on the outer peripheral side of the termination trench 54, the guard ring formed only in a shallow range near the surface 74. A depletion layer can reach the region 64. As a result, extension of the depletion layer in the outer peripheral region 50 is promoted by the plurality of guard ring regions 64. Further, since the guard ring regions 64 are separated from each other, the potential can be distributed relatively evenly in the outer peripheral region 50. For this reason, a high breakdown voltage in the outer peripheral region 50 is realized.
  • the Al high concentration region 61 is formed in the outer peripheral end of the outer peripheral p-type region 62 and in the range exposed to the surface 74.
  • a method for manufacturing the semiconductor device 10 will be described.
  • a semiconductor wafer 90 consisting only of the n-type layer 28 is prepared.
  • the n-type layer 28 is a region that becomes the drift region 28.
  • a p-type layer 26 is formed on the surface of the n-type layer 28 by epitaxial growth.
  • the p-type layer 26 is a region that becomes the body region 26.
  • the surface of the semiconductor wafer 90 within a predetermined range is partially etched.
  • etching is performed so that the p-type layer 26 is removed and the n-type layer 28 is exposed as shown in FIG.
  • a stepped portion 70 is formed on the surface of the semiconductor wafer 90.
  • the stepped portion 70 partitions the surface of the semiconductor wafer 90 into a surface 72 and a surface 74.
  • B is implanted into a range including the stepped portion 70 on the surface of the semiconductor wafer 90 (that is, a range extending from the surface 72 to the surface 74).
  • B is implanted so that B is distributed from a shallow position to a relatively deep position.
  • Al is implanted into the range including the outer peripheral end X1 of the implantation range X in the surface 74 of the semiconductor wafer 90 (that is, the implantation range Y in FIG. 8).
  • Al is implanted so that Al is implanted only in the vicinity of the surface 74 of the semiconductor wafer 90 by setting the Al implantation energy low.
  • ion implantation into the guard ring region 64 is performed. That is, Al is injected into the outer peripheral side (injection range Z corresponding to each guard ring region 64) of the surface 74 of the semiconductor wafer 90 from the injection range Y.
  • Al is implanted so that Al is implanted only in the vicinity of the surface 74 of the semiconductor wafer 90 by setting the Al implantation energy low.
  • the width of the injection range Z is narrower than the width of the injection range Y.
  • the implanted Al and B are diffused and activated.
  • a boundary p-type region 59 and a guard ring region 64 are formed.
  • the distribution range of B is widened. That is, compared with the implantation range X, the range in which B after diffusion is distributed becomes considerably wide.
  • the width of the Al implantation range Y is widened, the Al high concentration region 61 can be easily disposed at the outer peripheral edge of the boundary p-type region 59 even if the B distribution range is expanded. it can.
  • the guard ring region 64 is formed at a shallow position near the surface 74 of the semiconductor wafer 90, the guard ring region 64 can be formed with high accuracy.
  • Al implanted into the guard ring region 64 has a low diffusion coefficient in SiC, the guard ring region 64 can be formed with higher accuracy. Therefore, the interval between the guard ring regions 64 can be reduced. Furthermore, the interval between the outer peripheral p-type region 62 and the guard ring region 64 can also be reduced.
  • the termination trench 54 is formed at the end of the outer peripheral p-type region 62 (the end opposite to the Al high concentration region 61), and the insulating layer 53 is formed in the termination trench 54. To do.
  • the structure in the MOSFET region 20 is formed, and other necessary structures (diffusion layer, electrode, insulating layer, etc.) are formed, whereby the semiconductor device 10 of FIG. 1 is completed.
  • the order of each process of the manufacturing method mentioned above can be changed suitably.
  • the structure in the MOSFET region 20 may be formed before the structure in the outer peripheral region 50 or may be formed in parallel with the structure in the outer peripheral region 50.
  • the interval between the guard ring regions 64 can be reduced. Further, the interval between the outer peripheral p-type region 62 and the guard ring region 64 can also be reduced. Therefore, in this semiconductor device 10, the depletion layer tends to extend in the outer peripheral region 50. For this reason, according to this method, the semiconductor device 10 having a high breakdown voltage in the outer peripheral region 50 can be manufactured.
  • interval W3 shows the relationship between the interval W3 (see FIG. 2) between the termination trench 54 and the stepped portion 70 and the DS breakdown voltage (drain-source breakdown voltage) of the semiconductor device 10.
  • interval W3 is 10 micrometers or more.
  • the lower boundary p-type region 59 (that is, the lower end p-type region 60) of the termination trench 54 is not formed on the MOSFET region 20 side.
  • a part of the lower end p-type region 60 may protrude to the MOSFET region 20 side from the termination trench 54.
  • the drift region 28 between the gate trench 34 and the termination trench 54 is more easily depleted.
  • the protruding portion does not protrude above the lower end of the termination trench 54 (on the body region 26 side).
  • the lower end p-type region 60 when a part of the lower end p-type region 60 is located above the lower end depth D1 of the termination trench 54 in the MOSFET region 20 as shown in FIG.
  • the distance L1 between them becomes shorter.
  • the inter-DS breakdown voltage decreases.
  • a part of the lower end p-type region 60 may be disposed above the depth D1, and the distance L1 may be optimized to ensure the withstand voltage between the DSs.
  • the stepped portion 70 is formed on the surface of the semiconductor substrate 12, but the surface of the semiconductor substrate 12 may be flat as shown in FIG.
  • the body region 26 of the semiconductor device of FIG. 14 is formed by ion implantation. Unlike the epitaxial growth, the ion implantation allows the body region 26 to be formed only in a necessary region on the surface of the semiconductor wafer. Therefore, in the manufacturing process of the semiconductor device of FIG. 14, it is necessary to perform the step of etching part of the p-type layer 26 (body region 26) described in the above-described embodiment (that is, the step of forming the stepped portion 70). There is no. Therefore, in the semiconductor device of FIG. 14, the surface of the semiconductor substrate 12 is flat.
  • the lower end p-type region 60 is connected to the outer peripheral p-type region 62.
  • the lower end p-type region 60 may be separated from the outer peripheral p-type region 62.
  • the outer peripheral p-type region 62 is formed in a shallower range than the termination trench 54. For this reason, the lower end p-type region 60 is separated from the outer peripheral p-type region 62 by the drift region 28.
  • the distance L2 between the lower end p-type region 60 and the outer peripheral p-type region 62 is set to a distance at which the depletion layer can extend from the lower end p-type region 60 to the outer peripheral p-type region 62,
  • the breakdown voltage of the outer peripheral region 50 can be ensured as in the above-described embodiment.
  • the distance L2 is preferably set so as to satisfy the formula of L2 ⁇ ⁇ 2 ⁇ (Vbi ⁇ V) / q ⁇ Nb ⁇ 1/2 .
  • ⁇ is a dielectric constant of the drift region 28
  • Vbi is a built-in potential between the lower end p-type region 60 and the drift region 28
  • V is an applied voltage
  • q is an elementary charge
  • Nb is This is the n-type impurity concentration of the drift region 28.
  • the semiconductor device having the MOSFET has been described.
  • another element such as an IGBT may be formed instead of the MOSFET.
  • the semiconductor substrate 12 is made of SiC.
  • a semiconductor substrate made of another material such as Si may be used.

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