JP6231396B2 - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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Publication number
JP6231396B2
JP6231396B2 JP2014023869A JP2014023869A JP6231396B2 JP 6231396 B2 JP6231396 B2 JP 6231396B2 JP 2014023869 A JP2014023869 A JP 2014023869A JP 2014023869 A JP2014023869 A JP 2014023869A JP 6231396 B2 JP6231396 B2 JP 6231396B2
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region
type
outer peripheral
exposed
termination trench
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JP2015153787A5 (enExample
JP2015153787A (ja
Inventor
秀史 高谷
秀史 高谷
順 斎藤
順 斎藤
明高 添野
明高 添野
濱田　公守
公守 濱田
水野　祥司
祥司 水野
佐智子 青井
佐智子 青井
渡辺　行彦
行彦 渡辺
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Denso Corp
Toyota Motor Corp
Toyota Central R&D Labs Inc
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Denso Corp
Toyota Motor Corp
Toyota Central R&D Labs Inc
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Priority to JP2014023869A priority Critical patent/JP6231396B2/ja
Priority to PCT/JP2014/076722 priority patent/WO2015118721A1/ja
Priority to DE112014006350.9T priority patent/DE112014006350B4/de
Priority to CN201480075197.3A priority patent/CN105981173B/zh
Priority to US15/116,288 priority patent/US9640651B2/en
Publication of JP2015153787A publication Critical patent/JP2015153787A/ja
Publication of JP2015153787A5 publication Critical patent/JP2015153787A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2014023869A 2014-02-10 2014-02-10 半導体装置及び半導体装置の製造方法 Expired - Fee Related JP6231396B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2014023869A JP6231396B2 (ja) 2014-02-10 2014-02-10 半導体装置及び半導体装置の製造方法
PCT/JP2014/076722 WO2015118721A1 (ja) 2014-02-10 2014-10-06 半導体装置及び半導体装置の製造方法
DE112014006350.9T DE112014006350B4 (de) 2014-02-10 2014-10-06 Halbleitereinrichtungen und Verfahren zum Herstellen einer Halbleitereinrichtung
CN201480075197.3A CN105981173B (zh) 2014-02-10 2014-10-06 半导体装置以及半导体装置的制造方法
US15/116,288 US9640651B2 (en) 2014-02-10 2014-10-06 Semiconductor device and method of manufacturing semiconductor device

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Application Number Priority Date Filing Date Title
JP2014023869A JP6231396B2 (ja) 2014-02-10 2014-02-10 半導体装置及び半導体装置の製造方法

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JP2015153787A JP2015153787A (ja) 2015-08-24
JP2015153787A5 JP2015153787A5 (enExample) 2016-06-23
JP6231396B2 true JP6231396B2 (ja) 2017-11-15

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US (1) US9640651B2 (enExample)
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CN (1) CN105981173B (enExample)
DE (1) DE112014006350B4 (enExample)
WO (1) WO2015118721A1 (enExample)

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CN106252390A (zh) * 2016-09-19 2016-12-21 西安理工大学 一种沟槽‑场限环复合终端结构及其制备方法
JP2018082025A (ja) * 2016-11-16 2018-05-24 株式会社 日立パワーデバイス 半導体装置、電力変換装置及び半導体装置の製造方法
JP6870546B2 (ja) * 2017-09-14 2021-05-12 株式会社デンソー 半導体装置およびその製造方法
CN109346511A (zh) * 2018-10-15 2019-02-15 北京工业大学 一种应用于功率半导体器件的横向电阻结构
JP7061948B2 (ja) * 2018-10-23 2022-05-02 三菱電機株式会社 半導体装置、および、半導体装置の製造方法
US11158703B2 (en) * 2019-06-05 2021-10-26 Microchip Technology Inc. Space efficient high-voltage termination and process for fabricating same
IT201900013416A1 (it) * 2019-07-31 2021-01-31 St Microelectronics Srl Dispositivo di potenza a bilanciamento di carica e procedimento di fabbricazione del dispositivo di potenza a bilanciamento di carica
CN113054011B (zh) * 2021-02-09 2023-06-20 杭州士兰集昕微电子有限公司 功率半导体器件及其制造方法
JP7697255B2 (ja) * 2021-04-27 2025-06-24 富士電機株式会社 炭化珪素半導体装置および炭化珪素半導体装置の製造方法
JP7673530B2 (ja) * 2021-07-09 2025-05-09 住友電気工業株式会社 半導体チップ
JP7340726B1 (ja) * 2022-03-11 2023-09-07 ヌヴォトンテクノロジージャパン株式会社 半導体装置
TWI829510B (zh) * 2022-03-11 2024-01-11 日商新唐科技日本股份有限公司 半導體裝置
JP2023140037A (ja) * 2022-03-22 2023-10-04 株式会社東芝 半導体装置
TWI832716B (zh) * 2023-03-02 2024-02-11 鴻海精密工業股份有限公司 製作半導體裝置的方法與半導體裝置
US20250072044A1 (en) * 2023-08-22 2025-02-27 Wolfspeed, Inc. Power semiconductor devices having gate trenches with asymmetrically rounded upper and lower trench corners and/or recessed gate electrodes and methods of fabricating such devices

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JP3211490B2 (ja) 1993-06-30 2001-09-25 株式会社日立製作所 半導体装置及びその製造方法
JPH1098188A (ja) * 1996-08-01 1998-04-14 Kansai Electric Power Co Inc:The 絶縁ゲート半導体装置
JP4164892B2 (ja) * 1997-06-30 2008-10-15 株式会社デンソー 半導体装置及びその製造方法
JPH1187698A (ja) 1997-09-02 1999-03-30 Kansai Electric Power Co Inc:The 高耐圧半導体装置及びこの装置を用いた電力変換器
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JP2010147222A (ja) * 2008-12-18 2010-07-01 Denso Corp 炭化珪素半導体装置およびその製造方法
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JP5396953B2 (ja) 2009-03-19 2014-01-22 株式会社デンソー 炭化珪素半導体装置およびその製造方法
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JP5633992B2 (ja) * 2010-06-11 2014-12-03 トヨタ自動車株式会社 半導体装置および半導体装置の製造方法
JP5621340B2 (ja) * 2010-06-16 2014-11-12 株式会社デンソー 炭化珪素半導体装置の製造方法および炭化珪素半導体装置
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JP5482745B2 (ja) * 2011-08-10 2014-05-07 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP5758824B2 (ja) * 2012-03-14 2015-08-05 トヨタ自動車株式会社 半導体装置および半導体装置の製造方法
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JP6354525B2 (ja) * 2014-11-06 2018-07-11 株式会社デンソー 炭化珪素半導体装置の製造方法

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US20170012122A1 (en) 2017-01-12
CN105981173A (zh) 2016-09-28
DE112014006350T5 (de) 2016-10-20
CN105981173B (zh) 2019-05-10
US9640651B2 (en) 2017-05-02
JP2015153787A (ja) 2015-08-24
DE112014006350B4 (de) 2018-05-09
WO2015118721A1 (ja) 2015-08-13

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