WO2015109624A1 - 用于共同驱动栅极和公共电极的goa单元、驱动电路及阵列 - Google Patents

用于共同驱动栅极和公共电极的goa单元、驱动电路及阵列 Download PDF

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Publication number
WO2015109624A1
WO2015109624A1 PCT/CN2014/072288 CN2014072288W WO2015109624A1 WO 2015109624 A1 WO2015109624 A1 WO 2015109624A1 CN 2014072288 W CN2014072288 W CN 2014072288W WO 2015109624 A1 WO2015109624 A1 WO 2015109624A1
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Prior art keywords
input
output
gate
common electrode
signal
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PCT/CN2014/072288
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English (en)
French (fr)
Inventor
徐向阳
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深圳市华星光电技术有限公司
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Priority to GB1610478.8A priority Critical patent/GB2535936B/en
Priority to RU2016130156A priority patent/RU2628188C1/ru
Priority to JP2016544503A priority patent/JP6325676B2/ja
Priority to US14/383,029 priority patent/US9767750B2/en
Priority to KR1020167019901A priority patent/KR101937403B1/ko
Publication of WO2015109624A1 publication Critical patent/WO2015109624A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Definitions

  • GOA unit drive circuit and array for common drive gate and common electrode
  • the present invention relates to the field of liquid crystal display technology, and in particular to a GOA unit, a driving circuit and an array for jointly driving a gate and a common electrode.
  • the GOA technology Gate Driver on Array, directly replaces the gate driver circuit (Gate Driver ICs) on the array substrate Array instead of the external 3 ⁇ 4 wafer.
  • the application of this technology can directly make the gate drive circuit around the panel, which reduces the production process and reduces the product cost.
  • the high integration of the TFT-LCD panel is improved, and the panel is made thinner.
  • the Cgd feed through voltage is:
  • Vgjiigh and Vg-low are the voltages for opening and closing the gate drive circuit traces respectively, and Cgd, Clc and Cs are TFT parasitic capacitance, liquid crystal capacitance and storage capacitance, respectively.
  • the feed through voltage is mainly caused by the variation of the gate voltage when the TFT is turned off, the pixel voltage is pulled low by the parasitic capacitance Cgd. Regardless of whether the polarity of the pixel voltage is positive or negative, the feed through voltage is a negative pull on the pixel voltage.
  • the effect of the feed through voltage can be reduced by replenishing the voltage of the common electrode.
  • the dry Clc is not a fixed parameter, so the influence of the feed through cannot be eliminated by adjusting the driving voltage of the common electrode, so that the purpose of improving image quality is not easily achieved.
  • the present invention provides a kind of common driving of the cabinet pole and the common electrode.
  • a GOA unit comprising: a flip-flop comprising an input terminal, a clock terminal, a reset terminal, a low-level input terminal and a trigger output terminal; a first selection input circuit comprising two inverting-off diodes connected in parallel, the diode The anodes are respectively connected to the output lines of the 11-1 and the n+2th gates, and the cathode of the diode is connected as an output to the input terminal to select a level signal or an edge in the :: and n + 2 gate lines
  • the signal serves as a second selection input circuit of the flip-flop, the output of which is connected to the clock terminal, and includes four clock pulse inputs that operate asynchronously in the same cycle, and a common electrode high level input and a cabinet high level input. , strobing the common electrode high level input and the drain high level input to the clock terminal of the flip-flop respectively at different timings to pull up the voltage on the trigger output;
  • a third selection input circuit comprising two parallel-inverted diodes connected in parallel, the anodes of the diodes being respectively connected to the n-th and the first +4 gate lines, the cathode of the diode being used as an output and the reset Connecting, to select a level signal or an edge signal on the ir l and n+4th gate lines as a reset signal of the flip flop;
  • a fourth selection input circuit the output of which is connected to the low level input terminal for inputting a low level input or a common electrode low level under the control of the first -i and the T1+4 gate lines Strobe to the low level input of the flip-flop to pull the voltage T thereon;
  • An output circuit is selected, the input of which is coupled to the trigger output for selecting an output pole drive signal or an output common electrode drive signal at two of the four clock pulses operating asynchronously in the same cycle.
  • the two pulses are separated by three-quarters of the duty cycle.
  • the reverse-phase-cut diode is a diode equivalent circuit composed of a MOS tube or a TFT tube, wherein a MOS tube or a TFT tube is connected to a source as the anode, and a drain is used as a drain.
  • the cathode is a diode equivalent circuit composed of a MOS tube or a TFT tube, wherein a MOS tube or a TFT tube is connected to a source as the anode, and a drain is used as a drain.
  • the level signal or the edge signal in the first ⁇ -l and n-th gate lines is a low-level signal or a falling-edge signal, on the " ⁇ and the n+4 gate lines
  • the level signal or the edge signal is a high level signal or a rising edge signal.
  • the common electrode driving signal output by the GOA unit circuit is synchronized with the signal on the n+3th gate line.
  • the second selection input circuit comprises four TFT transistors, wherein two TFT transistors are connected to the source and the drain, and the two gates are respectively input by the second clock pulse and the third clock pulse. Control, used to access the gate high level input;
  • the other two TFT transistor sources are connected to the drain, and the two gates are respectively controlled by the first clock input and the fourth clock input to access the common electrode high level input.
  • the fourth selection input circuit comprises two TFT transistors, wherein the gates are respectively connected to the outputs of the n +1th and n +1th cabinet lines, and the source electrodes respectively correspond to the gates.
  • the flat input is connected to the common electrode low level input.
  • the selection output circuit comprises two TFT transistors, wherein the two gates are respectively controlled by a third: clock pulse input and a first clock pulse input, and the two sources are commonly connected to the trigger output end. , outputting the nth gate line output and the common electrode line output respectively at different timings.
  • a display panel drive circuit comprising any one of the GOA units as described above, wherein the GOA unit is cascaded in the following manner - a second line output and a T1
  • the +2 gate line output respectively triggers the trigger signal of the GOA unit of the stage.
  • the n+1th gate line output and the ⁇ +4 gate line output respectively serve as reset signals of the GOA unit of the current level, and the four ⁇ lines are respectively associated with the GOA of the present stage.
  • the clock input connection of the second selection input circuit of the unit is connected to provide a clock signal with the same period but with a phase difference, and respectively select the gate high level input and the common electrode high level input under different clock pulses. Passing the corresponding pull-up voltage;
  • the output of the COM voltage is synchronized with the output of the GATE and is opposite in direction to the direction in which the cabinet voltage changes, the feed through voltage is effectively cancelled, thereby improving the display.
  • the grayscale quality of the display since the output of the COM voltage is synchronized with the output of the GATE and is opposite in direction to the direction in which the cabinet voltage changes, the feed through voltage is effectively cancelled, thereby improving the display.
  • FIG. 1 shows a voltage waveform of a common electrode driving using a DC driving in the prior art, in which a storage capacitor Cs (Cs on Com) is formed on the common electrode;
  • Figure 2 shows an internal circuit diagram of a GOA unit used in the prior art
  • FIG. 3 is a schematic circuit diagram of a gate second-order driving for cascading GOA cells in the prior art
  • FIG. 4 is a pulse timing diagram of a gate driving circuit in the prior art
  • FIG. 5 shows a voltage waveform in which a common electrode driving circuit operates in synchronization with a gate driving circuit in accordance with the principles of the present invention
  • FIG. 6 shows an internal circuit diagram in which a common electrode driving output is integrated in a GOA unit in accordance with an embodiment of the present invention
  • Fig. 7 is a view showing a sequence of driving pulses generated by the driving circuit of the present invention.
  • Fig. 1 Fig. 4 shows a prior art GOA driving circuit and its generated pulse sequence diagram. It can be seen that the voltage on the common electrode COM is a direct current voltage. The voltage pulses on each of the gates (Gate l, Gate 2, Gate 3, ...) appear in sequence under the action of two opposite clock sequences. The length of time that all gate lines are scanned is one frame, and the length of time is also the period of the pulse on each gate line. Ffl uses two interleaved clocks for trigger control, and the width of the positive residual on the gate line is the same as the clock width.
  • the voltage waveform appearing on each line at the same time is shown.
  • 101 table The gate drive voltage pulse is shown, 102 represents the source drive voltage pulse, 103 represents the voltage on the pixel electrode, and 104 represents the difference between the source voltage and the pixel voltage, which difference is equivalent to the dry feed through voltage.
  • the original COM: voltage 106 can be corrected, and the corrected COM voltage is indicated by 07.
  • the correction is the same as the feed Profoug voltage. But with COM DC drive, it is not easy to correct the voltage.
  • the drive circuit is constructed by arranging GOA units on one side. These GOA units are cascaded to form a pulse sequence as shown in Figure 4 at each of their outputs.
  • Figure 2 shows the circuit inside the GOA unit in detail.
  • the GOA unit is essentially a flip-flop. It consists of 4 TFT switches and 1 capacitor. Among them, TFT1 is a driving transistor, TFT2 and TFT3 are reset switching transistors, and TFT4 is a pre-charging transistor. Cb is the potential holding capacitance of TFT1, which is mainly controlled by TFT4.
  • the conventional GOA driver requires four control signals, namely the clock signal Clk, the input signal, the reset signal Resei, and the cabinet output low potential Vss.
  • the clock signal is a pull-up signal output from the gate line.
  • FIG. 3 is a schematic diagram of a circuit for forming a single-sided gate second-order driving in which a GOA unit is cascaded in the prior art.
  • the output of the previous GOA unit serves as the trigger signal for the GOA unit, and the output of the next GOA unit serves as the reset signal for the GOA unit.
  • the bell signal uses two (Vclk-A, Vclk-B), which use GOA units of odd-numbered lines and GOA units of even-numbered lines.
  • the gate line output potential Vss determines the height or amplitude of the output pulse on the gate line.
  • the present invention is described in terms of how to adjust the COM voltage in view of the above principle.
  • the amount of change in the required COM voltage is known, which is equivalent to the feed through voltage. Therefore, the timing as shown in Fig. 5 is obtained.
  • 501 represents the gate drive voltage pulse
  • 502 represents the source drive voltage pulse
  • 503 represents the voltage on the pixel electrode
  • 506 represents the COM voltage drive signal.
  • the feed through is theoretically completely eliminated by the amount of change in the COM voltage.
  • the GOA drive circuit is set.
  • the core GOA unit of the driver circuit is shown in Figure 6.
  • the output of the GOA unit is used to drive the gate and the common electrode together. It is mainly composed of a flip-flop 602 and some peripheral circuits.
  • the flip-flop includes an input terminal 1, a clock terminal 2, a reset terminal 3, a low-level input terminal 4, and a trigger output terminal 5.
  • the GOA unit further includes A selection input circuit 603 is selected. It consists of two inverted reversed diodes in parallel. The anode of the diode is connected to the output of the n-1th and n+2th gate lines G[n-1] and BG[ir 2], respectively, and the cathode of the diode is connected to the input terminal 1 to select the ⁇ ⁇ -1 and The level signal or the edge signal in the ⁇ +2 cabinet line Gjn-1] and G[TI-;-2] serves as the excitation input of the flip-flop 602.
  • the GOA unit also includes a third selection input circuit 604. It can also consist of two parallel-cut diodes connected in parallel. Wherein, similar to the above, the anode of the diode is respectively connected to the ⁇ +: ⁇ and the n+4 gate line outputs G[rv l] and G[n+4], and the cathode of the diode is connected as an output to the reset terminal 3 to The level signal on the n+i and n+4th epipolar lines G[n+i] and G[ii+4] or the edge signal is selected as the reset signal of the flip-flop 602.
  • the level signal or the edge signal in the first and eleventh gate lines G[ii-1] and G[n+2] are low level signals or falling edge signals.
  • the level signal or the edge signal on the n+i and n+4th gate lines G[ii+1] and G[n+4] is a high level signal or a rising edge signal.
  • the diodes each employ a diode equivalent circuit composed of a TFT tube such as T9-T12, in which the gate and the source of the TFT tube are connected as an anode and the drain serves as a cathode.
  • a TFT tube such as T9-T12
  • the gate and the source of the TFT tube are connected as an anode and the drain serves as a cathode.
  • the present invention is not limited to this, and an equivalent design such as a MOS tube or the like can also be employed.
  • the GOA unit of the present invention includes a second selection input circuit 601.
  • the output of the second selection input circuit 601 is connected to the clock terminal 2 of the flip-flop, and includes four clock pulses input CikA, C!kB, ClkC, CikD, and the common electrode high-level input Cora_2 and gate which operate asynchronously in the same cycle.
  • the very high level input Vgh is used to strobe the common electrode high level input Com__2 and the gate high level input Vgh to the clock terminal 2 of the flip-flop 602 in different sequences, thereby further triggering the output terminal 5
  • the upper voltage pull-up forms a high level of the nth stage gate scan pulse output or a high level of the n +3th stage common electrode pulse.
  • the second selection input circuit 60i may include four TFT transistors, wherein the source and drain of the two TFT transistors T5, T6 are connected, and the two cabinets are respectively input with the second clock pulse CikB And the third clock pulse input CikC control, ] 3 ⁇ 4 to access the cabinet pole high level input.
  • the other two TFT transistors T7, ⁇ 8 are connected to the source and drain, and the two poles are respectively controlled by the first clock pulse input ClkA and the fourth clock pulse input ClkD for accessing the common electrode high level input.
  • clock-reciprocal inputs ClkA, CikB, ClkC, and ClkD operating asynchronously in the same cycle are sequentially one-fourth of a duty cycle in phase.
  • the output gate line pulse width and the common electrode line width are both one-half of the clock pulse width.
  • the GOA unit further includes a fourth selection input circuit 605, the output of which is connected to the low level input terminal 4 Connected to select the cabinet low level input or the common electrode low level input under the control of the nth tenth and the nth - 4th gate lines G[n10] and G[i+4] respectively Passing to the low level input 4 of the flip flop 602 to pull down the voltage thereon to form a low level of the nth stage gate scan pulse output or a low level of the nth - 3rd stage common electrode pulse.
  • a fourth selection input circuit 605 the output of which is connected to the low level input terminal 4 Connected to select the cabinet low level input or the common electrode low level input under the control of the nth tenth and the nth - 4th gate lines G[n10] and G[i+4] respectively Passing to the low level input 4 of the flip flop 602 to pull down the voltage thereon to form a low level of the nth stage gate scan pulse output or a low
  • the fourth selection input circuit 605 preferably includes two TFT transistors ⁇ 13 ⁇ 4, wherein the gates are respectively connected to the outputs G[ n +i] and G[n+4] of the n+:th and n+4th lines, the source Corresponding to the gate low level input Vss and the common electrode low level input Com-!
  • the selection output circuit 606 of the GOA unit has an input connected to the trigger output 5 for selecting an output gate drive signal or an output common electrode drive signal at two pulse timings of four clock pulses operating asynchronously in the same cycle.
  • the two pulse timings differ by three-quarters of the duty cycle, so the cabinet drive signal is three times longer than the common electrode drive signal.
  • the common electrode driving signal C[n ⁇ 3] outputted by the nth stage GOA unit circuit is synchronized with the signal on the n+3 cabinet line G[n+3].
  • the selection output circuit 606 preferably includes two TFT transistors T15, T16, wherein the two cabinets are respectively controlled by a third clock pulse input ClkC and a first clock pulse input ClkA, and the two sources are commonly connected to The output terminal 5 is triggered to output the T1 gate line output G[n
  • FIG. 7 a pulse timing diagram generated after the cascade of drive circuits constructed in accordance with the principles of the present invention.
  • the clock phases that operate asynchronously in the same four cycles differ by a quarter of the phase I: cycle.
  • a pulse occurs on the gate line Gatel, a pulse appears on the Coml, thereby achieving the same trick of the gate drive and the common electrode drive.
  • a display panel drive circuit comprising as many as one of the GOA units as described above, wherein the GOA units are cascaded in the following manner:
  • n-1th line output G[ii-i] and the n+2 cabinet line output G[ii+2] are respectively used as trigger signals of the GOA unit of the present stage, and the n+1th gate line outputs G[n+1] And the n+4 gate line output Gfn+4] is respectively used as a reset signal of the GOA unit of the current stage, and the four clock lines are respectively connected with the clock pulse inputs ClkA, ClkB, ClkC, ClkD on the second selection input circuit of the GOA unit of the present stage.
  • the GOA unit of the current stage The output is the II gate line output G and the ⁇ - ⁇ common electrode line output C[n+3
  • the present invention also provides an array substrate having a driving circuit formed thereon as described above, comprising - laterally parallel gate lines and common electrode lines;

Abstract

公开了一种用于栅极和公共电极的驱动电路，包括：触发器（602）；第一选择输入电路（603），以选择第n-1栅线信号（G［n-1］）和第n+2栅线信号（G［n+2］）至触发器（602）的输入端（1）；第二选择输入电路（601），用以在不同的时序下将公共电极高电平输入（Com_2）和栅极高电平输入（Vgh）分别选通至触发器（602）的时钟端（2）以将触发输出端（5）上的电压上拉；第三选择输入电路（604），以选择第n+1栅线信号（G［n+1］）和第n+4栅线信号（G［n+4］）至触发器（602）的复位端（3）；第四选择输入电路（605），用以在第n+1栅线信号（G［n+1］）和第n+4栅线信号（G［n+4］）的控制下将栅极低电平输入（Vss）和公共电极低电平输入（Com_1）分别选通至触发器（602）的低电平输入端（4）以将其上的电压下拉；选择输出电路（606），用以在不同脉冲时序f选择输出第n栅线信号（G［n］）或第n+3公共电极线信号（C［n+3］）。该驱动电路实现了公共电极输出与栅极同步，并与栅极电压变化方向相反，有效的抵消了馈通电压。还公开了一种显示面板驱动电路及阵列基板。

Description

用于共同驱动栅极和公共电极的 GOA单元、 驱动电路及阵列
技术领域
本发明涉及液晶显示技术领域， 具体说， 涉及一种用于共同驱动栅极和公共 电极的 GOA单元、 驱动电路及阵列。 背景技术
GOA技术即 Gate Driver on Array (阵列基板栅极驱动）是直接将栅极驱动电 路（Gate Driver ICs)制作在阵列基板 Array上， 来代替由外接 ¾晶片制作的一种 技术。该技术的应用可直接将栅极驱动电路做在面板周围，从而减少了制作程序， 并旦降低了产品成本。 此外， 还提高了 TFT- LCD 面板的高集成度， 使面板更薄 型化。
但是在二阶驱动原理中， 有各种不同的 feed through电压。 其中， 影响最大 的是经由 Cgd所产生的 feed through电压。 因此， 在二阶驱动 需要调整公共电 极的电压， 从而改进灰阶品质。
当公共电极 Com采用直流驱动时， 经过 Cgd的 Feed through电压为：
(Vg high― Vg jow) * Cgd / (Cgd + Clc十 Cs) ,
其中， Vgjiigh与 Vg—low分别为栅极驱动电路走线打开与关闭的电压， Cgd , Clc和 Cs分别为 TFT寄生电容、 液晶电容和存储电容。
由于 feed through 电压主要为 TFT关闭时栅极电压的变化通过寄生电容 Cgd 对像素电压的拉低而造成的。无论像素电压的极性为正还是为负， feed through电 压都是对像素电压的负^拉动。
现有技术中，可以通过对公共电极的电压进行 偿的方法来减小 feed through 电压的影响。 但由干 Clc并非是一个固定的参数， 因此无法通过调整公共电极的 驱动电压来消除 feed through的影响， 从而导致改进影像品质的目的不易达成。
目前，需要提供一种筒单可行的 GOA电路设计来实现 feed through电压的减 小甚至消除从而提高显示器的灰阶质量。 发明内容
为了解决上述技术问题， 本发明提供了一种] ¾于共同驱动櫥极和公共电极的
GOA单元， 其包括- 触发器， 其包括输入端、 时钟端、 复位端、 低电平输入端和触发输出端； 第一选择输入电路， 包括并联的两个反相截止的二极管， 所述二极管的阳极 分别与第 11-1和第 n+2栅线输出连接， 所述二极管的阴极作为输出与所述输入端 连接， 以选择第 : 和第 n+2栅线中的电平信号或边沿信号作为所述触发器的激 第二选择输入电路， 其输出与所述时钟端连接， 并包括四个相同周期异步工 作的时钟脉冲输入、 以及公共电极高电平输入和櫥极高电平输入， ^以在不同的 时序下将公共电极高电平输入和樋极高电平输入分别选通至所述触发器的时钟 端以将触发输出端上的电压上拉；
第：三选择输入电路， 包括并联的两个反相截止的二极管， 所述二极管的阳极 分别与第 η-Η和第 ι +4栅线输出连接， 所述二极管的阴极作为输出与所述复位端 连接， 以选择第 ir l和第 n+4栅线上的电平信号或者边沿信号作为所述触发器的 复位信号；
第四选择输入电路， 其输出与所述低电平输入端连接， 用以在所述第 -i和 第 T1+4栅线的控制下将栅极低电平输入或者公共电极低电平输入分别选通至所述 触发器的低电平输入端以将其上的电压 T拉；
选择输出电路， 其输入连接在所述触发输出端上， 用以在四个相同周期异步 工作的时钟脉冲中的两个脉冲时序下选择输出極极驱动信号或者输出公共电极 驱动信号。 这两个脉冲^序相差四分之三工作周期。
根据本发明的一个实施例， 所述反相截止的二极管为由 MOS管或 TFT管构 成的二极管等效电路， 其中， MOS管或 TFT管櫥极与源极连接作为所述阳极， 漏极作为所述阴极。
根据本发明的一个实施例， 第 ι -l和第 η- 2栅线中的电平信号或边沿信号为 低电平信号或下降沿信号， 第《·Η和第 η+4栅线上的电平信号或者边沿信号为高 电平信号或上升沿信号。
根据本发明的 ·个实施例， 四个相同周期异步工作的时钟脉冲输入在相位上 依次相差四分之一工诈周期。
根据本发明的 ·个实施例， 所述 GOA单元电路输出的公共电极驱动信号与 第 n+3栅线上的信号同步。
根据本发明的 ·个实施例， 所述第二选择输入电路包括四个 TFT晶体管， 其 中， 两个 TFT晶体管源漏极相连， 两个栅极分别由第二时钟脉冲输入和第三时钟 脉冲输入控制， 用以接入栅极高电平输入；
另两个 TFT晶体管源漏极相连，两个栅极分别由第一 钟脉冲输入和第四时 钟脉冲输入控制， 以接入公共电极高电平输入。
根据本发明的一个实施例， 所述第四选择输入电路包括两个 TFT晶体管， 其 中栅极分别与第 n+1和第 n+4櫥线的输出连接， 源极分别对应与栅极低电平输入 和公共电极低电平输入连接。
根据本发明的一个实施例， 所述选择输出电路包括两个 TFT晶体管， 其中两 个栅极分别由第 Ξ:时钟脉 输入和第一时钟脉冲输入控制， 两个源极共同连接到 触发输出端， 以在不同时序下分别输出第 η栅线输出和第 公共电极线输出。
根据本发明的一个方面， 还提供了一种显示面板驱动电路， 其包括若千如上 所述的任一种 GOA单元， 其中， 所述 GOA单元按照以下方式级联- 第 櫥线输出和第 T1+2栅线输出分别诈为本级 GOA单元的触发信号， 第 n+1栅线输出和第 ίΐ+4栅线输出分别作为本级 GOA单元的复位信号， 四条 ^钟 线分别与本级 GOA单元的第二选择输入电路上的时钟脉冲输入连接， 以提供周 期相同但具有相位差的^钟信号， 并在不同^钟脉冲下将栅极高电平输入和公共 电极高电平输入分别选通以输出相应的上拉电压；
其中， 本级 GOA单元的输出为第 11栅线输出和第 ίΐ+3公共电极线输出。 根据本发明的另一个方面， 还提供了一种其上形成有如上所述的驱动电路的 阵列， 其包括：
横向并行的栅线和公共电极线；
纵向并行的时钟输入线、 栅极高低电平输入线、 公共电极高低电平输入线， 其中， 栅线与公共电极线的输出在级联位置上相差 3个， 或者说， 时序上相差四 分之:三个工作周期。
根据本发明， 由于 COM电压的输出与 GATE的输出同步， 并且在方向上与 櫥极电压的变化方向相反， 因此有效地抵消了 feed through电压， .从而改进了显 示器的灰阶品质。
本发明的其它特征和优点将在随后的说明书中阐述， 并旦， 部分地从说明书 中变得显而易见， 或者通过实施本发明而了解。 本发明的目的和其他优点可通过 在说明书、 权利要求书以及附图中所特别指出的结构来实现和获得。 附图说明
附图 ^来提供对本发明的进一歩理解， 并 ϋ构成说明 ^的一部分， 与本发明 的实施倒共同 ^于解释本发明， 并不构成对本发明的限制。 在^图中- 图 1显示了现有技术中公共电极驱动采用直流驱动的电压波形， 其中， 公共 电极上形成有存储电容 Cs (Cs on Com) ；
图 2显示了现有技术中采用的 GOA单元的内部电路图；
图 3显示了现有技术中将 GOA单元级联的形成栅极二阶驱动的电路原理图； 图 4为现有技术中栅极驱动电路的脉冲时序图；
图 5显示了根据本发明原理的公共电极驱动电路与栅极驱动电路同步工作的 电压波形- 图 6显示了根据本发明一个实施飼在 GOA单元中还集成了公共电极驱动输 出的内部电路图； 以及
图 7显示了采 ]¾本发明的驱动电路产生的驱动脉冲序列图。 具钵实施方式
以 T将结合 Pfi图及实施例来详细说明本发明的实施方式， 借此对本发明如何 应用技术手段来解决技术问题， 并达成技术效果的实现过程能充分理解并据以实 施。 需要说明的是， 只要不构成冲突， 本发明中的各个实施例以及各实施例中的 各个特征可以相互结合， 所形成的技术方案均在本发明的保护范围之内。
图 1 图 4显示的是现有技术中的 GOA驱动电路以及其产生的脉冲^序图。 从中可以看出， 公共电极 COM上的电压为直流电压。各条檝线（Gate l， Gate 2, Gate 3, ……） 上的电压脉冲在两个相反的时钟序列的作用下依次出现。 扫描完 所有的栅线的时间长度为一帧， 该时间长度也是各个栅线上脉冲的周期。 ffl于采 用交错的两个时钟进行触发控制， 栅线上正餘冲的宽度与时钟宽度相同。
进一步地， 如图 1所示为同一时刻上各个线上出现的电压波形情况。 101表 示栅极驱动电压脉冲， 102表示源极驱动电压脉冲， 103表示像素电极上的电压， 104指示源极电压与像素电压的差， 该差值相当干 feed through电压。为了消除该 feed through电压， 可以对原先的 COM:电压 106进行修正， 修正后的 COM电压 用 1 07指示。 修正量与 feed ihroug电压值相同。 但是 COM直流驱动， 修正电压 不容易。
在现有技术中， 如图 3所示， 该驱动电路由单边布置了 GOA单元构成。 这 些 GOA单元级联以便能够在其各个输出上形成如图 4所示的脉冲序列。 图 2进 一歩详细地显示了 GOA单元內部的电路。
如图 2所示， 该 GOA单元实质上为一触发器。 其包括 4个 TFT开关管， 和 1个电容。其中 TFT1为驱动幵关晶体管， TFT2和 TFT3为复位开关晶体管， TFT4 为预充电开关晶体管。 Cb为 TFT1的电位保持电容， 主要由 TFT4控制。 传统的 GOA驱动需要四个控制信号， 即时钟信号 Clk、 输入信号、 复位信号 Resei以及 櫥极输出低电位 Vss。 时钟信号为栅线输出的上拉信号。
如图 3所示为现有技术中将 GOA单元级联的形成单边栅极二阶驱动的电路 原理图。 前一 GOA单元的输出作为本 GOA单元的触发信号， 下一 GOA单元的 输出作为本 GOA单元的复位信号。 ^钟信号采用两个 （Vclk— A, Vclk— B ) , 分 别用干奇数行的 GOA单元和偶数行的 GOA单元。栅线输出电位 Vss决定栅线上 输出脉冲的高度或者说是幅度。
如上所述， 这些均没有涉及到对 COM 电压的调整， 从而消除 feed through 电压。
以 T介绍本发明鉴于上述原理如何调整 COM电压。如上所述，其所需的 COM 电压变化量已经得知， 即相当于 feed through电压。 因此， 获得如图 5所示的时 序。 与图 i类似， 501表示栅极驱动电压脉冲， 502表示源极驱动电压脉冲， 503 表示像素电极上的电压， 506表示 COM 电压驱动信号。 ώ图可知， 在这种情况 下， feed through在理论上就完全被 COM电压的变化量消除了。
按照这个思想设† GOA驱动电路。该驱动电路的核心 GOA单元如图 6所示。
GOA单元的输出用于共同驱动栅极和公共电极。其主要由触发器 602及一些 外围电路构成。 该触发器包括输入端 1、 时钟端 2、 复位端 3、 低电平输入端 4和 触发输出端 5。
为了能够使公共电极驱动与栅极驱动共用该触发器， 该 GOA单元还包括第 一选择输入电路 603。 其包括并联的两个反相截止的二极管。 二极管的阳极分别 与第 n- 1和第 n+2栅线 G[n- 1]禾 B G[ir 2]输出连接， 二极管的阴极诈为输出与输入 端 1连接， 以选择第 ίΐ- 1和第 Ώ+2櫥线 Gjn- 1]和 G[TI-;-2]中的电平信号或边沿信号 作为触发器 602的激励输入。
如图 6所示，该 GOA单元还包括第三选择输入电路 604。其同样也可由并联 的两个反相截止的二极管构成。 其中， 与上类似， 二极管的阳极分别与第 ίΐ+:ί和 第 n+4栅线输出 G[rv l]和 G[n+4]连接， 二极管的阴极作为输出与复位端 3连接， 以选择第 n+i和第 n+4極线 G[n+i]和 G[ii+4]上的电平信号或者边沿信号诈为触 发器 602的复位信号。
在本发明中， 并如图 6所示， 第 和第 11十2栅线 G[ii-1]和 G[n+2]中的电平 信号或边沿信号为低电平信号或下降沿信号,第 n+i和第 n+4栅线 G[ii+1]和 G[n+4] 上的电平信号或者边沿信号为高电平信号或上升沿信号。
在图 6中， 该二极管均采用由 TFT管如 T9- T12构成的二极管等效电路， 其 中， TFT 管的栅极与源极连接作为阳极， 漏极作为阴极。 当然， 本发明不限于 此， 还可以采用例如 MOS管等来进行等效设计。
本发明的 GOA单元包括第二选择输入电路 601。第二选择输入电路 601的输 出与触发器的时钟端 2 连接， 并包括四个相同周期异步工作的^钟脉冲输入 CikA, C!kB, ClkC, CikD, 以及公共电极高电平输入 Cora_2和栅极高电平输入 Vgh， 用以在不同的^序下将公共电极高电平输入 Com__2和栅极高电平输入 Vgh 分别选通至触发器 602的时钟端 2， 从而进一步将触发输出端 5上的电压上拉， 形成第 n级栅极扫描脉冲输出的高电平或者第 n+3级公共电极脉冲的高电平。
具体地说，在一个实施例中，第二选择输入电路 60i可包括四个 TFT晶体管， 其中， 两个 TFT晶体管 T5 , T6的源漏极相连， 两个櫥极分别 ώ第二时钟脉冲输 入 CikB和第三时钟脉冲输入 CikC控制， ]¾以接入櫥极高电平输入。 而另两个 TFT晶体管 T7， Τ8的源漏极相连，两个極极分别由第一时钟脉冲输入 ClkA和第 四时钟脉冲输入 ClkD控制， 用以接入公共电极高电平输入。
优选地是， 四个相同周期异步工作的时钟餘冲输入 ClkA, CikB, ClkC, ClkD 在相位上依次相差四分之一工作周期。 这样， 输出的栅线脉冲宽度和公共电极线 脉 宽度均为时钟脉 宽度的二分之一。
此外， GOA单元还包括第四选择输入电路 605， 其输出与低电平输入端 4连 接， 用以在第 n十〗 和第 η- ί- 4栅线 G[n十 1]和 G[i +4]的控制下将櫥极低电平输入或 者公共电极低电平输入分别选通至触发器 602的低电平输入端 4以将其上的电压 下拉， 形成第 n级栅极扫描脉冲输出的低电平或者第 n- 3级公共电极脉冲的低电 在一个实施例中，第四选择输入电路 605优选包括两个 TFT晶体管 Τ13 Π4， 其中栅极分别与第 n+: 和第 n+4極线的输出 G[n+i]和 G[n+4]连接， 源极分别对 应与栅极低电平输入 Vss和公共电极低电平输入 Com—!连接。
GOA单元的选择输出电路 606， 其输入连接在触发输出端 5上， 用以在四个 相同周期异步工作的时钟脉冲中的两个脉冲时序下选择输出栅极驱动信号或者 输出公共电极驱动信号。 这两个脉冲时序相差四分之三工作周期， 因此櫥极驱动 信号比公共电极驱动信号早出现三个櫥线脉冲宽度的时间。
如图 6所示,第 n级 GOA单元电路输出的公共电极驱动信号 C[n÷3]与第 n+3 櫥线 G[n+3]上的信号同步。
在一个实施倒中， 选择输出电路 606优选包括两个 TFT晶体管 T15 , T16, 其中两个櫥极分别由第:三时钟脉冲输入 ClkC和第一时钟脉冲输入 ClkA控制，两 个源极共同连接到触发输出端 5 , 以在不同时序下分别输出第 T1栅线输出 G[n|和 第 ir 3公共电极线输出 C[ii- 3]。
如图 7所示，为根据本发明的原理构造的驱动电路级联后产生的脉冲时序图。 在图中可以看出， 四个相同周期异步工作的时钟脉冲相位上相差四分之一 I： 作周期。 在栅线 Gatel 上出现脉冲的时候， Coml上也出现了脉冲， 从而实现了 栅极驱动和公共电极驱动的同歩工诈。
根据本发明的一方面， 还提供了一种显示面板驱动电路， 其包括若千个如上 所述的 GOA单元， 其中， GOA单元按照以下方式级联：
第 n-1極线输出 G[ii-i]和第 n+2櫥线输出 G[ii+2]分别作为本级 GOA单元的 触发信号， 第 n+1栅线输出 G[n+1]和第 n+4栅线输出 Gfn+4]分别作为本级 GOA 单元的复位信号， 四条时钟线分别与本级 GOA单元的第二选择输入电路上的时 钟脉冲输入 ClkA, ClkB, ClkC, ClkD连接， 以提供周期相同但具有相位差的时 钟信号， 并在不同时钟脉冲下将栅极高电平输入和公共电极高电平输入分别选通 以输出相应的上拉电压- 其中， 本级 GOA单元的输出为第 II栅线输出 G 和第 η-β公共电极线输出 C[n+3
本发明还提供了一种其上形成有如上所述的驱动电路的阵列基板， 其包括- 横向并行的栅线和公共电极线；
纵向并行的时钟输入线、 栅极高低电平输入线、 公共电极高低电平输入线， 其中， 極线与公共电极线的输出在级联位置上相差 3个， 或者说， 序上相差四 分之三个工作周期。
虽然本发明所揭露的实施方式如上， 但所述的内容只是为了便于理解本发明 而采 ^的实施方式， 并非用以限定本发明。 任何本发明所属技术领域内的技术人 员， 在不脱离本发明所揭露的精神和范 I的前提下， 可以在实施的形式上及细节 上作任何的修改与变化， 但本发明的专利保护范围， 仍须以所附的权利要求书所 界定的范围为准。

Claims

权利要求书
1、 ·种用于共同驱动栅极和公共电极的 GOA单元， 其中， 包括： 触发器， 其包括输入端、 时钟端、 复位端、 低电平输入端和触发输出端； 第一选择输入电路， 包括并联的两个反相截止的二极管， 所述二极管的阳极 分别与第 ii-i和第 Π+2栅线输出连接， 所述二极管的阴极作为输出与所述输入端 连接， 以选择第 ίΐ-1和第 n+2栅线中的电平信号或边沿信号诈为所述触发器的激 励输入；
第二选择输入电路， 其输出与所述时钟端连接， 并包括四个相同周期异歩工 作的^钟脉冲输入、 以及公共电极高电平输入和櫥极高电平输入， ffl以在不同的 ^序下将公共电极高电平输入和檝极高电平输入分别选通至所述触发器的时钟 端以将触发输出端上的电压上拉- 第 选择输入电路， 包括并联的两个反相截止的二极管， 所述二极管的阳极 分别与第 η·+·1和第《÷4栅线输出连接， 所述二极管的阴极作为输出与所述复位端 连接， 以选择第 η+1和第 4櫥线上的电平信号或者边沿信号作为所述触发器的 复位信号；
第四选择输入电路， 其输出与所述低电平输入端连接， 用以在所述第 和 第 n+4櫥线的控制下将栅极低电平输入或者公共电极低电平输入分别选通至所述 触发器的低电平输入端以将其上的电压下拉；
选择输出电路， 其输入连接在所述触发输出端上， 用以在四个相同周期异步 工作的时钟脉冲中的两个脉冲时序下选择输出栅极驱动信号或者输出公共电极
2、如权利要求 1所述的 GOA单元，其中，所述反相截止的二极管为由 MOS 管或 TFT管构成的二极管等效电路， 其中， MOS管或 TFT管櫥极与源极连接作 为所述阳极， 漏极作为所述阴极。
3、 如权利要求 1所述的 GOA单元， 其中， 第 n-】和第 栅线中的电平信 号或边沿信号为低电平信号或下降沿信号， 第 n+〗和第 -4栅线上的电平信号或 者边沿信号为高电平信号或上升沿信号。
4、 如权利要求 1所述的 GOA单元， 其中， 四个相同周期异步工诈的时钟脉 冲输入在相位上依次相差四分之一工作周期。
5、 如权利要求 1所述的 GOA单元， 其中， 所述 GOA单元电路输出的公共 电极驱动信号与第 n+3栅线上的信号同步。
6、 如权利要求 5所述的 GOA单元， 其中， 所述第二选择输入电路包括四个 TFT晶体管， 其中， 两个 TFT晶体管源漏极相连， 两个栅极分别由第二 钟脉冲 输入和第三时钟脉冲输入控制， ]¾以接入櫥极高电平输入；
另两个 TFT晶体管源漏极相连，两个栅极分别由第一时钟脉冲输入和第四时 钟脉冲输入控制， ^以接入公共电极高电平输入。
7 , 如权利要求 5所述的 GOA单元， 其中， 所述第四选择输入电路包括两个 TFT晶体管， 其中櫥极分别与第 11+1和第《十4栅线的输出连接， 源极分别对应与 櫥极低电平输入和公共电极低电平输入连接。
8、 如权利要求 5所述的 GOA单元， 其中， 所述选择输出电路包括两个 ΊΤΤ 晶体管， 其中两个栅极分别由第-三时钟脉冲输入和第一时钟脉冲输入控制， 两个 源极共同连接到触发输出端， 以在不同时序下分别输出第 n栅线输出和第 公 共电极线输出， 其中， 这两个脉冲时序相差四分之三工作周期。
9、 一种驱动电路， 其中， 包括如权利要求 1所述的 GOA单元， 其中， 所述 GOA单元按照以下方式级联：
第 n-1櫥线输出和第 n+2栅线输出分别作为本级 GOA单元的触发信号， 第 11+1栅线输出和第 11+4栅线输出分别作为本级 GOA单元的复位信号， 四条时钟 线分别与本级 GOA单元的第二选择输入电路上的时钟脉冲输入连接， 以提供周 期相同但具有相位差的时钟信号， 并在不同时钟脉 下将栅极高电平输入和公共 电极高电平输入分别选通以输出相应的上拉电压；
其中， 本级 GOA单元的输出为第 II栅线输出和第 ι +3公共电极线输出。
10、如权利要求 9所述的驱动电路， 其中， 所述反相截止的二极管为 ffl MOS 管或 TFT管构成的二极管等效电路， 其中， MOS管或 TFT管栅极与源极连接作 为所述阳极， 漏极作为所述阴极。
11、 如权利要求 9所述的驱动电路， 其中， 第 n- i和第 n+2栅线中的电平信 号或边沿信号为低电平信号或下降沿信号， 第 n+1和第 ίΐ+4栅线上的电平信号或 者边沿信号为高电平信号或上升沿信号。
12、 如权利要求 9所述的驱动电路， 其中， 四个相同周期异步工作的时钟脉 冲输入在相位上依次相差四分之一工作周期。
13、 如权利要求 1所述的驱动电路， 其中， 所述 GOA单元电路输出的公共 电极驱动信号与第《十3栅线上的信号同步。
14、 如权利要求 13所述的 GOA单元， 其中， 所述第二选择输入电路包括四 个 TFT晶体管， 其中， 两个 TFT晶体管源漏极相连， 两个栅极分别由第二 ^钟 脉冲输入和第 时钟脉冲输入控制， 用以接入栅极高电平输入；
另两个 TFT晶体管源漏极相连，两个栅极分别由第 ·ΰί钟脉冲输入和第四时 钟脉冲输入控制， 用以接入公共电极高电平输入。
15. 如权利要求 13所述的 GOA单元， 其中， 所述第四选择输入电路包括两 个 TFT晶体管，其中栅极分别与第 n+i和第 n+4栅线的输出连接，源极分别对应 与栅极低电平输入和公共电极低电平输入连接。
16、 如权利要求 13 所述的 GOA单元， 其中， 所述选择输出电路包括两个
TFT晶体管， 其中两个極极分别由第三时钟脉冲输入和第一时钟脉冲输入控制， 两个源极共同连接到触发输出端，以在不同时序下分别输出第 ι 栅线输出和第 11+3 公共电极线输出， 其中， 这两个脉 时序相差四分之:三工作周期。 〗7、 一种其上形成有如权利要求 9所述的驱动电路的阵列， 包括- 横向并行的栅线和公共电极线；
纵向并行的时钟输入线、 栅极高低电平输入线、 公共电极高低电平输入线， 其中， 極线与公共电极线的输出在级联位置上相差 3个级， 或时序上相差四分之 三个工诈周期。
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KR20160100402A (ko) 2016-08-23
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US20160240158A1 (en) 2016-08-18
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