Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
  • G01R31/374—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with means for correcting the measurement for temperature or ageing
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
  • G01R31/382—Arrangements for monitoring battery or accumulator variables, e.g. SoC
  • G01R31/3842—Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01R19/0046—Arrangements for measuring currents or voltages or for indicating presence or sign thereof characterised by a specific application or detail not covered by any other subgroup of G01R19/00
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01R19/32—Compensating for temperature change
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
  • H01M10/00—Secondary cells; Manufacture thereof
  • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
  • H01M10/48—Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45048—Calibrating and standardising a dif amp
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45138—Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
  • Y02E60/10—Energy storage using batteries

Definitions

• FIG. 1 shows an example of a battery monitoring system or fuel gauge system. Battery current flows between a system node VSYS and a battery terminal VBATT through a main transistor (e.g., a transistor BATFET).
• a main transistor e.g., a transistor BATFET
• replica devices e.g., replica transistors Replica1 and Replica2
• the replica transistors Replica1 and Replica2 produce replica currents (e.g., a charging current I CHARGE and a discharge current I DISCHARGE ) that are a scaled down version of the battery current.
• the charging current I CHARGE and the discharge current I DISCHARGE flow through sensing resistors R1 and R2, respectively.
• An analog to digital converter (ADC) samples the voltage across resistors R1 and R2 to determine the charge across the battery.
• the battery monitoring system uses the output of the ADC to monitor the battery. [0003] For accuracy, it is important to control the voltage across control transistors M1 and M2 for the replica device.
• the system may use a feedback loop to control the voltage.
• amplifiers AMP1 and AMP2 control the voltage across control transistors M1 and M2, respectively.
• the inputs of amplifier AMP1 are coupled to the system node VSYS and the gate and source of replica transistor Replica2 and the output is coupled to a control transistor M1.
• the inputs of amplifier AMP2 are coupled to the system node VBATT and the drain of replica transistor Replica1 and the output is coupled to a control transistor M2.
• Amplifiers AMP1 and AMP2 control the voltage at the gate of control transistors M1 and M2, respectively, to produce the replica currents.
• offset error within each amplifier may cause errors in the replica currents.
• the resistor used to measure the voltage can cause errors across process and temperature variations.
• a circuit in one embodiment, includes a first amplifier having a first differential input, a second differential input, and an output.
• the first differential input is coupled to a replica device and a voltage of a battery and the output is coupled to a control device.
• the replica device is configured to generate a replica current of a current flowing through the battery where the first amplifier controls the control device to control the replica current.
• the circuit also includes a second amplifier having a third differential input, a fourth differential input, and an output.
• the second amplifier is configured to compensate for a first offset error of the first amplifier and a second offset error of the second amplifier based on selectively coupling the third differential input to the output of the first amplifier during a first phase, selectively coupling the output of the second amplifier to the second differential input during the first phase, and selectively coupling the output of the second amplifier to the fourth differential input during a second phase.
• the second amplifier stores the second offset error of the second amplifier on a first set of storage elements coupled to the fourth differential input of the second amplifier for use in compensating for the second offset error of the second amplifier during the first phase.
• the second amplifier stores the first offset error of the first amplifier on a second set of storage elements coupled to the second differential input of the first amplifier for use in compensating for the first offset error of the first amplifier during a subsequent second phase.
• a gain of the second amplifier is used to compensate for the first offset error during the first phase.
• the output of the second amplifier is a differential output, and the circuit further includes a common mode feedback circuit coupled to the differential output and configured to maintain a common mode portion of the differential output at a fixed value different from the voltage of the battery.
• the circuit further includes a resistor configured to receive the replica current, wherein a voltage across the resistor is sensed to monitor the voltage across the battery.
• a method includes: during a first phase, storing, by a second amplifier, a first offset error of a first amplifier on a first set of storage elements coupled to a differential input of the first amplifier for use in compensating for the first offset error of the first amplifier during a second phase; during the second phase, storing, by the second amplifier, a second offset error of the second amplifier on a second set of storage elements coupled to a differential input of the second amplifier for use in compensating for the second offset error of the second amplifier during a subsequent first phase; during the second phase, controlling, by the first amplifier, a control device to control a replica current generated by the replica device, the replica current being a replica of a current flowing through the battery, wherein the first offset error is compensated for using the first offset error stored during the first phase; and during the subsequent first phase, controlling, by
• FIG. 1 shows an example of a battery monitoring system or fuel gauge system.
• FIG. 2 depicts an example of a battery monitoring system according to one embodiment.
• FIG. 3 depicts an example of amplifier ErrAmp2 during clock phase ⁇ 2 according to one embodiment.
• FIG. 4 depicts an example of amplifiers ErrAmp1 (amplifiers A1 and A2) and ErrAmp2 (amplifiers An1 and An2) during clock phase ⁇ 1 according to one embodiment.
• FIG. 5 depicts an example of amplifier ErrAmp1 in clock phase ⁇ 2 according to one embodiment.
• FIGs. 6 and 7 show examples of implementations of ErrAmp1 and ErrAmp2, respectively.
• FIG. 8 shows an example of a battery monitoring system using a single output of amplifier ErrAmp2 according to one embodiment.
• FIG. 9 depicts a simplified flowchart of a method for compensating for offset error according to one embodiment.
• FIG. 10 shows an example implementation of resistor R 1 to compensate for temperature variations according to one embodiment.
• FIG. 11 depicts an example of the temperature correction using resistor rsp1 according to one embodiment. DETAILED DESCRIPTION
• FIG. 2 depicts an example of a battery monitoring system 200 according to one embodiment.
• Battery monitoring system 200 may monitor battery currents (e.g., discharging and charging currents) for a battery (BATT) 202 flowing through a transistor BATFET from a node VSYS to a node VBATT.
• BATT battery
• FIG. 2 only the charging current is shown, but a person skilled in the art will appreciate how to implement the battery monitoring system to monitor the discharging current.
• Battery monitoring system 200 may monitor the battery current using an internal (e.g., on chip) current-sensing resistor R 1 .
• System 200 uses a replica transistor Replica1 to generate a replica current of a battery current I B that flows through battery transistor BATFET and battery 202 through a node VBATT.
• transistors BATFET and replica1 may be N-channel MOSFET devices with their gate and sources coupled together.
• the replica current I CHARGE flows through transistor Replica1 and may be a scaled-down version of the battery current I B .
• Amplifiers ErrAmp1 and ErrAmp2 form a feedback loop that controls the voltage across a replica device, such as a control transistor M c , which operates in different operating regions (saturation or linear) depending on the mode of operation of a linear charger for battery 202.
• amplifier ErrAmp1 controls a gate voltage of control transistor M c to control the replica current I CHARGE through sensing resistor R 1 .
• the control of control transistor M c may regulate the replica current I CHARGE to be proportional to the battery current I B .
• an ADC (not shown) may measure the voltage across sensing resistor R 1 , where the output of the ADC is used by a battery management system or fuel gauge measurement algorithm.
• the offset error of the amplifiers may affect the performance of battery monitoring system 200.
• the replica current I CHARGE may be small and the voltage across sensing resistor R 1 may be as low as hundreds of microvolts.
• the offset error of amplifiers ErrAmp1 and ErrAmp2 may affect the measured voltage.
• Particular embodiments compensate for the amplifier offset error and also employ a technique to reduce the effect of temperature variations on resistor R 1 .
• amplifier ErrAmp1 may include a first differential input and a second differential input along with an output coupled to transistor M c .
• Amplifier ErrAmp2 may include a first differential input, a second differential input, and a differential output.
• amplifier ErrAmp1 and amplifier ErrAmp2 have two gain stages as will be described in more detail below.
• amplifier ErrAmp2 is described as having a differential output, amplifier ErrAmp2 may have a single output. As will be discussed in more detail below, the differential output allows system 200 the compensation to be performed at a different voltage than VBATT or a rail voltage of the system.
• Amplifier ErrAmp2 may be a nulling amplifier that is used to compensate for the offset error in the main amplifier ErrAmp1. Further, Amplifier ErrAmp2 also compensates for its own offset error. As will be discussed in more detail below, the technique may be used continuously to track changes in the offset error and effectively compensate for the changes in the offset error.
• Battery monitoring system 200 may use multiple clock phases, such as a clock phase ⁇ 1 and a clock phase ⁇ 2, to compensate for the offset errors of amplifier ErrAmp1 and amplifier ErrAmp2.
• clock phase ⁇ 1 amplifier ErrAmp2 stores the offset error of amplifier ErrAmp1 on capacitors C1. This value will be used to compensate for the offset error of amplifier ErrAmp1 in a subsequent clock phase ⁇ 2.
• clock phase ⁇ 2 system 200 stores the offset error of amplifier ErrAmp2 on capacitors C2.
• switches S1 and S2 may be open or closed based on the clock phase. For example, switches S1 are closed during clock phase ⁇ 1 and open during clock phase ⁇ 2, and switches S2 are closed during clock phase ⁇ 2, and open during clock phase ⁇ 1.
• the use of switches S1 and S2 couples the inputs and outputs of amplifiers ErrAmp1 and ErrAmp2 differently depending on the clock phase.
• Amplifier ErrAmp2 includes a first amplifier An1 and a second amplifier An2 that receive a first differential input and a second differential input, respectively. Both inputs of the differential input of amplifier An1 are coupled to battery 102.
• the offset error of amplifier An1 is shown as an offset error voltage Von1 at the input of one of the differential inputs.
• a feedback path from the output of amplifier ErrAmp2 to the differential input of amplifier An2 is used.
• the output of amplifier ErrAmp2 e.g., differential output VonullN and VonullP
• capacitors C2 which can store the offset error during clock phase ⁇ 2.
• the offset error stored on capacitors C2 includes an inferred offset error voltage Von2 on one input of the differential input of amplifier An2 and the offset error voltage Von1.
• CMFB common mode feedback circuit
• the differential output may be the combination of vn1 + vn2, which reflect the offset errors Von1 and Von2.
• the outputs VonullN and VonullP are then stored on capacitors C2 during clock phase ⁇ 2.
• the voltage of the common mode amplifier Acm is based on the gain of amplifier Acm and a voltage Vref. Voltage Vref may be different from the voltage of the battery or rail, such as Vdd/2.
• Equation 1 shows the calculation for output VonullP and equation 2 shows the calculation for output VonullN.
• output VonullP is the common mode output voltage Vocm plus half of the differential output of vn1 and vn2.
• Output VonullN is equal to the common mode voltage Vocm minus half of the differential output of vn1 and vn2.
• Equation 3 shows the calculation of the differential between outputs VonullN and VonullP and equations 4 and 5 show the calculation of the amplifier outputs of vn2 and vn1.
• equation 3 shows that the differential output ⁇ Vonull is equal to the amplifier outputs vn1 and vn2 as the common mode voltage Vocm cancels.
• Output vn2 is equal to the gain of amplifier An2 and the offset error of amplifier An2 minus the differential output.
• Output vn1 is equal to the gain of amplifier An1 and the offset error of amplifier An1.
• the differential output voltage ⁇ Vonull may be determined based on equations 3, 4, and 5.
• Equation 6 shows that the differential output of amplifier ErrAmp2 is based on the offset errors Von1 and Von2 of amplifiers An1 and An2 and the gain of error amplifiers An1 and An2. These values are stored on capacitors C2 during clock phase ⁇ 2. As will be discussed in the next figure, the values stored on capacitors C2 are used to cancel the offset errors Von1 and Von2 during the next clock phase ⁇ 1.
• FIG. 4 depicts an example of amplifiers ErrAmp1 (amplifiers A1 and A2) and ErrAmp2 (amplifiers An1 and An2) during clock phase ⁇ 1 according to one embodiment. During clock phase ⁇ 1, switches S1 are closed and switches S2 are open.
• the differential input of amplifier A2 is coupled to the differential output of amplifier ErrAmp2. Also, the offset error of amplifier A2 is shown as an offset error voltage Vo2 on one of the inputs of amplifier A2.
• amplifier ErrAmp2 stores outputs VonullN and VonullP on capacitors C1. Equation 7 shows the differential voltage across capacitors C1: rAmp2 is equal to the gain of amplifier An1 times the difference between the battery voltage VBATT and the output voltage of amplifier ErrAmp1. The offset errors Von1 and Von2 of amplifiers An1 and An2 have been canceled in this case via the values stored on capacitors C2.
• Equation 8 shows the output of amplifier ErrAmp1 as follows:
• equation 8 can be approximated to:
• FIG. 5 depicts an example of amplifier ErrAmp1 in clock phase ⁇ 2 according to one embodiment.
• the inputs of amplifier A1 are coupled to the output Vout of amplifier ErrAmp1 and to the battery voltage VBATT.
• the offset error voltage Vo1 is also shown at an input of amplifier A1.
• the inputs of amplifier A2 are coupled to capacitors C1.
• the offset error voltage Vo2 is also shown at an input of amplifier A2.
• capacitors C1 hold the differential voltage ⁇ Vonull1, which is based on the gain of amplifiers A1 and A2 and the offset errors of amplifiers A1 and A2 of Vo1 and Vo2.
• the differential output voltage of amplifier ErrAmp2 is equal to the gain of Amplifier An1 times the difference of VBATT and Vout.
• the values stored on capacitors C1 are a function of the gain of amplifiers A1 and A2 and the offset errors Vo1 and Vo2. Equation 10 summarizes these values:
• Equation 11 represents the determination of the output voltage Vout of ErrAmp1, which shows the cancellation of offset errors Vo1 and Vo2 as follows:
• FIG. 6 shows examples of implementations of ErrAmp1 and ErrAmp2, respectively. However, it will be understood that other implementations may be appreciated.
• differential amplifiers A1 and A2 are shown as a differential pair of transistors M A1 and a differential pair of transistors M A2 . Amplifiers A1 and A2 are coupled to a shared output stage 602.
• Shared output stage 602 provides a resistor gain that converts a current output of differential amplifiers A1 and A2 into a voltage output. Different variations of shared output stage 602 may be appreciated.
• differential amplifiers An1 and An2 are shown as a differential pair of transistors M AN2 and a differential pair of transistors M AN1 , respectively.
• the output of amplifiers An1 and An2 are coupled to a shared output stage 702.
• Shared output stage 702 also converts a current output of amplifiers An1 and An2 to a voltage, but the output of shared output stage 702 is a differential output Out and Out+.
• a common mode feedback circuit 704 is coupled to the differential output and maintains an average value of the differential output at a fixed level based on a voltage Vref, which may be at a different level than the rail voltage, such as 1 ⁇ 2(Vdd).
• Vref a voltage
• Vref a voltage
• the differential voltage measurement is moved away from the rail voltage or battery voltage VBATT. For example, if the differential voltage measurement is close to the rail, then it might be hard to measure the differential voltage accurately.
• setting the common mode differential output voltage to a value, such as 1 ⁇ 2 of the rail voltage makes calculating the offset at the average value more accurate. That is, outputs Out+ and Out- are both set at a common mode voltage.
• FIG. 8 shows an example of a battery monitoring system 800 using a single output of amplifier ErrAmp2 according to one embodiment.
• a single output of amplifier ErrAmp2 is coupled to amplifier ErrAmp1.
• the single output of amplifier ErrAmp2 is coupled to an input of amplifier ErrAmp2 in a feedback configuration.
• Another input of amplifier ErrAmp2 and another input of amplifier ErrAmp1 are coupled to a voltage Vref, which may be a voltage different from the rail voltage.
• Vref the voltage stored across capacitors C2
• these stored offset errors compensate for the offset errors of amplifier ErrAmp2.
• Vout ⁇ VBATT due to the gain of amplifier An2 (not shown) of amplifier ErrAmp2 substantially canceling the offset errors of amplifier ErrAmp1.
• FIG. 9 depicts a simplified flowchart 900 of a method for compensating for offset error according to one embodiment.
• amplifier ErrAm2 stores a first offset error of amplifier ErrAmp1on capacitors C1 for use in compensating for the offset error of amplifier ErrAmp1during a second phase.
• amplifier ErrAmp2 stores an offset error of amplifier ErrAmp2 on capacitors C2 for use in compensating for the offset error of amplifier ErrAmp2 during a subsequent first phase.
• amplifier ErrAmp1 controls control transistor M C to control a replica current generated by the replica device.
• the first offset error is compensated for using the first offset error stored during the first phase.
• amplifier ErrAmp1 controls control transistor M C to control the replica current where a gain of the second amplifier is used to compensate for the offset error of amplifier ErrAmp1 and the offset error of amplifier ErrAmp2 is compensated for using the offset error of amplifier ErrAmp2 stored on capacitors C2 during the second phase.
• sensing resistor R 1 may be located on chip and thus may be sensitive to temperature variations of the chip.
• resistor R 1 shows an example implementation of resistor R 1 to compensate for temperature variations according to one embodiment.
• the temperature variations may be compensated for during the current voltage conversion using two types of resistors.
• the first type of resistor R is a poly resistor with P+ doping having a negative temperature coefficient.
• the second type of resistors rsp are silicided and having a positive temperature coefficient. The opposite temperature coefficients can be used to compensate for temperature variations.
• the size of resistor rsp e.g., rsp 1, rsp 2, rsp 3, . . ., rsp N
• taps 1002 can be adjusted via taps 1002.
• FIG. 11 depicts an example of the temperature correction using resistor rsp1 according to one embodiment.
• Resistor RSP in FIG. 10 represents the combination of resistors rsp1 - rspN that are coupled to the replica current based on the tap settings.
• Vout may be determined as follows: [0059] Vout ⁇ I/2 (R + 1/2rsp).
• the output voltage Vout across sensing resistor R 1 is equal to the resistance of R that is compensated by the resistance of resistor rsp.
• internal resistors are discussed as being used, particular embodiments may also use external resistors that are off-chip and thus do not need temperature compensation.
• the above description illustrates various embodiments of the present disclosure along with examples of how aspects of the particular embodiments may be implemented. The above examples should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the particular embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the present disclosure as defined by the claims. WHAT IS CLAIMED IS:

Landscapes

• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Electrochemistry (AREA)
• General Chemical & Material Sciences (AREA)
• Amplifiers (AREA)
• Measurement Of Current Or Voltage (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=52424124

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (5)

Citations (4)

Family Cites Families (23)

• 2014
  • 2014-01-07 US US14/149,739 patent/US9217780B2/en active Active
• 2015
  • 2015-01-07 WO PCT/US2015/010529 patent/WO2015105915A1/en not_active Ceased
  • 2015-01-07 JP JP2016542735A patent/JP6602766B2/ja active Active
  • 2015-01-07 CN CN201580003828.5A patent/CN105899958B/zh not_active Expired - Fee Related
  • 2015-01-07 EP EP15701441.6A patent/EP3092501B1/en not_active Not-in-force
  • 2015-01-07 KR KR1020167021298A patent/KR101740581B1/ko active Active

Patent Citations (4)

Also Published As

Similar Documents

Legal Events