WO2015096721A1 - 扫描驱动器及使用该扫描驱动器的有机发光显示器 - Google Patents

扫描驱动器及使用该扫描驱动器的有机发光显示器 Download PDF

Info

Publication number
WO2015096721A1
WO2015096721A1 PCT/CN2014/094751 CN2014094751W WO2015096721A1 WO 2015096721 A1 WO2015096721 A1 WO 2015096721A1 CN 2014094751 W CN2014094751 W CN 2014094751W WO 2015096721 A1 WO2015096721 A1 WO 2015096721A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
scan
line
clock
output
Prior art date
Application number
PCT/CN2014/094751
Other languages
English (en)
French (fr)
Inventor
胡思明
朱晖
黄秀颀
高孝裕
Original Assignee
昆山工研院新型平板显示技术中心有限公司
昆山国显光电有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昆山工研院新型平板显示技术中心有限公司, 昆山国显光电有限公司 filed Critical 昆山工研院新型平板显示技术中心有限公司
Priority to US16/416,284 priority Critical patent/USRE48737E1/en
Priority to US15/108,284 priority patent/US9847062B2/en
Priority to JP2016558253A priority patent/JP2017503217A/ja
Priority to KR1020167016624A priority patent/KR101844701B1/ko
Priority to EP14873458.5A priority patent/EP3067878A4/en
Publication of WO2015096721A1 publication Critical patent/WO2015096721A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to an organic light emitting tube display, and more particularly to a scanning driver capable of reducing power consumption of a scan driver and an organic light emitting display using the same.
  • a light-emitting device used in an organic light-emitting display is an organic light-emitting diode (Organic)
  • OLED Light-Emitting Diode
  • TFT Thin Film Transistor
  • the conventional scan driving circuit is composed of a plurality of transistors, a start signal line IN, a clock line CLK1, CLK2, a power supply high level VGH, and a power supply low level VGL.
  • the clock lines CLK1 and CLK2 are hopped, the circuit has a parasitic capacitance, which causes a weak reverse current in the circuit. Therefore, when the entire screen N lines work together, a reverse current of several milliamperes or more is generated, which causes the display of the screen to be uneven and the power consumption is too high.
  • the present invention provides a scan driver comprising: a plurality of cascade structures for receiving signals of a first clock line having opposite phases and signals of a second clock line, The joint structure sequentially generates a scan signal, wherein each of the cascade structures includes: a first transistor connected to the start signal line or the scan output line of the previous cascade structure, the first transistor including the first clock line connected to the first clock a second transistor connected to the second clock line and the scan output line, the second transistor includes a gate connected to the output end of the first transistor; and a third transistor connected to the power supply high level VGH, Three crystal
  • the tube includes a gate connected to the output end of the second transistor; a fourth transistor connected to the power supply low level VGL and the output terminal of the third transistor, and the fourth transistor includes a gate connected to the first clock line; a fifth transistor connected to the power supply high level VGH and the scan output line, the fifth transistor includes a gate connected to the output end of the fourth transistor and the output end of the third transistor; connected to
  • each of the cascade structures further includes: a second capacitor connected between the output terminal of the first transistor and a fixed potential.
  • the fixed potential is the power supply low level VGL.
  • the fixed potential is the power supply high level VGH.
  • the first clock terminal of the odd cascade structure is connected to the first clock line
  • the second clock end is connected to the second clock line
  • the first clock of the even cascade structure is connected.
  • the end is connected to the second clock line
  • the second clock end is connected to the first clock line.
  • the transistor is a bidirectional PMOS transistor or a bidirectional P-type thin film field effect transistor.
  • the present invention also provides an organic light emitting display, comprising: a pixel array connected to a data line and a scan output line; a data driver providing a data signal to the data line; a scan driver providing a scan signal to the scan output line; The driver provides the sequencing signal and the sequencing controller of the power supply high level VGH and the power supply low level VGL.
  • the present invention has the following beneficial effects: By adding a first capacitor C1 between the output end of M1 and the scan output line, the first capacitor C1 is hopped on the second clock line, preventing M2 micro-conduction Bypassing, thereby reducing the reverse current of the scan driver, reducing power consumption, and improving the display quality of the screen.
  • FIG. 1 is a circuit diagram of an embodiment of an organic light emitting display of the present invention.
  • FIG. 2 is a circuit diagram of a pixel display unit in an organic light emitting display
  • FIG. 3 is a circuit diagram of a scan driver of the present invention.
  • FIG. 4 is a circuit diagram of the first embodiment of the cascade structure 1 of FIG. 3; 5 is a circuit sequence diagram of the cascading structure 1 of FIG. 4 in one frame; [0017] FIG.
  • FIG. 6 is a circuit diagram of a second embodiment of the cascade structure 1 of FIG. 3;
  • FIG. 7 is a circuit diagram of a third embodiment of the cascade structure 1 of FIG. 3.
  • the organic light emitting display includes a data driver 110 that supplies a data signal to a data line, and a scan driver 111 that sequentially supplies a scan signal to the scan output line.
  • the scan driver 111 is provided with a sequence signal and a power supply high level VGH, a power supply low level VGL sequence controller 112, and a plurality of pixel display units 113.
  • the purpose of the scan driver circuit is to sequentially generate scan signals for the display panel to drive the pixels in the display panel.
  • the pixel circuit includes a transistor T1, a transistor ⁇ 2, and a capacitor C0.
  • the gate of T1 is connected to the scan output line of the scan driver, and the source of T1 is connected to the data line of the data driver.
  • the capacitor CO- terminal is connected to the fixed power supply, and the other end is connected to the drain of T1.
  • the gate of T2 is connected to the drain of T1, the source is connected to a fixed power supply, and the drain is connected to the OLED.
  • the working principle of the circuit is as follows:
  • the scan driver supplies a scan signal to T1 through the scan output line, and the data driver provides a data signal to T1.
  • T1 When T1 is turned on, the data voltage is transmitted to the T2 gate, and the TFT T2 generates a corresponding current. Flows to the OLED, causing the OLED to emit light.
  • the scan driver 111 employs a scan driver in the following embodiments.
  • the scan driver includes a plurality of cascade structures, each of which is connected to the clock lines CLK1 and CLK2 having opposite phases. Each cascade structure sequentially generates an output signal, that is, a scan signal, to scan output lines S1 to SN.
  • the first clock terminal of the odd cascade structure is connected to the first clock line
  • the second clock end is connected to the second clock line
  • the first clock of the even cascade structure is connected.
  • the end is connected to the second clock line
  • the second clock end is connected to the first clock line.
  • the cascode structure 1 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor. M4, the fifth transistor M5, the first capacitor C1, the start signal line IN, the first clock line CLK1, the second clock line CLK2, the power supply high level VGH, and the power supply low level VGL.
  • the gate of the first transistor M1 is connected to the first clock line CLK1, the source of M1 is connected to the start signal line IN, and the drain is connected to the gate of the second transistor M2.
  • the source of the second transistor M2 is connected to the second clock line CLK2, and the drain is connected to the scan output line.
  • the gate of the third transistor M3 is connected to the drain of the second transistor, the source is connected to the power supply high level VGH, and the drain is connected to the source of the fourth transistor M4.
  • the gate of the fourth transistor M4 is connected to the first clock line CLK1, the source is connected to the drain of M3, and the drain of M4 is connected to the power supply low level VGL.
  • the gate of the fifth transistor M5 is connected to the source of M4, the source of M5 is connected to the power supply high level VGH, and the drain of M5 is connected to the scan output line.
  • the first capacitor C 1 has one end connected to the drain of M1 and the other end connected to the scan output line.
  • the transistors M1, M2, M3, M4, and M5 are bidirectional PMOS transistors or bidirectional P-type thin film field effect transistors, and the source and the drain are interchangeable.
  • FIG. 5 is a circuit sequence diagram of the cascading structure of FIG. 4 in one frame.
  • IN is a sequence diagram of the start signal line
  • CLK1 is a sequence of the first clock line.
  • CLK2 is a sequence diagram of the second chirp clock line
  • N 1 is a sequence diagram of the output end of M1
  • S1 to SN are sequence diagrams of the cascading structure 1 to the cascade structure n scan output line signals, respectively.
  • the working principle of the cascading structure 1 circuit is:
  • Vth is the absolute value of the threshold voltage of M1
  • M2 remains on; when CLK2 changes from high to low, due to the coupling of capacitor C1, the voltage at N1 drops from VGL+Vth to 2VGL+Vth (Vth is Ml's threshold voltage is absolute), M2 remains on, so the drain of M2 outputs a low level to Sl.
  • the gate of M3 is low and the source is very high VGH, so M3 turns on and outputs a high level.
  • the capacitor C1 When the capacitor C1 is present, after the M1 is turned off, the capacitor C1 can maintain the original high potential of the N1 terminal, thereby preventing the micro-conduction of the M2, reducing the power consumption of the scan driver, and improving the display quality of the screen.
  • the transistor is a bidirectional PMOS transistor or a bidirectional P-type thin film field effect transistor.
  • the cascade structure 2 to the cascade structure n sequentially receives the signals of the scan output lines of the previous connected structure, and the sequence diagram jumps as shown in FIG. 5.
  • the first capacitor C1 is added between the output end of the M1 and the scan output line, so that the first capacitor C1 jumps on the second clock line, preventing M2.
  • Micro-conduction reduces the reverse current of the scan driver, reduces power consumption, and improves the display quality of the screen.
  • FIG. 6 is a circuit diagram of a second embodiment of the cascade structure 1 of FIG. 3, the circuit further including a second capacitor C2 connected between the output terminal of the first transistor M1 and a fixed potential.
  • the fixed potential is the power supply low level VGL.
  • the second capacitor C2 can further maintain the voltage stability at the N1 terminal, and minimize the voltage difference of the first capacitor C1, and minimize the leakage current.
  • 7 is a circuit diagram of a third embodiment of the cascade structure 1 of FIG. 3, the circuit further including a first transistor connected to the first transistor.
  • the fixed potential is a power supply high level VGH.
  • the second capacitor C2 can further maintain the voltage at the N1 terminal to be stable, and minimize the voltage difference of the first capacitor C1 and minimize the leakage current.
  • the organic light emitting display includes a data driver that supplies a data signal to the data line, a scan driver that sequentially supplies a scan signal to the scan output line, and provides a scan signal to the scan driver and Power supply high level VGH, power low level VGL sequence controller and multiple pixel display units.
  • the purpose of the scan driver circuit is to sequentially generate a scan signal for the display panel to drive the pixels in the display panel.
  • the scan driver includes a plurality of cascade structures, each of which is connected to the clock lines CLK1 and CLK2 having opposite phases, and each of the cascade structures sequentially generates an output signal, that is, a scan signal to a scan output. Lines S1 to SN.
  • each of the cascade structures specifically includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first capacitor C1, a start signal line IN, and a first The sequence clock line CLK1, the second clock line CLK2, the power supply high level VGH, and the power supply low level VGL.
  • the first clock terminal of the odd-numbered cascade structure is connected to the first clock line
  • the second clock end is connected to the second clock line
  • the first cascade structure is first.
  • the end of the bell is connected to the second clock line
  • the second clock end is connected to the first clock line.
  • the transistor is a bidirectional PMOS transistor or a bidirectional P-type thin film field effect transistor.
  • the first capacitor C1 is added between the output end of the M1 and the scan output line, so that the first capacitor C1 jumps on the second clock line, preventing M2.
  • Micro-conduction reduces the reverse current of the scan driver, reduces power consumption, and improves the display quality of the screen.
  • the organic light emitting display includes a data driver that supplies a data signal to the data line, a scan driver that sequentially supplies a scan signal to the scan output line, and provides a scan signal to the scan driver and Power supply high level VGH, power low level VGL sequence controller and multiple pixel display units.
  • the function of the scan driving circuit is to sequentially generate a scan letter for the display panel. Number to drive the pixels in the display panel.
  • the scan driver includes a plurality of cascade structures, each of which is connected to the clock lines CLK1 and CLK2 having opposite phases, and each of the cascade structures sequentially generates an output signal, that is, a scan signal to a scan output. Lines S1 to SN.
  • each of the cascade structures specifically includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first capacitor C1, a start signal line IN, and a first The sequence clock line CLK1, the second clock line CLK2, the power supply high level VGH, and the power supply low level VGL.
  • the circuit also includes a second capacitor C2 coupled between the output of the first transistor M1 and a fixed potential. The fixed potential is the power supply low level VGL.
  • the second capacitor C2 can further maintain the voltage at the N1 terminal to be stable, and minimize the voltage difference of the first capacitor C1 and minimize the leakage current.
  • the organic light emitting display includes a data driver that supplies a data signal to the data line, a scan driver that sequentially supplies a scan signal to the scan output line, and provides a scan signal to the scan driver and Power supply high level VGH, power low level VGL sequence controller and multiple pixel display units.
  • the purpose of the scan driver circuit is to sequentially generate a scan signal for the display panel to drive the pixels in the display panel.
  • the scan driver includes a plurality of cascade structures, each of which is connected to the clock lines CLK1 and CLK2 having opposite phases, and each of the cascade structures sequentially generates an output signal, that is, a scan signal to a scan output. Lines S1 to SN.
  • each of the cascade structures specifically includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first capacitor C1, a start signal line IN, and a first The sequence clock line CLK1, the second clock line CLK2, the power supply high level VGH, and the power supply low level VGL.
  • the circuit also includes a second capacitor C2 coupled between the output of the first transistor M1 and a fixed potential. The fixed potential is the power supply high level VGH.
  • the second capacitor C2 can further maintain the voltage at the N1 terminal to be stable, and minimize the voltage difference of the first capacitor C1, and minimize the leakage current. It should be noted that the above embodiments are only intended to illustrate the present invention and are not intended to be limiting, and the present invention is not limited to the above examples, and all the technical solutions and improvements thereof without departing from the spirit and scope of the present invention should be covered by the present invention. In the scope of the claims.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种扫描驱动器及使用该扫描驱动器的有机发光显示器，该扫描驱动器包括：多个接收具有相反相位的第一时序时钟线（CK1）的信号和第二时序时钟线（CK2）的信号的级联结构，级联结构依次产生输出信号，其中每个级联结构包括：与起始信号线（IN）或前一级联结构的扫描输出线（S1，S2…）相连的第一晶体管（M1）；与第二时序时钟线（CK2）及扫描输出线（S1，S2…）相连的第二晶体管（M2）；与电源高电平VGH相连的第三晶体管（M3）；与电源低电平VGL及第三晶体管（M3）的输出端相连的第四晶体管（M4）；与电源高电平VGH及扫描输出线（S1，S2…）相连的第五晶体管（M5）；连接于第一晶体管（M1）输出端和扫描输出线（S1，S2…）之间的第一电容器（C1）。通过在M1的输出端及扫描输出线（S1，S2…）之间增加第一电容器（C1），阻止了第二晶体管（M2）微导通，从而减少了扫描驱动器的反向电流，减小功耗。

Description

扫描驱动器及使用该扫描驱动器的有机发光显示器 技术领域
[0001] 本发明涉及有机发光管显示器， 特别是涉及一种能够减少扫描驱动器功耗的扫 描驱动器及使用该扫描驱动器的有机发光显示器。
背景技术
[0002] 有机发光显示器中所使用的发光器件为有机发光二极管 （Organic
Light-Emitting Diode, 简称 OLED) 。 相比现在的主流平板显示技术薄膜晶体管 (Thin Film Transistor, 简称 TFT) 液晶显示器， OLED具有高对比度， 广视角 ， 低功耗， 体积更薄等优点， 有望成为继 LCD之后的下一代平板显示技术， 是 目前平板显示技术中受到关注最多的技术之一。
[0003] 现有扫描驱动电路由多个晶体管、 起始信号线 IN， 吋序吋钟线 CLK1、 CLK2, 电源高电平 VGH和电源低电平 VGL组成。 当吋序吋钟线 CLK1、 CLK2发生跳变 吋， 由于晶体管存在寄生电容， 会造成该电路产生微弱的反向电流。 因此当整 个屏体 N行共同工作吋， 会产生几毫安甚至更高的反向电流， 使得屏体显示不均 ， 且功耗过高。
技术问题
[0004] 针对传统技术中存在的扫描驱动器功耗过高的问题， 提供一种减少 OLED显示 器扫描驱动器的反向电流的装置。
问题的解决方案
技术解决方案
[0005] 为了解决上述技术问题， 本发明提供一种扫描驱动器包括： 多个接收具有相反 相位的第一吋序吋钟线的信号和第二吋序吋钟线的信号的级联结构， 级联结构 依次产生扫描信号， 其中每个级联结构包括： 与起始信号线或前一级联结构的 扫描输出线相连的第一晶体管， 第一晶体管包括与第一吋序吋钟线相连的栅极 ； 与第二吋序吋钟线及扫描输出线相连的第二晶体管， 第二晶体管包括与第一 晶体管的输出端相连的栅极； 与电源高电平 VGH相连的第三晶体管， 第三晶体 管包括与第二晶体管的输出端相连的栅极； 与电源低电平 VGL及第三晶体管的 输出端相连的第四晶体管， 第四晶体管包括第一吋序吋钟线相连的栅极； 与电 源高电平 VGH及扫描输出线相连的第五晶体管， 第五晶体管包括与第四晶体管 的输出端及第三晶体管的输出端相连的栅极； 连接于第一晶体管输出端和扫描 输出线之间的第一电容器。
[0006] 优选地， 每个级联结构还包括： 连接于第一晶体管输出端和固定电位之间的第 二电容器。
[0007] 优选地， 固定电位为电源低电平 VGL。
[0008] 优选地， 固定电位为电源高电平 VGH。
[0009] 优选地， 奇数级联结构的第一吋钟端与第一吋序吋钟线相连， 第二吋钟端与第 二吋序吋钟线相连， 偶数级联结构的第一吋钟端与第二吋序吋钟线相连， 第二 吋钟端与第一吋序吋钟线相连。
[0010] 优选地， 晶体管为双向 PMOS管或双向 P型薄膜场效应晶体管。
[0011] 本发明还提供一种有机发光显示器， 包括： 与数据线和扫描输出线连接的像素 阵列； 向数据线提供数据信号的数据驱动器； 向扫描输出线提供扫描信号的扫 描驱动器； 向扫描驱动器提供吋序信号及电源高电平 VGH和电源低电平 VGL的 吋序控制器。
发明的有益效果
有益效果
[0012] 本发明具有以下有益效果： 通过在 Ml的输出端及扫描输出线之间增加第一电 容器 Cl， 使得第一电容器 C1在第二吋序吋钟线发生跳变吋， 阻止 M2微导通， 从 而减少了扫描驱动器的反向电流， 减小功耗， 改善了屏体的显示品质。
对附图的简要说明
附图说明
[0013] 图 1为本发明有机发光显示器实施例的电路图；
[0014] 图 2为有机发光显示器中像素显示单元的电路图；
[0015] 图 3为本发明扫描驱动器的电路图；
[0016] 图 4为图 3中级联结构 1第一实施例的电路图； [0017] 图 5为图 4级联结构 1在一帧内的电路吋序图；
[0018] 图 6为图 3中级联结构 1第二实施例的电路图；
[0019] 图 7为图 3中级联结构 1第三实施例的电路图。
本发明的实施方式
[0020] 图 1为本发明有机发光显示器实施例的电路图， 如图 1所示， 该有机发光显示器 包括向数据线提供数据信号的数据驱动器 110、 依次向扫描输出线提供扫描信号 的扫描驱动器 111、 向扫描驱动器 111提供吋序信号和电源高电平 VGH、 电源低 电平 VGL的吋序控制器 112以及多个像素的显示单元 113。 扫描驱动电路的作用 是依次产生提供给显示面板扫描信号以驱动显示面板中的像素。
[0021] 图 2为有机发光显示器中像素显示单元的电路图， 如图 2所示， 该像素电路中包 括晶体管 Tl、 晶体管 Τ2、 电容 C0。 其中 T1的栅极与扫描驱动器的扫描输出线相 连， T1的源极与数据驱动器的数据线相连。 电容 CO—端与固定电源相连， 另一 端与 T1的漏极相连。 T2的栅极与 T1的漏极相连， 其源极与固定电源相连， 漏极 与 OLED相连。
[0022] 该电路的工作原理为： 扫描驱动器通过扫描输出线向 T1提供扫描信号， 数据驱 动器向 T1提供数据信号， 当 T1导通吋， 数据电压传输到 T2栅极， TFT T2产生相 应的电流流向 OLED， 从而使得 OLED发光。
[0023] 扫描驱动器 111采用以下实施例中的扫描驱动器。
[0024] 图 3为本发明扫描驱动器的电路图， 如图 3所示， 扫描驱动器中包括多个级联结 构， 每个级联结构均与具有相反相位的吋序吋钟线 CLK1和 CLK2连接， 每个级 联结构依次产生输出信号即扫描信号至扫描输出线 S1至 SN。
[0025] 优选地， 奇数级联结构的第一吋钟端与第一吋序吋钟线相连， 第二吋钟端与第 二吋序吋钟线相连， 偶数级联结构的第一吋钟端与第二吋序吋钟线相连， 第二 吋钟端与第一吋序吋钟线相连。
[0026] 或奇数级联结构的第一吋钟端与第二吋序吋钟线相连， 第二吋钟端与第一吋序 吋钟线相连， 偶数级联结构的第一吋钟端与第一吋序吋钟线相连， 第二吋钟端 与第二吋序吋钟线相连。 [0027] 图 4为图 3中级联结构 1第一实施例的电路图， 如图 4所示， 级联结构 1中包括第 一晶体管 Ml、 第二晶体管 M2、 第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5 、 第一电容器 Cl、 起始信号线 IN、 第一吋序吋钟线 CLKl、 第二吋序吋钟线 CLK 2、 电源高电平 VGH以及电源低电平 VGL。
[0028] 其中， 第一晶体管 Ml的栅极与第一吋序吋钟线 CLK1相连， Ml的源极与起始 信号线 IN相连， 漏极与第二晶体管 M2的栅极连接。 第二晶体管 M2的源极与第二 吋序吋钟线 CLK2相连， 漏极与扫描输出线相连。 第三晶体管 M3的栅极与第二晶 体管的漏极相连， 源极与电源高电平 VGH相连， 漏极与第四晶体管 M4的源极相 连。 第四晶体管 M4的栅极与第一吋序吋钟线 CLK1相连， 源极与 M3的漏极相连 ， M4的漏极与电源低电平 VGL相连。 第五晶体管 M5的栅极与 M4的源极相连， M5的源极与电源高电平 VGH相连， M5的漏极与扫描输出线相连。 第一电容器 C 1一端连接于 Ml的漏极， 另一端连接于扫描输出线。
[0029] 优选地， 晶体管 Ml、 M2、 M3、 M4、 M5采用双向 PMOS管或双向 P型薄膜场效 应晶体管， 其源极与漏极可互换。
[0030] 图 5为图 4级联结构在一帧内的电路吋序图， 如图 5所示， IN为起始信号线的吋 序图， CLK1为第一吋序吋钟线的吋序图， CLK2为第二吋序吋钟线的吋序图， N 1为 Ml的输出端的吋序图， S1至 SN分别为级联结构 1至级联结构 n扫描输出线信 号的吋序图。 级联结构 1的电路的工作原理为：
[0031] 当起始信号线 IN信号跳变为低电平、 CLK1为低电平、 CLK2为高电平吋， Ml 导通， 其输出电压 N1为低电平 VGL+Vth (Vth为 Ml的阈值电压绝对值） 。 电容 C 1被充电。 M2的栅极为低电平， 源极为高电平， 因此 M2导通， 从而 S1输出高电 平。 同吋由于 CLK1为低电平， M4也导通并输出低电平至 M5的栅极， 从而导致 M5导通， 因此 M5输出高电平 VGH至 Sl。
[0032] 当起始信号线 IN信号跳变为高电平， CLK1为高电平， CLK2为低电平吋， Ml 截止。 当 CLK2为高电平吋， N1由于电容 C1放电能够暂吋保持低电平 VGL+Vth
(Vth为 Ml的阈值电压绝对值） ， M2保持导通状态； 当 CLK2从高变为低电平吋 ， 由于电容 C1的耦合作用， N1端电压从 VGL+Vth下降为 2VGL+Vth (Vth为 Ml 的阈值电压绝对值） ， M2依然保持导通状态， 因此 M2的漏极输出低电平至 Sl。 M3的栅极为低电平， 源极为高电平 VGH， 因此 M3导通并输出高电平。 导致 M5 的栅极为高电平， 使得 M5截止。 因此可保持 S1输出稳定的低电平。
[0033] 当起始信号线 IN继续保持高电平， 而 CLK1为低电平， CLK2为高电平吋， Ml 导通， N1端变为高电平， C1再次被充电。 M2的栅极变为高电平导致截止。 而 M 4由于 CLK1变为低电平而被导通， 并输出低电平至 M5的栅极。 M5被导通， 并输 出高电平 VGH至 Sl。 当 CLKl为高电平， CLK2为低电平吋， Ml截止， N1端保持 高电平因此 M2也截止。 且由于 C1放电阻止了 M2微导通。 CLK1为高电平， M4截 止。 M4漏极保持低电压， 因此 M5继续保持导通， S1继续输出高电平。
[0034] 以此类推， 当起始信号线 IN在一帧内保持高电平吋， S1持续输出高电平。
[0035] 当电容 C1不存在吋， CLK1变为高电平后， Ml截止， N1端电压会迅速下降。 M 2中存在寄生电容， 因此会导致 CLK2在从高电平变为低电平的过程中， M2微导 通， M5本来就导通， 于是出现从 VGH到 OUT端， OUT端再到 CLK2的反向电流 。 当多个级联结构共同工作吋， 会产生几毫安甚至更高的反向电流， CLK2和 CL K1的低电位会抬高， 造成扫描驱动器功耗过大， 使得屏体显示不均， 严重影响 屏体的显示品质。
[0036] 当电容 C1存在吋， Ml截止后， 电容 C1能够维持 N1端的原来的高电位， 从而防 止了 M2的微导通， 减小了扫描驱动器的功耗， 改善了屏体的显示品质。
[0037] 优选地， 晶体管为双向 PMOS管或双向 P型薄膜场效应晶体管。
[0038] 同理， 级联结构 2至级联结构 n依次接收前一接连结构扫描输出线的信号， 其吋 序图跳变如图 5所示。
[0039] 在本实施例的技术方案中， 通过在 Ml的输出端及扫描输出线之间增加第一电 容器 Cl， 使得第一电容器 C1在第二吋序吋钟线发生跳变吋， 阻止 M2微导通， 从 而减少了扫描驱动器的反向电流， 减小功耗， 改善了屏体的显示品质。
[0040] 图 6为图 3中级联结构 1第二实施例的电路图， 该电路还包括连接于第一晶体管 Ml输出端和固定电位之间的第二电容器 C2。
[0041] 该固定电位为电源低电平 VGL。
[0042] 在本实施例的技术方案中， 第二电容器 C2能够进一步保持 N1端的电压稳定， 且使得第一电容器 C1的电压差最小， 漏电量最少。 [0043] 图 7为图 3中级联结构 1第三实施例的电路图， 该电路还包括连接于第一晶体管
Ml输出端和固定电位之间的第二电容器 C2。
[0044] 该固定电位为电源高电平 VGH。
[0045] 在本实施例的技术方案中， 第二电容器 C2能够进一步保持 N1端的电压稳定， 且使得第一电容器 C1的电压差最小， 漏电量最少。
[0046] 在本发明有机发光显示器另一实施例中， 该有机发光显示器包括向数据线提供 数据信号的数据驱动器、 依次向扫描输出线提供扫描信号的扫描驱动器、 向扫 描驱动器提供吋序信号和电源高电平 VGH、 电源低电平 VGL的吋序控制器以及 多个像素的显示单元。 扫描驱动电路的作用是依次产生提供给显示面板扫描信 号以驱动显示面板中的像素。
[0047] 其中扫描驱动器中包括多个级联结构， 每个级联结构均与具有相反相位的吋序 吋钟线 CLK1和 CLK2连接， 每个级联结构依次产生输出信号即扫描信号至扫描 输出线 S1至 SN。
[0048] 其中每个级联结构具体包括第一晶体管 Ml、 第二晶体管 M2、 第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5、 第一电容器 Cl、 起始信号线 IN、 第一吋序吋 钟线 CLK1、 第二吋序吋钟线 CLK2、 电源高电平 VGH以及电源低电平 VGL。
[0049] 优选地， 奇数所述级联结构的第一吋钟端与第一吋序吋钟线相连， 第二吋钟端 与第二吋序吋钟线相连， 偶数级联结构的第一吋钟端与第二吋序吋钟线相连， 第二吋钟端与第一吋序吋钟线相连。
[0050] 优选地， 晶体管为双向 PMOS管或双向 P型薄膜场效应晶体管。
[0051] 具体电路结构与上述实施例相同， 在此不再赘述。
[0052] 在本实施例的技术方案中， 通过在 Ml的输出端及扫描输出线之间增加第一电 容器 Cl， 使得第一电容器 C1在第二吋序吋钟线发生跳变吋， 阻止 M2微导通， 从 而减少了扫描驱动器的反向电流， 减小功耗， 改善了屏体的显示品质。
[0053] 在本发明有机发光显示器另一实施例中， 该有机发光显示器包括向数据线提供 数据信号的数据驱动器、 依次向扫描输出线提供扫描信号的扫描驱动器、 向扫 描驱动器提供吋序信号和电源高电平 VGH、 电源低电平 VGL的吋序控制器以及 多个像素的显示单元。 扫描驱动电路的作用是依次产生提供给显示面板扫描信 号以驱动显示面板中的像素。
[0054] 其中扫描驱动器中包括多个级联结构， 每个级联结构均与具有相反相位的吋序 吋钟线 CLK1和 CLK2连接， 每个级联结构依次产生输出信号即扫描信号至扫描 输出线 S1至 SN。
[0055] 其中每个级联结构具体包括第一晶体管 Ml、 第二晶体管 M2、 第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5、 第一电容器 Cl、 起始信号线 IN、 第一吋序吋 钟线 CLK1、 第二吋序吋钟线 CLK2、 电源高电平 VGH以及电源低电平 VGL。 该 电路还包括连接于第一晶体管 Ml输出端和固定电位之间的第二电容器 C2。 该固 定电位为电源低电平 VGL。
[0056] 具体电路结构与上述实施例相同， 在此不再赘述。
[0057] 在本实施例的技术方案中， 第二电容器 C2能够进一步保持 N1端的电压稳定， 且使得第一电容器 C1的电压差最小， 漏电量最少。
[0058] 在本发明有机发光显示器另一实施例中， 该有机发光显示器包括向数据线提供 数据信号的数据驱动器、 依次向扫描输出线提供扫描信号的扫描驱动器、 向扫 描驱动器提供吋序信号和电源高电平 VGH、 电源低电平 VGL的吋序控制器以及 多个像素的显示单元。 扫描驱动电路的作用是依次产生提供给显示面板扫描信 号以驱动显示面板中的像素。
[0059] 其中扫描驱动器中包括多个级联结构， 每个级联结构均与具有相反相位的吋序 吋钟线 CLK1和 CLK2连接， 每个级联结构依次产生输出信号即扫描信号至扫描 输出线 S1至 SN。
[0060] 其中每个级联结构具体包括第一晶体管 Ml、 第二晶体管 M2、 第三晶体管 M3、 第四晶体管 M4、 第五晶体管 M5、 第一电容器 Cl、 起始信号线 IN、 第一吋序吋 钟线 CLK1、 第二吋序吋钟线 CLK2、 电源高电平 VGH以及电源低电平 VGL。 该 电路还包括连接于第一晶体管 Ml输出端和固定电位之间的第二电容器 C2。 该固 定电位为电源高电平 VGH。
[0061] 具体电路结构与上述实施例相同， 在此不再赘述。
[0062] 在本实施例的技术方案中， 第二电容器 C2能够进一步保持 N1端的电压稳定， 且使得第一电容器 C1的电压差最小， 漏电量最少。 应说明的是： 以上实施例仅用以说明本发明而非限制， 本发明也并不仅限于上 述举例， 一切不脱离本发明的精神和范围的技术方案及其改进， 其均应涵盖在 本发明的权利要求范围中。

Claims

权利要求书
[权利要求 1] 一种扫描驱动器， 包括：
多个接收具有相反相位的第一吋序吋钟线的信号和第二吋序吋钟 线的信号的级联结构， 所述级联结构依次产生扫描信号， 其中每 个所述级联结构包括：
与起始信号线或前一所述级联结构的扫描输出线相连的第一晶体 管， 所述第一晶体管包括与所述第一吋序吋钟线相连的栅极； 与所述第二吋序吋钟线及所述扫描输出线相连的第二晶体管， 所 述第二晶体管包括与所述第一晶体管的输出端相连的栅极； 与电源高电平 VGH相连的第三晶体管， 所述第三晶体管包括与所 述第二晶体管的输出端相连的栅极；
与电源低电平 VGL及所述第三晶体管的输出端相连的第四晶体管 ， 所述第四晶体管包括所述第一吋序吋钟线相连的栅极； 与电源高电平 VGH及扫描输出线相连的第五晶体管， 所述第五晶 体管包括与所述第四晶体管的输出端及所述第三晶体管的输出端 相连的栅极；
连接于所述第一晶体管输出端和所述扫描输出线之间的第一电容 器。
[权利要求 2] 根据权利要求 1所述的扫描驱动器， 其特征在于， 每个所述级联结 构还包括：
连接于所述第一晶体管输出端和固定电位之间的第二电容器。
[权利要求 3] 根据权利要求 2所述的扫描驱动器， 其特征在于， 所述固定电位为 电源低电平 VGL。
[权利要求 4] 根据权利要求 2所述的扫描驱动器， 其特征在于， 所述固定电位为 电源高电平 VGH。
[权利要求 5] 根据权利要求 1所述的扫描驱动器， 其特征在于， 奇数所述级联结 构的第一吋钟端与所述第一吋序吋钟线相连， 第二吋钟端与所述 第二吋序吋钟线相连， 偶数所述级联结构的第一吋钟端与所述第 二吋序吋钟线相连， 第二吋钟端与所述第一吋序吋钟线相连。
[权利要求 6] 根据权利要求 1至 5中任一所述的扫描驱动器， 其特征在于， 所述 晶体管为双向 PMOS管或双向 P型薄膜场效应晶体管。
[权利要求 7] —种有机发光显示器， 包括：
与数据线和扫描输出线连接的像素阵列；
向所述数据线提供数据信号的数据驱动器； 权利要求 1至 6任一所述的向所述扫描输出线提供扫描信号的扫描 驱动器；
向所述扫描驱动器提供吋序信号及电源高电平 VGH和电源低电平 VGL的吋序控制器。
PCT/CN2014/094751 2013-12-25 2014-12-24 扫描驱动器及使用该扫描驱动器的有机发光显示器 WO2015096721A1 (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US16/416,284 USRE48737E1 (en) 2013-12-25 2014-12-24 Scan driver and organic light-emitting display using same
US15/108,284 US9847062B2 (en) 2013-12-25 2014-12-24 Scan driver and organic light-emitting display using same
JP2016558253A JP2017503217A (ja) 2013-12-25 2014-12-24 スキャンドライバ及びこのスキャンドライバを使用した有機発光ディスプレイ
KR1020167016624A KR101844701B1 (ko) 2013-12-25 2014-12-24 스캔 드라이버 및 그 스캔 드라이버를 사용하는 유기발광 디스플레이
EP14873458.5A EP3067878A4 (en) 2013-12-25 2014-12-24 SCAN DRIVER AND ORGANIC LIGHT EMITTING DISPLAY WITH IT

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310725080.2 2013-12-25
CN201310725080.2A CN104751769A (zh) 2013-12-25 2013-12-25 扫描驱动器及使用该扫描驱动器的有机发光显示器

Publications (1)

Publication Number Publication Date
WO2015096721A1 true WO2015096721A1 (zh) 2015-07-02

Family

ID=53477555

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/094751 WO2015096721A1 (zh) 2013-12-25 2014-12-24 扫描驱动器及使用该扫描驱动器的有机发光显示器

Country Status (7)

Country Link
US (2) US9847062B2 (zh)
EP (1) EP3067878A4 (zh)
JP (1) JP2017503217A (zh)
KR (1) KR101844701B1 (zh)
CN (1) CN104751769A (zh)
TW (1) TWI525597B (zh)
WO (1) WO2015096721A1 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104183219B (zh) * 2013-12-30 2017-02-15 昆山工研院新型平板显示技术中心有限公司 扫描驱动电路和有机发光显示器
CN104537979B (zh) * 2015-01-28 2017-03-15 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路
CN104835531B (zh) * 2015-05-21 2018-06-15 京东方科技集团股份有限公司 一种移位寄存器单元及其驱动方法、移位寄存器和显示装置
CN106920498B (zh) 2015-12-25 2019-10-25 昆山工研院新型平板显示技术中心有限公司 Gip电路及其驱动方法和平板显示装置
CN106157893B (zh) * 2016-09-09 2018-12-11 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、驱动电路和显示装置
KR101914546B1 (ko) 2017-02-10 2018-11-05 성균관대학교산학협력단 게이트 구동 회로 및 그 구동 방법
CN108573677B (zh) * 2017-03-07 2019-12-24 昆山工研院新型平板显示技术中心有限公司 控制信号驱动电路与驱动方法以及像素电路驱动方法
CN108573679B (zh) * 2017-03-07 2019-12-24 昆山工研院新型平板显示技术中心有限公司 控制信号驱动电路与驱动方法以及像素电路驱动方法
KR101996893B1 (ko) 2017-03-16 2019-07-05 한양대학교 산학협력단 게이트 드라이버 및 그 구동 방법
CN108665837B (zh) * 2017-03-27 2021-07-30 昆山工研院新型平板显示技术中心有限公司 扫描驱动电路及其驱动方法和平板显示装置
CN108665854A (zh) * 2017-03-27 2018-10-16 昆山工研院新型平板显示技术中心有限公司 控制信号驱动电路与驱动方法以及像素电路驱动方法
CN108665838A (zh) * 2017-03-27 2018-10-16 昆山工研院新型平板显示技术中心有限公司 扫描驱动电路及其驱动方法和平板显示装置
CN108665853B (zh) * 2017-03-27 2020-11-13 昆山工研院新型平板显示技术中心有限公司 控制信号驱动电路与驱动方法以及像素电路驱动方法
CN107978277B (zh) 2018-01-19 2019-03-26 昆山国显光电有限公司 扫描驱动器及其驱动方法、有机发光显示器
KR20200061448A (ko) * 2018-11-23 2020-06-03 삼성디스플레이 주식회사 주사 구동부
KR20210062770A (ko) 2019-11-21 2021-06-01 삼성디스플레이 주식회사 유기 발광 표시 장치
CN112333879B (zh) * 2020-11-20 2022-01-28 珠海格力电器股份有限公司 一种led驱动电路的控制方法及控制装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339631B1 (en) * 1999-03-02 2002-01-15 Lg. Philips Lcd Co., Ltd. Shift register
JP2004325940A (ja) * 2003-04-25 2004-11-18 Toshiba Matsushita Display Technology Co Ltd アクティブマトリクス型表示装置及びその駆動方法
CN1937020A (zh) * 2005-09-20 2007-03-28 三星Sdi株式会社 扫描驱动电路和使用该扫描驱动电路的有机发光显示器
CN1937022A (zh) * 2005-09-20 2007-03-28 三星Sdi株式会社 扫描驱动电路及使用该电路的有机发光显示器
CN101051440A (zh) * 2006-04-06 2007-10-10 三星Sdi株式会社 扫描驱动电路以及采用其的有机发光显示器
CN102831861A (zh) * 2012-09-05 2012-12-19 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动器及显示装置
CN102831860A (zh) * 2012-09-05 2012-12-19 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动器及显示装置
CN203849978U (zh) * 2013-12-25 2014-09-24 昆山工研院新型平板显示技术中心有限公司 扫描驱动器及使用该扫描驱动器的有机发光显示器

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU756482A1 (ru) * 1978-10-11 1980-08-15 Taganrogskij Radiotech Inst ЯЧЕЙКА ПАМЯТИ ДЛЯ РЕГИСТРА СДВИГА1 "
KR100281336B1 (ko) * 1998-10-21 2001-03-02 구본준 쉬프트 레지스터 회로
JP4310939B2 (ja) 2001-06-29 2009-08-12 カシオ計算機株式会社 シフトレジスタ及び電子装置
TW200703195A (en) 2005-03-22 2007-01-16 Koninkl Philips Electronics Nv A shift register circuit
KR100762690B1 (ko) * 2005-11-07 2007-10-01 삼성에스디아이 주식회사 데이터구동회로와 이를 이용한 유기발광표시장치
KR100776510B1 (ko) * 2006-04-18 2007-11-16 삼성에스디아이 주식회사 주사구동회로 및 이를 이용한 유기발광표시장치
EP2226788A4 (en) * 2007-12-28 2012-07-25 Sharp Kk DISPLAY CONTROL, DISPLAY ARRANGEMENT AND DISPLAY CONTROL PROCEDURE
JP5190285B2 (ja) * 2008-03-21 2013-04-24 株式会社ジャパンディスプレイイースト 表示装置
US8054935B2 (en) * 2009-11-13 2011-11-08 Au Optronics Corporation Shift register with low power consumption
KR101084182B1 (ko) * 2010-01-05 2011-11-17 삼성모바일디스플레이주식회사 스캔 드라이버 및 이를 포함하는 평판 디스플레이 장치
KR20120033672A (ko) * 2010-09-30 2012-04-09 삼성모바일디스플레이주식회사 구동 장치 및 이를 포함하는 표시 장치
KR101804315B1 (ko) * 2010-12-06 2018-01-11 삼성디스플레이 주식회사 표시 장치, 표시 장치를 위한 주사 구동 장치 및 그 구동 방법
CN103460602A (zh) * 2012-04-10 2013-12-18 松下电器产业株式会社 缓冲电路以及缓冲电路的驱动方法
CN103295641B (zh) * 2012-06-29 2016-02-10 上海天马微电子有限公司 移位寄存器及其驱动方法
KR101975533B1 (ko) * 2012-06-29 2019-05-08 삼성디스플레이 주식회사 구동회로, 그를 구비하는 평판표시장치 및 구동회로의 리페어 방법
CN202771772U (zh) * 2012-09-05 2013-03-06 京东方科技集团股份有限公司 移位寄存器、栅极驱动器及显示装置
CN103295642B (zh) * 2012-09-19 2016-02-17 上海中航光电子有限公司 移位寄存器和平板显示装置
CN103198782B (zh) * 2013-03-07 2016-02-10 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及其修复方法和显示装置
US9583063B2 (en) * 2013-09-12 2017-02-28 Semiconductor Energy Laboratory Co., Ltd. Display device
CN104183219B (zh) * 2013-12-30 2017-02-15 昆山工研院新型平板显示技术中心有限公司 扫描驱动电路和有机发光显示器

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339631B1 (en) * 1999-03-02 2002-01-15 Lg. Philips Lcd Co., Ltd. Shift register
JP2004325940A (ja) * 2003-04-25 2004-11-18 Toshiba Matsushita Display Technology Co Ltd アクティブマトリクス型表示装置及びその駆動方法
CN1937020A (zh) * 2005-09-20 2007-03-28 三星Sdi株式会社 扫描驱动电路和使用该扫描驱动电路的有机发光显示器
CN1937022A (zh) * 2005-09-20 2007-03-28 三星Sdi株式会社 扫描驱动电路及使用该电路的有机发光显示器
CN101051440A (zh) * 2006-04-06 2007-10-10 三星Sdi株式会社 扫描驱动电路以及采用其的有机发光显示器
CN102831861A (zh) * 2012-09-05 2012-12-19 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动器及显示装置
CN102831860A (zh) * 2012-09-05 2012-12-19 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动器及显示装置
CN203849978U (zh) * 2013-12-25 2014-09-24 昆山工研院新型平板显示技术中心有限公司 扫描驱动器及使用该扫描驱动器的有机发光显示器

Also Published As

Publication number Publication date
USRE48737E1 (en) 2021-09-14
KR101844701B1 (ko) 2018-04-02
CN104751769A (zh) 2015-07-01
EP3067878A4 (en) 2016-12-07
TWI525597B (zh) 2016-03-11
US20160314745A1 (en) 2016-10-27
EP3067878A1 (en) 2016-09-14
JP2017503217A (ja) 2017-01-26
US9847062B2 (en) 2017-12-19
KR20160089451A (ko) 2016-07-27
TW201525969A (zh) 2015-07-01

Similar Documents

Publication Publication Date Title
WO2015096721A1 (zh) 扫描驱动器及使用该扫描驱动器的有机发光显示器
TWI534781B (zh) Scan drive circuit and organic light emitting display
US9620241B2 (en) Shift register unit, method for driving the same, shift register and display device
WO2017206542A1 (zh) 移位寄存器及其操作方法、栅极驱动电路和显示装置
TWI493557B (zh) 移位暫存器電路
TWI421872B (zh) 能降低耦合效應之移位暫存器
US7978809B2 (en) Shift register of a display device
TWI404036B (zh) 液晶顯示器
US8494108B2 (en) Switch device and shift register circuit using the same
US20140253424A1 (en) Shift register, bidirectional shift register apparatus, and liquid crystal display panel using the same
US9728147B2 (en) GOA circuit of LTPS semiconductor TFT
WO2017121133A1 (zh) 移位寄存器单元、栅极驱动电路、显示面板及显示装置
US20160268004A1 (en) Shift register unit and gate driving circuit
US10629108B2 (en) Shift register unit and drive method thereof, shift register and display device
CN107895562B (zh) 高稳定性的脉冲宽度可调式移位寄存器
US9704437B2 (en) Gate driving circuit, array substrate, and display device
US20170154602A1 (en) Shift register unit, its driving method, gate driver circuit and display device
WO2015058553A1 (zh) 移位寄存器单元、goa电路、阵列基板以及显示装置
WO2014173025A1 (zh) 移位寄存器单元、栅极驱动电路与显示器件
WO2015100967A1 (zh) 移位寄存器单元、栅极驱动电路及显示装置
WO2013174118A1 (zh) 移位寄存器、驱动装置及显示器
US9767753B2 (en) Scan driver
WO2014153872A1 (zh) 移位寄存器单元、移位寄存器、显示面板以及显示器
CN105788644B (zh) 移位寄存器、扫描驱动器和有机发光显示器
TWI714317B (zh) 畫素電路與相關的顯示裝置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14873458

Country of ref document: EP

Kind code of ref document: A1

REEP Request for entry into the european phase

Ref document number: 2014873458

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014873458

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2016558253

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20167016624

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 15108284

Country of ref document: US