WO2015076373A1 - 回路形成層付支持基板、両面回路形成層付支持基板、多層積層板、多層プリント配線板の製造方法及び多層プリント配線板 - Google Patents
回路形成層付支持基板、両面回路形成層付支持基板、多層積層板、多層プリント配線板の製造方法及び多層プリント配線板 Download PDFInfo
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- WO2015076373A1 WO2015076373A1 PCT/JP2014/080919 JP2014080919W WO2015076373A1 WO 2015076373 A1 WO2015076373 A1 WO 2015076373A1 JP 2014080919 W JP2014080919 W JP 2014080919W WO 2015076373 A1 WO2015076373 A1 WO 2015076373A1
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- Prior art keywords
- layer
- copper foil
- support substrate
- carrier
- build
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1536—Temporarily stacked PCBs
Definitions
- the present invention relates to a support substrate with a circuit formation layer, a support substrate with a double-sided circuit formation layer, a method for producing a multilayer printed wiring board, and a multilayer printed wiring board.
- it does not leave a core substrate as a support during the build-up layer formation, the support substrate with a circuit-forming layer that can be suitably used when producing a build-up multilayer printed wiring board, a support substrate with a double-sided circuit-forming layer
- the present invention relates to a method for manufacturing a multilayer printed wiring board using the support substrate with a circuit forming layer, and a multilayer printed wiring board.
- a manufacturing method of a coreless buildup multilayer printed wiring board that does not leave a core substrate as a support for forming a so-called buildup layer at the time of manufacturing due to a demand for a thinner buildup multilayer printed wiring board. has been adopted.
- Patent Document 1 describes a method of manufacturing a multilayer printed wiring board by a coreless build-up method using a metal foil with a carrier that can be peeled off at an interface between an adhesive and a metal foil.
- a synthetic resin plate carrier and a metal foil with a carrier made of a metal foil mechanically peelably adhered to at least one surface of the carrier are used.
- a method is disclosed in which a buildup layer is laminated on both sides of a metal foil with a carrier to which a copper foil is bonded, and then the metal foil on both sides is peeled from the metal foil with a carrier.
- Patent Document 1 uses a resin or prepreg as the synthetic resinous plate-like carrier, and has a thickness of 50 to 900 ⁇ m so that the position of the circuit caused by the difference in thermal expansion between the metal foil and the synthetic resin. It is disclosed to prevent deviation and reduce bending.
- the inventors of the present invention have come up with a method for manufacturing a multilayer printed wiring board by a coreless buildup method using a support substrate with a circuit forming layer shown below.
- the support substrate with a circuit formation layer has a layer configuration of copper foil layer / peeling layer / carrier layer / resin layer, and the maximum unevenness on the surface of the carrier layer on the resin layer side.
- the copper foil layer having a height difference (PV) of 3 ⁇ m to 12 ⁇ m and a thickness of the resin layer of 1.5 ⁇ m to 15 ⁇ m is used as a circuit forming layer. is there.
- a manufacturing method of a multilayer printed wiring board according to the present application is a method of manufacturing a multilayer printed wiring board by the coreless buildup method using the support substrate with a circuit forming layer, and includes the following steps: It is characterized by.
- Build-up wiring layer forming step A build-up wiring layer is formed on the surface of the copper foil layer of the circuit-forming layer-attached substrate to obtain a support substrate with a build-up wiring layer.
- Step of separating support substrate with buildup wiring layer A multilayer in which the support substrate with buildup wiring layer is separated by the release layer of the support substrate with circuit forming layer, and a buildup layer is formed on the copper foil layer A laminate is obtained.
- Multilayer printed wiring board forming step Necessary processing is performed on the multilayer laminated board to obtain a multilayer printed wiring board.
- first manufacturing method In the method for manufacturing a multilayer printed wiring board according to the present application, by applying the above basic manufacturing method, the following “first manufacturing method”, “second manufacturing method”, and “third manufacturing method” are used. It is also preferable to manufacture.
- This first manufacturing method includes the following steps. Each step will be described in detail in the following description of the embodiment of the invention.
- Manufacturing process of support substrate with double-sided circuit forming layer Using two copper foils with a carrier having a layer structure of resin layer / carrier layer / peeling layer / copper foil layer, these resin layers are directly bonded together, or a core material A support substrate with a double-sided circuit forming layer having a layer structure of copper foil layer / peeling layer / carrier layer / center resin layer / carrier layer / peeling layer / copper foil layer is obtained by laminating on both sides .
- Build-up wiring layer forming step A build-up wiring layer is formed on the surface of each copper foil layer of the substrate with a double-sided circuit forming layer to obtain a support substrate with a build-up wiring layer.
- Support substrate separation step with build-up wiring layer A multilayer laminate having a build-up layer formed on a copper foil layer is obtained by separation with a release layer of the support substrate with a double-sided circuit formation layer.
- This second manufacturing method includes the following steps.
- Manufacturing process of support substrate with double-sided circuit forming layer First copper foil with carrier having layer structure of carrier layer / peeling layer / copper foil layer and layer structure of resin layer / carrier layer / peeling layer / copper foil layer
- the carrier of the first carrier-attached copper foil and the resin layer of the second carrier-attached copper foil are directly attached to each other, or are attached to both surfaces of the core material, thereby providing a copper foil layer.
- a support substrate with a double-sided circuit forming layer having a layer structure of: / peeling layer / carrier layer / central resin layer / carrier layer / peeling layer / copper foil layer is obtained.
- Build-up wiring layer forming step A build-up wiring layer is formed on the surface of each copper foil layer of the double-sided circuit forming layer-supported substrate to obtain a build-up wiring layer-supported substrate.
- Support substrate separation step with build-up wiring layer A multilayer laminate having a build-up layer formed on a copper foil layer is obtained by separation with a release layer of the support substrate with a double-sided circuit formation layer.
- This third manufacturing method includes the following steps.
- each carrier layer of each copper foil with a carrier is made of a resin core material Are bonded together to obtain a support substrate with a double-sided circuit forming layer having a layer structure of copper foil layer / peeling layer / carrier layer / central resin layer / carrier layer / peeling layer / copper foil layer.
- Build-up wiring layer forming step A build-up wiring layer is formed on the surface of each copper foil layer of the double-sided circuit forming layer-supported substrate to obtain a build-up wiring layer-supported substrate.
- Support substrate separation step with build-up wiring layer A multilayer laminate having a build-up layer formed on a copper foil layer is obtained by separation with a release layer of the support substrate with a double-sided circuit formation layer.
- the support substrate with a circuit forming layer according to the present invention can be used when a multilayer printed wiring board is manufactured by a coreless buildup method, and has a layer configuration of copper foil layer / peeling layer / carrier layer / resin layer as a basic configuration. Prepare.
- This support substrate with a circuit-forming layer is excellent in the adhesion between the resin layer and the carrier, and can be excellent in the smoothness of the circuit formed on the copper foil layer.
- the support substrate with circuit forming layer is a support substrate that can be used when a multilayer printed wiring board is manufactured by a coreless buildup method, and a copper foil layer / peeling layer It is a support substrate with a circuit formation layer having a layer configuration of / carrier layer / resin layer, and a basic configuration in which a copper foil layer is used as a circuit formation layer.
- the carrier layer 2 / the release layer 3 / the copper foil layer 4 are sequentially formed on both surfaces of the resin layer (center resin layer 8) from the resin layer side.
- a support substrate 1 with a double-sided circuit formation layer having a layer structure As a support substrate 1 with a double-sided circuit formation layer having a layer structure, a build-up layer is laminated on a copper foil layer, and then the carrier layer / resin layer side is separated in the release layer of the support substrate, thereby coreless build-up It is also preferable to obtain a multilayer printed wiring board.
- each layer which comprises the said support substrate with a circuit formation layer is demonstrated in order.
- the resin layer of the support substrate with a circuit forming layer preferably has a thickness of 1.5 ⁇ m to 15 ⁇ m.
- the thickness of the resin layer is used to prevent peeling from the end face of the substrate when the support substrate with a circuit formation layer is formed and a buildup layer is formed. Is preferably 1.5 ⁇ m or more.
- the thickness of the resin layer is preferably 15 ⁇ m or less from the viewpoint that surface smoothness when forming a circuit on the copper foil layer can be ensured.
- the thickness of the resin layer is more preferably 2 ⁇ m to 10 ⁇ m, and further preferably 2 ⁇ m to 8 ⁇ m.
- the thickness of the central resin layer of the support substrate with the double-sided circuit layer is preferably 3 ⁇ m to 30 ⁇ m, and the thickness of the central resin layer is 4 ⁇ m to More preferably, it is 20 ⁇ m, and more preferably 4 ⁇ m to 16 ⁇ m.
- the resin constituting the resin layer is a resin generally used for printed circuit board production such as epoxy resin, polyimide resin, polyamide resin, polyamideimide resin, phenol resin, etc. Is preferred.
- the resin layer is also preferably composed of a prepreg or the like in which these resins are impregnated in a skeletal material such as glass cloth or glass nonwoven fabric.
- Carrier layer Here, the reason for the carrier layer (carrier) is described.
- the support substrate with a circuit formation layer according to the present application is provided with the layer configuration (copper foil layer 4 / peeling layer 3 / carrier layer 2 / resin layer) of the above basic configuration, As long as the layer structure of copper foil layer 4 / peeling layer 3 / carrier layer 2 / central resin layer 8 / carrier layer 2 / peeling layer 3 / copper foil layer 4 is provided, there is no particular limitation on the manufacturing method. However, it is preferable to manufacture using the copper foil 10 with a carrier provided with the layer structure of copper foil layer 4 / peeling layer 3 / carrier layer 2 as shown in FIG. 2 (A), for example. As shown in FIG. 2A, the carrier-attached copper foil 10 may include a roughening treatment layer 5 and a roughening treatment layer 6 on the outer layers of the copper foil layer 4 and the carrier layer 2, respectively. It is not limited.
- the carrier layer constituting the support substrate with a circuit forming layer is generally a resin film having a thickness of 12 ⁇ m to 70 ⁇ m, or an electrolytic copper foil or a rolled copper foil. From the viewpoint of reducing waste and handling properties. In view of the above, those of 12 ⁇ m to 35 ⁇ m are preferable. In addition, from the viewpoint of maintaining rigidity against a high temperature heat load when forming the buildup layer on the support substrate with a circuit forming layer, the carrier layer is subjected to a heat treatment at 250 ° C. for 60 minutes, and then 40 kgf / More preferably, it is made of a copper foil having a tensile strength of mm 2 or more.
- the bonding surface of the carrier layer with the resin layer is a rough surface capable of appropriately maintaining the adhesive strength with the resin layer.
- the maximum peak height of the sample surface and the maximum valley depth measured directly using a three-dimensional surface structure analysis microscope is used as an index. Use.
- the value of the “maximum height difference (PV)” of the surface of the carrier layer is that the adhesion between the carrier layer and the resin layer can be secured, and the smoothness of the circuit formed on the copper foil layer is maintained. From the point (in other words, the reduction of unevenness on the surface of the copper foil layer after pressing based on the uneven shape of the carrier layer), the thickness is preferably 3 ⁇ m to 12 ⁇ m, more preferably 4 ⁇ m to 10 ⁇ m.
- the measurement of the “maximum height difference (PV) of unevenness” uses ZygogNew View 5032 (manufactured by Zygo) as measurement equipment, and “Metro Pro Ver. 8.0.2” as analysis software, and the low frequency filter is 11 ⁇ m. Measured with setting. Specifically, the measurement was performed by the following procedures a) to c).
- the release layer is an organic release layer, it preferably contains at least one compound selected from the group consisting of nitrogen-containing compounds, sulfur-containing compounds and carboxylic acids.
- the nitrogen-containing organic compound mentioned here includes a nitrogen-containing organic compound having a substituent.
- examples of the nitrogen-containing organic compound include 1,2,3-benzotriazole, carboxybenzotriazole, N ′, N′-bis (benzotriazolylmethyl) urea, which are triazole compounds having a substituent, and 1H. It is preferable to use -1,2,4-triazole, 3-amino-1H-1,2,4-triazole and the like.
- the sulfur-containing organic compound it is preferable to use mercaptobenzothiazole, thiocyanuric acid, 2-benzimidazolethiol, or the like.
- the carboxylic acid it is particularly preferable to use a monocarboxylic acid, and it is particularly preferable to use oleic acid, linoleic acid, linolenic acid, or the like. This is because these organic components are excellent in heat resistance at high temperatures, and it is easy to form a bonding interface layer having a thickness of 5 nm to 60 nm on the surface of the carrier.
- the inorganic component is selected from the group consisting of Ni, Mo, Co, Cr, Fe, Ti, W, P, carbon, or an alloy or compound containing these as a main component. It is preferable to use at least one of the above.
- these inorganic bonding interface layers they can be formed using a known method such as an electrodeposition method, an electroless method, or a physical vapor deposition method.
- the copper foil layer is formed by a physical vapor deposition method such as sputtering, a chemical vapor reaction method, an electroless plating method, an electrolytic plating method, a composite plating method using both electroless plating and electrolytic plating, or the like.
- a physical vapor deposition method such as sputtering, a chemical vapor reaction method, an electroless plating method, an electrolytic plating method, a composite plating method using both electroless plating and electrolytic plating, or the like.
- the thickness of the copper foil is preferably 1 ⁇ m to 10 ⁇ m from the viewpoint of preventing the occurrence of pinhole defects and securing the etching factor when forming the fine circuit.
- the copper foil layer is also used as a circuit forming layer of a multilayer printed wiring board.
- an embedded circuit forming layer or an outer layer circuit forming layer is used. It is used as.
- the timing at which circuit formation is performed on the copper foil layer is not particularly limited. Before the buildup layer is laminated on the copper foil layer, circuit formation may be performed using the copper foil layer as an embedded circuit formation layer.
- a buildup layer is laminated on the copper foil layer, and after a multilayer laminated board is obtained in a support substrate separating process with a buildup wiring layer described later, circuit formation is performed using the copper foil layer as an outer circuit forming layer. It may be broken.
- a conventionally known circuit forming method can be appropriately employed.
- MSAP Mode Semi-Additive Process
- the subtractive method in which an unnecessary portion is removed from the copper foil layer and the pattern is formed. Etc. are preferably employed.
- a multilayer printed wiring board can be manufactured by the following coreless buildup method using the support substrate with a circuit forming layer according to the present application described above.
- the manufacturing method of the multilayer printed wiring board according to the present application can be applied to the following three manufacturing methods based on the following basic manufacturing method.
- the description will be divided into “basic manufacturing method”, “first manufacturing method”, “second manufacturing method”, and “third manufacturing method”.
- the build-up wiring layer forming step, the build-up wiring layer-attached support substrate separating step, and the multilayer printed wiring board forming step, which are referred to as the basic manufacturing method, are common to all manufacturing methods.
- each manufacturing method will be described.
- the basic manufacturing method is a method of manufacturing a multilayer printed wiring board by the coreless buildup method using the support substrate with a circuit forming layer having the above basic configuration, and includes the following steps.
- Build-up wiring layer forming step A build-up wiring layer is formed on the surface of the copper foil layer of the circuit-forming layer-attached substrate to obtain a support substrate with a build-up wiring layer.
- Step of separating support substrate with buildup wiring layer A multilayer in which the support substrate with buildup wiring layer is separated by the release layer of the support substrate with circuit forming layer, and a buildup layer is formed on the copper foil layer A laminate is obtained.
- Multilayer printed wiring board forming step Necessary processing is performed on the multilayer laminated board to obtain a multilayer printed wiring board.
- the first manufacturing method includes the following steps. Hereinafter, it demonstrates for every process.
- FIG. 3 (C-1) 2 copper foils 20 with a carrier having a resin layer 7 having a layer structure of resin layer 7 / carrier layer 2 / peeling layer 3 / copper foil layer 4 are prepared.
- the resin layers 7 are directly attached to each other using a sheet.
- FIG. 3 (D) “copper foil layer 4 / peeling layer 3 / carrier layer 2 / central resin layer 8 / carrier layer 2 / peeling including a copper foil layer 4 as a circuit forming layer on both surfaces.
- the support substrate 1 with a double-sided circuit forming layer having a layer configuration of “layer 3 / copper foil layer 4” can be obtained.
- the copper foil layer of the carrier-attached copper foil 20 and the copper foil layer as the circuit formation layer (outer layer circuit formation layer) of the double-sided circuit formation layer-attached support substrate 1 mean the same place. , Shown as the same reference numeral 4.
- Build-up wiring layer forming step In this step, the build-up wiring layer Bu is formed on the surfaces of the copper foil layers 4 on both surfaces of the support substrate 1 with the double-sided circuit forming layer.
- the support substrate with a double-sided circuit formation layer 1 on which the build-up wiring layer Bu is formed is referred to as the support substrate with a build-up wiring layer 40 as described above.
- the specific method for forming the buildup wiring layer Bu is not particularly limited. As long as it is a method included in a so-called build-up method, a desired multilayer and inner layer circuit may be formed by any method. As an example, in FIG.
- the build-up wiring layer Bu is “a first build-up wiring layer 30 including a first circuit layer 31 including a via hole 28 and a first circuit 23 including a plating layer 24. ”,“ A second build-up wiring layer 32 including the via hole 28 and the second circuit layer 33 including the second circuit 25 including the plating layer 24 ”“ a wiring layer 34 composed of a copper foil or the like and an interlayer insulating resin layer 35. A third build-up layer 36 "and so on.
- Support substrate separation step with build-up wiring layer In this step, as shown in FIG. 5 (F), the support substrate with build-up wiring layer 40 is separated by the release layer 3 of the support substrate with circuit formation layer 1. Thus, two multilayer laminates 50 having the build-up layer Bu formed on the copper foil layer 4 are obtained. At this time, by separating the support substrate 40 with the build-up wiring layer simultaneously with the release layer 3 of the support substrate 1 with the double-sided circuit formation layer, the two multilayer laminates 50 can be obtained at the same time.
- Multilayer printed wiring board forming step In this step, the multilayer laminated board 50 can be processed to obtain a multilayer printed wiring board. Since there is no special limitation regarding this process, illustration is abbreviate
- the resin layers 7 are bonded together, but a core material may be interposed between the resin layers 7.
- a core material may be interposed between the resin layers 7.
- a resin-made core material can be used, and a semi-cured (B stage) resin film or a resin film having a semi-cured resin layer is preferably used as the core material.
- the core material By interposing the core material, the rigidity of the support substrate can be ensured even when the thickness of the resin layer of the copper foil with carrier 20 is thin.
- the thickness of the central resin layer 8 is preferably within the above-described range.
- bonding the said resin film with the resin layer 7 it can carry out by hot press molding etc. similarly to the case where the resin layers 7 are bonded together.
- This second manufacturing method includes the following steps. Since the difference from the first manufacturing method is only the manufacturing process of the support substrate with a circuit forming layer, in the description of the embodiment of the invention below, the description with the first manufacturing method is omitted, and therefore, with a double-sided circuit forming layer. Only the manufacturing process of the support substrate will be described in detail.
- FIG. 7D and FIG. 3D of the first manufacturing method have the same form. Therefore, the following steps of the second manufacturing method, the “build-up wiring layer forming step”, the “support substrate separating step with build-up wiring layer”, and the “multilayer printed wiring board forming step” are the same as those in the first manufacturing method. is there. Therefore, the duplicate description here is omitted.
- the carrier foil surface of the first carrier-attached copper foil 10 and the surface of the resin layer 7 of the second carrier-attached copper foil 20 are directly bonded.
- a core material may be interposed between the carrier surface and the resin layer 7.
- the core material the same material as described in the first manufacturing method can be used, and the same method as described above can be adopted for the bonding method and the like.
- This third manufacturing method includes the following steps. Since the difference from the first manufacturing method is only the manufacturing process of the support substrate with a double-sided circuit forming layer, in the following description of the embodiment of the invention, the double-sided circuit forming layer is omitted in order to avoid duplication with the first manufacturing method. Only the manufacturing process of the attached support substrate will be described.
- the copper foil layer 4 which contains the copper foil layer 4 as a double-sided circuit formation copper foil layer on both surfaces / peeling layer 3 / carrier layer 2 / center resin layer 8 / carrier layer 2 / peeling layer 3 / copper foil layer 4 A support substrate 1 with a double-sided circuit forming layer having the layer structure is obtained.
- FIG. 7D and FIG. 3D of the first manufacturing method have the same form. Therefore, the following steps of the third manufacturing method, the “build-up wiring layer forming step”, the “support substrate separating step with build-up wiring layer”, and the “multilayer printed wiring board forming step” are the same as the first manufacturing step. is there. Therefore, the duplicate description here is omitted.
- the film-like resin F corresponds to the core material described in the first manufacturing method or the second manufacturing method.
- Example 1 In Example 1, a multilayer printed wiring board was manufactured by the first manufacturing method described above. Specifically, a multilayer printed wiring board was manufactured by the following steps.
- Resin layer / carrier layer / peeling in which the maximum height difference (PV) of unevenness on the surface of the resin layer side of the resin layer (thickness 2.5 ⁇ m) and the carrier layer (thickness 18 ⁇ m) is 3.8 ⁇ m as the copper foil with carrier
- PV maximum height difference
- the resin layer component was blended as follows, and the varnish adjusted so that the total solid content was 20% by weight was coated on the carrier layer using an applicator.
- the support substrate with a buildup wiring layer is separated at each release layer of the support substrate with a double-sided circuit formation layer by a support substrate separation process with a buildup wiring layer.
- Two multilayer laminates hereinafter referred to as laminate A) having a build-up layer formed on a copper foil layer were obtained.
- Example 2 to Example 4 are the same as Example 1 except that the maximum height difference (PV) of the unevenness on the surface of the carrier layer on the resin layer side and the resin layer thickness are as shown in Table 1, respectively.
- a support substrate (a) and a laminate (i) were produced.
- Comparative Examples 1 to 5 the same method as in Example 1 except that the maximum height difference (PV) of the unevenness on the surface of the carrier layer on the resin layer side and the resin layer thickness are as shown in Table 1, respectively.
- the support substrate (a) and the laminated board (i) were manufactured.
- Evaluation method 1-1 Adhesion between the central resin layer and the carrier layer
- Adhesion between the central resin layer and the carrier layer was evaluated as follows. After the support substrate was cut into a width of 1 cm, the carrier layer on one side of the carrier layers arranged on both sides of the resin layer was pulled up at an angle of 90 ° and a speed of 50 mm / min, and the peel strength was measured. At that time, a pass / fail judgment was made based on the following criteria.
- the substrate smoothness was evaluated by the following method for Examples 1 to 3 and Comparative Example 2 in which the evaluation result was “ ⁇ ” in the above-described adhesion evaluation.
- the 10-point average roughness Rz hereinafter referred to as “Rz 0 ”
- the Rz 0 measurement sample was obtained by laminating a carrier-attached copper foil having a layer structure of resin layer / carrier layer / release layer / copper foil layer to a smooth glass plate, and then peeling the carrier to expose the copper foil layer surface. It was.
- Adhesion evaluation is ⁇
- circuit formability is ⁇
- Adhesion evaluation is x or circuit formability is x
- Table 1 shows the evaluation results regarding the adhesion between the central resin layer and the carrier layer in Examples and Comparative Examples. As shown in Table 1, it was confirmed that all the support substrates with a double-sided circuit forming layer produced in Examples 1 to 4 had good adhesion between the central resin layer and the carrier layer. About an Example, it was confirmed that the one where the value of the maximum height difference (PV) of the unevenness
- PV maximum height difference
- the thickness of the resin layer is 20 ⁇ m (the thickness of the central resin layer is 40 ⁇ m), and the maximum height difference (PV) of the unevenness on the surface of the carrier layer on the resin layer is within the scope of the present invention.
- the adhesion between the central resin layer and the carrier layer was good, but for the other comparative examples, the adhesion between the central resin layer and the carrier layer was not good, and the buildup layer was formed. In the process, it was peeled off from the end of the substrate, and the substrate smoothness of the laminated plate i could not be evaluated.
- Circuit formability (substrate smoothness) Table 1 shows the evaluation results regarding circuit formability in Examples and Comparative Examples. As shown in Table 1, it was confirmed that each of the support substrates with double-sided circuit forming layers produced in Examples 1 to 4 had good circuit formability. In particular, when the thickness of the resin layer is within the above-described preferable range (1.5 ⁇ m to 15 ⁇ m), it was confirmed that better circuit forming properties are exhibited.
- multilayer prints with excellent circuit formation stability in the build-up layer formation process by providing a support substrate with excellent adhesion and circuit smoothness A wiring board can be obtained.
- Support substrate with circuit forming layer 2 Carrier layer (carrier) 3 peeling layer 4 copper foil layer 7 resin layer 8 central resin layer 10 copper foil with carrier 20 electrolytic copper foil with carrier provided with resin layer 23 first circuit 25 second circuit 24 plating layer 28 via hole 30 first buildup wiring layer 30 31 1st circuit layer 32 2nd buildup wiring layer 33 2nd circuit layer 34 wiring layer 35 interlayer insulation resin layer 36 3rd buildup layer 40 support substrate 50 with buildup wiring layer multilayer laminated board Bu buildup wiring layer F film Resin
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Abstract
Description
本件出願に係る回路形成層付支持基板は、銅箔層/剥離層/キャリア層/樹脂層の層構成を備え、当該キャリア層の当該樹脂層側の表面の凹凸の最大高低差(PV)が3μm~12μmであり、当該樹脂層の厚さが、1.5μm~15μmである前記銅箔層が回路形成層として用いられることを特徴とすることを特徴とするものである。
2-1.基本製造方法
本件出願に係る多層プリント配線板の製造方法は、上記回路形成層付支持基板を用いて、コアレスビルドアップ法で多層プリント配線板を製造する方法であって、以下の工程を備えることを特徴とする。
ビルドアップ配線層付支持基板分離工程: 当該ビルドアップ配線層付支持基板を、前記回路形成層付支持基板の前記剥離層で分離して、前記銅箔層上にビルドアップ層が形成された多層積層板を得る。
多層プリント配線板形成工程: 前記多層積層板に必要な加工を施し、多層プリント配線板を得る。
この第1製造方法は、以下の工程を備える。各工程に関しては、以下の発明の形態の説明において詳細に述べる。
ビルドアップ配線層形成工程: 当該両面回路形成層付基板の各銅箔層の表面に、ビルドアップ配線層を形成して、ビルドアップ配線層付支持基板を得る。
ビルドアップ配線層付支持基板分離工程: 当該両面回路形成層付支持基板の剥離層で分離して、銅箔層上にビルドアップ層が形成された多層積層板を得る。
この第2製造方法は、以下の工程を備える。
ビルドアップ配線層形成工程: 当該両面回路形成層付支持基板の各銅箔層の表面に、ビルドアップ配線層を形成して、ビルドアップ配線層付支持基板を得る。
ビルドアップ配線層付支持基板分離工程: 当該両面回路形成層付支持基板の剥離層で分離して、銅箔層上にビルドアップ層が形成された多層積層板を得る。
この第3製造方法は、以下の工程を備える。
ビルドアップ配線層形成工程: 当該両面回路形成層付支持基板の各銅箔層の表面に、ビルドアップ配線層を形成して、ビルドアップ配線層付支持基板を得る。
ビルドアップ配線層付支持基板分離工程: 当該両面回路形成層付支持基板の剥離層で分離して、銅箔層上にビルドアップ層が形成された多層積層板を得る。
本件出願に係る回路形成層付支持基板は、コアレスビルドアップ法で多層プリント配線板を製造する際に用いることのできる支持基板であって、銅箔層/剥離層/キャリア層/樹脂層の層構成を備え、銅箔層が回路形成層として用いられることを基本構成とする回路形成層付支持基板である。また、基本構成を応用して、例えば、図1に示すように、樹脂層(中央樹脂層8)の両面に、当該樹脂層側から順に、キャリア層2/剥離層3/銅箔層4の層構成を備えた両面回路形成層付支持基板1として、銅箔層上にビルドアップ層を積層した後、当該支持基板の剥離層においてキャリア層/樹脂層側を分離することにより、コアレスビルドアップ多層プリント配線板を得ることも好ましい。以下、当該回路形成層付支持基板を構成する各層について順に説明する。
b)当該試料片の1cm角の範囲内において108μm×144μmの視野を6点選択して測定する。
c)6箇所の測定点から得られた最大高低差(PV)値の平均値を、「凹凸の最大高低差(PV)」として採用した。
以上に述べてきた本件出願に係る回路形成層付支持基板を用いて、以下のようなコアレスビルドアップ法で多層プリント配線板を製造することが出来る。本件出願に係る多層プリント配線板の製造方法は、下記基本製造方法を基本として、以下の3つの製造方法に応用することができる。以下、「基本製造方法」、「第1製造方法」、「第2製造方法」、「第3製造方法」に分けて説明する。なお、基本製造方法にいうビルドアップ配線層形成工程、ビルドアップ配線層付支持基板分離工程、多層プリント配線板形成工程は、どの製造方法においても共通する。以下、各製造方法について説明する。
当該基本製造方法は、上記基本構成の回路形成層付支持基板を用いて、コアレスビルドアップ法で多層プリント配線板を製造する方法であって、以下の工程を備える。
ビルドアップ配線層付支持基板分離工程: 当該ビルドアップ配線層付支持基板を、前記回路形成層付支持基板の前記剥離層で分離して、前記銅箔層上にビルドアップ層が形成された多層積層板を得る。
多層プリント配線板形成工程: 前記多層積層板に必要な加工を施し、多層プリント配線板を得る。
この第1製造方法は、以下の工程を備えることを特徴とする。以下、工程毎に説明する。
この第2製造方法は、以下の工程を備える。第1製造方法との差異は、回路形成層付支持基板の製造工程のみであるから、以下の発明の形態の説明において、第1製造方法との重複記載を省略するため、両面回路形成層付支持基板の製造工程に関してのみ詳細に述べる。
実施例1では、上述した第1製造方法により多層プリント配線板を製造した。具体的には下記の工程により、多層プリント配線板を製造した。
DIC株式会社製 エピクロン850S:43重量部
新日鉄住金化学株式会社製 YD-907:25重量部
〔硬化剤〕
日本カーバイド工業株式会社製 D25F:固形分として5重量部
〔混合樹脂〕
ポリビニルアセタール樹脂(積水化学工業株式会社製KS-5):25重量部
イソシアネート樹脂(東ソー株式会社製 コロネートAPステーブル):2重量部
〔イミダゾール系硬化触媒〕
四国化成工業株式会社製 2MZ-H:0.1重量部
〔混合溶媒〕
メチルエチルケトン:プロピレングリコールモノメチルエーテル=4:1混合液
実施例2~実施例4は、キャリア層の樹脂層側の表面の凹凸の最大高低差(PV)及び樹脂層厚さをそれぞれ表1に示すとおりとした以外は、実施例1と同じ方法で支持基板ア及び積層板イを製造した。
上記実施例及び比較例において、多層プリント配線板を製造する際に、支持基板を構成する中央樹脂層とキャリア層との密着性と、ビルドアップ層を形成する際の回路形成性(基板平滑性)について評価した。
1-1.中央樹脂層とキャリア層との密着性
中央樹脂層とキャリア層との密着性は次のようにして評価した。上述の支持基板アを幅1cmに切断した後、樹脂層の両面に配置されたキャリア層のうち、片面側のキャリア層を角度90°、速度50mm/minで引き上げて、ピール強度を測定した。その際、下記の判定基準に基づき合否判定を行った。
×:強度測定可能(ピール強度 2.5kgf/cm未満)
上記の密着性評価で評価結果が「○」であった実施例1~3と、比較例2につき、次の方法で基板平滑性を評価した。まず、キャリア付銅箔の初期状態における剥離層側の銅箔層表面の10点平均粗さRz(以下、「Rz0」と称する。)をRz0測定用サンプルを用いて測定した。Rz0測定用サンプルは、樹脂層/キャリア層/剥離層/銅箔層の層構成を備えるキャリア付銅箔を平滑ガラス板に張り合わせた後、キャリアを剥離し銅箔層表面を露出させたものとした。そして、上述の積層板イの銅箔層表面に対し、接触式表面粗さ計を用いて、JIS B 0601(2001)に準拠して求められる10点平均粗さRz(以下、「Rz1」と称する。)を測定した。その結果得られる銅箔層表面の10点平均粗さRzの変化量(以下、「ΔRz」と称する。但し、ΔRz=Rz1-Rz0である。)に基づき、回路平滑性を評価した。また、その際、下記の判定基準に基づき合否判定を行った。
×: ΔRz>0.3μm
上記の密着性及び回路形成性の評価結果に基づき、以下の判定基準に基づき下記の総合判定を行った。
×: 密着性評価が×、または回路形成性が×
2-1.中央樹脂層とキャリア層との密着性
実施例及び比較例における中央樹脂層とキャリア層との密着性に関する評価結果を表1に示す。表1に示すように、実施例1~実施例4で製造した両面回路形成層付支持基板では、いずれも中央樹脂層とキャリア層との密着性が良好であることが確認された。実施例については、中央樹脂層の厚さによらず、キャリア層の樹脂層側の表面の凹凸の最大高低差(PV)の値が低い方がより良好な密着が得られることが確認された。
実施例及び比較例における回路形成性に関する評価結果を表1に示す。表1に示すように、実施例1~実施例4で製造した両面回路形成層付支持基板では、いずれも良好な回路形成性を有することが確認された。特に、樹脂層の厚さが上述した好ましい範囲内(1.5μm~15μm)である場合、より良好な回路形成性を示すことが確認された。
2 キャリア層(キャリア)
3 剥離層
4 銅箔層
7 樹脂層
8 中央樹脂層
10 キャリア付銅箔
20 樹脂層を備えたキャリア付電解銅箔
23 第1回路
25 第2回路
24 めっき層
28 ビアホール
30 第1ビルドアップ配線層30
31 第1回路層
32 第2ビルドアップ配線層
33 第2回路層
34 配線層
35 層間絶縁樹脂層
36 第3ビルドアップ層
40 ビルドアップ配線層付支持基板
50 多層積層板
Bu ビルドアップ配線層
F フィルム状樹脂
Claims (15)
- 銅箔層/剥離層/キャリア層/樹脂層の層構成を備え、
当該キャリア層の当該樹脂層側の表面の凹凸の最大高低差(PV)が3μm~12μmであり、
前記樹脂層の厚さが、1.5μm~15μmである、
ことを特徴とする回路形成層付支持基板。 - 前記剥離層は、窒素含有化合物、硫黄含有化合物及びカルボン酸からなる群から選択される化合物の少なくとも一つ以上を含む有機剥離層である請求項1に記載の回路形成層付支持基板。
- 前記剥離層は、無機成分を用いて形成した無機剥離層である請求項1に記載の回路形成層付支持基板。
- 樹脂層の両面に、当該樹脂層側から順にキャリア層/剥離層/銅箔層を備え、
当該キャリア層の当該樹脂層側の表面の凹凸の最大高低差(PV)が3μm~12μmであり、
前記樹脂層の厚さが1.5μm~30μmである、
ことを特徴とする両面回路形成層付支持基板。 - 請求項1~請求項3のいずれか一項に記載の回路形成層付支持基板を用いて製造された多層積層板であって、
前記銅箔層上に、少なくとも一層の絶縁層及び配線層を含むビルドアップ層が積層された後に、前記剥離層において分離され、前記銅箔層上に当該ビルドアップ層が積層された積層体であることを特徴とする多層積層板。 - 前記銅箔層上に、前記ビルドアップ層が積層される前に、前記銅箔層に対して回路形成が行われた請求項5に記載の多層積層板。
- 前記剥離層において分離された後、前記銅箔層に対して回路形成が行われた請求項5に記載の多層積層板。
- 請求項1~請求項3のいずれか一項に記載の回路層付支持基板を用いて、ビルドアップ法により多層プリント配線板を製造する方法であって、以下の工程を備えることを特徴とする多層プリント配線板の製造方法。
ビルドアップ配線層形成工程: 前記回路形成層付基板の前記銅箔層の表面に、ビルドアップ配線層を形成して、ビルドアップ配線層付支持基板を得る。
ビルドアップ配線層付支持基板分離工程: 当該ビルドアップ配線層付支持基板を、前記回路形成層付支持基板の前記剥離層で分離して、前記銅箔層上にビルドアップ層が形成された多層積層板を得る。 - 請求項4に記載の両面回路形成層付支持基板を用いて、ビルドアップ法により多層プリント配線板を製造する方法であって、以下の工程を備えることを特徴とする多層プリント配線板の製造方法。
両面回路形成層付支持基板の製造工程: 樹脂層/キャリア層/剥離層/銅箔層の層構成を備えるキャリア付銅箔を2枚用いて、この樹脂層同士を直接張り合わせ、又は、コア材の両面に張り合わせて中央樹脂層とすることで、銅箔層/剥離層/キャリア層/中央樹脂層/キャリア層/剥離層/銅箔層の層構成を有する両面回路形成層付支持基板を得る。
ビルドアップ配線層形成工程: 当該両面回路形成層付基板の各銅箔層の表面に、ビルドアップ配線層を形成して、ビルドアップ配線層付支持基板を得る。
ビルドアップ配線層付支持基板分離工程: 当該両面回路形成層付支持基板の剥離層で分離して、銅箔層上にビルドアップ層が形成された多層積層板を得る。 - 請求項4に記載の両面回路形成層付支持基板を用いて、ビルドアップ法により、多層プリント配線板を製造する方法であって、以下の工程を備えることを特徴とする多層プリント配線板の製造方法。
両面回路形成層付支持基板の製造工程: キャリア層/剥離層/銅箔層の層構成を備える第1キャリア付銅箔と、樹脂層/キャリア層/剥離層/銅箔層の層構成を備える第2キャリア付銅箔とを用いて、第1キャリア付銅箔のキャリアと、第2キャリア付銅箔の樹脂層とを直接張り合わせ、又はコア材の両面に張り合わせることで、銅箔層/剥離層/キャリア層/中央樹脂層/キャリア層/剥離層/銅箔層の層構成を有する前記両面回路形成層付支持基板を得る。
ビルドアップ配線層形成工程: 当該両面回路形成層付支持基板の各銅箔層の表面に、ビルドアップ配線層を形成して、ビルドアップ配線層付支持基板を得る。
ビルドアップ配線層付支持基板分離工程: 当該両面回路形成層付支持基板の剥離層で分離して、銅箔層上にビルドアップ層が形成された多層積層板を得る。 - 請求項4に記載の両面回路形成層付支持基板を用いて、ビルドアップ法により多層プリント配線板を製造する方法であって、以下の工程を備えることを特徴とする多層プリント配線板の製造方法。
両面回路形成層付支持基板の製造工程: キャリア層/剥離層/銅箔層の層構成を備えるキャリア付銅箔を2枚用いて、各キャリア付銅箔のキャリア層をコア材の両面に張り合わせることで、銅箔層/剥離層/キャリア層/中央樹脂層/キャリア層/剥離層/銅箔層の層構成を有する前記両面回路形成層付支持基板を得る。
ビルドアップ配線層形成工程: 当該両面回路形成層付支持基板の各銅箔層の表面に、ビルドアップ配線層を形成して、ビルドアップ配線層付支持基板を得る。
ビルドアップ配線層付支持基板分離工程: 当該両面回路形成層付支持基板の剥離層で離して、銅箔層上にビルドアップ層が形成された多層積層板を得る。 - 前記コア材が、半硬化状態の樹脂フィルム又は半硬化状態の樹脂層を有するフィルムである請求項9~請求項11のいずれか一項に記載の多層プリント配線板の製造方法。
- 前記ビルドアップ配線層形成工程において、前記銅箔層の表面に前記ビルドアップ層を形成する前に、当該銅箔層に対して回路形成が行われる請求項8~請求項12のいずれか一項に記載の多層プリント配線板の製造方法。
- 前記ビルドアップ配線層付支持基板分離工程において、前記多層積層板を得た後、前記銅箔層に対して回路形成が行われる請求項8~請求項12のいずれか一項に記載の多層プリント配線板の製造方法。
- 請求項8~請求項14のいずれか一項に記載の多層プリント配線板の製造方法で得られた多層プリント配線板。
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| CN109564899A (zh) * | 2016-08-05 | 2019-04-02 | 三菱瓦斯化学株式会社 | 支撑基板、带有支撑基板的层叠体及半导体元件搭载用封装基板的制造方法 |
| EP3672379A1 (en) * | 2018-12-19 | 2020-06-24 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with included electrically conductive base structure and method of manufacturing |
| CN114641126A (zh) * | 2021-02-09 | 2022-06-17 | 广州方邦电子股份有限公司 | 电磁屏蔽膜及线路板 |
| CN114641196A (zh) * | 2021-02-09 | 2022-06-17 | 广州方邦电子股份有限公司 | 电磁屏蔽膜及线路板 |
| WO2025047971A1 (ja) * | 2023-09-01 | 2025-03-06 | 三井金属鉱業株式会社 | 再配線積層体の製造方法及びキャリア付金属箔 |
| WO2025094612A1 (ja) * | 2023-11-01 | 2025-05-08 | 三井金属鉱業株式会社 | プリント配線板の製造方法 |
| WO2025094611A1 (ja) * | 2023-11-01 | 2025-05-08 | 三井金属鉱業株式会社 | プリント配線板の製造方法 |
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| JP6834121B2 (ja) * | 2015-09-17 | 2021-02-24 | 味の素株式会社 | 配線板の製造方法 |
| CN111356309B (zh) * | 2020-04-15 | 2021-04-23 | 江苏普诺威电子股份有限公司 | 具有高线路对位精度的多层电路板的制作方法 |
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| TWI600097B (zh) * | 2011-03-09 | 2017-09-21 | 日立化成股份有限公司 | Manufacturing method of package substrate for mounting semiconductor device, package substrate for mounting semiconductor device, and semiconductor package |
| JP2013140856A (ja) | 2011-12-28 | 2013-07-18 | Jx Nippon Mining & Metals Corp | キャリア付金属箔 |
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- 2014-11-21 KR KR1020167013103A patent/KR102191918B1/ko active Active
- 2014-11-21 TW TW103140379A patent/TWI584701B/zh active
- 2014-11-21 WO PCT/JP2014/080919 patent/WO2015076373A1/ja not_active Ceased
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| WO2012133638A1 (ja) * | 2011-03-30 | 2012-10-04 | 三井金属鉱業株式会社 | 多層プリント配線板の製造方法及びその製造方法で得られる多層プリント配線板 |
| JP2012216824A (ja) * | 2011-03-31 | 2012-11-08 | Hitachi Chem Co Ltd | 半導体素子搭載用パッケージ基板の製造方法 |
| JP2013219191A (ja) * | 2012-04-09 | 2013-10-24 | Shinko Electric Ind Co Ltd | 配線基板及び配線基板の製造方法 |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109564899A (zh) * | 2016-08-05 | 2019-04-02 | 三菱瓦斯化学株式会社 | 支撑基板、带有支撑基板的层叠体及半导体元件搭载用封装基板的制造方法 |
| EP3496138A4 (en) * | 2016-08-05 | 2019-10-09 | Mitsubishi Gas Chemical Company, Inc. | SUPPORT SUBSTRATE, LAMINATE WITH SUPPORTING SUBSTRATE AND METHOD FOR PRODUCING A HOUSING SUBSTRATE FOR ASSEMBLING A SEMICONDUCTOR ELEMENT |
| US11217445B2 (en) | 2016-08-05 | 2022-01-04 | Mitsubishi Gas Chemical Company, Inc. | Supporting substrate, supporting substrate-attached laminate and method for manufacturing a package substrate for mounting a semiconductor device |
| CN109564899B (zh) * | 2016-08-05 | 2023-06-06 | 三菱瓦斯化学株式会社 | 支撑基板、带有支撑基板的层叠体及半导体元件搭载用封装基板的制造方法 |
| EP3672379A1 (en) * | 2018-12-19 | 2020-06-24 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with included electrically conductive base structure and method of manufacturing |
| US11387117B2 (en) | 2018-12-19 | 2022-07-12 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with included electrically conductive base structure and method of manufacturing |
| CN114641126A (zh) * | 2021-02-09 | 2022-06-17 | 广州方邦电子股份有限公司 | 电磁屏蔽膜及线路板 |
| CN114641196A (zh) * | 2021-02-09 | 2022-06-17 | 广州方邦电子股份有限公司 | 电磁屏蔽膜及线路板 |
| CN114641126B (zh) * | 2021-02-09 | 2024-03-08 | 广州方邦电子股份有限公司 | 电磁屏蔽膜及线路板 |
| WO2025047971A1 (ja) * | 2023-09-01 | 2025-03-06 | 三井金属鉱業株式会社 | 再配線積層体の製造方法及びキャリア付金属箔 |
| WO2025094612A1 (ja) * | 2023-11-01 | 2025-05-08 | 三井金属鉱業株式会社 | プリント配線板の製造方法 |
| WO2025094611A1 (ja) * | 2023-11-01 | 2025-05-08 | 三井金属鉱業株式会社 | プリント配線板の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2015076373A1 (ja) | 2017-03-16 |
| TWI584701B (zh) | 2017-05-21 |
| CN105746004B (zh) | 2019-06-07 |
| TW201536120A (zh) | 2015-09-16 |
| CN105746004A (zh) | 2016-07-06 |
| KR20160089365A (ko) | 2016-07-27 |
| JP6678029B2 (ja) | 2020-04-08 |
| KR102191918B1 (ko) | 2020-12-17 |
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