WO2015039492A1 - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
WO2015039492A1
WO2015039492A1 PCT/CN2014/082558 CN2014082558W WO2015039492A1 WO 2015039492 A1 WO2015039492 A1 WO 2015039492A1 CN 2014082558 W CN2014082558 W CN 2014082558W WO 2015039492 A1 WO2015039492 A1 WO 2015039492A1
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WIPO (PCT)
Prior art keywords
layer
conductor
signal line
array substrate
forming
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PCT/CN2014/082558
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English (en)
French (fr)
Inventor
张明
樊超
崔立全
郝昭慧
尹雄宣
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/429,886 priority Critical patent/US10229938B2/en
Publication of WO2015039492A1 publication Critical patent/WO2015039492A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same. Background technique
  • the array substrate is provided with a structure of a gate line, a data line, a thin film transistor, a pixel electrode, etc.; the above structure is formed of a conductive material of a different layer.
  • the array substrate has a layered structure and includes a gate metal layer forming a gate electrode, a source/drain metal layer forming a source and a drain of the thin film transistor, a pixel electrode layer forming a pixel electrode, and the like.
  • Some array substrates further include a common electrode layer forming a common electrode.
  • the gate line is connected to the gate of the thin film transistor; the data line is connected to the source of the thin film transistor; the gate line is used to turn on the thin film transistor, and the data line is used to input a voltage signal to the pixel electrode through the thin film transistor.
  • the gate lines and data lines may be collectively referred to as signal lines.
  • a wiring area (or a sector) is disposed in the non-display area of the edge of the array substrate to realize connection of the signal line and the driving circuit; each of the signal lines includes a portion distributed in the display area of the array substrate and distributed in the array The non-display area portion of the substrate; generally, a plurality of signal lines are concentrated in the wiring area.
  • the signal line will cause the path of the signal line to travel differently.
  • the path through which the signal line travels is different.
  • the length of the formed signal line is poor, which causes the signal line to form a resistance difference. Therefore, the length of the signal line affects the length of the path of the electrical signal transmission, and the length of the conductive path is different, resulting in a difference in resistance and capacitance, which eventually causes different delays in the signal transmission process, thereby forming a display defect.
  • the existing method forms a conductive path by a signal line in a wiring area in a fold line manner, thereby extending the length thereof to form a length similar to that of other signal lines, thereby ensuring resistance between the signal line and the signal line.
  • the difference is within a predetermined range, thereby ensuring that the delays of the transmission lines of the respective signal lines are uniform.
  • the area enclosed by the broken line in the figure is the wiring area, that is, the wiring area SS, and the wiring area SS is provided with the signal line 011 near the wiring area SS, the edge, and the signal located in the middle of the wiring area S-S'. Line 012.
  • the signal line 012 is formed in a zigzag line, but the formation of the fold line causes the width of the wiring area occupied by the signal line 012 to be widened, as shown in FIG.
  • the width of the signal line 012 is d, so that the number of signal lines that can be accommodated in the wiring area of the same area is reduced, which leads to an increase in the number of driving (COF, etc.), and an increase in the number of driving forces necessarily leads to an increase in the driving IC, which ultimately leads to an increase in cost.
  • an array substrate including a plurality of wiring regions disposed in a non-display region, wherein a plurality of signal lines are disposed in the wiring region, and at least a portion of the signal lines in each of the wiring regions are The wires in different layers are connected in series; the resistance difference of any two signal lines in the same wiring area is within a wide range.
  • the wires are located in a gate metal layer, a source/drain metal layer, a pixel electrode layer, or a common electrode layer.
  • an insulating layer is disposed between any two of the gate metal layer, the source/drain metal layer, the pixel electrode layer, and the common electrode layer; and the wires located in different layers are through via holes provided on the insulating layer. Concatenation.
  • different layers of wires of the same signal line are all in the same cross section; the cross section is perpendicular to the plane in which the array substrate is located.
  • one end of the signal line is connected to the data line or the gate line of the display area, and the other end is connected to the driving circuit.
  • At least one layer forming the same signal line includes two or more intermittent wires, and the two or more intermittent wires are serially connected by the wires of different layers to form the signal line.
  • each layer forming the same signal line includes only one wire, and wires between different layers are connected in series through via holes to form the signal line.
  • a method of fabricating an array substrate comprising the steps of forming a signal line in a non-display area and connected to a gate line or a data line, wherein the signal line is formed by connecting wires in different layers in series
  • the signal line is located in a wiring area of the non-display area of the array substrate; and the resistance difference of any two signal lines in the same wiring area is within a wide range.
  • the method includes:
  • a gate metal layer including a gate line in the display region, and simultaneously forming a plurality of intermittent first wires of the signal line in the non-display area;
  • the method includes:
  • a gate metal layer including a gate line in the display region, and simultaneously forming a plurality of intermittent first wires of the signal line in the non-display area;
  • a pixel electrode layer including a pixel electrode over the passivation layer Forming a pixel electrode layer including a pixel electrode over the passivation layer, and simultaneously forming a third wire at least at a portion where the second wire is not formed in a discontinuity corresponding to the first wire, and in the second Filling a via hole with a conductive material for forming the pixel electrode;
  • the first wire, the second wire and the third wire form a signal line through the conductive material in the first via hole and the conductive material in the second via hole in series.
  • the method includes:
  • a gate metal layer including a gate line in the display region, and simultaneously forming a first wire of the signal line in the non-display region;
  • a source/drain metal layer including a source, a drain, and a data line over the active layer, and simultaneously forming a second wire, and filling the first via hole to form the source and drain And a conductive material of the data line and the data line to connect the first wire and the second wire in series.
  • the method includes:
  • a gate metal layer including a gate line in the display region, and simultaneously forming a non-display area The first wire of the line;
  • the manufacturing method further includes the step of forming a via hole; the first wire, the second wire, and the third wire are connected in series by a via to form a signal line.
  • the step of forming a via hole includes:
  • the first via is used to connect the first wire and the second wire
  • the second via is used to connect the second wire and the third wire.
  • the step of forming a via hole includes:
  • the first via is used to connect the first wire and the second wire
  • the third via is used to connect the first wire and the third wire.
  • the step of forming a via hole includes:
  • the second via is used to connect the second wire and the third wire
  • the third via is used to connect the first wire and the third wire.
  • FIG. 1 is a schematic structural view of a wiring area of a prior art array substrate
  • FIG. 2a is a schematic top plan view of a wiring area of an array substrate according to Embodiment 1 of the present invention
  • FIG. 2b is a partial cross-sectional view of FIG. 2a;
  • FIG. 3 is a schematic plan view showing a signal line of an array substrate according to Embodiment 1 of the present invention.
  • Figure 4 is a cross-sectional view taken along line A-A' of Figure 3;
  • Figure 5 is a cross-sectional view taken along line B-B' of Figure 3;
  • FIG. 6 is a schematic plan view showing a signal line of an array substrate according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic top plan view of a signal line formed by the method for fabricating an array substrate according to Embodiment 3 of the present invention.
  • Figure 8 is a cross-sectional view taken along line C-C' of Figure 7;
  • FIG. 9 is a second schematic structural view of a signal line fabricated by the method for fabricating an array substrate according to Embodiment 3 of the present invention. detailed description
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the embodiment provides an array substrate, including a plurality of wiring regions disposed in a non-display area, wherein the wiring area is provided with a plurality of signal lines, and at least part of the signal lines in each of the wiring areas are located at different layers.
  • the wires are connected in series; the resistance difference of any two signal lines in each wiring area is within a wide range.
  • the array substrate includes a display area (also commonly referred to as an AA area) at an intermediate position and a non-display area located at the periphery of the display area. Usually assembled into an array on the array substrate and the opposite substrate After that, the non-display area is covered by the frame of the display device. a plurality of wiring areas are disposed in the non-display area; each of the wiring areas is provided with a plurality of signal lines; the signal lines may be gate lines or data lines; and the signal lines are located in the wiring area It is connected to the driving circuit, that is, one end of the signal line is connected to the gate line or the data line of the display area, and the other end is connected to the driving circuit.
  • a display area also commonly referred to as an AA area
  • non-display area located at the periphery of the display area.
  • the non-display area is covered by the frame of the display device.
  • a plurality of wiring areas are disposed in the non-display area; each of the wiring areas is
  • the array substrate is a layered structure comprising a plurality of electrically conductive layers; and for example, an insulating layer for insulating is provided between the conductive layers.
  • the signal line components are all located in the same layer of the array substrate.
  • the signal lines located in the same layer are made of the same material, and usually the widths of the signal lines are also equal.
  • the length difference between the signal lines should also be kept within a certain range. Therefore, the signal line in the middle of the wiring area will be bent. For details, see signal line 012 in Figure 1.
  • the wiring area SS includes a signal line 111 which is located at the edge of the wiring area S-S' and is composed of wires located in the same layer of the array substrate, and is located.
  • the wiring area SS is a signal line 112 at an intermediate position and which is formed by connecting different layers of wires in series.
  • the signal line 112 located at the intermediate position of the wiring area S-S' is formed by the first wire 121 and the second wire 123 being connected in series through the via 122.
  • An insulating layer 113 is disposed between the first wire 121 and the second wire 123, and the structure of the insulating layer is different according to the layer of the first wire 121 and the second wire 123.
  • the width d of the wiring area where the signal line 012 is located in Fig. 1 is larger than the width D of the signal line 112 in Fig. 2.
  • the signal line at the intermediate position of the wiring area SS is formed by connecting wires of different layers in series, thereby forming a bend in a plane perpendicular to the plane of the array substrate, and achieving the effect of lengthening the length of the signal line.
  • the width of the signal line in the wiring area is narrowed. Therefore, the number of signal lines that can be set in the wiring area is increased, the number of wiring areas on the array substrate can be reduced, and the number of driving can be reduced, thereby saving cost.
  • the resistance difference of any two signal lines in the same wiring area is within a wide range.
  • the threshold may be a value determined according to factors such as the size of the array substrate. For example, the resistance ratio between the signal line of the maximum resistance and the signal line of the minimum resistance is limited to a range of 3:1.
  • the number of connection points ie, via holes
  • Bend the wire to extend the wire at the layer where it is not connected to the drive circuit The transmission path realizes that the resistance difference of any two signal lines is controlled within a wide range.
  • the number, length and width of one of the wires of all the signal lines are equal; and in the other layer, all The number of wires included in the signal line is equal and the width of the wires is also equal.
  • the difference is that the direction of the signal lines in the wiring area is aligned, and the length of the wires included in the signal lines is gradually shortened from the sides of the intermediate wiring area.
  • all the signal lines can be serially connected by multiple layers of wires, and all the wires have the same number of wires in the same layer, the difference is the transmission path formed by the same layer of wires, in the wiring area
  • the inner side is gradually shortened from both sides of the wiring area to achieve the final effect of the equal resistance.
  • the different layer wires of the same signal line are located in the same cross section, for example, the signal line 112 in FIG. 2a-2b. Shown.
  • the wires of one layer are bent, and the wires of the same signal line in different layers may be located in two or more sections of the vertical array substrate, for example: ⁇ : ⁇ Figure 3 Show.
  • the array substrate includes a gate metal layer, a gate insulating layer, an active layer, a source/drain metal layer, a passivation layer, and a pixel electrode layer; a gate metal layer for forming a gate line; the gate insulating layer is disposed at the Above the gate line metal layer; the active layer includes a semiconductor layer and a doped semiconductor layer; the source and drain metal layers are used to form a source, a drain, and a data line of the thin film transistor; and the passivation layer is used to protect the structure below .
  • the pixel electrode layer is used to form a pixel electrode.
  • the pixel electrode is connected to the drain of the thin film transistor.
  • the gate metal layer, the source/drain metal layer, and the pixel electrode layer in the above layer all belong to the conductive layer; therefore, the conductive layer can form a wire for forming a signal line by a patterning process while forming a structure included in the array substrate.
  • the wires in the different layers are connected through via holes to form signal lines.
  • the passivation layer, the gate insulating layer, and the active layer may be considered to be between the conductive layers and to the insulating layer.
  • At least a portion of the wires are located in a gate metal layer, a source/drain metal layer, a pixel electrode layer, or a common electrode layer.
  • a wire located in the gate metal layer and a wire located in the source/drain metal layer are connected through a through-gate insulating layer and a via hole on the active layer; a wire located in the source-drain metal layer and a pixel electrode layer
  • the wires are connected by via holes provided in the passivation layer; the wires located in the gate metal layer and the wires located in the pixel electrode layer pass through an intermediate layer penetrating the gate insulating layer, the passivation layer or the like Vias are connected.
  • the signal line includes a wire located in the pixel electrode layer 120, a wire located in the source/drain metal layer 130, and located in the gate metal layer 110; the wires are connected in series to form a conductive Signal line. Since the signal lines are bent and connected in different layers, the length of the wires is increased, and then the resistance is increased, so that the resistance difference between the signal lines can be adjusted by adjusting the distribution and the number of the wires. Further, by increasing the number of times the signal line is bent between different layers, the line resistance of the signal at the intermediate position of the wiring area is continuously increased, and the difference in resistance between the signal lines at the middle and the periphery in the wiring area is reduced, and finally realized. The difference in resistance between any two signal lines in the wiring area is within the wide range.
  • the effect achieved by the above structure is: the area occupied by the signal lines in the gate metal layer or the source/drain metal layer is reduced, so that the density of the signal lines in the wiring area can be further increased, so that one signal line region corresponding to one drive is driven.
  • the number of connected signal lines has increased, which is beneficial to reduce the drive (such as
  • the above array substrate can be completed without adding an additional patterning process, and has the advantages of simple implementation, and is advantageous for reducing the area of the non-display area, and contributing to the realization of the narrow frame.
  • the structure of the signal lines includes at least the following two types:
  • At least one layer forming the same signal line includes more than two intermittent wires.
  • the signal line A includes two intermittent first wires located in the gate metal layer and a second wire located in the source/drain metal layer corresponding to the discontinuity of the two wires in the gate metal layer; the first wire and the first wire
  • the two wires are connected by via holes penetrating the gate insulating layer and the active layer.
  • the second wire serves as an intermediate connection portion of the two first wires.
  • Each layer forming the same signal line includes only one wire, and wires of different layers are connected in series through via holes to form the signal line.
  • the signal line includes a first wire located in the gate metal layer, a second wire located in the source/drain metal layer, and a third wire located in the pixel electrode layer.
  • the first wire, the second wire, and the third wire may penetrate the entire wiring area at a layer where they are located, thereby forming a spatially bent signal line in a plane perpendicular to the array substrate. .
  • Both of the above structures can achieve the purpose of reducing the signal line resistance difference, and at the same time reduce the width of the wiring area occupied by the single signal line, thereby increasing the density of the signal line in the wiring area and reducing the driving. Number.
  • the wires in different layers shown in FIG. 3 can be bent, because the signal lines are bent between layers.
  • at least one of the wires is bent in a plane in which the parallel array substrate is located, thereby ensuring that the bending radius d of the signal line of the wiring area is smaller than that of the existing signal lines in the same type and same size array substrate. It occupies the width, thereby facilitating the concentration of the connected signal lines and the reduction in the number of driving.
  • FIG. 4 is a cross-sectional view of FIG. 3 at AA' where 160 is a passivation layer, 150 is an active layer, and 140 is a gate insulating layer.
  • the wires of the pixel electrode layer 120 are connected to the wires located in the gate metal layer 110 through the via holes, and the conductive material for connecting the two is a conductive material constituting the pixel electrode layer 120.
  • Figure 5 is a cross-sectional view of Figure 3 at B-B.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the array substrate of this embodiment includes a plurality of wiring regions disposed in the non-display area, wherein the wiring area is provided with a plurality of signal lines, and at least part of the signal lines in each of the wiring areas are connected by wires located in different layers.
  • the resistance difference of any two signal lines in the same wiring area is within a wide range.
  • the wires of the different layers are sequentially connected in accordance with the extending direction of the signal lines.
  • the array substrate includes a pixel electrode layer, a gate line metal layer, and a source/drain metal layer.
  • the signal line in FIG. 6 is located in a non-display area portion of the array substrate, and includes a signal line 210, a signal line 220, and a signal line 230.
  • the signal line 210 is composed only of the wires of the source/drain metal layer 310, and the signal line 220 is formed by connecting the wires of the source/drain metal layer 310, the wires of the pixel electrode layer 320, and the wires of the gate metal layer 330.
  • the signal line 230 is formed by connecting the wires of the source/drain metal layer 310, the wires of the pixel electrode layer 320, and the wires of the gate metal layer 330; wherein 410 is a wire connecting the wires of the source/drain metal layer 310 and the pixel electrode layer 320. Via 420 is a connection via of the pixel electrode layer 320 wire and the gate metal layer 330 wire.
  • the signal line 220 and the signal line 230 are used in the array substrate of the embodiment.
  • the signal line described in the above is formed by connecting different layers of wires in series, thereby lengthening the lengths of the signal lines 220 and the signal lines 230 in a three-dimensional space, and swapping 230 originally located at the center of the wiring area to the edge of the wiring area, thereby It contributes to the realization of resistance such as wiring area.
  • the position of the wires located in different layers can be changed as needed,
  • the signal line which should originally be located in the middle of the wiring area is exchanged with the signal line originally located at the edge of the wiring area, and the resistance difference between the signal lines can be again reduced by the exchange.
  • the signal line 230 located at the center of the wiring area and the signal line 220 near the edge of the wiring area are exchanged by the arrangement of the wires between the different layers, thereby achieving the purpose of extending the length of 230, while The 230 moves to the outside of the wiring area, and other signal lines located in the wiring area, such as 220, have more space to achieve horizontal bending, thereby facilitating the equal resistance of the overall wiring area.
  • a common electrode layer is further included on the array substrate.
  • the IPS In-Plane Switching plane conversion liquid crystal panel
  • the common electrode and the pixel electrode are all located on the array substrate.
  • the common electrode and the pixel electrode are both located on the array substrate, but are located in different layers of the array substrate with an insulating layer therebetween.
  • the material for forming the common electrode is also a conductive material, so that the wiring can be formed in the common electrode layer including the common electrode by merely changing the mask, and then connected in series between the different layers to form a signal line.
  • the signal line may be formed by connecting only the wires located in two layers, or may be formed by connecting two or more wires in series.
  • the signal line includes a gate line and a data line; the output end is connected to the gate of the thin film transistor in the array substrate as a gate line for gate signal transmission; and the output end is connected to the drain of the thin film transistor in the array substrate
  • the data line is used to input a corresponding signal to the pixel electrode.
  • the gate line is connected to the gate drive for inputting a gate scan signal to turn on or off the corresponding thin film transistor.
  • the data line is drivingly connected to the data line for inputting a voltage to the pixel electrode for supplying a deflection voltage of the liquid crystal molecule to the pixel electrode when used in a liquid crystal display. The difference in resistance of each signal line will cause the delay of the signal to be transmitted to be different.
  • the difference between the length of the signal line, the conductive material formed, and various wire connections can be used to make the difference in resistance. Adjustment. Further, in this embodiment, it is provided that the difference in resistance between the signal lines is smaller than the threshold.
  • the threshold value can be set as needed. In a specific implementation process, the resistance ratio between the signal lines is maintained within a range of 3:1, which does not adversely affect the display or has a slight adverse effect, and at the same time, the manufacturing process The requirements are also low and easy to implement.
  • the signal line may be connected to the driving circuit at any one of the conductive layers of the array substrate, for example, the wire of the gate metal layer and the wire of the source/drain metal layer are connected to the driving circuit.
  • At least part of the signal lines of the array substrate in the embodiment are realized between multiple layers of the array substrate.
  • the bending in three-dimensional space, the wires in different layers are connected in series to form a signal line satisfying the required signal line, and the problem that the area occupied by the signal line is not too wide, and the formation of a narrow frame which is disadvantageous for the non-display area is avoided. problem.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the embodiment provides a method for fabricating an array substrate, and the manufacturing method includes:
  • the wire forming signal lines located in different layers include at least the following two structures:
  • a plurality of wires are formed, and the plurality of wires are connected in series by wires located in different layers.
  • one wire is formed corresponding to one signal line, and the wires located at different layers are connected in series.
  • Manner 1 When the signal line is formed by a series of wires in two layers; and each layer includes at least two wires, the manufacturing method specifically includes:
  • Step 1 forming a gate metal layer including a gate line in the display region, and simultaneously forming a plurality of intermittent first wires of the signal line in the non-display area;
  • Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
  • Step 3 forming a through-gate insulating layer and an active layer corresponding to an end point of the first wire First via;
  • Step 4 forming a source/drain metal layer including a source, a drain, and a data line over the active layer, and simultaneously forming a second wire at a discontinuity of the first wire, and at the first A via is filled with a conductive material for forming the source, the drain, and the signal line to connect the first and second wires in series.
  • At least part of the signal lines in the array substrate produced by the method are formed by connecting the wires of the gate metal layer and the wires of the source and drain metal layers in series, and the through-gate insulating layer and the active layer are used in series connection. hole.
  • the signal line includes a first wire on the gate metal layer 530 and a second wire on the source/drain metal layer 520.
  • the first wire and the second wire are connected by a via.
  • Figure 8 Figure 7 is a cross-sectional view at CC.
  • the array substrate includes a gate metal layer 530 , a gate insulating layer 560 , an active layer 550 , a source/drain metal layer 520 , and a passivation layer 540 .
  • the gate line metal layer 530 is connected to the source/drain metal layer 520 in FIG. 7, the step of forming a via hole is added once, and the connection in this manner can effectively ensure the reliability of the connection and reduce the contact resistance of the connection point. .
  • the wires constituting the signal lines may also be located in other layers, such as a pixel electrode layer, and a common electrode layer.
  • the first wire is formed together with the gate line, and it is only necessary to change the mask plate, and no additional steps are added, thereby achieving simplicity.
  • the same formation principle is also applicable to the formation of the second wire, and the connection of the first wire and the second wire is also formed synchronously when the second wire is formed, thereby achieving simplicity.
  • the formed signal lines are not limited to the same layer of the array substrate, but are formed in the plurality of layers, and converted from the bent signal lines in the original plane to the signal lines bent in the space described in the embodiment of the invention.
  • the second method is for an array substrate including signal lines serially connected by wires in three layers in the array substrate; and each layer includes at least two wires forming the same signal line.
  • the manufacturing method specifically includes:
  • Step 1 forming a gate metal layer including a gate line in the display region, and simultaneously forming a plurality of intermittent first wires of the signal line in the non-display area;
  • Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
  • Step 3 forming a through-gate insulating layer and an active layer corresponding to an end point of the first wire First via;
  • Step 4 forming a source/drain metal layer including a source, a drain, and a signal line over the active layer, and simultaneously forming a second wire at least at a portion of the discontinuous correspondence of the first wire, and The first via hole is filled with a conductive material for forming the source, the drain, and the signal line;
  • Step 5 forming a passivation layer over the source/drain metal layer and simultaneously forming a second via hole;
  • Step 6 forming a pixel electrode layer including a pixel electrode over the passivation layer, and at the same time at least A third wire is formed at the second wire in the discontinuity of the first wire, and a conductive material for forming the pixel electrode is filled in the second via hole.
  • the first wire, the second wire, and the third wire are connected in series by the conductive material in the first via hole and the conductive material in the second via hole to form a signal line.
  • the signal lines in the array substrate are formed by the wires located in the three layers, and the formed signal lines can be referred to FIG. 4 or FIG.
  • Method 3 The manufacturing method is used to form an array substrate, wherein the array substrate includes signal lines formed by connecting wires in four layers; and each of the conductive layers provided with the wires includes at least two Wires that form the same signal line.
  • some array substrate fabrication methods also include the steps of forming a common electrode, such as an ADS-array field mode array substrate.
  • the array substrate of the ADS mode includes a pixel electrode and a common electrode; and the pixel electrode and the common electrode are located in different layers, and are usually formed of ITO.
  • the manufacturing method specifically includes:
  • the first ITO layer 610 including a transparent electrode for forming a fringe electric field is formed by the first process of patterning ITO, and the wires located in the first ITO layer 610 are simultaneously formed.
  • the first process of patterning ITO is used to form a pixel electrode or a common electrode. If the first patterning process of ITO is used to form a pixel electrode, the second patterning process of ITO is used to form a common electrode. If the process of patterning the ITO for the first time is to form a common electrode, the second patterning process of the ITO is used to form the pixel electrode.
  • the conductive material inside makes the connection between the wires.
  • the signal lines in the substrate are connected by wires located in four different layers.
  • the patterning process is one or more fabrication processes including deposition, coating, exposure, development, etching, and the like.
  • Method 1 This method is used to form an array substrate including signal lines formed by connecting two layers of wires; and only one wire is included in one layer for forming the same signal line.
  • Step 1 forming a gate metal layer including a gate line in the display region, and simultaneously forming a first wire of the signal line in the non-display area;
  • Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
  • Step 3 forming a through-gate insulating layer and an active layer above the end of the first wire First via;
  • Step 4 forming a source/drain metal layer including a source, a drain, and a data line over the active layer, and simultaneously forming a second wire, and filling the first via hole to form the source Conductive materials of the poles, the drains, and the data lines are connected in series to the first and second wires.
  • the conductive layer where the first wire or the second wire is located may also be changed.
  • Method 2 part of the signal lines in the array substrate produced by the method are formed by three layers of wires; and each layer for forming the same signal line includes only one wire.
  • the manufacturing method specifically includes: Step 1: forming a gate metal layer including a gate line in a display region, and simultaneously forming a first wire of the signal line in the non-display area;
  • Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
  • Step 3 forming a source including a source, a drain, and a signal line over the active layer Leaking a metal layer and simultaneously forming a second wire;
  • Step 4 forming a passivation layer over the source/drain metal layer
  • Step 5 forming a pixel electrode layer including a pixel electrode over the passivation layer, and simultaneously forming a third wire.
  • the method for fabricating the array substrate further includes the steps of forming via holes:
  • Step A forming a first via hole penetrating the gate insulating layer and the active layer; in a specific implementation process, the step A is located between step 2 and step 3;
  • Step B forming a second via hole on the passivation layer; the step B is located between step 4 and step 5;
  • the first via hole is used to connect the first wire and the second wire; and the second via hole is used to connect the second wire and the third wire.
  • the first wire of the array substrate is only connected to the second wire; the third wire is only connected to the second wire, and the second wire is connected to the first wire and the second wire.
  • the wires form a bridging portion of the signal lines.
  • Method 3 part of the signal lines in the array substrate produced by the method are formed by three layers of wires; and each layer for forming the same signal line includes only one wire.
  • the manufacturing method specifically includes: Step 1: forming a gate metal layer including a gate line in a display region, and simultaneously forming a first wire of the signal line in the non-display area;
  • Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
  • Step 3 forming a source including a source, a drain, and a signal line over the active layer Leaking a metal layer and simultaneously forming a second wire;
  • Step 4 forming a passivation layer over the source/drain metal layer
  • Step 5 forming a pixel electrode layer including a pixel electrode over the passivation layer, and simultaneously forming a third wire.
  • the manufacturing method further includes the step of forming a via hole, and specifically includes:
  • Step A forming a first via hole penetrating the gate insulating layer and the active layer; step A is located between step 2 and step 3;
  • Step B forming a third via hole penetrating the gate insulating layer, the active layer and the passivation layer; step B is located between step 4 and step 5;
  • the first via is used to connect the first wire and the second wire
  • the third via is used to connect the first wire and the third wire.
  • the first wire of the array substrate is only connected to the second wire; the third wire is only connected to the first wire, and the first wire forms a signal for connecting the third wire and the second wire.
  • the bridging portion of the line is only connected to the second wire; the third wire is only connected to the first wire, and the first wire forms a signal for connecting the third wire and the second wire.
  • Method 4 part of the signal lines in the array substrate produced by the method are formed by three layers of wires; and each layer for forming the same signal line includes only one wire.
  • the manufacturing method specifically includes: Step 1: forming a gate metal layer including a gate line in a display region, and simultaneously forming a first wire of the signal line in the non-display area;
  • Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
  • Step 3 forming a source including a source, a drain, and a signal line over the active layer Leaking a metal layer and simultaneously forming a second wire;
  • Step 4 forming a passivation layer over the source/drain metal layer;
  • Step 5 forming a pixel electrode layer including a pixel electrode over the passivation layer, and simultaneously forming a third wire.
  • the manufacturing method further includes the step of forming a via hole: the step of forming the via hole specifically includes: Step A: forming a second via hole on the passivation layer;
  • Step B forming a third via hole penetrating the gate insulating layer, the active layer, and the passivation layer;
  • the second via is used to connect the second wire and the third wire
  • the third via is used to connect the first wire and the third wire.
  • the first via hole and the second via hole may be formed by the same patterning process.
  • the step of forming the via is located between step 4 and step 5.
  • the first wire of the array substrate is only connected to the third wire; the second wire is only connected to the third wire, and the third wire is used as a signal for connecting the first wire and the second wire.
  • the bridging portion of the line is used as a signal for connecting the first wire and the second wire.
  • the array substrate produced by the method for fabricating the array substrate of the present embodiment can be considered as the array substrate of the present invention.
  • the method for fabricating the array substrate according to the embodiment is used for fabricating the array substrate of the present invention, and the manufacturing process is less improved, and only the structure of the mask is changed to complete the fabrication of the wires and the connection between the wires, thereby realizing
  • the advantage of the simplicity is that the array substrate formed by the method for fabricating the array substrate of the present invention has a small bending radius of signal lines and a large density of signal lines, which is advantageous for reducing driving data to save consumables and manufacturing costs. advantage.

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Abstract

一种阵列基板及其制作方法。阵列基板包括设置在非显示区域的多个布线区域（S-S'），布线区域（S-S'）内设置有若干信号线（111，112），每一布线区域（S-S'）内至少部分信号线（111，112）由位于不同层的导线（121，123）串接而成；同一布线区域（S-S'）内任意两根信号线（111，112）的电阻差均在阈值范围内。采用将同一根信号线（111，112）设置在不同层，使信号线（111，112）在垂直于阵列基板的平面内进行弯折，达到延长信号线（111，112）长度的目的，从而增大了需要增大电阻的信号线（111，112）长度和电阻。与此同时没有增加信号线（111，112）所占的宽度，从而可以使得信号线（111，112）在布线区域（S-S'）的密度更大、从而可以达到减少驱动数目的目的，降低了制作成本，同时避免了因单根信号线（111，112）所占用的面积大，而导致非显示区域的面积大不利于实现窄边框的问题。

Description

阵列基板及其制作方法 技术领域
本发明的实施例涉及一种阵列基板及其制作方法。 背景技术
阵列基板上设有栅线、 数据线、 薄膜晶体管、 像素电极等结构； 上述结 构釆用不同层的导电材质构成。 通常阵列基板为分层结构并包括形成栅极的 栅极金属层、 形成薄膜晶体管源极和漏极的源漏金属层以及形成像素电极的 像素电极层等。 有的阵列基板上还包括形成公共电极的公共电极层。 栅线与 薄膜晶体管的栅极相连； 数据线与薄膜晶体管的源极相连； 栅线用以开启薄 膜晶体管， 数据线用以通过所述薄膜晶体管向像素电极输入电压信号。 所述 栅线和数据线可以统称为信号线。 在阵列基板边缘的非显示区域内设有布线 区域（或称为扇区） 以实现信号线与驱动电路的连接； 每一条所述信号线均 包括分布在阵列基板显示区域的部分以及分布在阵列基板非显示区域部分； 通常所述布线区域内集中若干条信号线。
信号线在所述布线区域集中的过程中， 将造成信号线所走过的路径的远 近不同。 信号线所走过的路径不同， 在导电材质以及信号线宽度一致的情况 下， 形成的信号线的长度差， 将导致信号线形成电阻差。 从而信号线长度长 短影响了电信号传输的路径的长短， 从而导电通路长度不一， 造成电阻电容 差异， 最终导致信号传输过程中形成不同时延， 从而形成显示不良。
为了解决上述问题， 现有的做法将位于布线区域内的信号线以折线方式 形成导电通路， 从而延长其长度， 以形成与其他信号线差不多的长度， 从而 确保信号线与信号线之间的电阻差在预定的范围内， 从而保证各信号线对传 输信号的时延一致。 如图 1所示， 图中虚线围成的区域为布线区域即布线区 域 S-S，， 布线区域 S-S，内设有靠近布线区域 S-S，边缘的信号线 011 以及位 于布线区域 S-S'中间的信号线 012。 为了使信号线 011与信号线 012形成等 电阻的导通路径， 将所述信号线 012做成了折线状， 但是形成折线将导致信 号线 012所占的布线区域的宽度变宽， 在图 1中所述信号线 012所占宽度为 d，从而同样面积的布线区域所能容纳的信号线数目减少，进而导致驱动（ COF 等）数量增加， 驱动数量的增加必然导致驱动 IC的增加， 最终导致了成本的 增力口。 发明内容
根据本发明的实施例， 提供一种阵列基板， 包括设置在非显示区域的多 个布线区域， 所述布线区域内设置有若干信号线， 每一所述布线区域内至少 部分所述信号线由位于不同层的导线串接而成； 同一布线区域内任意两根信 号线的电阻差均在阔值范围内。
例如， 所述导线位于栅极金属层、 源漏金属层、 像素电极层或公共电极 层。
例如， 所述栅极金属层、 源漏金属层、 像素电极层以及公共电极层中任 意两层之间均设有绝缘层； 位于不同层的导线通过设置在所述绝缘层上的过 孔进行串接。
例如， 同一所述信号线的不同层导线均位于同一截面内； 所述截面垂直 于所述阵列基板所在的平面。
例如， 所述信号线一端与显示区域的数据线或栅线相连接， 另一端与驱 动电路连接。
例如， 形成同一所述信号线的至少一层中包括两条以上间断的导线， 由 不同层的导线将该两条以上间断的导线串接形成所述信号线。
例如， 形成同一所述信号线的每一层都仅包括一条导线， 不同层间的导 线通过过孔串接形成所述信号线。
根据本发明的实施例， 提供一种阵列基板的制作方法， 包括形成位于非 显示区域且与栅线或数据线相连的信号线的步骤， 所述信号线由位于不同层 的导线串接而形成； 其中， 所述信号线位于所述阵列基板的非显示区域的布 线区域内； 且同一布线区域内任意两根信号线的电阻差均在阔值范围内。
例如， 所述方法包括：
在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区域所述信 号线的若干间断的第一导线；
在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 对应于所述第一导线的端点处形成贯穿栅绝缘层和有源层的第一过孔； 在所述有源层之上形成包括源极、 漏极以及数据线的源漏金属层， 且同 时在所述第一导线的间断对应处形成第二导线， 并在所述第一过孔内填充用 以形成所述源极、 漏极以及信号线的导电材料以串接所述第一导线和第二导 线。
例如， 所述方法包括：
在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区域所述信 号线的若干间断的第一导线；
在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 对应于所述第一导线的端点处形成贯穿栅绝缘层和有源层的第一过孔； 在所述有源层之上形成包括源极、 漏极以及信号线的源漏金属层， 且同 时至少在所述第一导线的部分间断对应处形成第二导线， 并在所述第一过孔 内填充用以形成所述源极、 漏极以及信号线的导电材料；
在所述源漏金属层之上形成钝化层， 且同时形成第二过孔；
在所述钝化层之上形成包括像素电极的像素电极层， 且同时至少在对应 所述第一导线的间断中未形成有所述第二导线处形成第三导线， 并在所述第 二过孔内填充用以形成所述像素电极的导电材料；
其中， 第一导线、 第二导线以及第三导线通过第一过孔内的导电材料以 及第二过孔内的导电材料串接形成信号线。
例如， 所述方法包括：
在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区域所述信 号线的第一导线；
在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 在所述第一导线的端点处的上方形成贯穿栅绝缘层和有源层的第一过 孔；
在所述有源层之上形成包括源极、 漏极以及数据线的源漏金属层， 且同 时形成第二导线， 并在所述第一过孔内填充用以形成所述源极、 漏极以及数 据线的导电材料以串接所述第一导线和第二导线。
例如， 所述方法包括：
在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区域所述信 号线的第一导线；
在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 在所述有源层之上形成包括源极、 漏极以及信号线的源漏金属层， 且同 时形成第二导线；
在所述源漏金属层之上形成钝化层；
在所述钝化层之上形成包括像素电极的像素电极层， 且同时形成第三导 线；
其中， 所述制作方法还包括形成过孔的步骤； 第一导线、 第二导线以及 第三导线以过孔串接形成信号线。
例如， 所述形成过孔的步骤包括：
形成贯穿所述栅绝缘层及有源层的第一过孔；
在所述钝化层上形成第二过孔；
其中，
所述第一过孔用以连接第一导线和第二导线；
所述第二过孔用以连接第二导线和第三导线。
例如， 所述形成过孔的步骤包括：
形成贯穿所述栅绝缘层及有源层上的第一过孔；
形成贯穿所述栅绝缘层、 有源层、 源漏极层及所述钝化层的第三过孔； 其中，
所述第一过孔用以连接第一导线和第二导线；
所述第三过孔用以连接第一导线和第三导线。
例如， 所述形成过孔的步骤包括：
在所述钝化层上形成第二过孔；
形成贯穿所述栅绝缘层、 有源层、 源漏极层及所述钝化层的第三过孔； 其中，
所述第二过孔用以连接第二导线和第三导线；
所述第三过孔用以连接第一导线和第三导线。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术阵列基板的布线区域的结构示意图；
图 2a为本发明实施例一所述的阵列基板的布线区域的俯视结构示意图； 图 2b为图 2a的部分截面示意图；
图 3 为本发明实施例一所述的阵列基板的一种信号线的俯视结构示意 图；
图 4为图 3 A-A'处的剖视图；
图 5为图 3 B-B'处的剖视图；
图 6 为本发明实施例二所述的阵列基板的一种信号线的俯视结构示意 图；
图 7为本发明实施例三所述的阵列基板制作方法制作的信号线的俯视结 构示意图之一；
图 8为图 7 C-C'处的剖视图；
图 9本发明实施例三所述的阵列基板制作方法制作的信号线的俯视结构 示意图之二。 具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图， 对本发明实施例的技术方案进行清楚、 完整地描述。 显然， 所描述的实施例 是本发明的一部分实施例， 而不是全部的实施例。 基于所描述的本发明的实 施例， 本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实 施例， 都属于本发明保护的范围。
实施例一：
本实施例提供一种阵列基板， 包括设置在非显示区域的多个布线区域， 所述布线区域内设置有若干信号线， 每一所述布线区域内至少部分所述信号 线由位于不同层的导线串接而成； 每一布线区域内任意两根信号线的电阻差 均在阔值范围内。
阵列基板包括位于中间位置处的显示区域（通常也成为 AA区域） 以及 位于显示区域外围的非显示区域。 通常在阵列基板与对向基板组装成显示装 置后， 所述非显示区域由显示装置的边框覆盖住。 在非显示区域内设有多个 布线区域； 每一所述布线区域内均设有若干信号线； 所述信号线可以为栅线 或数据线； 所述信号线位于所述布线区域内的部分用以与驱动电路连接， 即 所述信号线一端与显示区域的栅线或数据线相连， 另一端与驱动电路相连。
阵列基板为分层结构， 包括若干可以导电的导电层； 且例如导电层之间 设有起到绝缘作用的绝缘层。
在现有技术中， 所述信号线组成部分都是位于阵列基板的同一层中。 位 于同一层中的信号线的制作材质一样， 且通常信号线的宽度也相等， 为了使 布线区域的边缘位置的信号线与中间位置处的信号线形成的电阻差在阔值范 围内， 需使信号线间的长度差也应保持在一定范围内。 故布线区域中间的信 号线会进行弯折， 具体的可以参见图 1中信号线 012。
然而， 在本发明实施例中， 如图 2a-图 2b所示布线区域 S-S，内， 包括位 于布线区域 S-S'边缘位置处且由位于阵列基板同一层的导线构成的信号线 111 以及位于布线区域 S-S，中间位置处且由不同层导线串接而成的信号线 112。 例如， 位于所述布线区域 S-S'中间位置处的信号线 112是由第一导线 121以及第二导线 123通过过孔 122串接而成的。 第一导线 121与第二导线 123之间设置有绝缘层 113，根据所述第一导线 121与第二导线 123所在层的 不同， 所述绝缘层的构成不同。 对比图 1和图 2a可知， 图 1 中信号线 012 所在布线区域的宽度 d大于图 2中信号线 112的所占的宽度 D。图 2a中位于 布线区域 S-S，中间位置处的信号线由位于不同层的导线串接而成， 从而在垂 直于阵列基板所在平面的平面内形成了弯折， 在达到延长信号线长度的效果 的同时使信号线在布线区域内的所占宽度变窄了。 因此， 布线区域内可设置 的信号线的数目增多了，可以减少阵列基板上布线区域数目，减少驱动数量， 从而节省了成本。
在本发明实施例中， 同一布线区域内任意两根信号线的电阻差均在阔值 范围内。 所述阔值可以是根据阵列基板的尺寸等因素决定的取值。 例如， 最 大阻值的信号线与最小阻值的信号线之间的阻值比限制在 3: 1的范围内。 可 以通过增加位于不同层的导线的数目， 从而形成的连接点 （即过孔） 的数目 增多了， 延长用于连接的信号线路径， 也可以在不影响布线区域的信号线密 度的情况下， 在不与驱动电路相连的所在层， 将导线进行弯折， 以延长导线 的传输路径， 实现任意两根信号线的电阻差控制在阔值范围内。
在具体的实现过程中， 如将所有的信号线都由位于两层中的导线串接构 成， 使所有信号线其中一层导线的数目、 长度以及宽度都相等； 而在另一层 中， 所有信号线所包含的导线数目相等且导线宽度也相等， 不同的是沿布线 区域内信号线排列的方向， 由中间向布线区域的两侧， 信号线所包含导线的 长度逐步变短。 此外， 还可以将所有的信号线都由多层导线串接而成， 且所 有导线在同一层中所包含的导线的条数相等， 不同的是同一层导线所形成的 传输路径， 在布线区域内由中间向布线区域的两侧逐步缩短， 以达到等电阻 的最终效果。
在具体的实现过程中， 当位于不同层的导线， 位于阵列基板的同一截面 内时， 则同一所述信号线的不同层导线位于同一截面内， 例如如图 2a-图 2b 中的信号线 112所示。 当位于不同层的导线，有其中一层的导线进行了弯折， 同一信号线位于不同层的导线可能位于垂直阵列基板的两个或两个以上截面 内， 例:^口:^图 3所示。
根据显示器的类型不同， 阵列基板的分层结构以及各层之间的位置关系 不同。 例如， 阵列基板包括栅极金属层、 栅绝缘层、 有源层、 源漏金属层、 钝化层以及像素电极层； 栅极金属层用以形成栅线； 所述栅绝缘层设置在所 述栅线金属层上方； 有源层包括半导体层以及掺杂半导体层； 源漏金属层用 于形成薄膜晶体管的源极、 漏极以及数据线； 所述钝化层用以保护位于其以 下的结构。 所述像素电极层用以形成像素电极。 像素电极与薄膜晶体管的漏 极相连。在上述层中的栅极金属层、 源漏金属层、像素电极层都属于导电层； 故上述导电层在形成阵列基板所包含结构的同时， 可以通过构图工艺形成用 于形成信号线的导线。再通过过孔使不同层内的导线连接，从而形成信号线。 在本实施例中所述钝化层、 栅绝缘层以及有源层均可认为位于导电层之间且 ^^到绝缘作用的绝缘层。
至少部分所述导线位于栅极金属层、 源漏金属层、 像素电极层或公共电 极层。 位于所述栅极金属层中的导线与位于源漏金属层的导线之间通过贯穿 栅绝缘层以及有源层上的过孔连接； 位于所述源漏金属层中的导线与位于像 素电极层的导线之间通过设置在钝化层的过孔连接； 位于所述栅极金属层中 的导线与位于像素电极层的导线之间通过贯穿栅绝缘层、 钝化层等中间层的 过孔相连。
例如， 如图 3所示， 所述信号线包括位于像素电极层 120中的导线、 位 于源漏金属层 130中以及位于栅极金属层 110中的导线； 上述导线进行串接 形成一个可导通的信号线。 由于所述的信号线在不同层之间进行弯折串连， 从而导线的长度增加了， 继而电阻增加了， 从而可以通过调整导线的分布和 数目， 来调整各信号线之间的电阻差。 进一步地， 通过增大信号线在不同层 之间的弯折次数， 将布线区域中间位置处信号的线电阻继续增大， 减小布线 区域内中间与周边处信号线间的电阻差异， 最终实现布线区域任意两信号线 的电阻差均在阔值范围之内。
上述结构达到的效果为： 在栅极金属层或源漏金属层中信号线所占的面 积减小了， 从而布线区域内的信号线的密度可以进一步提高， 使得一个驱动 对应的一个信号线区域的所连接的信号线数目增加了， 有利于减少驱动 （如
COF )数量， 节省成本并充分利用了不同层的面积。 进一步地， 上述阵列基 板无需增加额外的构图工艺即可完成， 具有实现简便的优点， 同时有利于非 显示区域的面积的缩小， 有助于窄边框的实现。
进一步地， 通过改变位于不同层中导线的分布、 条数， 所述信号线的结 构至少包括以下两种：
第一种， 形成同一所述信号线的至少一层中包括两条以上间断的导线。 如信号线 A， 包括位于栅极金属层中的两条间断的第一导线以及位于源漏金 属层中对应所述栅极金属层中两条导线间断处的第二导线； 第一导线和第二 导线通过贯穿栅极绝缘层和有源层的过孔进行连接。 所述第二导线作为两条 第一导线的中间连接部分。
第二种： 形成同一所述信号线的每一层都仅包括一条导线， 不同层间的 导线通过过孔串接形成所述信号线。 如信号线 包括位于栅极金属层的第 一导线、 位于源漏金属层中的第二导线以及位于像素电极层中第三导线。 例 如， 沿信号传输的方向， 所述第一导线、 第二导线以及第三导线都可在其所 在层贯穿整个布线区域， 从而在垂直于阵列基板所在的平面内形成空间上的 弯折信号线。
上述两种结构都能艮好的实现缩小信号线电阻差的目的， 且同时减少单 根信号线所占布线区域的宽度， 从而提高布线区域信号线的密度， 减少驱动 数目。
为了进一步的缩小信号线之间的电阻差， 即减少信号线之间的长度差， 可将图 3所示位于不同层的导线进行弯折， 由于信号线在层与层之间进行了 弯折，且同时在其中至少一层导线在平行阵列基板所在的平面内进行了弯折， 从而可以保证布线区域信号线的弯折半径 d小于现有的同型号、 同尺寸阵列 基板中的信号线所占宽度， 从而有利于连接信号线的集中以及驱动数量的减 少。
图 4为图 3在 A-A'处的剖视图，其中 160为钝化层、 150为有源层， 140 为栅绝缘层。 参见图 4， 像素电极层 120的导线通过过孔与位于栅极金属层 110 中的导线进行连接， 且用于连接两者的导电材质为构成像素电极层 120 的导电材质。 图 5为图 3在 B-B， 处的剖视图。
实施例二：
本实施例的阵列基板包括设置在非显示区域的多个布线区域， 所述布线 区域内设置有若干信号线， 每一所述布线区域内至少部分所述信号线由位于 不同层的导线串接而成； 同一布线区域内任意两根信号线的电阻差均在阔值 范围内。 所述不同层的导线按照信号线的延伸方向依次相连。
如图 6所示， 所述阵列基板包括像素电极层、栅线金属层、 源漏金属层。 如图 6中信号线位于阵列基板的非显示区域部分， 包括信号线 210、 信号线 220以及信号线 230。所述信号线 210仅由源漏金属层 310的导线构成、所述 信号线 220由源漏金属层 310的导线、 像素电极层 320的导线以及栅极金属 层 330的导线串接而成； 所述信号线 230由源漏金属层 310的导线、 像素电 极层 320的导线以及栅极金属层 330的导线串接而成； 其中 410为连接位于 源漏金属层 310导线与像素电极层 320的导线的过孔； 420为像素电极层 320 导线与栅极金属层 330导线的连接过孔。为了实现信号线 220以及信号线 230 与信号线 210的电阻差在阔值范围，从而实现不同信号线间的传输时延差小， 而使得信号线 220和信号线 230釆用本实施例阵列基板中所述的信号线， 由 不同层导线串接而成， 从而在三维空间内延长了信号线 220和信号线 230的 长度， 且将原本位于布线区域中心的 230调换到布线区域边缘处， 从而有助 于布线区域等电阻的实现。
在具体的实施过程中， 可以根据需要改变位于不同层中导线的位置， 将 原本应位于布线区域中间位置的信号线与原本位于布线区域边缘的信号线进 行位置的交换， 通过交换可以再次实现信号线之间的电阻差的减小。 如图 6 中所示将位于布线区域中央位置的信号线 230与靠近布线区域边缘的信号线 220通过不同层之间的导线的设置进行了位置的交换， 达到了延长 230长度 的目的， 同时随着 230移动到布线区域外侧， 其他位于布线区域的信号线如 220等有更大的空间来实现水平弯折，从而有利于整体布线区域电阻的相等。
在具体的实现过程中， 阵列基板上还包括的公共电极层。如 IPS:In-Plane Switching平面转换液晶面板， 公共电极以及像素电极均位于阵列基板上。 另 夕卜， 在如 ADS边缘电场显示面板， 公共电极与像素电极均位于阵列基板上， 但是位于阵列基板的不同层， 且两者之间设有绝缘层。 形成公共电极的材质 同样的是导电材质， 故可以仅通过改变掩膜板， 在包括有公共电极的公共电 极层中形成导线， 再在不同层导线之间进行串接， 形成信号线。
在具体的实施过程中，所述信号线可以是仅由位于两层的导线串接而成， 也可以是两层以上的导线串接连接而成。
进一步的， 所述信号线包括栅线和数据线； 输出端与阵列基板中薄膜晶 体管的栅极相连的为栅线， 用以栅极信号传输； 输出端与阵列基板中薄膜晶 体管的漏极相连的为数据线， 用以向像素电极输入相应的信号。 栅线与栅极 驱动连接， 用以输入栅极扫描信号， 从而开启或关闭相应的薄膜晶体管。 所 述数据线与数据线驱动连接， 用以向像素电极输入电压， 用于液晶显示器时 向像素电极提供液晶分子的偏转电压。 各信号线的电阻不同将导致其所传输 信号的时延不同， 若时延差过大将导致显示不良， 故可以通过调整信号线的 长度、 形成的导电材质以及各种导线连接， 来进行电阻差的调整。 在本实施 例中进一步的规定了， 所述信号线间的电阻差小于阔值。 所述阔值可以根据 需要进行设置， 在具体的实现过程中， 信号线之间的电阻比值维持在 3:1 的 范围内， 对显示不造成不良影响或不良影响轻微， 同时这对制作工艺的要求 也较低， 容易实现。
在具体的实施过程中， 所述信号线可以在阵列基板的任意一个导电层与 驱动电路进行连接， 例如由栅极金属层的导线以及源漏金属层的导线与驱动 电路进行连接。
本实施例所述阵列基板至少有部分信号线在阵列基板的多个层之间实现 三维空间上的弯折， 由位于不同层中的导线相互串接形成电阻满足需要的信 号线， 同时不会导致信号线所占面积过宽的问题， 避免了不利于非显示区域 窄边框形成的问题。
实施例三：
本实施例提供一种阵列基板的制作方法， 所述制作方法包括：
形成位于非显示区域且与栅线或数据线相连的信号线， 所述信号线由位 于不同层的导线串接而形成； 其中， 所述信号线位于所述阵列基板的非显示 区域的布线区域内； 且同一布线区域内任意两根信号线的电阻差均在阔值范 围内。
例如， 位于不同层的导线形成信号线至少包括以下两种结构：
第一种， 在阵列基板中用于形成导线的至少一个导电层中， 形成有若干 条导线， 再由位于不同层的导线将该若干条导线串接起来。
第二种， 在阵列基板用于形成导线的导电层中， 对应一个信号线形成一 条导线， 再将位于不同层的导线串接起来。
针对第一种结构可以釆用以下提供几种具体的实施方式：
方式一： 当所述信号线仅由两层中的导线串接而成； 且每一层中至少包 括两条导线时， 所述制作方法具体包括：
步骤 1 : 在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区 域所述信号线的若干间断的第一导线；
步骤 2:在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 步骤 3: 对应于所述第一导线的端点处形成贯穿栅绝缘层和有源层的第 一过孔；
步骤 4: 在所述有源层之上形成包括源极、 漏极以及数据线的源漏金属 层， 且同时在所述第一导线的间断处对应形成第二导线， 并在所述第一过孔 内填充用以形成所述源极、 漏极以及信号线的导电材料以串接所述第一导线 和第二导线。
本方式制作的阵列基板中的至少部分信号线是由栅极金属层中导线与源 漏金属层的导线串接而成的，串接时釆用的是贯穿栅绝缘层和有源层的过孔。
如图 7所示， 所述信号线包括位于栅极金属层 530的第一导线以及位于 源漏金属层 520的第二导线。 第一导线与第二导线通过过孔进行连接。 图 8 为图 7在 C-C，处的剖视图。 从图 8可知， 在本实施例中所述阵列基板包括栅 极金属层 530、栅绝缘层 560、有源层 550、 源漏金属层 520以及钝化层 540。 图 7中栅线金属层 530与源漏金属层 520形成连接时， 增加了一次形成过孔 的步骤， 釆用这种方式进行连接可以有效的保证连接的可靠性， 并减小连接 点接触电阻。
在具体的实现过程中， 构成信号线的导线还可以是位于其他层， 如像素 电极层中， 公共电极层。 第一导线是与栅线一同形成的， 具体的只需改变掩 膜板即可， 不会增加额外的步骤， 从而实现简便。 同样形成原理也适用于形 成第二导线， 且第一导线与第二导线的连接也在形成第二导线时同步形成， 从而实现简便。 形成的信号线不局限在阵列基板的同一层中， 而是形成于多 层中， 由原来的平面内的弯折的信号线转换成本发明实施例所述的空间内弯 折的信号线， 可以减少单个信号线在阵列基板一层内所占的面积， 从而有利 于提高连接布线区域内的信号线密度， 从而在布线区域面积不变的情况下， 一个驱动电路的可连接的信号线的数目增加， 从而减小驱动的数目， 从而有 利于降低成本。
方式二， 用于包括由阵列基板中三层中的导线串接而成的信号线的阵列 基板； 且每一层中包括了至少两条形成同一信号线的导线。 所述制作方法具 体包括：
步骤 1 : 在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区 域所述信号线的若干间断的第一导线；
步骤 2:在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 步骤 3 : 对应于所述第一导线的端点处形成贯穿栅绝缘层和有源层的第 一过孔；
步骤 4: 在所述有源层之上形成包括源极、 漏极以及信号线的源漏金属 层， 且同时至少在所述第一导线的部分间断对应处形成第二导线， 并在所述 第一过孔内填充用以形成所述源极、 漏极以及信号线的导电材料；
步骤 5: 在所述源漏金属层之上形成钝化层， 且同时形成第二过孔； 步骤 6: 在所述钝化层之上形成包括像素电极的像素电极层， 且同时至 少在所述第一导线的间断中未形成有所述第二导线处形成第三导线， 并在所 述第二过孔内填充用以形成所述像素电极的导电材料。 其中， 第一导线、 第二导线以及第三导线通过第一过孔内的导电材料以 及第二过孔内的导电材料串接形成信号线。
上述实施方法， 是实现了阵列基板中信号线由位于三层中的导线构成， 形成后的信号线可以参照图 4或图 5所示。
图 4或图 5中利用 ITO连通的方式，在现有工艺流程中就可以简便实现， 工艺简单且可靠性高。
方式三： 所述制作方法用于形成阵列基板， 所述阵列基板包括由四层中 的导线串接而成的信号线； 且设有导线的导电层中， 每一层均包括了至少两 条形成同一信号线的导线。 在具体的实施过程中， 有些阵列基板的制作方法 还包括形成公共电极的步骤， 如 ADS——边缘电场模式的阵列基板。 ADS 模式的阵列基板包括了像素电极和公共电极； 且像素电极和公共电极位于不 同的层， 且通常都是釆用 ITO形成的。
如图 9所示， 所述制作方法具体包括：
形成包括栅极的栅极金属层 620的步骤， 且同时形成用以形成信号线的 导线；
釆用第一次图案化 ITO的工艺形成包括用以形成边缘电场的透明电极的 第一 ITO层 610， 且同步形成位于第一 ITO层 610中的导线。 所述第一次图 案化 ITO的工艺用以形成像素电极或公共电极。若第一次图案化 ITO的工艺 用以形成像素电极， 则第二次图案化 ITO的工艺用以形成公共电极。 若第一 次图案化 ITO的工艺用以形成公共电极，则第二次图案化 ITO的工艺用以形 成像素电极。
形成源漏金属层 640， 且同步形成位于源漏金属层 640中的导线； 釆用第二次图案化 ITO的工艺形成包括用以形成边缘电场的透明电极的 第二 ITO层 630， 且同步通过构图工艺形成位于第二 ITO层 630中的导线； 若两由导电材料构成的导电层之间设有绝缘层， 则形成绝缘层时同步形 成连接两导电层内两导线的过孔， 以过孔内的导电材质实现导线间的连接。
上述实施方式中，基板中的信号线由位于四个不同层中的导线连接而成。 在上述实施方式中， 所述的构图工艺为包括沉积、 涂布、 曝光、 显影、 刻蚀等一个或多个制作工艺。
针对第二种结构可以釆用以下提供的几种具体的实施方式： 方式一：本方式用于形成包括由两层导线串接而成的信号线的阵列基板； 且用于形成同一信号线的一层中只包括一条导线。
步骤 1 : 在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区 域所述信号线的第一导线；
步骤 2:在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 步骤 3: 在所述第一导线的端点处的上方形成贯穿栅绝缘层和有源层的 第一过孔；
步骤 4: 在所述有源层之上形成包括源极、 漏极以及数据线的源漏金属 层， 且同时形成第二导线， 并在所述第一过孔内填充用以形成所述源极、 漏 极以及数据线的导电材料以串接所述第一导线和第二导线。
在具体的实施过程中， 还可以改变第一导线或第二导线所在的导电层。 方式二：本方式制作的阵列基板中的部分信号线是由三层导线串接而成； 且用于形成同一信号线的每一层中只包括一条导线。所述制作方法具体包括： 步骤 1 : 在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区 域所述信号线的第一导线；
步骤 2:在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 步骤 3: 在所述有源层之上形成包括源极、 漏极以及信号线的源漏金属 层， 且同时形成第二导线；
步骤 4: 在所述源漏金属层之上形成钝化层；
步骤 5: 在所述钝化层之上形成包括像素电极的像素电极层， 且同时形 成第三导线。
所述阵列基板的制作方法还包括形成过孔的步骤包括：
步骤 A: 形成贯穿所述栅绝缘层及有源层的第一过孔； 在具体的实现过 程中， 所述步骤 A位于步骤 2和步骤 3之间；
步骤 B:在所述钝化层上形成第二过孔； 所述步骤 B位于步骤 4和步骤 5 之间；
其中， 所述第一过孔用以连接第一导线和第二导线； 所述第二过孔用以 连接第二导线和第三导线。
在本实施例所述阵列基板的实现方法中， 阵列基板的第一导线仅和第二 导线连接； 第三导线仅和第二导线连接， 第二导线作为连接第一导线和第二 导线形成信号线的桥接部分。
方式三：本方式制作的阵列基板中的部分信号线是由三层导线串接而成； 且用于形成同一信号线的每一层中只包括一条导线。所述制作方法具体包括: 步骤 1 : 在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区 域所述信号线的第一导线；
步骤 2:在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 步骤 3: 在所述有源层之上形成包括源极、 漏极以及信号线的源漏金属 层， 且同时形成第二导线；
步骤 4: 在所述源漏金属层之上形成钝化层；
步骤 5: 在所述钝化层之上形成包括像素电极的像素电极层， 且同时形 成第三导线。
所述制作方法还包括形成过孔的步骤， 具体包括：
步骤 A:形成贯穿所述栅绝缘层及有源层上的第一过孔；步骤 A位于步骤 2和步骤 3之间；
步骤 B:形成贯穿所述栅绝缘层、 有源层及所述钝化层上的第三过孔； 步 骤 B位于步骤 4和步骤 5之间；
其中，
所述第一过孔用以连接第一导线和第二导线；
所述第三过孔用以连接第一导线和第三导线。
在本实施例所述阵列基板的实现方法中， 阵列基板的第一导线仅和第二 导线连接； 第三导线仅和第一导线连接， 第一导线作为连接第三导线和第二 导线形成信号线的桥接部分。
方式四：本方式制作的阵列基板中的部分信号线是由三层导线串接而成； 且用于形成同一信号线的每一层中只包括一条导线。所述制作方法具体包括: 步骤 1 : 在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区 域所述信号线的第一导线；
步骤 2:在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 步骤 3: 在所述有源层之上形成包括源极、 漏极以及信号线的源漏金属 层， 且同时形成第二导线；
步骤 4: 在所述源漏金属层之上形成钝化层； 步骤 5: 在所述钝化层之上形成包括像素电极的像素电极层， 且同时形 成第三导线。
所述制作方法还包括形成过孔的步骤： 所述形成过孔的步骤具体包括： 步骤 A:在所述钝化层上形成第二过孔；
步骤 B:形成贯穿所述栅绝缘层、 有源层及所述钝化层上的第三过孔； 其中，
所述第二过孔用以连接第二导线和第三导线；
所述第三过孔用以连接第一导线和第三导线。 在本实施例所述的形成过 孔的步骤， 可以将所述第一过孔以及第二过孔釆用同一次构图工艺形成。 所 述形成过孔的步骤位于步骤 4和步骤 5之间。
在本实施例所述阵列基板的实现方法中， 阵列基板的第一导线仅和第三 导线连接； 第二导线仅和第三导线连接， 第三导线作为连接第一导线和第二 导线形成信号线的桥接部分。
本实施例所述阵列基板的制作方法， 制作出的阵列基板均可认为为本发 明所述的阵列基板。
本实施例所述的阵列基板的制作方法，用于制作本发明所述的阵列基板， 制作工艺改进少， 仅需改变掩膜板的结构就完成导线的制作以及导线间的连 接， 从而具有实现简便的优点， 且釆用本发明所述的阵列基板的制作方法形 成的阵列基板具有信号线的弯折半径小， 信号线集中的密度大， 有利于驱动 数据的减少以节省耗材和制作成本的优点。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。 相关申请的交叉引用
本申请要求于 2013年 9月 17曰递交的第 201310425475.0号中国专利申 请的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种阵列基板， 包括设置在非显示区域的多个布线区域， 所述布线区 域内设置有若干信号线， 其中每一所述布线区域内至少部分所述信号线由位 于不同层的导线串接而成； 同一布线区域内任意两根信号线的电阻差均在阔 值范围内。
2、根据权利要求 1所述的阵列基板， 其中所述导线位于栅极金属层、 源 漏金属层、 像素电极层或公共电极层。
3、根据权利要求 2所述的阵列基板，其中所述栅极金属层、源漏金属层、 像素电极层以及公共电极层中任意两层之间均设有绝缘层； 位于不同层的导 线通过设置在所述绝缘层上的过孔进行串接。
4、 根据权利要求 1、 2或 3所述的阵列基板， 其中同一所述信号线的不 同层导线均位于同一截面内；
所述截面垂直于所述阵列基板所在的平面。
5、根据权利要求 1所述的阵列基板，其中所述信号线一端与显示区域的 数据线或栅线相连接， 另一端与驱动电路连接。
6、 根据权利要求 1、 2或 3所述的阵列基板， 其中形成同一所述信号线 的至少一层中包括两条以上间断的导线， 由不同层的导线将该两条以上间断 的导线串接形成所述信号线。
7、 根据权利要求 1、 2或 3所述的阵列基板， 其中形成同一所述信号线 的每一层都仅包括一条导线，不同层间的导线通过过孔串接形成所述信号线。
8、一种阵列基板的制作方法， 包括形成位于非显示区域且与栅线或数据 线相连的信号线的步骤， 所述信号线由位于不同层的导线串接而形成；
其中所述信号线位于所述阵列基板的非显示区域的布线区域内； 且同一 布线区域内任意两根信号线的电阻差均在阔值范围内。
9、 根据权利要求 8所述的阵列基板的制作方法， 包括：
在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区域所述信 号线的若干间断的第一导线；
在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 对应于所述第一导线的端点处形成贯穿栅绝缘层和有源层的第一过孔； 在所述有源层之上形成包括源极、 漏极以及数据线的源漏金属层， 且同 时在所述第一导线的间断对应处形成第二导线， 并在所述第一过孔内填充用 以形成所述源极、 漏极以及信号线的导电材料以串接所述第一导线和第二导 线。
10、 根据权利要求 8所述的阵列基板的制作方法， 包括：
在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区域所述信 号线的若干间断的第一导线；
在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 对应于所述第一导线的端点处形成贯穿栅绝缘层和有源层的第一过孔； 在所述有源层之上形成包括源极、 漏极以及信号线的源漏金属层， 且同 时至少在所述第一导线的部分间断对应处形成第二导线， 并在所述第一过孔 内填充用以形成所述源极、 漏极以及信号线的导电材料；
在所述源漏金属层之上形成钝化层， 且同时形成第二过孔；
在所述钝化层之上形成包括像素电极的像素电极层， 且同时至少在对应 所述第一导线的间断中未形成有所述第二导线处形成第三导线， 并在所述第 二过孔内填充用以形成所述像素电极的导电材料；
其中， 第一导线、 第二导线以及第三导线通过第一过孔内的导电材料以 及第二过孔内的导电材料串接形成信号线。
11、 根据权利要求 8所述的阵列基板的制作方法， 包括：
在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区域所述信 号线的第一导线；
在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 在所述第一导线的端点处的上方形成贯穿栅绝缘层和有源层的第一过 孔；
在所述有源层之上形成包括源极、 漏极以及数据线的源漏金属层， 且同 时形成第二导线， 并在所述第一过孔内填充用以形成所述源极、 漏极以及数 据线的导电材料以串接所述第一导线和第二导线。
12、 根据权利要求 8所述的阵列基板的制作方法， 包括：
在显示区域形成包括栅线的栅极金属层， 且同步形成非显示区域所述信 号线的第一导线； 在所述栅极金属层上和所述第一导线上形成栅绝缘层及有源层； 在所述有源层之上形成包括源极、 漏极以及信号线的源漏金属层， 且同 时形成第二导线；
在所述源漏金属层之上形成钝化层；
在所述钝化层之上形成包括像素电极的像素电极层， 且同时形成第三导 线；
其中， 所述制作方法还包括形成过孔的步骤； 第一导线、 第二导线以及 第三导线以过孔串接形成信号线。
13、根据权利要求 12所述的阵列基板的制作方法，其中所述形成过孔的 步骤包括：
形成贯穿所述栅绝缘层及有源层的第一过孔；
在所述钝化层上形成第二过孔；
其中，
所述第一过孔用以连接第一导线和第二导线；
所述第二过孔用以连接第二导线和第三导线。
14、根据权利要求 12所述的阵列基板的制作方法，其中所述形成过孔的 步骤包括：
形成贯穿所述栅绝缘层及有源层的第一过孔；
形成贯穿所述栅绝缘层、 有源层、 源漏极层及所述钝化层的第三过孔； 其中，
所述第一过孔用以连接第一导线和第二导线；
所述第三过孔用以连接第一导线和第三导线。
15、根据权利要求 12所述的阵列基板的制作方法，其中所述形成过孔的 步骤包括：
在所述钝化层上形成第二过孔；
形成贯穿所述栅绝缘层、 有源层、 源漏极层及所述钝化层的第三过孔； 其中，
所述第二过孔用以连接第二导线和第三导线；
所述第三过孔用以连接第一导线和第三导线。
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