WO2015039492A1 - 阵列基板及其制作方法 - Google Patents
阵列基板及其制作方法 Download PDFInfo
- Publication number
- WO2015039492A1 WO2015039492A1 PCT/CN2014/082558 CN2014082558W WO2015039492A1 WO 2015039492 A1 WO2015039492 A1 WO 2015039492A1 CN 2014082558 W CN2014082558 W CN 2014082558W WO 2015039492 A1 WO2015039492 A1 WO 2015039492A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- conductor
- signal line
- array substrate
- forming
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 106
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 claims description 105
- 239000004020 conductor Substances 0.000 claims description 61
- 238000002161 passivation Methods 0.000 claims description 35
- 230000000149 penetrating effect Effects 0.000 claims description 20
- 238000009413 insulation Methods 0.000 claims 6
- 230000002411 adverse Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 57
- 238000000059 patterning Methods 0.000 description 12
- 239000010409 thin film Substances 0.000 description 11
- 238000005452 bending Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000001934 delay Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Definitions
- Embodiments of the present invention relate to an array substrate and a method of fabricating the same. Background technique
- the array substrate is provided with a structure of a gate line, a data line, a thin film transistor, a pixel electrode, etc.; the above structure is formed of a conductive material of a different layer.
- the array substrate has a layered structure and includes a gate metal layer forming a gate electrode, a source/drain metal layer forming a source and a drain of the thin film transistor, a pixel electrode layer forming a pixel electrode, and the like.
- Some array substrates further include a common electrode layer forming a common electrode.
- the gate line is connected to the gate of the thin film transistor; the data line is connected to the source of the thin film transistor; the gate line is used to turn on the thin film transistor, and the data line is used to input a voltage signal to the pixel electrode through the thin film transistor.
- the gate lines and data lines may be collectively referred to as signal lines.
- a wiring area (or a sector) is disposed in the non-display area of the edge of the array substrate to realize connection of the signal line and the driving circuit; each of the signal lines includes a portion distributed in the display area of the array substrate and distributed in the array The non-display area portion of the substrate; generally, a plurality of signal lines are concentrated in the wiring area.
- the signal line will cause the path of the signal line to travel differently.
- the path through which the signal line travels is different.
- the length of the formed signal line is poor, which causes the signal line to form a resistance difference. Therefore, the length of the signal line affects the length of the path of the electrical signal transmission, and the length of the conductive path is different, resulting in a difference in resistance and capacitance, which eventually causes different delays in the signal transmission process, thereby forming a display defect.
- the existing method forms a conductive path by a signal line in a wiring area in a fold line manner, thereby extending the length thereof to form a length similar to that of other signal lines, thereby ensuring resistance between the signal line and the signal line.
- the difference is within a predetermined range, thereby ensuring that the delays of the transmission lines of the respective signal lines are uniform.
- the area enclosed by the broken line in the figure is the wiring area, that is, the wiring area SS, and the wiring area SS is provided with the signal line 011 near the wiring area SS, the edge, and the signal located in the middle of the wiring area S-S'. Line 012.
- the signal line 012 is formed in a zigzag line, but the formation of the fold line causes the width of the wiring area occupied by the signal line 012 to be widened, as shown in FIG.
- the width of the signal line 012 is d, so that the number of signal lines that can be accommodated in the wiring area of the same area is reduced, which leads to an increase in the number of driving (COF, etc.), and an increase in the number of driving forces necessarily leads to an increase in the driving IC, which ultimately leads to an increase in cost.
- an array substrate including a plurality of wiring regions disposed in a non-display region, wherein a plurality of signal lines are disposed in the wiring region, and at least a portion of the signal lines in each of the wiring regions are The wires in different layers are connected in series; the resistance difference of any two signal lines in the same wiring area is within a wide range.
- the wires are located in a gate metal layer, a source/drain metal layer, a pixel electrode layer, or a common electrode layer.
- an insulating layer is disposed between any two of the gate metal layer, the source/drain metal layer, the pixel electrode layer, and the common electrode layer; and the wires located in different layers are through via holes provided on the insulating layer. Concatenation.
- different layers of wires of the same signal line are all in the same cross section; the cross section is perpendicular to the plane in which the array substrate is located.
- one end of the signal line is connected to the data line or the gate line of the display area, and the other end is connected to the driving circuit.
- At least one layer forming the same signal line includes two or more intermittent wires, and the two or more intermittent wires are serially connected by the wires of different layers to form the signal line.
- each layer forming the same signal line includes only one wire, and wires between different layers are connected in series through via holes to form the signal line.
- a method of fabricating an array substrate comprising the steps of forming a signal line in a non-display area and connected to a gate line or a data line, wherein the signal line is formed by connecting wires in different layers in series
- the signal line is located in a wiring area of the non-display area of the array substrate; and the resistance difference of any two signal lines in the same wiring area is within a wide range.
- the method includes:
- a gate metal layer including a gate line in the display region, and simultaneously forming a plurality of intermittent first wires of the signal line in the non-display area;
- the method includes:
- a gate metal layer including a gate line in the display region, and simultaneously forming a plurality of intermittent first wires of the signal line in the non-display area;
- a pixel electrode layer including a pixel electrode over the passivation layer Forming a pixel electrode layer including a pixel electrode over the passivation layer, and simultaneously forming a third wire at least at a portion where the second wire is not formed in a discontinuity corresponding to the first wire, and in the second Filling a via hole with a conductive material for forming the pixel electrode;
- the first wire, the second wire and the third wire form a signal line through the conductive material in the first via hole and the conductive material in the second via hole in series.
- the method includes:
- a gate metal layer including a gate line in the display region, and simultaneously forming a first wire of the signal line in the non-display region;
- a source/drain metal layer including a source, a drain, and a data line over the active layer, and simultaneously forming a second wire, and filling the first via hole to form the source and drain And a conductive material of the data line and the data line to connect the first wire and the second wire in series.
- the method includes:
- a gate metal layer including a gate line in the display region, and simultaneously forming a non-display area The first wire of the line;
- the manufacturing method further includes the step of forming a via hole; the first wire, the second wire, and the third wire are connected in series by a via to form a signal line.
- the step of forming a via hole includes:
- the first via is used to connect the first wire and the second wire
- the second via is used to connect the second wire and the third wire.
- the step of forming a via hole includes:
- the first via is used to connect the first wire and the second wire
- the third via is used to connect the first wire and the third wire.
- the step of forming a via hole includes:
- the second via is used to connect the second wire and the third wire
- the third via is used to connect the first wire and the third wire.
- FIG. 1 is a schematic structural view of a wiring area of a prior art array substrate
- FIG. 2a is a schematic top plan view of a wiring area of an array substrate according to Embodiment 1 of the present invention
- FIG. 2b is a partial cross-sectional view of FIG. 2a;
- FIG. 3 is a schematic plan view showing a signal line of an array substrate according to Embodiment 1 of the present invention.
- Figure 4 is a cross-sectional view taken along line A-A' of Figure 3;
- Figure 5 is a cross-sectional view taken along line B-B' of Figure 3;
- FIG. 6 is a schematic plan view showing a signal line of an array substrate according to Embodiment 2 of the present invention.
- FIG. 7 is a schematic top plan view of a signal line formed by the method for fabricating an array substrate according to Embodiment 3 of the present invention.
- Figure 8 is a cross-sectional view taken along line C-C' of Figure 7;
- FIG. 9 is a second schematic structural view of a signal line fabricated by the method for fabricating an array substrate according to Embodiment 3 of the present invention. detailed description
- Embodiment 1 is a diagrammatic representation of Embodiment 1:
- the embodiment provides an array substrate, including a plurality of wiring regions disposed in a non-display area, wherein the wiring area is provided with a plurality of signal lines, and at least part of the signal lines in each of the wiring areas are located at different layers.
- the wires are connected in series; the resistance difference of any two signal lines in each wiring area is within a wide range.
- the array substrate includes a display area (also commonly referred to as an AA area) at an intermediate position and a non-display area located at the periphery of the display area. Usually assembled into an array on the array substrate and the opposite substrate After that, the non-display area is covered by the frame of the display device. a plurality of wiring areas are disposed in the non-display area; each of the wiring areas is provided with a plurality of signal lines; the signal lines may be gate lines or data lines; and the signal lines are located in the wiring area It is connected to the driving circuit, that is, one end of the signal line is connected to the gate line or the data line of the display area, and the other end is connected to the driving circuit.
- a display area also commonly referred to as an AA area
- non-display area located at the periphery of the display area.
- the non-display area is covered by the frame of the display device.
- a plurality of wiring areas are disposed in the non-display area; each of the wiring areas is
- the array substrate is a layered structure comprising a plurality of electrically conductive layers; and for example, an insulating layer for insulating is provided between the conductive layers.
- the signal line components are all located in the same layer of the array substrate.
- the signal lines located in the same layer are made of the same material, and usually the widths of the signal lines are also equal.
- the length difference between the signal lines should also be kept within a certain range. Therefore, the signal line in the middle of the wiring area will be bent. For details, see signal line 012 in Figure 1.
- the wiring area SS includes a signal line 111 which is located at the edge of the wiring area S-S' and is composed of wires located in the same layer of the array substrate, and is located.
- the wiring area SS is a signal line 112 at an intermediate position and which is formed by connecting different layers of wires in series.
- the signal line 112 located at the intermediate position of the wiring area S-S' is formed by the first wire 121 and the second wire 123 being connected in series through the via 122.
- An insulating layer 113 is disposed between the first wire 121 and the second wire 123, and the structure of the insulating layer is different according to the layer of the first wire 121 and the second wire 123.
- the width d of the wiring area where the signal line 012 is located in Fig. 1 is larger than the width D of the signal line 112 in Fig. 2.
- the signal line at the intermediate position of the wiring area SS is formed by connecting wires of different layers in series, thereby forming a bend in a plane perpendicular to the plane of the array substrate, and achieving the effect of lengthening the length of the signal line.
- the width of the signal line in the wiring area is narrowed. Therefore, the number of signal lines that can be set in the wiring area is increased, the number of wiring areas on the array substrate can be reduced, and the number of driving can be reduced, thereby saving cost.
- the resistance difference of any two signal lines in the same wiring area is within a wide range.
- the threshold may be a value determined according to factors such as the size of the array substrate. For example, the resistance ratio between the signal line of the maximum resistance and the signal line of the minimum resistance is limited to a range of 3:1.
- the number of connection points ie, via holes
- Bend the wire to extend the wire at the layer where it is not connected to the drive circuit The transmission path realizes that the resistance difference of any two signal lines is controlled within a wide range.
- the number, length and width of one of the wires of all the signal lines are equal; and in the other layer, all The number of wires included in the signal line is equal and the width of the wires is also equal.
- the difference is that the direction of the signal lines in the wiring area is aligned, and the length of the wires included in the signal lines is gradually shortened from the sides of the intermediate wiring area.
- all the signal lines can be serially connected by multiple layers of wires, and all the wires have the same number of wires in the same layer, the difference is the transmission path formed by the same layer of wires, in the wiring area
- the inner side is gradually shortened from both sides of the wiring area to achieve the final effect of the equal resistance.
- the different layer wires of the same signal line are located in the same cross section, for example, the signal line 112 in FIG. 2a-2b. Shown.
- the wires of one layer are bent, and the wires of the same signal line in different layers may be located in two or more sections of the vertical array substrate, for example: ⁇ : ⁇ Figure 3 Show.
- the array substrate includes a gate metal layer, a gate insulating layer, an active layer, a source/drain metal layer, a passivation layer, and a pixel electrode layer; a gate metal layer for forming a gate line; the gate insulating layer is disposed at the Above the gate line metal layer; the active layer includes a semiconductor layer and a doped semiconductor layer; the source and drain metal layers are used to form a source, a drain, and a data line of the thin film transistor; and the passivation layer is used to protect the structure below .
- the pixel electrode layer is used to form a pixel electrode.
- the pixel electrode is connected to the drain of the thin film transistor.
- the gate metal layer, the source/drain metal layer, and the pixel electrode layer in the above layer all belong to the conductive layer; therefore, the conductive layer can form a wire for forming a signal line by a patterning process while forming a structure included in the array substrate.
- the wires in the different layers are connected through via holes to form signal lines.
- the passivation layer, the gate insulating layer, and the active layer may be considered to be between the conductive layers and to the insulating layer.
- At least a portion of the wires are located in a gate metal layer, a source/drain metal layer, a pixel electrode layer, or a common electrode layer.
- a wire located in the gate metal layer and a wire located in the source/drain metal layer are connected through a through-gate insulating layer and a via hole on the active layer; a wire located in the source-drain metal layer and a pixel electrode layer
- the wires are connected by via holes provided in the passivation layer; the wires located in the gate metal layer and the wires located in the pixel electrode layer pass through an intermediate layer penetrating the gate insulating layer, the passivation layer or the like Vias are connected.
- the signal line includes a wire located in the pixel electrode layer 120, a wire located in the source/drain metal layer 130, and located in the gate metal layer 110; the wires are connected in series to form a conductive Signal line. Since the signal lines are bent and connected in different layers, the length of the wires is increased, and then the resistance is increased, so that the resistance difference between the signal lines can be adjusted by adjusting the distribution and the number of the wires. Further, by increasing the number of times the signal line is bent between different layers, the line resistance of the signal at the intermediate position of the wiring area is continuously increased, and the difference in resistance between the signal lines at the middle and the periphery in the wiring area is reduced, and finally realized. The difference in resistance between any two signal lines in the wiring area is within the wide range.
- the effect achieved by the above structure is: the area occupied by the signal lines in the gate metal layer or the source/drain metal layer is reduced, so that the density of the signal lines in the wiring area can be further increased, so that one signal line region corresponding to one drive is driven.
- the number of connected signal lines has increased, which is beneficial to reduce the drive (such as
- the above array substrate can be completed without adding an additional patterning process, and has the advantages of simple implementation, and is advantageous for reducing the area of the non-display area, and contributing to the realization of the narrow frame.
- the structure of the signal lines includes at least the following two types:
- At least one layer forming the same signal line includes more than two intermittent wires.
- the signal line A includes two intermittent first wires located in the gate metal layer and a second wire located in the source/drain metal layer corresponding to the discontinuity of the two wires in the gate metal layer; the first wire and the first wire
- the two wires are connected by via holes penetrating the gate insulating layer and the active layer.
- the second wire serves as an intermediate connection portion of the two first wires.
- Each layer forming the same signal line includes only one wire, and wires of different layers are connected in series through via holes to form the signal line.
- the signal line includes a first wire located in the gate metal layer, a second wire located in the source/drain metal layer, and a third wire located in the pixel electrode layer.
- the first wire, the second wire, and the third wire may penetrate the entire wiring area at a layer where they are located, thereby forming a spatially bent signal line in a plane perpendicular to the array substrate. .
- Both of the above structures can achieve the purpose of reducing the signal line resistance difference, and at the same time reduce the width of the wiring area occupied by the single signal line, thereby increasing the density of the signal line in the wiring area and reducing the driving. Number.
- the wires in different layers shown in FIG. 3 can be bent, because the signal lines are bent between layers.
- at least one of the wires is bent in a plane in which the parallel array substrate is located, thereby ensuring that the bending radius d of the signal line of the wiring area is smaller than that of the existing signal lines in the same type and same size array substrate. It occupies the width, thereby facilitating the concentration of the connected signal lines and the reduction in the number of driving.
- FIG. 4 is a cross-sectional view of FIG. 3 at AA' where 160 is a passivation layer, 150 is an active layer, and 140 is a gate insulating layer.
- the wires of the pixel electrode layer 120 are connected to the wires located in the gate metal layer 110 through the via holes, and the conductive material for connecting the two is a conductive material constituting the pixel electrode layer 120.
- Figure 5 is a cross-sectional view of Figure 3 at B-B.
- Embodiment 2 is a diagrammatic representation of Embodiment 1:
- the array substrate of this embodiment includes a plurality of wiring regions disposed in the non-display area, wherein the wiring area is provided with a plurality of signal lines, and at least part of the signal lines in each of the wiring areas are connected by wires located in different layers.
- the resistance difference of any two signal lines in the same wiring area is within a wide range.
- the wires of the different layers are sequentially connected in accordance with the extending direction of the signal lines.
- the array substrate includes a pixel electrode layer, a gate line metal layer, and a source/drain metal layer.
- the signal line in FIG. 6 is located in a non-display area portion of the array substrate, and includes a signal line 210, a signal line 220, and a signal line 230.
- the signal line 210 is composed only of the wires of the source/drain metal layer 310, and the signal line 220 is formed by connecting the wires of the source/drain metal layer 310, the wires of the pixel electrode layer 320, and the wires of the gate metal layer 330.
- the signal line 230 is formed by connecting the wires of the source/drain metal layer 310, the wires of the pixel electrode layer 320, and the wires of the gate metal layer 330; wherein 410 is a wire connecting the wires of the source/drain metal layer 310 and the pixel electrode layer 320. Via 420 is a connection via of the pixel electrode layer 320 wire and the gate metal layer 330 wire.
- the signal line 220 and the signal line 230 are used in the array substrate of the embodiment.
- the signal line described in the above is formed by connecting different layers of wires in series, thereby lengthening the lengths of the signal lines 220 and the signal lines 230 in a three-dimensional space, and swapping 230 originally located at the center of the wiring area to the edge of the wiring area, thereby It contributes to the realization of resistance such as wiring area.
- the position of the wires located in different layers can be changed as needed,
- the signal line which should originally be located in the middle of the wiring area is exchanged with the signal line originally located at the edge of the wiring area, and the resistance difference between the signal lines can be again reduced by the exchange.
- the signal line 230 located at the center of the wiring area and the signal line 220 near the edge of the wiring area are exchanged by the arrangement of the wires between the different layers, thereby achieving the purpose of extending the length of 230, while The 230 moves to the outside of the wiring area, and other signal lines located in the wiring area, such as 220, have more space to achieve horizontal bending, thereby facilitating the equal resistance of the overall wiring area.
- a common electrode layer is further included on the array substrate.
- the IPS In-Plane Switching plane conversion liquid crystal panel
- the common electrode and the pixel electrode are all located on the array substrate.
- the common electrode and the pixel electrode are both located on the array substrate, but are located in different layers of the array substrate with an insulating layer therebetween.
- the material for forming the common electrode is also a conductive material, so that the wiring can be formed in the common electrode layer including the common electrode by merely changing the mask, and then connected in series between the different layers to form a signal line.
- the signal line may be formed by connecting only the wires located in two layers, or may be formed by connecting two or more wires in series.
- the signal line includes a gate line and a data line; the output end is connected to the gate of the thin film transistor in the array substrate as a gate line for gate signal transmission; and the output end is connected to the drain of the thin film transistor in the array substrate
- the data line is used to input a corresponding signal to the pixel electrode.
- the gate line is connected to the gate drive for inputting a gate scan signal to turn on or off the corresponding thin film transistor.
- the data line is drivingly connected to the data line for inputting a voltage to the pixel electrode for supplying a deflection voltage of the liquid crystal molecule to the pixel electrode when used in a liquid crystal display. The difference in resistance of each signal line will cause the delay of the signal to be transmitted to be different.
- the difference between the length of the signal line, the conductive material formed, and various wire connections can be used to make the difference in resistance. Adjustment. Further, in this embodiment, it is provided that the difference in resistance between the signal lines is smaller than the threshold.
- the threshold value can be set as needed. In a specific implementation process, the resistance ratio between the signal lines is maintained within a range of 3:1, which does not adversely affect the display or has a slight adverse effect, and at the same time, the manufacturing process The requirements are also low and easy to implement.
- the signal line may be connected to the driving circuit at any one of the conductive layers of the array substrate, for example, the wire of the gate metal layer and the wire of the source/drain metal layer are connected to the driving circuit.
- At least part of the signal lines of the array substrate in the embodiment are realized between multiple layers of the array substrate.
- the bending in three-dimensional space, the wires in different layers are connected in series to form a signal line satisfying the required signal line, and the problem that the area occupied by the signal line is not too wide, and the formation of a narrow frame which is disadvantageous for the non-display area is avoided. problem.
- Embodiment 3 is a diagrammatic representation of Embodiment 3
- the embodiment provides a method for fabricating an array substrate, and the manufacturing method includes:
- the wire forming signal lines located in different layers include at least the following two structures:
- a plurality of wires are formed, and the plurality of wires are connected in series by wires located in different layers.
- one wire is formed corresponding to one signal line, and the wires located at different layers are connected in series.
- Manner 1 When the signal line is formed by a series of wires in two layers; and each layer includes at least two wires, the manufacturing method specifically includes:
- Step 1 forming a gate metal layer including a gate line in the display region, and simultaneously forming a plurality of intermittent first wires of the signal line in the non-display area;
- Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
- Step 3 forming a through-gate insulating layer and an active layer corresponding to an end point of the first wire First via;
- Step 4 forming a source/drain metal layer including a source, a drain, and a data line over the active layer, and simultaneously forming a second wire at a discontinuity of the first wire, and at the first A via is filled with a conductive material for forming the source, the drain, and the signal line to connect the first and second wires in series.
- At least part of the signal lines in the array substrate produced by the method are formed by connecting the wires of the gate metal layer and the wires of the source and drain metal layers in series, and the through-gate insulating layer and the active layer are used in series connection. hole.
- the signal line includes a first wire on the gate metal layer 530 and a second wire on the source/drain metal layer 520.
- the first wire and the second wire are connected by a via.
- Figure 8 Figure 7 is a cross-sectional view at CC.
- the array substrate includes a gate metal layer 530 , a gate insulating layer 560 , an active layer 550 , a source/drain metal layer 520 , and a passivation layer 540 .
- the gate line metal layer 530 is connected to the source/drain metal layer 520 in FIG. 7, the step of forming a via hole is added once, and the connection in this manner can effectively ensure the reliability of the connection and reduce the contact resistance of the connection point. .
- the wires constituting the signal lines may also be located in other layers, such as a pixel electrode layer, and a common electrode layer.
- the first wire is formed together with the gate line, and it is only necessary to change the mask plate, and no additional steps are added, thereby achieving simplicity.
- the same formation principle is also applicable to the formation of the second wire, and the connection of the first wire and the second wire is also formed synchronously when the second wire is formed, thereby achieving simplicity.
- the formed signal lines are not limited to the same layer of the array substrate, but are formed in the plurality of layers, and converted from the bent signal lines in the original plane to the signal lines bent in the space described in the embodiment of the invention.
- the second method is for an array substrate including signal lines serially connected by wires in three layers in the array substrate; and each layer includes at least two wires forming the same signal line.
- the manufacturing method specifically includes:
- Step 1 forming a gate metal layer including a gate line in the display region, and simultaneously forming a plurality of intermittent first wires of the signal line in the non-display area;
- Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
- Step 3 forming a through-gate insulating layer and an active layer corresponding to an end point of the first wire First via;
- Step 4 forming a source/drain metal layer including a source, a drain, and a signal line over the active layer, and simultaneously forming a second wire at least at a portion of the discontinuous correspondence of the first wire, and The first via hole is filled with a conductive material for forming the source, the drain, and the signal line;
- Step 5 forming a passivation layer over the source/drain metal layer and simultaneously forming a second via hole;
- Step 6 forming a pixel electrode layer including a pixel electrode over the passivation layer, and at the same time at least A third wire is formed at the second wire in the discontinuity of the first wire, and a conductive material for forming the pixel electrode is filled in the second via hole.
- the first wire, the second wire, and the third wire are connected in series by the conductive material in the first via hole and the conductive material in the second via hole to form a signal line.
- the signal lines in the array substrate are formed by the wires located in the three layers, and the formed signal lines can be referred to FIG. 4 or FIG.
- Method 3 The manufacturing method is used to form an array substrate, wherein the array substrate includes signal lines formed by connecting wires in four layers; and each of the conductive layers provided with the wires includes at least two Wires that form the same signal line.
- some array substrate fabrication methods also include the steps of forming a common electrode, such as an ADS-array field mode array substrate.
- the array substrate of the ADS mode includes a pixel electrode and a common electrode; and the pixel electrode and the common electrode are located in different layers, and are usually formed of ITO.
- the manufacturing method specifically includes:
- the first ITO layer 610 including a transparent electrode for forming a fringe electric field is formed by the first process of patterning ITO, and the wires located in the first ITO layer 610 are simultaneously formed.
- the first process of patterning ITO is used to form a pixel electrode or a common electrode. If the first patterning process of ITO is used to form a pixel electrode, the second patterning process of ITO is used to form a common electrode. If the process of patterning the ITO for the first time is to form a common electrode, the second patterning process of the ITO is used to form the pixel electrode.
- the conductive material inside makes the connection between the wires.
- the signal lines in the substrate are connected by wires located in four different layers.
- the patterning process is one or more fabrication processes including deposition, coating, exposure, development, etching, and the like.
- Method 1 This method is used to form an array substrate including signal lines formed by connecting two layers of wires; and only one wire is included in one layer for forming the same signal line.
- Step 1 forming a gate metal layer including a gate line in the display region, and simultaneously forming a first wire of the signal line in the non-display area;
- Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
- Step 3 forming a through-gate insulating layer and an active layer above the end of the first wire First via;
- Step 4 forming a source/drain metal layer including a source, a drain, and a data line over the active layer, and simultaneously forming a second wire, and filling the first via hole to form the source Conductive materials of the poles, the drains, and the data lines are connected in series to the first and second wires.
- the conductive layer where the first wire or the second wire is located may also be changed.
- Method 2 part of the signal lines in the array substrate produced by the method are formed by three layers of wires; and each layer for forming the same signal line includes only one wire.
- the manufacturing method specifically includes: Step 1: forming a gate metal layer including a gate line in a display region, and simultaneously forming a first wire of the signal line in the non-display area;
- Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
- Step 3 forming a source including a source, a drain, and a signal line over the active layer Leaking a metal layer and simultaneously forming a second wire;
- Step 4 forming a passivation layer over the source/drain metal layer
- Step 5 forming a pixel electrode layer including a pixel electrode over the passivation layer, and simultaneously forming a third wire.
- the method for fabricating the array substrate further includes the steps of forming via holes:
- Step A forming a first via hole penetrating the gate insulating layer and the active layer; in a specific implementation process, the step A is located between step 2 and step 3;
- Step B forming a second via hole on the passivation layer; the step B is located between step 4 and step 5;
- the first via hole is used to connect the first wire and the second wire; and the second via hole is used to connect the second wire and the third wire.
- the first wire of the array substrate is only connected to the second wire; the third wire is only connected to the second wire, and the second wire is connected to the first wire and the second wire.
- the wires form a bridging portion of the signal lines.
- Method 3 part of the signal lines in the array substrate produced by the method are formed by three layers of wires; and each layer for forming the same signal line includes only one wire.
- the manufacturing method specifically includes: Step 1: forming a gate metal layer including a gate line in a display region, and simultaneously forming a first wire of the signal line in the non-display area;
- Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
- Step 3 forming a source including a source, a drain, and a signal line over the active layer Leaking a metal layer and simultaneously forming a second wire;
- Step 4 forming a passivation layer over the source/drain metal layer
- Step 5 forming a pixel electrode layer including a pixel electrode over the passivation layer, and simultaneously forming a third wire.
- the manufacturing method further includes the step of forming a via hole, and specifically includes:
- Step A forming a first via hole penetrating the gate insulating layer and the active layer; step A is located between step 2 and step 3;
- Step B forming a third via hole penetrating the gate insulating layer, the active layer and the passivation layer; step B is located between step 4 and step 5;
- the first via is used to connect the first wire and the second wire
- the third via is used to connect the first wire and the third wire.
- the first wire of the array substrate is only connected to the second wire; the third wire is only connected to the first wire, and the first wire forms a signal for connecting the third wire and the second wire.
- the bridging portion of the line is only connected to the second wire; the third wire is only connected to the first wire, and the first wire forms a signal for connecting the third wire and the second wire.
- Method 4 part of the signal lines in the array substrate produced by the method are formed by three layers of wires; and each layer for forming the same signal line includes only one wire.
- the manufacturing method specifically includes: Step 1: forming a gate metal layer including a gate line in a display region, and simultaneously forming a first wire of the signal line in the non-display area;
- Step 2 forming a gate insulating layer and an active layer on the gate metal layer and the first wire;
- Step 3 forming a source including a source, a drain, and a signal line over the active layer Leaking a metal layer and simultaneously forming a second wire;
- Step 4 forming a passivation layer over the source/drain metal layer;
- Step 5 forming a pixel electrode layer including a pixel electrode over the passivation layer, and simultaneously forming a third wire.
- the manufacturing method further includes the step of forming a via hole: the step of forming the via hole specifically includes: Step A: forming a second via hole on the passivation layer;
- Step B forming a third via hole penetrating the gate insulating layer, the active layer, and the passivation layer;
- the second via is used to connect the second wire and the third wire
- the third via is used to connect the first wire and the third wire.
- the first via hole and the second via hole may be formed by the same patterning process.
- the step of forming the via is located between step 4 and step 5.
- the first wire of the array substrate is only connected to the third wire; the second wire is only connected to the third wire, and the third wire is used as a signal for connecting the first wire and the second wire.
- the bridging portion of the line is used as a signal for connecting the first wire and the second wire.
- the array substrate produced by the method for fabricating the array substrate of the present embodiment can be considered as the array substrate of the present invention.
- the method for fabricating the array substrate according to the embodiment is used for fabricating the array substrate of the present invention, and the manufacturing process is less improved, and only the structure of the mask is changed to complete the fabrication of the wires and the connection between the wires, thereby realizing
- the advantage of the simplicity is that the array substrate formed by the method for fabricating the array substrate of the present invention has a small bending radius of signal lines and a large density of signal lines, which is advantageous for reducing driving data to save consumables and manufacturing costs. advantage.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/429,886 US10229938B2 (en) | 2013-09-17 | 2014-07-18 | Array substrate and fabrication method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310425475.0 | 2013-09-17 | ||
CN2013104254750A CN103474435A (zh) | 2013-09-17 | 2013-09-17 | 阵列基板及其制作方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015039492A1 true WO2015039492A1 (zh) | 2015-03-26 |
Family
ID=49799227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2014/082558 WO2015039492A1 (zh) | 2013-09-17 | 2014-07-18 | 阵列基板及其制作方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10229938B2 (zh) |
CN (1) | CN103474435A (zh) |
WO (1) | WO2015039492A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109767689A (zh) * | 2019-01-14 | 2019-05-17 | 京东方科技集团股份有限公司 | 显示基板、显示面板 |
CN113421890A (zh) * | 2021-06-24 | 2021-09-21 | 武汉天马微电子有限公司 | 一种阵列基板及其制备方法、显示面板、显示装置 |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103474435A (zh) | 2013-09-17 | 2013-12-25 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法 |
CN103560134B (zh) | 2013-10-31 | 2016-11-16 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
KR102086644B1 (ko) * | 2013-12-31 | 2020-03-09 | 엘지디스플레이 주식회사 | 플렉서블표시장치 및 이의 제조방법 |
CN104765897A (zh) * | 2014-01-06 | 2015-07-08 | 北京华大九天软件有限公司 | 一种双向增加布线长度的等电阻布线方法 |
CN104700813B (zh) | 2015-04-01 | 2017-10-03 | 上海中航光电子有限公司 | 阵列基板及其形成方法 |
CN104952418A (zh) * | 2015-07-27 | 2015-09-30 | 武汉华星光电技术有限公司 | 一种显示面板驱动装置及制造方法 |
CN105388647B (zh) * | 2015-12-15 | 2019-09-24 | 武汉华星光电技术有限公司 | 液晶面板的扇出走线结构及液晶面板 |
JP6634302B2 (ja) * | 2016-02-02 | 2020-01-22 | 株式会社ジャパンディスプレイ | 表示装置 |
CN106252360A (zh) * | 2016-08-29 | 2016-12-21 | 昆山国显光电有限公司 | 显示屏及其制作方法 |
CN106842740A (zh) * | 2016-12-27 | 2017-06-13 | 深圳市华星光电技术有限公司 | 一种液晶显示面板及其制作方法 |
CN106611089B (zh) * | 2016-12-28 | 2019-11-19 | 北京华大九天软件有限公司 | 一种平行端口之间奇偶相间等电阻布线方法 |
CN106782270A (zh) * | 2017-01-09 | 2017-05-31 | 厦门天马微电子有限公司 | 一种显示面板及显示装置 |
CN107037646A (zh) * | 2017-04-21 | 2017-08-11 | 京东方科技集团股份有限公司 | 一种显示基板及显示装置 |
CN107039377B (zh) * | 2017-06-16 | 2019-10-25 | 京东方科技集团股份有限公司 | 一种显示面板、其制作方法及显示装置 |
CN107491217B (zh) * | 2017-08-30 | 2020-11-13 | 厦门天马微电子有限公司 | 一种显示面板和显示装置 |
KR102377527B1 (ko) * | 2017-09-01 | 2022-03-24 | 삼성디스플레이 주식회사 | 입력감지유닛 및 이를 구비한 표시장치 |
CN108258025B (zh) | 2018-01-29 | 2020-02-28 | 京东方科技集团股份有限公司 | 扇出结构及其制造方法、显示面板 |
CN110993623A (zh) * | 2019-12-16 | 2020-04-10 | Tcl华星光电技术有限公司 | 阵列基板、显示面板及阵列基板的制作方法 |
CN111564454B (zh) * | 2020-05-19 | 2022-07-12 | 京东方科技集团股份有限公司 | 一种显示基板及其制造方法、显示装置 |
CN115443538A (zh) * | 2021-04-01 | 2022-12-06 | 京东方科技集团股份有限公司 | 阵列基板和显示装置 |
CN114171516B (zh) * | 2021-12-08 | 2023-07-25 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板的制作方法以及阵列基板、显示面板 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101217155A (zh) * | 2008-01-09 | 2008-07-09 | 上海广电光电子有限公司 | 双层配线结构的tft阵列基板 |
CN102798994A (zh) * | 2011-05-25 | 2012-11-28 | 上海中航光电子有限公司 | 液晶显示器阵列基板配线结构 |
CN103022033A (zh) * | 2012-12-11 | 2013-04-03 | 京东方科技集团股份有限公司 | 阵列基板、制作方法及显示装置 |
CN103185999A (zh) * | 2011-12-31 | 2013-07-03 | 上海中航光电子有限公司 | 液晶显示器阵列基板及其扫描线结构 |
CN103474435A (zh) * | 2013-09-17 | 2013-12-25 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI277133B (en) * | 2005-09-05 | 2007-03-21 | Au Optronics Corp | Fan-out wire structure |
US8008665B2 (en) * | 2007-01-02 | 2011-08-30 | Samsung Electronics Co., Ltd. | Fan-out, display substrate having the same and method for manufacturing the display substrate |
KR20080076519A (ko) * | 2007-02-16 | 2008-08-20 | 삼성전자주식회사 | 표시 기판 |
JP5280024B2 (ja) * | 2007-08-28 | 2013-09-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN102314003B (zh) * | 2010-06-29 | 2015-07-29 | 上海天马微电子有限公司 | 液晶显示面板及其液晶显示装置 |
KR101888423B1 (ko) | 2011-06-10 | 2018-08-17 | 엘지디스플레이 주식회사 | 평판 표시장치 |
CN102998865B (zh) * | 2012-11-16 | 2015-02-11 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
TWI505010B (zh) * | 2013-11-12 | 2015-10-21 | E Ink Holdings Inc | 主動元件陣列基板 |
-
2013
- 2013-09-17 CN CN2013104254750A patent/CN103474435A/zh active Pending
-
2014
- 2014-07-18 US US14/429,886 patent/US10229938B2/en not_active Expired - Fee Related
- 2014-07-18 WO PCT/CN2014/082558 patent/WO2015039492A1/zh active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101217155A (zh) * | 2008-01-09 | 2008-07-09 | 上海广电光电子有限公司 | 双层配线结构的tft阵列基板 |
CN102798994A (zh) * | 2011-05-25 | 2012-11-28 | 上海中航光电子有限公司 | 液晶显示器阵列基板配线结构 |
CN103185999A (zh) * | 2011-12-31 | 2013-07-03 | 上海中航光电子有限公司 | 液晶显示器阵列基板及其扫描线结构 |
CN103022033A (zh) * | 2012-12-11 | 2013-04-03 | 京东方科技集团股份有限公司 | 阵列基板、制作方法及显示装置 |
CN103474435A (zh) * | 2013-09-17 | 2013-12-25 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109767689A (zh) * | 2019-01-14 | 2019-05-17 | 京东方科技集团股份有限公司 | 显示基板、显示面板 |
CN113421890A (zh) * | 2021-06-24 | 2021-09-21 | 武汉天马微电子有限公司 | 一种阵列基板及其制备方法、显示面板、显示装置 |
Also Published As
Publication number | Publication date |
---|---|
US20160035747A1 (en) | 2016-02-04 |
CN103474435A (zh) | 2013-12-25 |
US10229938B2 (en) | 2019-03-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2015039492A1 (zh) | 阵列基板及其制作方法 | |
US9711541B2 (en) | Display panel and method for forming an array substrate of a display panel | |
WO2018018893A1 (zh) | 薄膜晶体管及其制备方法、阵列基板和显示装置 | |
CN109037235B (zh) | 阵列基板及其制作方法 | |
WO2016119344A1 (zh) | 阵列基板及其制造方法和显示面板 | |
CN104977740A (zh) | 显示基板及其制备方法、显示装置 | |
CN104253132B (zh) | 具有金属氧化物半导体的薄膜晶体管基板及其制造方法 | |
CN102629059B (zh) | 阵列基板及制造方法、液晶面板和液晶显示器 | |
US20150072484A1 (en) | Thin film transistor array panel and manufacturing method thereof | |
WO2015039389A1 (zh) | 阵列基板及其制作方法、显示装置 | |
WO2014153838A1 (zh) | 阵列基板及其制造方法和液晶面板 | |
WO2013017088A1 (zh) | 液晶显示面板及液晶显示器 | |
WO2015096340A1 (zh) | 阵列基板及其制备方法、显示装置 | |
WO2013170594A1 (zh) | 阵列基板及其制造方法、显示装置 | |
JP5936839B2 (ja) | アレイ基板およびその製造方法、並びに液晶ディスプレー | |
WO2014176876A1 (zh) | 显示面板及其制作方法、液晶显示器 | |
CN104460163A (zh) | 一种阵列基板及其制作方法及显示装置 | |
WO2021248605A1 (zh) | 阵列基板及显示面板 | |
CN105824160B (zh) | 显示面板 | |
CN105280648A (zh) | 阵列基板及其制作方法、显示面板和显示装置 | |
CN104733478A (zh) | 一种阵列基板及其制作方法、显示装置 | |
WO2015003461A1 (zh) | 阵列基板及显示器 | |
WO2019137044A1 (zh) | 像素结构及其制作方法、阵列基板和显示装置 | |
CN113433747B (zh) | 阵列基板及制作方法、移动终端 | |
WO2021190049A1 (zh) | 显示基板及其制作方法、和显示面板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 14429886 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14845999 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 24.05.2016) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 14845999 Country of ref document: EP Kind code of ref document: A1 |