CN109037235B - 阵列基板及其制作方法 - Google Patents
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Abstract
本发明提供一种阵列基板及其制作方法,通过将阵列基板的扇出线的第一导线分为多个第一区段,所述扇出线的第二导线分为与所述第一区段对应的多个第二区段,并将每个所述第一区段与其对应的第二区段电连接,从而使得当所述第一导线或者第二导线的某个位置断开时,仅改变所述断开位置所在的第一区段或第二区段的电阻,使得对于所述扇出线整体的阻止影响不大,进而减轻或者避免所述淡线的出现。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种阵列基板及其制作方法。
背景技术
在显示面板中,阵列基板上设置有多条纵横交错的信号线,以通过传输至所述信号线上的驱动信号及数据信号实现画面的显示。所述驱动信号及数据信号一般通过控制芯片发出,并通过扇出线(Fanout)传输至所述信号线。现有技术中,为了使所述扇出线的阻值减小,以减小信号损耗,设计所述扇出线一般包括第一导线及与层叠于所述第一导线上的第二导线,所述第一导线与第二导线并联后,一端连接至一条所述信号线,另一端连接至所述控制芯片上的一个连接端子。但是,在实际制程中,制作所述第一导线或者所述第二导线时,可能会由于成膜异物等原因造成所述第一导线或者所述第二导线断开,进而使得还条所述第一导线或者所述第二导线所在的扇出线的电阻增大,进而使得通过该条所述扇出线传输的信号损耗较大,使得显示画面出现淡线,影响显示效果。
发明内容
本发明的提供一种阵列基板及其制作方法,减轻所述显示面板出现淡线的情况。
所述阵列基板包括显示区及围绕所述显示区的非显示区,所述显示区内有多条信号线,所述非显示区内设有控制芯片以及多条间隔设置的扇出线;每条所述扇出线均电连接在所述控制芯片和与所述扇出线对应的一条所述信号线之间;所述扇出线为双层导线结构,包括层叠设置在第一绝缘层两侧的第一导线第二导线,所述第一导线包括多个依次连接的第一区段,所述第二导线包括多个依次连接的第二区段,且每个所述第二区段与一个所述第一区段相对应,每个所述第二区段与其相对应的所述第一区段电连接。
其中,所述绝缘层上设有间隔设置的多个过孔,所述第二区段与同其对应的第一区段之间通过所述过孔实现电连接。
其中,所述第二导线上层叠有导电桥层,且所述第二导线与所述导电桥层之间通过第二绝缘层间隔,所述导电桥层包括间隔设置的多个导电桥,每个所述导电桥与一个所述第二区段相对应;所述导电桥的一端通过过孔与所述第二区段电连接,另一端与同所述第二区段对应的第一区段电连接。
其中,所述阵列基板的显示区内设有像素电极层,所述像素电极层与所述导电桥层位于同一层并通过同一制程得到。
其中,所述信号线包括栅极线,所述第一导线与所述栅极线位于同一层并通过同一制程得到。
其中,所述信号线包括数据线,所述第二导线与所述数据线位于同一层并通过同一制程得到。
其中,所述第一区段的阻值与同其对应的所述第二区段的阻值相同。
其中,所述第一导线与所述第二导线的材料相同的导电材料,所述第一导线与所述第二导线的线宽相同,且所述第一区段的长度与同其对应的第二区段的长度相同。
其中,所述第一导线在所述第二导线上的投影与所述第二导线重合。
所述阵列基板的制作方法包括步骤:
提供一基板,在所述基板上形成第一金属层,对所述第一金属层进行图案化,得到栅极层、与所述栅极层电连接的栅极线及所述第一导线;
在所述第一金属层上依次沉积栅极绝缘层,半导体层及第二金属层,同时对所述半导体层及所述第二金属层进行图案化,所述第二金属层图案化得到源漏极层、与所述源漏极层电连接的数据线及所述第二导线,所述半导体层图案化得到半导体沟道层;
依次沉积钝化层及平坦层,对所述钝化层及所述平坦层进行图案化以形成多个过孔,多个所述过孔中包括深孔及浅孔,所述浅孔连通至所述第二导线,所述深孔连通至所述第一导线;
在所述平坦层上沉积像素电极材料层,对所述像素电极材料层进行图案化得到像素电极层及导电桥层,所述导电桥层包括多个导电桥,每个所述导电桥的一端通过所述浅口连接至所述第二导线,另一端通过所述深孔连接至所述第一导线,以通过所述导电桥电连接所述第一导线与所述第二导线。
本发明提供的所述阵列基板其制作方法,通过将所述第一导线分为多个第一区段,所述第二导线分为与所述第一区段对应的多个第二区段,并将每个所述第一区段与其对应的第二区段电连接,从而使得当所述第一导线或者第二导线的某个位置断开时,仅改变所述断开位置所在的第一区段或第二区段的电阻,使得对于所述扇出线整体的阻止影响不大,进而减轻或者避免所述淡线的出现。
附图说明
为更清楚地阐述本发明的构造特征和功效,下面结合附图与具体实施例来对其进行详细说明。
图1是本发明的阵列基板的结构示意图;
图2是本发明一实施例扇出线沿其延伸方向的截面示意图;
图3是本发明另一实施例扇出线沿其延伸方向的截面示意图;
图4是本发明的阵列基板的截面示意图;
图5是图3所述实施例的阵列基板制作方法的流程图;
图6-图8是图5所述阵列基板制作方法的各步骤中的截面示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述。其中,附图仅用于示例性说明,表示的仅是示意图,不能理解为对本专利的限制。本申请所述的图案化构图工艺包括成膜、显影、曝光、蚀刻等构图工艺。
本发明提供一种显示面板,所述显示面板可以为液晶显示面板,也可以为OLED显示面板。所述显示面板为液晶显示面板时,所述显示面板包括阵列基板及与所述阵列基板相对的彩膜基板,以及位于所述阵列基板与所述彩膜基板之间的液晶层。当所述显示面板为OLED显示面板时,所述阵列基板为所述OLED显示面板的一部分,所述阵列基板上还包括发光材料层、阴极层及封装层等。
请参阅图1,本发明提供一种阵列基板100。所述阵列基板100包括显示区S1及围绕所述显示区S1的非显示区S2。所述显示区S1内有多条信号线(图中未示出),所述非显示区S2内设有控制芯片10以及多条间隔设置的扇出线20。每条所述扇出线20一端与所述控制芯片10连接,另一端与一条所述信号线连接,从而通过所述扇出线20电连接所述控制芯片10及所述信号线,以将所述控制芯片10产生的驱动信号及数据信号传输至所述信号线中。
请参阅图2,所述扇出线20为双层导线结构,包括第一导线21及层叠于所述第一导线21上的第二导线22,所述第一导线21与所述第二导线22之间通过第一绝缘层23间隔开。所述第一导线21包括多个依次连接的第一区段21a,所述第二导线22包括多个依次连接的第二区段22a,且每个所述第二区段22a与一个所述第一区段21a相对应,每个所述第二区段22a与其相对应的所述第一区段21a电连接,即相当于每个所述第一区段21a与一个第二区段22a进行并联以得到并联结构,再将多个所述并联结构串联起来。从而当所述第一导线21或者所述第二导线22在某个位置断开时,仅所述断开位置所在的并联结构的电阻发生变化,从而不会影响其它的所述并联结构的电阻,进而避免出现线路断开问题的所述扇出线20的电阻发生大的变化,减轻或者避免出现线路断开问题的所述扇出线20对控制信号的损耗,从而减轻或者避免所述显示面板出现淡线的情况。经过试验发现,现有技术的显示面板由于所述阵列基板中的所述第一导线或者所述第二导线的断开而产生淡线问题的发生概率约为1%,而使用本发明的阵列基板的显示面板,基本可以解决显示面板由于所述第一导线或者所述第二导线的断开而产生淡线问题,具有良好的实际应用效果。
并且,本发明中,当一条所述扇出线20的所述第一导线21及所述第二导线22均断开时,只要所述第一导线21上的断开位置与所述第二导线22上的断开位置不在相对应的第一区段21a和第二区段22a内,则该条所述扇出线20则可进行正常的信号传输。相对于现有技术中一条所述扇出线20的所述第一导线21与所述第二导线22均断开,则该所述扇出线20则不能进行信号传输的情况来说,本发明还能够进一步的避免所述显示面板的由于所述扇出线20断裂而不能正常工作的问题。本实施例中,每个所述第一区段21a与同其对应的第二区段22a的长度相同,且所述第二区段22a位于所述第一区段21a的正上方,所述第二区段22a在所述第一区段21a所在平面上的投影与所述第一区段21a重合。
请再次参阅图2,本发明一些实施例中,所述第一绝缘层23上设有间隔设置的多个过孔24,所述第一导线21位于相邻的两个所述过孔24之间的部分为所述第一区段21a;所述第二导线22位于相邻的两个所述过孔24之间的部分为所述第二区段22a,位于相同的两个所述过孔24之间的所述第一区段21a与所述第二区段22a相对应。每个所述过孔24连接一个所述第一区段21a及与所述第一区段21a对应的第二区段22a对应,从而实现所述第二区段22a与同其对应的第一区段21a的电连接。
进一步的,本发明一些实施例中,多个所述过孔之间的间距相同,以使得所述第一导线21上的每条所述第一区段21a的长度相同,从而使得无论所述第一导线21或者所述第二导线22上在哪一个区段出现断口,所述扇出线20的电阻变化均相同,避免当所述第一导线21/第二导线22上的某一第一区段21a/第二区段22a的长度较别的第一区段21a/第二区段22a区段长,而当该所述第一区段21a出现断开时,使得所述第一导线21/第二导线22的电阻大大增加的情况。
请参阅图3,本发明另一实施例中,所述第二导线22上层叠有导电桥层30,并且,所述第二导线22与所述导电桥层30之间设有第二绝缘层40,以通过所述第二绝缘层40将所述第二导线22与所述导电桥层30进行间隔并绝缘。所述导电桥层30包括间隔设置的多个导电桥31,每个所述导电桥31与一个所述第二区段22a相对应;所述导电桥31的一端通过过孔与所述第二区段22a电连接,另一端与同所述第二区段22a对应的第一区段21a电连接。具体的,本实施例的所述过孔包括深孔32a及浅孔32b,所述深孔32a的穿过所述第二绝缘层40、所述第二导线22及所述第一绝缘层23,以使其两端分别连接所述导电桥31及所述第一导线21;所述浅孔32b穿过所述第二绝缘层40,以使其两端分别连接所述导电桥31及所述第二导线22,最终通过所述深孔32a及所述浅孔32b使得所述导电桥31电连接第一导线21与所述第二导线22。
所述阵列基板100的显示区S1内的信号线20包括多条平行设置的数据线及多条平行设置的扫描线,所述数据线与扫描线位于不同层并通过所述第一绝缘层23进行绝缘。本发明中,所述第一导线21与所述扫描线位于同一层并通过同一制程得到;所述第二导线22与所述数据线位于同一层并通过同一制程得到。所述阵列基板100的显示区S1内设有像素电极层,所述像素电极层位于所述数据线层的上方,所述像素电极层与所述导电桥层30位于同一层并通过同一制程得到。因此,本发明不需要增加新的制程以得到所述阵列基板100,从而在得到具有良好的显示效果的显示面板的同时,避免增加成本,具有良好的实际应用效果。
具体的,请参阅图4,本发明的所述阵列基板100的具体结构为:所述阵列基板100的显示区S1内设有多条平行设置的所述扫描线及多条平行设置的数据线,所述数据线与所述扫面线垂直相交,且相邻的两条数据线与相邻的两条扫描线围城一个像素区域,每个所述像素区域内设有一薄膜晶体管及与所述薄膜晶体管连接的像素电极。其中,所述薄膜晶体管同其相邻的数据线及扫描线电连接,以通过所述扫描线传输的扫描信号控制所述薄膜晶体管的开关,再将所述数据线传输的数据信号通过所述薄膜晶体管传输至所述像素电极,以控制所述像素区域内的图像显示。具体的,所述薄膜晶体管包括依次层叠的栅极层51、栅极绝缘层52、半导体沟道层53、源漏极层54、钝化层55及平坦层56。所述像素电极层57层叠于所述平坦层56上,并通过过孔与所述源漏极层54电连接。并且,所述栅极层51与所述扫描线及所述第一导线21位于同一层并通过同一制程得到;所述源漏极层54与所述数据线及所述第二导线22位于同一层并通过同一制程得到;所述第一绝缘层23与所述栅极绝缘层52及所述半导体沟道层53位于同一层并通过同一制程得到;所述第二绝缘层40与所述钝化层55及平坦层56位于同一层并通过同一制程得到。
进一步的,本发明中,所述第一导线21与所述第二导线22的阻值相同,且每个所述第一区段21a与同其对应的第二区段22a的阻值相同,从而使得所述第一导线21与所述第二导线22并联以后的所述扇出线20的阻值最小,使得信号传输更好,从而增强所述显示面板的显示效果。具体的,本实施例中,所述第一导线21与所述第二导线22的材料相同的导电材料,且所述第一导线21与所述第二导线22的线宽相同,从而使得所述第一导线21与所述第二导线22的阻值相同。并且,由于本实施例中,所述第一区段21a的长度与同其对应的第二区段22a的长度相同,从而使得每个所述第一区段21a与同其对应的第二区段22a的阻值相同。进一步的,所述第一导线21在所述第二导线22上的投影与所述第二导线22重合,即所述第二导线22位于所述第一导线21的正上方,从而使得每条所述扇出线20占据所述非显示区S2的面积最小,使得相邻两条扇出线20之间的距离尽量的宽,从而减小布线难度,并防止相邻两条扇出线20之间信号的互窜,保证所述扇出线20上信号的传输效果。
本发明的所述阵列基板100,通过将所述第一导线21分为多个第一区段21a,所述第二导线22分为与所述第一区段21a对应的多个第二区段22a,并将每个所述第一区段21a与其对应的第二区段22a电连接,从而使得当所述第一导线21或者第二导线22的某个位置断开时,仅改变所述断开位置所在的第一区段21a或第二区段22a的电阻,使得对于所述扇出线20整体的阻止影响不大,进而减轻或者避免所述淡线的出现。例如,现有技术中,如果某段所述第一区段21a或者第二区段22a断开时,则所述扇出线20的阻值为R。而本发明中,所述第一导线21与所述第二导线22的阻值均为R时,所述第一区段21a及所述第二区段22a均为5段时,每段所述第一区段21a及第二区段22a的阻值均为R/5,则所述扇出线20的阻值为R/2。当某段所述第一区段21a或者第二区段22a断开时,则所述扇出线20的阻值为3R/5,相较于现有技术大大减小。
请参阅图5,本发明还提供一种阵列基板100的制作方法,用于得到图3所述实施例的阵列基板100。所述阵列基板100的制作方法包括步骤:
步骤510、请参阅图6,提供一基板50,在所述基板50上形成第一金属层,对所述第一金属层进行图案化,得到栅极层51、与所述栅极层51电连接的栅极线(图中未示出)及所述第一导线21。该步骤中,通过第一道光罩工艺对所述第一金属层进行图案化。
步骤520、请参阅图7,在所述第一金属层上依次沉积栅极绝缘层52,半导体层及第二金属层,同时对所述半导体层及所述第二金属层进行图案化,所述第二金属层图案化得到源漏极层54、与所述源漏极层54电连接的数据线及所述第二导线22,所述半导体层图案化得到半导体沟道层53。该步骤中,通过第二道光罩工艺对所述半导体层及第二金属层进行图案化。
步骤530、请参阅图8,依次沉积钝化层55及平坦层56,对所述钝化层55及所述平坦层56进行图案化以形成多个过孔32,多个所述过孔32中包括深孔32a及浅孔32b,所述浅孔32b连通至所述第二导线22,所述深孔32a连通至所述第一导线21。并且,所述过孔32中还包括穿过所述钝化层55及平坦层56连通至所述源漏极层54的过孔。该步骤中,通过第三道光罩工艺对所述钝化层55及所述平坦层56进行图案化以形成所述过孔32。
步骤540、请重新参阅图4,在所述平坦层上沉积像素电极材料层,对所述像素电极材料层进行图案化得到像素电极层57及导电桥层30,所述导电桥层30包括多个导电桥31,每个所述导电桥31的一端通过所述浅口32b连接至所述第二导线22,另一端通过所述深孔32a连接至所述第一导线21,以通过所述导电桥电连接所述第一导线21与所述第二导线22。所述像素电极层57包括阵列设置的像素电极,每个所述像素电极通过一个所述过孔与所述源漏极层54电连接。该步骤中,通过第四道光罩工艺对所述像素电极材料层进行图案化得到像素电极层及导电桥层。
通过所述阵列基板100的制作方法,仅通过四道光罩工艺即可得到所述阵列基板100,使得所述阵列基板100的制程简单,提高所述阵列基板100的制作效率,并降低生产成本。
以上所述为本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也视为本发明的保护范围。
Claims (8)
1.一种阵列基板,其特征在于,包括显示区及围绕所述显示区的非显示区,所述显示区内有多条信号线,所述非显示区内设有控制芯片以及多条间隔设置的扇出线;每条所述扇出线均电连接在所述控制芯片和与所述扇出线对应的一条所述信号线之间;所述扇出线为双层导线结构,包括层叠设置在第一绝缘层两侧的第一导线第二导线,所述第一导线包括多个依次连接的第一区段,所述第二导线包括多个依次连接的第二区段,且每个所述第二区段与一个所述第一区段相对应,每个所述第二区段与其相对应的所述第一区段电连接;
所述绝缘层上设有间隔设置的多个过孔,所述第二区段与同其对应的第一区段之间通过所述过孔实现电连接;
所述第二导线上层叠有导电桥层,且所述第二导线与所述导电桥层之间通过第二绝缘层间隔,所述导电桥层包括间隔设置的多个导电桥,每个所述导电桥与一个所述第二区段相对应;所述导电桥的一端通过过孔与所述第二区段电连接,另一端与同所述第二区段对应的第一区段电连接。
2.如权利要求1所述的阵列基板,其特征在于,所述阵列基板的显示区内设有像素电极层,所述像素电极层与所述导电桥层位于同一层并通过同一制程得到。
3.如权利要求1或2所述阵列基板,其特征在于,所述信号线包括栅极线,所述第一导线与所述栅极线位于同一层并通过同一制程得到。
4.如权利要求1或2所述的阵列基板,其特征在于,所述信号线包括数据线,所述第二导线与所述数据线位于同一层并通过同一制程得到。
5.如权利要求1的所述的阵列基板,其特征在于,所述第一区段的阻值与同其对应的所述第二区段的阻值相同。
6.如权利要求5的所述的阵列基板,其特征在于,所述第一导线与所述第二导线的材料相同的导电材料,所述第一导线与所述第二导线的线宽相同,且所述第一区段的长度与同其对应的第二区段的长度相同。
7.如权利要求6的所述的阵列基板,其特征在于,所述第一导线在所述第二导线上的投影与所述第二导线重合。
8.一种阵列基板的制作方法,其特征在于,包括步骤:
提供一基板,在所述基板上形成第一金属层,对所述第一金属层进行图案化,得到栅极层、与所述栅极层电连接的栅极线及第一导线;
在所述第一金属层上依次沉积栅极绝缘层,半导体层及第二金属层,同时对所述半导体层及所述第二金属层进行图案化,所述第二金属层图案化得到源漏极层、与所述源漏极层电连接的数据线及第二导线,所述半导体层图案化得到半导体沟道层;
依次沉积钝化层及平坦层,对所述钝化层及所述平坦层进行图案化以形成多个过孔,多个所述过孔中包括深孔及浅孔,所述浅孔连通至所述第二导线,所述深孔连通至所述第一导线;
在所述平坦层上沉积像素电极材料层,对所述像素电极材料层进行图案化得到像素电极层及导电桥层,所述导电桥层包括多个导电桥,每个所述导电桥的一端通过所述浅孔连接至所述第二导线,另一端通过所述深孔连接至所述第一导线,以通过所述导电桥电连接所述第一导线与所述第二导线。
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