WO2013017088A1 - 液晶显示面板及液晶显示器 - Google Patents

液晶显示面板及液晶显示器 Download PDF

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Publication number
WO2013017088A1
WO2013017088A1 PCT/CN2012/079530 CN2012079530W WO2013017088A1 WO 2013017088 A1 WO2013017088 A1 WO 2013017088A1 CN 2012079530 W CN2012079530 W CN 2012079530W WO 2013017088 A1 WO2013017088 A1 WO 2013017088A1
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Prior art keywords
liquid crystal
layer
crystal display
pixel electrode
electrode layer
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Application number
PCT/CN2012/079530
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English (en)
French (fr)
Inventor
王世君
陈小川
Original Assignee
北京京东方光电科技有限公司
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Priority to US13/699,565 priority Critical patent/US9176346B2/en
Publication of WO2013017088A1 publication Critical patent/WO2013017088A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • Embodiments of the invention relate to liquid crystal display panels and liquid crystal displays. Background technique
  • a Propel Link Gate (PLG) trace in a liquid crystal display panel is mainly used to transfer a signal output from a source integrated circuit (IC) to a gate IC, or to be used in at least two gates. Signals are passed between the pole ICs.
  • the PLG trace is placed on the edge of the liquid crystal display panel, and is fabricated in the same layer as the gate line and the storage capacitor bottom electrode line.
  • the fabrication process is as follows: A gate metal film is formed on the array substrate, and a gate line, a storage capacitor electrode line, and a PLG trace are formed by a patterning process.
  • the inventor Since the resistance of the PLG trace needs to be less than an upper limit value to avoid affecting the picture quality of the liquid crystal display, the inventor has at least found the following problems in the process of designing and fabricating the above PLG trace:
  • the embodiment of the invention provides a liquid crystal display panel, comprising: a color filter substrate and an array substrate of the pair of boxes; a liquid crystal layer disposed between the color film substrate and the array substrate; and a layer structure for driving the liquid crystal layer
  • the layer structure includes a gate metal layer, a pixel electrode layer, and a common electrode layer, wherein the gate metal layer includes a connection gate trace, and the common electrode layer includes an electrically insulated first auxiliary electrode and a common electrode, the pixel electrode layer includes a pixel electrode, the common electrode and the pixel electrode are used to form an electric field to drive the liquid crystal; wherein the first auxiliary electrode is electrically connected to the connection gate trace to make two The parallel connection is formed in the circuit.
  • the embodiment of the invention further provides a liquid crystal display comprising the above liquid crystal display panel.
  • FIG. 1 is a schematic structural view of a liquid crystal display panel according to a first embodiment
  • FIG. 2 is a schematic structural view of a liquid crystal display panel according to a second embodiment
  • FIG. 3 is a schematic structural diagram of a liquid crystal display panel according to a third embodiment. detailed description
  • Embodiments of the present invention provide a liquid crystal display panel and a liquid crystal display, wherein the PLG traces can be fabricated with low design complexity and fabrication process precision.
  • the common electrode layer By forming the common electrode layer to include the first auxiliary electrode and the common electrode electrically insulated, and the first auxiliary electrode is electrically connected to the PLG trace in parallel, so that the resistance of the circuit portion including the PLG trace is effectively reduced to PLG.
  • the resistance of the line itself in parallel with the first auxiliary electrode can greatly reduce the fineness of drawing the PLG trace during the design of the PLG trace, and can also overcome the influence of the process variation on the resistance of the PLG trace. The purpose of reducing the design complexity of the PLG trace and the precision of its manufacturing process is achieved.
  • the liquid crystal display panel comprises: a color filter substrate 10 and an array substrate 16 of a pair of boxes; a liquid crystal layer 50 disposed between the color filter substrate 10 and the array substrate 16; and a layer structure for driving the liquid crystal of the liquid crystal layer 50 to rotate.
  • the layer structure includes: a gate metal layer, a pixel electrode layer, and a common electrode layer.
  • the gate metal layer includes PLG traces 15; the common electrode layer includes electrically insulated first auxiliary electrodes 21 and common electrodes 22; and the first auxiliary electrodes 21 are electrically connected to the PLG traces 15.
  • the PLG trace 15 is formed, for example, in a peripheral region outside the display area of the liquid crystal panel.
  • the first auxiliary electrode 21 is electrically connected to the PLG trace 15, that is, the PLG in the circuit
  • the trace 15 is connected in parallel with the first auxiliary electrode 21. This can effectively reduce the resistance of the circuit portion including the PLG trace 15, thereby achieving the purpose of reducing the design complexity of the PLG trace 15 and the precision of its fabrication process.
  • the common electrode layer is formed on the color filter substrate 10, and the pixel electrode layer is formed on the array substrate 16 and includes a pixel electrode 32.
  • the liquid crystal display panel of such a structure drives the rotation of the liquid crystal by a vertical electric field formed between the common electrode in the common electrode layer and the pixel electrode in the pixel electrode layer. Therefore, the liquid crystal display panel is of a vertical electric field drive type.
  • the pixel electrode layer further includes a second auxiliary electrode 31 electrically insulated from the pixel electrode 32.
  • the common electrode 22 of the above common electrode layer and the pixel electrode 32 of the pixel electrode layer are formed for each sub-pixel of the display region of the liquid crystal panel, that is, each sub-pixel includes the common electrode 22 and the pixel electrode 32.
  • first auxiliary electrode 21 and the PLG trace 15 are electrically connected to each other in the following manner.
  • the first auxiliary electrode 21 is electrically connected to the second auxiliary electrode 31, and the second auxiliary electrode 31 is electrically connected to the PLG trace 15 through a via 12, for example.
  • the above layer structure can be produced as follows.
  • An array substrate 16 having a gate metal layer including a PLG trace sequentially formed thereon, a gate insulating layer, an active layer, a source/drain metal layer, and a protective layer.
  • the PLG trace 15 is covered by the gate insulating layer 14 and the protective layer 13, as shown in FIG. 1; a via 12 is formed in each layer directly above the PLG trace by a patterning process to take the PLG The line portion is exposed; thereafter, a pixel electrode layer is formed on the array substrate on which the via hole 12 is formed, and the pixel electrode layer is divided into the electrically insulating second auxiliary electrode 31 and the pixel electrode 32 by a patterning process.
  • electrically connecting the first auxiliary electrode 21 and the second auxiliary electrode 31 can be realized in the following manner.
  • the first auxiliary electrode 21 is electrically connected to the second auxiliary electrode 31 through a conductive paste 11;
  • the conductive paste 11 is an anisotropic conductive paste; the anisotropic conductive paste is, for example, vertically conductive, and laterally non-conductive.
  • An example of the conductive paste 11 may be a sealant in which a gold ball (Au Ball) is doped.
  • the liquid crystal display includes: a liquid crystal display panel.
  • the liquid crystal display panel includes: a color filter substrate 10 and an array substrate 16 of a pair of boxes; disposed between the color filter substrate 10 and the array substrate 16.
  • the liquid crystal layer 50 ; and a layer structure for driving the liquid crystal of the liquid crystal layer 50 to rotate.
  • the layer structure includes: a gate metal layer, a pixel electrode layer, and a common electrode layer.
  • the gate metal layer includes a connection gate (PLG) trace 15.
  • the common electrode layer includes an electrically insulating first auxiliary electrode 21 and a common electrode 22.
  • the first auxiliary electrode 21 is electrically connected to the PLG trace 15 .
  • the first auxiliary electrode 21 is electrically connected to the PLG trace 15, that is, the PLG trace 15 is connected in parallel with the first auxiliary electrode 21 in the circuit, so that the circuit portion including the PLG trace 15 can be effectively reduced.
  • the resistance of the PLG trace 15 is designed to reduce the design complexity of the PLG trace 15 and the precision of its fabrication process.
  • the common electrode layer is formed on the color filter substrate 10, and the pixel electrode layer is formed on the array substrate 16 and includes a pixel electrode 32.
  • the liquid crystal display panel of such a structure drives the rotation of the liquid crystal by a vertical electric field formed between the common electrode in the common electrode layer and the pixel electrode in the pixel electrode layer.
  • the pixel electrode layer further includes a second auxiliary electrode 31 electrically insulated from the pixel electrode 32.
  • first auxiliary electrode 21 and the PLG trace 15 are electrically connected to each other in the following manner.
  • the first auxiliary electrode 21 is electrically connected to the second auxiliary electrode 31, and the second auxiliary electrode 31 is electrically connected to the PLG trace 15 through the via 12.
  • the layer structure in the liquid crystal display of the present embodiment can be fabricated by referring to the manufacturing method described for the liquid crystal display panel shown in Fig. 1, and will not be described herein.
  • the first auxiliary electrode 21 and the second auxiliary electrode 31 may be electrically connected in the following manner.
  • the first auxiliary electrode 21 is electrically connected to the second auxiliary electrode 31 through a conductive paste 11;
  • the conductive paste 11 is an anisotropic conductive paste; and the anisotropic conductive paste is, for example, vertically conductive and laterally non-conductive.
  • An example of the conductive paste 11 may be a sealant in which a gold ball (Au Ball) is incorporated.
  • the first auxiliary electrode 21 is electrically connected to the second auxiliary electrode 31 through the conductive adhesive 11, and the second auxiliary electrode 31 passes through the via 12 and
  • the PLG traces 15 are electrically connected, such that the PLG traces 15 and the first auxiliary electrodes 21 can be electrically connected, that is, the first auxiliary electrodes 21 and the PLG traces 15 in the circuit.
  • Parallel connection can reduce the resistance of the circuit portion including the PLG trace 15 to achieve the purpose of reducing the design complexity of the PLG trace and the precision of its fabrication process.
  • the liquid crystal display panel includes: a color filter substrate 10 and an array substrate 16 of a pair of boxes; a liquid crystal layer 50 disposed between the color filter substrate 10 and the array substrate 16; and a layer structure for driving the liquid crystal of the liquid crystal layer 50 to rotate.
  • the layer structure includes: a gate metal layer, a pixel electrode layer, and a common electrode layer.
  • the gate metal layer includes: a connection gate (PLG) trace 15;
  • the common electrode layer includes: an electrically insulating first auxiliary electrode 21 and a common electrode 22; the first auxiliary electrode 21 and the PLG trace 15 Electrical connection.
  • the PLG trace 15 is formed, for example, in a peripheral region outside the display area of the liquid crystal panel.
  • the common electrode layer and the pixel electrode layer are both formed on the array substrate 16, and the common electrode layer is on the pixel electrode layer.
  • the pixel electrode layer includes a pixel electrode.
  • the liquid crystal display panel of such a structure drives liquid crystal rotation by an edge field formed between a common electrode in the common electrode layer and a pixel electrode in the pixel electrode layer. Therefore, the liquid crystal display panel is a fringe electric field switching type.
  • the first auxiliary electrode 21 is electrically connected to the PLG trace 15 for example: the first auxiliary electrode 21 is electrically connected to the PLG trace 15 through the via 12 .
  • the "lower” is a position closer to the array substrate 16.
  • the common electrode layer is below the pixel electrode layer, that is, the common electrode layer is closer to the array substrate 16 with respect to the pixel electrode layer.
  • the common electrode 22 of the above common electrode layer and the pixel electrode 32 of the pixel electrode layer are formed for each sub-pixel of the display region of the liquid crystal panel, that is, each sub-pixel includes the common electrode 22 and the pixel electrode 32.
  • the pixel electrode 32 may be formed with a slit (not shown) to expose the common electrode 22 of the slit.
  • the common electrode 22 may be further formed with a slit.
  • the layer structure of the liquid crystal display panel shown in FIG. 2 can be produced by referring to the following method.
  • An array substrate is provided on which a gate metal layer, a gate insulating layer, and an active layer are sequentially formed.
  • a PLG trace 15 is formed on the edge of the array substrate 16 and covered by the gate insulating layer 14; a via hole 12 is formed directly above the PLG trace 15 by a patterning process; thereafter, an array substrate in which the via 12 is formed Forming a common electrode layer thereon, and dividing the common electrode layer into electrically insulating first auxiliary electrode 21 and common electrode 22 by a patterning process; forming a first protective layer, a source/drain metal layer on the array substrate on which the common electrode layer is formed a second protective layer and a pixel electrode layer; the protective layer 13 in FIG. 2 includes a first protective layer and a second protective layer.
  • the element electrode layer includes a pixel electrode 32 and a second auxiliary electrode 31 electrically insulated from the pixel electrode 32.
  • the second auxiliary electrode 31 is electrically connected to the first auxiliary electrode 21 through the second via hole 12 .
  • the PLG trace and the first auxiliary electrode 21 and the second auxiliary electrode 31 are connected in parallel in the circuit for the purpose of further reducing the resistance of the circuit portion including the PLG trace.
  • the liquid crystal display comprises: a liquid crystal display panel.
  • the liquid crystal display panel includes: a color filter substrate 10 and an array substrate 16 of a pair of boxes. a liquid crystal layer 50 disposed between the color filter substrate 10 and the array substrate 16; and a layer structure for driving the liquid crystal of the liquid crystal layer 50 to rotate.
  • the layer structure includes: a gate metal layer, a pixel electrode layer, and a common electrode layer.
  • the gate metal layer includes: a connection gate (PLG) trace 15;
  • the common electrode layer includes: an electrically insulating first auxiliary electrode 21 and a common electrode 22; the first auxiliary electrode 21 and the PLG trace 15 Electrical connection.
  • PLG connection gate
  • the common electrode layer and the pixel electrode layer are both formed on the array substrate 16, and the common electrode layer is below the pixel electrode layer, and the pixel electrode layer includes a pixel electrode.
  • the liquid crystal display panel of such a structure drives liquid crystal rotation by a fringe field formed between a common electrode in the common electrode layer and a pixel electrode in the pixel electrode layer.
  • the first auxiliary electrode 21 is electrically connected to the PLG trace 15 for example: the first auxiliary electrode 21 is electrically connected to the PLG trace 15 through the first via 12 .
  • the "lower” is a position close to the array substrate 16.
  • the common electrode layer is below the pixel electrode layer, that is, the common electrode layer is closer to the array substrate 16 than the pixel electrode layer.
  • the pixel electrode layer further includes a second auxiliary electrode 31 electrically insulated from the pixel electrode 32.
  • the second auxiliary electrode 32 is electrically connected to the first auxiliary electrode 21 through the second via hole 12. At this time, the PLG trace 15 and the first auxiliary electrode 21 and the second auxiliary electrode 31 are connected in parallel in the circuit for the purpose of further reducing the resistance of the circuit portion including the PLG trace.
  • the layer structure in the liquid crystal display of the present embodiment can be fabricated by referring to the manufacturing method described in the liquid crystal display panel shown in FIG. 2, and details are not described herein.
  • the first auxiliary electrode 21 can be directly connected to the PLG trace 15 through the first via 12, that is, the first auxiliary electrode 21 and the PLG are in the circuit.
  • the lines are connected in parallel such that the resistance of the circuit portion including the PLG trace 15 is reduced, Furthermore, the purpose of reducing the design complexity of the PLG trace and the precision of its manufacturing process is achieved.
  • the liquid crystal display panel comprises: a color filter substrate 10 and an array substrate 16 of a pair of boxes; a liquid crystal layer 50 disposed between the color filter substrate 10 and the array substrate 16; and a layer structure for driving the liquid crystal of the liquid crystal layer 50 to rotate.
  • the layer structure includes: a gate metal layer, a pixel electrode layer, and a common electrode layer.
  • the gate metal layer includes a connection gate (PLG) trace 15; the common electrode layer includes an electrically insulating first auxiliary electrode 21 and a common electrode 22; the first auxiliary electrode 21 is electrically connected to the PLG trace 15 .
  • the PLG trace 15 is formed, for example, in a peripheral region outside the display area of the liquid crystal panel.
  • the common electrode layer and the pixel electrode layer are both formed on the array substrate 16, and the pixel electrode layer is below the common electrode layer and Includes pixel electrodes.
  • the liquid crystal display panel of this structure is similar to the liquid crystal display panel provided by the second embodiment, and also drives the liquid crystal rotation by the fringe field formed between the common electrode in the common electrode layer and the pixel electrode in the pixel electrode layer. Therefore, the liquid crystal display panel is a fringe electric field switching type.
  • the pixel electrode layer further includes: a second auxiliary electrode 31 electrically insulated from the pixel electrode 32.
  • first auxiliary electrode 21 and the PLG trace 15 are electrically connected to each other as follows.
  • the first auxiliary electrode 21 is electrically connected to the second auxiliary electrode 31 through the second via hole 12, and the second auxiliary electrode 31 is electrically connected to the PLG trace 15 through the first via hole 12.
  • the "lower” is a position close to the array substrate 16; the pixel electrode layer is below the common electrode layer, that is, the pixel electrode layer is closer to the array substrate 16 with respect to the common electrode layer.
  • the common electrode 22 of the above common electrode layer and the pixel electrode 32 of the pixel electrode layer are formed for each sub-pixel of the display region of the liquid crystal panel, that is, each sub-pixel includes the common electrode 22 and the pixel electrode 32.
  • the common electrode 22 may be formed with a slit (not shown) to expose the pixel electrode 32 of the slit.
  • the pixel electrode 32 may be further formed with a slit.
  • the layer structure of the liquid crystal display panel shown in FIG. 3 can be fabricated by referring to the following method: An array substrate having a gate metal layer including a PLG trace, a gate insulating layer, and an active layer sequentially formed thereon is provided.
  • the PLG trace 15 is covered by the gate insulating layer 14 at the edge of the array substrate as shown in FIG. 3; the via hole 12 is formed directly above the PLG by a patterning process; thereafter, the via hole 12 is formed.
  • a pixel electrode layer is formed on the array substrate, and the pixel electrode layer is divided into electrically insulated second auxiliary electrode 31 and pixel electrode 32 by a patterning process; a source/drain metal layer is formed on the array substrate on which the pixel electrode layer is formed, and protection
  • the layer 13 can be formed using the same mask as the first via 12, and the second via 12 is formed on the protective layer 13 at the position of the first via 12; on the array substrate on which the second via 12 is formed.
  • the common electrode layer is divided into electrically-insulated first auxiliary electrode 21 and common electrode 22 by a patterning process.
  • the liquid crystal display comprises: a liquid crystal display panel.
  • the liquid crystal display panel includes: a color filter substrate 10 and an array substrate 16 of a pair of boxes; a liquid crystal layer 50 disposed between the color filter substrate 10 and the array substrate 16; and a liquid crystal rotation for driving the liquid crystal layer 50.
  • the layer structure includes: a gate metal layer, a pixel electrode layer, and a common electrode layer.
  • the gate metal layer includes a connection gate (PLG) trace 15;
  • the common electrode layer includes an electrically insulating first auxiliary electrode 21 and a common electrode 22; the first auxiliary electrode 21 is electrically connected to the PLG trace 15 .
  • PLG connection gate
  • the common electrode layer and the pixel electrode layer are both formed on the array substrate 16, and the pixel electrode layer is below the common electrode layer and Includes pixel electrodes.
  • the liquid crystal display panel of such a structure is similar to the liquid crystal display panel provided by the second embodiment, and also drives the liquid crystal rotation by a fringe field formed between the common electrode in the common electrode layer and the pixel electrode in the pixel electrode layer;
  • the pixel electrode layer further includes a second auxiliary electrode 31 electrically insulated from the pixel electrode 32.
  • first auxiliary electrode 21 and the PLG trace 15 are electrically connected to each other as follows.
  • the first auxiliary electrode 21 is electrically connected to the second auxiliary electrode 31 through the second via hole 12, and the second auxiliary electrode 31 is electrically connected to the PLG trace 15 through the first via hole 12.
  • the "lower” is a position close to the array substrate 16; the pixel electrode layer is below the common electrode layer, that is, the pixel electrode layer is closer to the array substrate 16 with respect to the common electrode layer.
  • the layer structure in the liquid crystal display of the present embodiment can be fabricated by referring to the manufacturing method described in the liquid crystal display panel shown in FIG. 3, and details are not described herein.
  • the first auxiliary electrode 21 is electrically connected to the second auxiliary electrode 31 through the second via hole 12, and the second auxiliary electrode 31 passes the first
  • the via 12 is electrically connected to the PLG trace 15 to thereby make the first auxiliary electrode 21 is electrically connected to the PLG trace 15, that is, the first auxiliary electrode 21 is connected in parallel with the PLG trace 15 in the circuit, so that the resistance of the circuit portion including the PLG trace 15 is reduced, thereby realizing the reduction of the PLG.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种液晶显示面板，包括：对盒的彩膜基板(10)和阵列基板(16)；设置于彩膜基板(10)和阵列基板(16)之间的液晶层(50)；以及用于驱动液晶层(50)的液晶旋转的层结构，层结构包括：栅金属层，像素电极层以及公共电极层；其中，栅金属层包括连接栅极走线(15)；公共电极层包括电性绝缘的第一辅助电极(21)和公共电极(22)，像素电极层包括像素电极(32)，公共电极(22)和像素电极(32)用于形成电场以驱动液晶；其中，第一辅助电极(21)与连接栅极走线(15)电连接以使两者在电路中形成并联。

Description

液晶显示面板及液晶显示器 技术领域
本发明的实施例涉及液晶显示面板及液晶显示器。 背景技术
在传统工艺中， 液晶显示面板中的连接栅极（Propel Link Gate, PLG ) 走线主要用于将源极集成电路（ IC )输出的信号传递至栅极 IC, 或者用于在 至少两个栅极 IC之间传递信号。通常 PLG走线设置在液晶显示面板的边缘， 且与栅线、 存储电容底电极线同层制作。 制作过程如下： 在阵列基板上制作 栅金属薄膜， 通过构图工艺形成栅线、 存储电容电极线以及 PLG走线。
由于 PLG走线的电阻需要小于一上限值从而避免影响液晶显示器的画 面品质， 因此在设计并制作上述 PLG走线的过程中，发明人至少发现以下问 题：
首先， 在设计 PLG走线时， 为了使设计出的 PLG走线的电阻小于该上 限值，在设计版图的时候需要对 PLG走线进行很细致的绘制， 并且需要不断 改变 PLG走线的形状， 以满足该上限值的要求， 这就加大了设计版图的复杂 度； 其次， 在实际制作过程中， 由于工艺的偏差有时会导致 PLG走线的电阻 大于该上限值，为了避免这种工艺偏差，从而提高了对制作工艺精度的要求。 发明内容
本发明实施例提供一种液晶显示面板， 包括： 对盒的彩膜基板和阵列基 板； 设置于所述彩膜基板和阵列基板之间的液晶层； 以及层结构， 用于驱动 所述液晶层的液晶旋转， 所述层结构包括栅金属层、 像素电极层以及公共电 极层， 其中， 所述栅金属层包括连接栅极走线， 所述公共电极层包括电性绝 缘的第一辅助电极和公共电极， 所述像素电极层包括像素电极， 所述公共电 极和所述像素电极用于形成电场以驱动液晶； 其中， 所述第一辅助电极与所 述连接栅极走线电连接以使两者在电路中形成并联。
本发明实施例还提供一种液晶显示器， 包括上述液晶显示面板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例或现有技 术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附图 仅仅涉及本发明的一些实施例， 并非对本发明的限制。
图 1为第一实施例提供的一种液晶显示面板的结构示意图；
图 2为第二实施例提供的一种液晶显示面板的结构示意图；
图 3为第三实施例提供的一种液晶显示面板的结构示意图。 具体实施方式
下面将结合附图，对本发明实施例中的技术方案进行清楚、完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做出创造性劳动前提下 所获得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例提供一种液晶显示面板及液晶显示器，其中 PLG走线可 釆用较低的设计复杂度及制作工艺精度制作完成。
通过将公共电极层形成为包括电性绝缘的第一辅助电极和公共电极， 且 第一辅助电极与 PLG走线电连接以并联， 从而使得包括 PLG走线的电路部 分的电阻有效降低为 PLG走线本身与第一辅助电极并联后的电阻，进而能够 大大降低在设计 PLG走线过程中对 PLG走线绘制的精细程度， 同时还可以 克服工艺变差对 PLG走线的电阻带来的影响， 实现了降低 PLG走线的设计 复杂度及其制作工艺精度的目的。
第一实施例
本发明的该实施例提供了一种液晶显示面板， 如图 1所示。 所述液晶显 示面板包括： 对盒的彩膜基板 10和阵列基板 16; 设置在彩膜基板 10和阵列 基板 16之间的液晶层 50; 以及用于驱动液晶层 50的液晶旋转的层结构。 所 述层结构包括： 栅金属层， 像素电极层以及公共电极层。 栅金属层包括 PLG 走线 15; 所述公共电极层包括电性绝缘的第一辅助电极 21和公共电极 22; 所述第一辅助电极 21与所述 PLG走线 15电连接。该 PLG走线 15例如形成 在液晶面板的显示区域之外的周边区域中。
所述第一辅助电极 21与所述 PLG走线 15电连接，即在电路中所述 PLG 走线 15与所述第一辅助电极 21并联。 这样可以有效的降低包括 PLG走线 15的电路部分的电阻， 从而达到降低 PLG走线 15的设计复杂度及其制作工 艺精度的目的。
进一步的， 在图 1所示的液晶显示面板的实施例中， 所述公共电极层形 成在所述彩膜基板 10上， 所述像素电极层形成在所述阵列基板 16上并且包 括像素电极 32。这种结构的液晶显示面板是通过在公共电极层中的公共电极 和在像素电极层中的像素电极之间形成的垂直电场驱动液晶的旋转。 因此该 液晶显示面板为垂直电场驱动型。 在本实施中， 所述像素电极层还包括与像 素电极 32电性绝缘的第二辅助电极 31。
上述公共电极层的公共电极 22和像素电极层的像素电极 32针对液晶面 板的显示区域的每个亚像素形成， 即，每个亚像素包括公共电极 22和像素电 极 32。
这种情况下，所述第一辅助电极 21与所述 PLG走线 15电连接可以如下 方式形成。 所述第一辅助电极 21与所述第二辅助电极 31电连接， 以及所述 第二辅助电极 31例如通过过孔 12与所述 PLG走线 15电连接。
具体的， 上述层结构可如下制作。
提供阵列基板 16, 其具有依次形成在其上的包括 PLG走线的栅金属层、 栅绝缘层、 有源层、 源漏金属层、 保护层。 在阵列基板 16的边缘， PLG走 线 15被栅绝缘层 14和保护层 13覆盖， 如图 1所示； 通过构图工艺在 PLG 走线正上方的各层中制作过孔 12, 以将 PLG走线部分暴露； 之后， 在形成 有过孔 12的阵列基板上制作像素电极层，并通过构图工艺将该像素电极层分 成电性绝缘的第二辅助电极 31和像素电极 32。
例如， 在该液晶显示面板中， 第一辅助电极 21与第二辅助电极 31电连 接可以如下方式实现。 所述第一辅助电极 21通过导电胶 11与所述第二辅助 电极 31电连接； 例如， 所述导电胶 11为各向异性导电胶； 各向异性导电胶 例如竖向导电， 而横向不导电。所述导电胶 11的一个示例可以为掺入了金球 ( Au Ball ) 的封框胶（seal胶） 。
本发明的该实施例还提供一种应用上述液晶显示面板的液晶显示器。 所 述液晶显示器包括： 液晶显示面板。 参考图 1 , 所述液晶显示面板包括： 对 盒的彩膜基板 10和阵列基板 16; 设置在在彩膜基板 10和阵列基板 16之间 的液晶层 50; 以及用于驱动液晶层 50的液晶旋转的层结构。 所述层结构包 括： 栅金属层、 像素电极层以及公共电极层。 栅金属层包括连接栅极（PLG ) 走线 15。 所述公共电极层包括电性绝缘的第一辅助电极 21和公共电极 22。 所述第一辅助电极 21与所述 PLG走线 15电连接。
所述第一辅助电极 21与所述 PLG走线 15电连接，即在电路中所述 PLG 走线 15与所述第一辅助电极 21并联， 这样可以有效的降低包括 PLG走线 15的电路部分的电阻， 从而达到降低 PLG走线 15的设计复杂度及其制作工 艺精度的目的。
进一步的， 在所述液晶显示器中， 所述公共电极层形成在所述彩膜基板 10上， 所述像素电极层形成在所述阵列基板 16上且包括像素电极 32。 这种 结构的液晶显示面板是通过在公共电极层中的公共电极和在像素电极层中的 像素电极之间形成的垂直电场驱动液晶的旋转。 在本实施中， 所述像素电极 层还包括与像素电极 32电性绝缘的第二辅助电极 31。
这种情况下，所述第一辅助电极 21与所述 PLG走线 15电连接可以如下 方式形成。 所述第一辅助电极 21与所述第二辅助电极 31电连接， 以及所述 第二辅助电极 31通过过孔 12与所述 PLG走线 15电连接。
本实施例的液晶显示器中的层结构可以参考针对图 1所示液晶显示面板 所介绍的制作方法来制作， 在此不加赘述。
例如，在所述液晶显示器中，所述第一辅助电极 21与所述第二辅助电极 31电连接可以如下方式实现。所述第一辅助电极 21通过导电胶 11与所述第 二辅助电极 31电连接； 例如， 所述导电胶 11为各向异性导电胶； 各向异性 导电胶例如竖向导电，横向不导电。所述导电胶 11的一个示例可以为掺入了 金球（Au Ball ) 的封框胶（seal胶） 。
本发明实施例提供的液晶显示面板及液晶显示器中， 所述第一辅助电极 21通过所述导电胶 11与所述第二辅助电极 31电连接，所述第二辅助电极 31 通过过孔 12与所述 PLG走线 15电连接， 这样， 所述 PLG走线 15与所述第 一辅助电极 21之间就可以电连接， 即在电路中所述第一辅助电极 21和所述 PLG走线 15并联， 便可使包括 PLG走线 15的电路部分的电阻降低， 即可 达到降低 PLG走线的设计复杂度及其制作工艺精度的目的。
第二实施例 本发明的该实施例提供了一种液晶显示面板， 如图 2所示。 所述液晶显 示面板包括： 对盒的彩膜基板 10和阵列基板 16; 设置在彩膜基板 10和阵列 基板 16之间的液晶层 50; 以及用于驱动液晶层 50的液晶旋转的层结构。 所 述层结构包括： 栅金属层， 像素电极层以及公共电极层。 栅金属层包括： 连 接栅极（PLG )走线 15; 所述公共电极层包括： 电性绝缘的第一辅助电极 21 和公共电极 22; 所述第一辅助电极 21与所述 PLG走线 15电连接。 该 PLG 走线 15例如形成在液晶面板的显示区域之外的周边区域中。
进一步的， 在图 2所示的液晶显示面板的实施例中， 所述公共电极层和 所述像素电极层均形成在所述阵列基板 16上，且所述公共电极层在所述像素 电极层的下方， 所述像素电极层包括像素电极。 这种结构的液晶显示面板通 过在公共电极层中的公共电极和在像素电极层中的像素电极之间形成的边缘 场驱动液晶旋转。 因此该液晶显示面板为边缘电场切换型。 在这样的液晶显 示面板中， 所述第一辅助电极 21与所述 PLG走线 15电连接例如为： 所述第 一辅助电极 21通过过孔 12与所述 PLG走线 15电连接。
所述 "下方"为更靠近阵列基板 16的位置。 所述公共电极层在所述像素 电极层的下方， 即为所述公共电极层相对于所述像素电极层而言更靠近阵列 基板 16。
上述公共电极层的公共电极 22和像素电极层的像素电极 32针对液晶面 板的显示区域的每个亚像素形成， 即，每个亚像素包括公共电极 22和像素电 极 32。 另外， 像素电极 32可以形成有狭缝（未示出） ， 以露出狭缝的公共 电极 22。 或者， 公共电极 22也可以进一步形成有狭缝。
具体的， 可以参考如下方法制作图 2所示的液晶显示面板的层结构。 提供阵列基板， 其上依次形成有栅金属层、 栅绝缘层、 有源层。 如图 2 所示， PLG走线 15形成在阵列基板 16的边缘， 被栅绝缘层 14覆盖； 通过 构图工艺在 PLG走线 15正上方制作过孔 12; 之后， 在形成过孔 12的阵列 基板上制作公共电极层， 并通过构图工艺将该公共电极层分成电性绝缘的第 一辅助电极 21和公共电极 22; 在形成有公共电极层的阵列基板上制作第一 保护层、 源漏金属层、第二保护层以及像素电极层； 图 2中的保护层 13包括 第一保护层和第二保护层。
为进一步的减小包括 PLG走线的电路部分的电阻，如图 2所示， 所述像 素电极层包括像素电极 32和与像素电极 32电性绝缘的第二辅助电极 31。 所述第二辅助电极 31通过第二过孔 12与所述第一辅助电极 21电连接。 显然， 此时 PLG走线和第一辅助电极 21、 第二辅助电极 31并联在电路 中， 达到进一步减小包括 PLG走线的电路部分的电阻的目的。
本发明的该实施例还提供了应用上述液晶显示面板的液晶显示器。 所述 液晶显示器包括： 液晶显示面板。 参考图 2, 所述液晶显示面板包括： 对盒 的彩膜基板 10和阵列基板 16。 设置在彩膜基板 10和阵列基板 16之间的液 晶层 50; 以及用于驱动液晶层 50的液晶旋转的层结构。 所述层结构包括： 栅金属层， 像素电极层以及公共电极层。 栅金属层包括： 连接栅极（PLG ) 走线 15; 所述公共电极层包括： 电性绝缘的第一辅助电极 21和公共电极 22; 所述第一辅助电极 21与所述 PLG走线 15电连接。
进一步的，所述公共电极层和所述像素电极层均形成在所述阵列基板 16 上， 且所述公共电极层在所述像素电极层的下方， 所述像素电极层包括像素 电极。 这种结构的液晶显示面板通过在公共电极层中的公共电极和在像素电 极层中的像素电极之间形成的边缘场驱动液晶旋转。 在这样的液晶显示面板 中， 所述第一辅助电极 21与所述 PLG走线 15电连接例如为： 所述第一辅助 电极 21通过第一过孔 12与所述 PLG走线 15电连接。
所述 "下方"为靠近阵列基板 16的位置。 所述公共电极层在所述像素电 极层的下方， 即为所述公共电极层相对与所述像素电极层而言更靠近阵列基 板 16。
为进一步的减小包括 PLG走线的电路部分的电阻，如图 2所示， 所述像 素电极层还包括与像素电极 32电性绝缘的第二辅助电极 31。
所述第二辅助电极 32通过第二过孔 12与所述第一辅助电极 21电连接。 此时 PLG走线 15和第一辅助电极 21、 第二辅助电极 31并联在电路中， 达到进一步减小包括 PLG走线的电路部分的电阻的目的。
需要说明的是， 本实施例的液晶显示器中的层结构可以参考针对图 2所 示液晶显示面板所介绍的制作方法来制作， 在此不加赘述。
本发明实施例提供的液晶显示面板及液晶显示器，第一辅助电极 21可直 接通过第一过孔 12与所述 PLG走线 15电连接，即在电路中所述第一辅助电 极 21与 PLG走线并联，从而使得包括 PLG走线 15的电路部分的电阻减小， 进而实现了降低 PLG走线的设计复杂度及其制作工艺精度的目的。
第三实施例：
本发明的该实施例提供了一种液晶显示面板， 如图 3所示。 所述液晶显 示面板包括： 对盒的彩膜基板 10和阵列基板 16; 设置在彩膜基板 10和阵列 基板 16之间的液晶层 50; 以及用于驱动液晶层 50的液晶旋转的层结构。 所 述层结构包括： 栅金属层， 像素电极层以及公共电极层。 栅金属层包括连接 栅极 ( PLG )走线 15; 所述公共电极层包括电性绝缘的第一辅助电极 21和 公共电极 22; 所述第一辅助电极 21与所述 PLG走线 15电连接。 该 PLG走 线 15例如形成在液晶面板的显示区域之外的周边区域中。
进一步的， 在图 3所示的液晶显示面板中， 所述公共电极层和所述像素 电极层均形成在所述阵列基板 16上，且所述像素电极层在所述公共电极层的 下方且包括像素电极。 这种结构的液晶显示面板同第二实施例提供的液晶显 示面板相似， 也是通过公共电极层中的公共电极和像素电极层中的像素电极 之间形成的边缘场驱动液晶旋转。 因此该液晶显示面板为边缘电场切换型。 在这样的液晶显示面板中，所述像素电极层还包括： 与像素电极 32电性绝缘 的第二辅助电极 31。
进一步的，所述第一辅助电极 21与所述 PLG走线 15电连接可以如下方 式实现。所述第一辅助电极 21通过第二过孔 12与所述第二辅助电极 31电连 接， 所述第二辅助电极 31通过第一过孔 12与所述 PLG走线 15电连接。
所述 "下方"为靠近阵列基板 16的位置； 所述像素电极层在所述公共电 极层的下方， 即为所述像素电极层相对于所述公共电极层而言更靠近阵列基 板 16。
上述公共电极层的公共电极 22和像素电极层的像素电极 32针对液晶面 板的显示区域的每个亚像素形成， 即，每个亚像素包括公共电极 22和像素电 极 32。 另外， 公共电极 22可以形成有狭缝（未示出） ， 以露出狭缝的像素 电极 32。 或者， 像素电极 32也可以进一步形成有狭缝。
具体的， 可以参考如下方法制作图 3所示的液晶显示面板的层结构： 提供阵列基板， 其具有依次形成在其上的包括 PLG走线的栅金属层、栅 绝缘层、 有源层的。 PLG走线 15在阵列基板的边缘被栅绝缘层 14覆盖， 如 图 3所示； 通过构图工艺在 PLG正上方制作过孔 12; 之后， 在形成过孔 12 的阵列基板上制作像素电极层， 并通过构图工艺将该像素电极层分成电性绝 缘的第二辅助电极 31和像素电极 32; 在形成有像素电极层的阵列基板上制 作源漏金属层、 保护层 13 , 可以使用与制作第一过孔 12相同的掩膜板， 在 保护层 13上第一过孔 12的位置形成第二过孔 12; 在形成有第二过孔 12的 阵列基板上制作公共电极层， 并通过构图工艺将所述公共电极层分为电性绝 缘的第一辅助电极 21和公共电极 22。
本发明的该实施例还提供了应用上述液晶显示面板的液晶显示器。 所述 液晶显示器包括： 液晶显示面板。 参考图 1 , 所述液晶显示面板包括： 对盒 的彩膜基板 10和阵列基板 16; 设置在彩膜基板 10和阵列基板 16之间的液 晶层 50; 以及用于驱动液晶层 50的液晶旋转的层结构。 所述层结构包括： 栅金属层， 像素电极层以及公共电极层。 栅金属层包括连接栅极（PLG )走 线 15; 所述公共电极层包括电性绝缘的第一辅助电极 21和公共电极 22; 所 述第一辅助电极 21与所述 PLG走线 15电连接。
进一步的， 在图 3所示的液晶显示面板中， 所述公共电极层和所述像素 电极层均形成在所述阵列基板 16上，且所述像素电极层在所述公共电极层的 下方且包括像素电极。 这种结构的液晶显示面板同第二实施例提供的液晶显 示面板相似， 也是通过在公共电极层中的公共电极和在像素电极层中的像素 电极之间形成的边缘场驱动液晶旋转； 在这样的液晶显示面板中， 所述像素 电极层还包括与像素电极 32电性绝缘的第二辅助电极 31。
进一步的，所述第一辅助电极 21与所述 PLG走线 15电连接可以如下方 式实现。所述第一辅助电极 21通过第二过孔 12与所述第二辅助电极 31电连 接， 所述第二辅助电极 31通过第一过孔 12与所述 PLG走线 15电连接。
所述 "下方"为靠近阵列基板 16的位置； 所述像素电极层在所述公共电 极层的下方， 即为所述像素电极层相对于所述公共电极层而言更靠近阵列基 板 16。
需要说明的是， 本实施例的液晶显示器中的层结构可以参考针对图 3所 示液晶显示面板所介绍的制作方法来制作， 在此不加赘述。
本发明的该实施例提供的液晶显示面板及液晶显示器中， 所述第一辅助 电极 21通过第二过孔 12与所述第二辅助电极 31电连接，所述第二辅助电极 31通过第一过孔 12与所述 PLG走线 15 电连接， 从而使所述第一辅助电极 21和所述 PLG走线 15电连接，即在电路中所述第一辅助电极 21与所述 PLG 走线 15并联，使得包括 PLG走线 15的电路部分的电阻减小，从而实现了降 低 PLG走线 15的设计复杂度及其制作工艺精度的目的。
以上所述， 仅为本发明的一些实施方式， 但本发明的保护范围并不局限 于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保护 范围应以所述权利要求的保护范围为准。

Claims

权利要求书
1、 一种液晶显示面板， 包括：
对盒的彩膜基板和阵列基板；
设置于所述彩膜基板和阵列基板之间的液晶层； 以及
层结构， 用于驱动所述液晶层的液晶旋转， 所述层结构包括栅金属层、 像素电极层以及公共电极层，
其中， 所述栅金属层包括连接栅极走线， 所述公共电极层包括电性绝缘 的第一辅助电极和公共电极， 所述像素电极层包括像素电极， 所述公共电极 和所述像素电极用于形成电场以驱动液晶；
其中， 所述第一辅助电极与所述连接栅极走线电连接以使两者在电路中 形成并联。
2、根据权利要求 1所述的液晶显示面板， 其中， 所述公共电极层形成在 所述彩膜基板上， 所述像素电极层形成在所述阵列基板上。
3、根据权利要求 2所述的液晶显示面板， 其中， 所述像素电极层还包括 与所述像素电极电性绝缘的第二辅助电极，
所述第一辅助电极与所述第二辅助电极电连接， 并且所述第二辅助电极 通过过孔与所述连接栅极走线电连接。
4、根据权利要求 3所述的液晶显示面板， 其中， 所述第一辅助电极通过 导电胶与所述第二辅助电极电连接。
5、根据权利要求 4所述的液晶显示面板， 其中， 所述导电胶为各向异性 导电胶。
6、根据权利要求 1所述的液晶显示面板， 其中， 所述公共电极层和所述 像素电极层均形成在所述阵列基板上方， 且所述公共电极层在所述像素电极 层的下方；
所述第一辅助电极通过第一过孔与所述连接栅极走线直接电连接。
7、根据权利要求 6所述的液晶显示面板， 其中， 所述像素电极层还包括 与所述像素电极电性绝缘的第二辅助电极；
所述第二辅助电极通过第二过孔与所述第一辅助电极电连接。
8、根据权利要求 7所述的液晶显示面板， 其中， 所述像素电极形成有狭 缝。
9、根据权利要求 1所述的液晶显示面板， 其中， 所述公共电极层和所述 像素电极层均形成在所述阵列基板上方， 且所述像素电极层在所述公共电极 层的下方；
所述像素电极层还包括与所述像素电极电性绝缘的第二辅助电极； 和 所述第一辅助电极通过第二过孔与所述第二辅助电极电连接， 以及所述 第二辅助电极通过第一过孔与所述连接栅极走线电连接。
10、 根据权利要求 9所述的液晶显示面板， 其中， 所述公共电极形成有 狭缝。
11、 一种液晶显示器， 包括权利要求 1所述的液晶显示面板。
PCT/CN2012/079530 2011-08-02 2012-08-01 液晶显示面板及液晶显示器 WO2013017088A1 (zh)

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