WO2014202409A1 - Transistor et procédé de fabrication d'un transistor - Google Patents

Transistor et procédé de fabrication d'un transistor Download PDF

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Publication number
WO2014202409A1
WO2014202409A1 PCT/EP2014/061800 EP2014061800W WO2014202409A1 WO 2014202409 A1 WO2014202409 A1 WO 2014202409A1 EP 2014061800 W EP2014061800 W EP 2014061800W WO 2014202409 A1 WO2014202409 A1 WO 2014202409A1
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WIPO (PCT)
Prior art keywords
layer
transistor
carrier substrate
recess
semiconductor
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PCT/EP2014/061800
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German (de)
English (en)
Inventor
Walter Daves
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to EP14730126.1A priority Critical patent/EP3011598A1/fr
Priority to JP2016520370A priority patent/JP2016524819A/ja
Priority to CN201480034526.XA priority patent/CN105283959A/zh
Publication of WO2014202409A1 publication Critical patent/WO2014202409A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a transistor and a method of manufacturing a transistor.
  • a HEMT transistor (high-electron mobility transistor) is a special design of the field effect transistor, which passes through a conductive channel with a high
  • Carrier mobility distinguishes.
  • this channel is formed by heteroepitaxially growing a suitable semiconductor heterostructure on a substrate which is as inexpensive as possible, for example silicon.
  • Transistor fabrication is possible to eliminate the substrate leakage currents and thus a significant improvement in the breakdown properties of the
  • Gallium nitride film with a low defect density by gas-phase epitaxy Gallium nitride film with a low defect density by gas-phase epitaxy.
  • the present invention provides a transistor and a method for producing a transistor according to the main claims.
  • Advantageous embodiments emerge from the respective subclaims and the following description.
  • the present invention provides a transistor comprising: a carrier substrate;
  • heterostructure a second semiconductor layer of a second semiconductor material applied to the first semiconductor layer, the band gap of the first semiconductor material being different from the band gap of the second semiconductor material (so-called heterostructure);
  • drain terminal and a source terminal which are embedded at least in the second semiconductor layer, wherein by means of
  • Drain terminal and the source terminal at least one boundary layer between the first and second semiconductor material is electrically contacted;
  • Source terminal opposite side of the carrier substrate is disposed and at least partially overlaps the channel region, wherein a lateral edge of the recess is covered by an insulating layer.
  • the present invention provides a method of manufacturing a transistor, the method comprising the steps of:
  • drain terminal and a source terminal which are embedded at least in the second semiconductor layer, wherein by means of the drain terminal and the source terminal at least one
  • Boundary layer between the first and second semiconductor material is electrically contacted and by the drain terminal and the source terminal, a channel region between the drain terminal and the source terminal is defined;
  • Insulation layer is covered.
  • a carrier substrate can be understood as meaning a layer of a single material or a composite of several material layers.
  • Control range can be understood, for example, the channel of a transistor, in particular a field effect transistor.
  • a field-effect transistor can be understood, for example.
  • a recess may be understood to mean a recess or opening in the carrier substrate or at least a part of the carrier substrate.
  • a lateral edge of the recess may be understood to mean a lateral edge and / or a bottom of the recess which is covered by the insulating layer.
  • an insulating layer for example, a layer of Si0 2 , Si 3 N4 or AIN can be understood: This
  • Isolation layer for example, by passivating trained
  • a portion of the carrier substrate can be made thinner, so that a leakage current through this thinner portion of the carrier substrate would encounter a greater resistance, which reduces or completely prevents this leakage.
  • the insulating layer which is arranged on a lateral edge of the recess, thus can continue to establish an isolation barrier against a normally occurring leakage current.
  • the provision of the recess with the insulating layer also offers a possibility for thermal coupling with a heat dissipation facility, so that there is also a possibility to use the transistor according to the approach presented here also for switching higher powers, in which a greater heat development in the transistor to expect and dissipate this heat accordingly.
  • the insulating layer extends from the recess to a main surface of the carrier substrate opposite the gate connection.
  • the insulating layer can also extend to a region of the carrier substrate, in which there is no interpretation.
  • Insulation layer in such an arrangement particularly safe to prevent or at least reduce leakage.
  • a filling layer which has a thermal and / or electrically conductive material is arranged at least in the region of the recess on a side of the insulating layer opposite the carrier substrate.
  • a filling layer which has a thermal and / or electrically conductive material
  • it can be deposited in the form of a layer or layer, so that a surface connection to the insulating layer is possible, via which a heat dissipation and / or power supply of an element of the transistor is made technically simple.
  • the filling layer may comprise, at least in the region of the recess, a metallic material, in particular copper, polysilicon, in particular a doped polysilicon and / or a SiC, in particular a highly doped SiC.
  • a metallic material in particular copper, polysilicon, in particular a doped polysilicon and / or a SiC, in particular a highly doped SiC.
  • the recess should have a depth, so that a partial layer of the first semiconductor layer between the first semiconductor layer and the insulating layer
  • Carrier substrate is arranged.
  • Such a sub-layer of the carrier substrate may comprise a homogeneous material and be, for example, a buffer layer formed by a material consisting of or at least partially comprising silicon dioxide, silicon nitride or aluminum nitride.
  • An embodiment of the present invention in which a further carrier substrate covering the second semiconductor layer, the source terminal, the drain terminal and / or the gate terminal is particularly stable is provided.
  • Such an embodiment of the present invention offers the advantage of a possibility of compensation by the recess in the
  • Support substrate formed weakening of the holding force of the carrier substrate by the additional holding force of the other carrier substrate.
  • a further recess may be provided which differs from one of the gate terminal opposite side of the carrier substrate extends to the first or second semiconductor layer, in particular wherein the further recess is disposed in a non-overlapping the channel region portion of the carrier substrate.
  • the further recess laterally adjacent to the drain or the source outside the
  • Channel or channel region may be arranged.
  • Edge of the further recess at least partially the insulating layer or a further insulating layer may be arranged. Under one edge of a
  • Recess or further exercise for example, a side wall and / or the bottom of the further recess to the carrier substrate to be understood.
  • the filling layer or a further filling layer is arranged, which have a thermal and / or electrically conductive material, in particular wherein the further filling layer with the source terminal, the Drain connection or the boundary layer is electrically conductively connected.
  • the first and second semiconductor materials may form an Ill / V compound semiconductor composite.
  • Another advantage is an embodiment of the present invention in which the first semiconductor material AIGaN and the second semiconductor material comprises GaN, or in which the first semiconductor material GaN and the second
  • Semiconductor material AIGaN includes. Such an embodiment of
  • present invention offers the advantage that technically particularly good and easy to process semiconductor materials can be used for a transistor, so that such a transistor in addition to its good
  • Carrier substrate has a holding layer made of a holding material, wherein the holding material is different from a main material of the carrier substrate, in particular wherein the main material of the carrier substrate comprises silicon, wherein the first semiconductor material is arranged on the holding layer.
  • a holding layer made of a holding material, wherein the holding material is different from a main material of the carrier substrate, in particular wherein the main material of the carrier substrate comprises silicon, wherein the first semiconductor material is arranged on the holding layer.
  • the gate connection and the channel region may be electrically insulated by gate oxide or gate dielectric layer, in particular wherein at least one predetermined type of charge carriers is embedded in the gate oxide layer or gate dielectric layer and / or wherein the gate oxide layer or gate dielectric layer has a predetermined density Containing charge carriers.
  • Such an embodiment of the present invention offers the advantage of the possibility of adjusting a conductivity type of the transistor, in particular the characteristic of the transistor as self-blocking or self-conducting.
  • a breakdown voltage or activation voltage can be set by a thickness of the gate oxide layer (gate dielectric layer) and / or the density of the predetermined charge carriers in the gate oxide layer (gate dielectric layer).
  • Fig. 1 is a cross-sectional view through a transistor according to a
  • 2A to 2C are cross-sectional views through a transistor according to a
  • FIG. 3 is a cross-sectional view through a transistor according to a
  • FIG. 4 is a cross-sectional view through a transistor according to a
  • Fig. 5 is a cross-sectional view through a transistor according to a
  • FIG. 6 is a flowchart of a method according to a
  • the transistor 100 includes a semiconductor or carrier substrate 1 10, which is a main component 1 15
  • the buffer layer 120 may be made of an aluminum nitride layer followed by a suitable sequence of AIGaN layers with decreasing Al concentration, for example, which optimally adapts to the lattice structure of the layer to be deposited on the carrier substrate.
  • the buffer layer 120 serves as a very good adhesion base for one the buffer layer 120 disposed semiconductor heterostructure 125th
  • This semiconductor heterostructure 125 may be, for example, a stack of two layers of different semiconductor materials.
  • these different semiconductor materials may consist of or comprise semiconductor materials having a different band gap or a different band gap
  • the semiconductor materials of Heterostructure 125 can thereby be arranged as a first semiconductor layer 130 (made of a first semiconductor material) and a second semiconductor layer 135 (made of a second semiconductor material) arranged on the first semiconductor layer and an III-V semiconductor composite or an III-V semiconductor Form composite system. This means that the semiconductor material of the first semiconductor layer
  • the semiconductor material of the second semiconductor layer 135 may be a V material (i.e., a material of the 5th main group of the Periodic Table).
  • the first semiconductor material may be a V-type material and the second semiconductor material may be an III-type material.
  • the first semiconductor material AIGaN and the second semiconductor material may be GaN (or comprise these materials accordingly) or vice versa.
  • an interface layer 140 is formed, in which electrons have a particularly high mobility.
  • Boundary layer 140 acts as a two-dimensional electron gas (2DEG) and offers a very good circuit option for high power, d. H. high currents and / or voltages.
  • 2DEG two-dimensional electron gas
  • a drain terminal 145 and a source terminal 150 are provided, which extends through the second semiconductor layer 135 as far as the barrier layer 140 or into the first semiconductor layer. Laterally to the drain terminal 145 and the source terminal 150, d. H. each to the other connection
  • a lateral insulating layer 153 is provided, which is a drain of electrons from a channel region 160 between the
  • Gate oxide layer 165 arranged as a gate dielectric. On the gate oxide layer 165, a gate terminal 170 is provided in the region of the channel region 155, so that the transistor 100 is formed as a field-effect transistor. In that sense, the
  • Channel region 155 also be understood as a channel of a field effect transistor.
  • the gate oxide layer 165 is now "contaminated” or doped with charge carriers Gatean gleich 170 voltage applied to the charge carrier mobility in the channel region 155 and / or in the boundary layer 140 to be changed.
  • a recess 180 can be arranged on the carrier substrate 110. This recess 180 is arranged or formed in particular in the main material 1 15 of the carrier substrate 1 10, wherein the buffer layer 120 between the first
  • Lateral walls or edges 182 and a bottom 183 of the recess 180 are of a
  • Insulating layer 185 covered, which consists for example of an electrically insulating material such as SiO 2, Si 3 N 4 or AIN. Furthermore, this insulating layer 185 can also be applied over a main surface 186 of the
  • Main material or main component 1 15 extend out of the support substrate 1 10, in which no recess 180 is included. As a result, a particularly good electrical insulation can be achieved. Furthermore, a filling layer 187 may be applied to a side of the insulating layer opposite the carrier substrate 1 10. This filling layer 187 may include, for example, a thermally and / or electrically conductive material such as copper, doped polysilicon or highly doped SiC or from such
  • This filling layer 187 can, for example, fill up the still remaining recess (notwithstanding the existing insulating layer 185) of the recess 180 so that the insulating layer 185 is sandwiched between the edges 182 and the bottom 183 of the recess 180 on the one hand and the filling layer 187 on the other hand.
  • the recess 180 and the insulating layer 185 onto the edges 182 and the bottom 183 of the recess 180, a leakage current through the carrier substrate 110 or a part (such as the main component 15) of the carrier substrate 110 can thus be at least reduced. if not completely prevent.
  • the recess should be arranged in at least one section 190 of the carrier substrate 110 which at least partially overlaps into the channel region 155.
  • the insulation layer 185 should not be less than 0.1 ⁇ m, for example, in order to ensure a sufficient electrical insulation effect.
  • insulating layer 185 should also have a thickness of not more than 10 ⁇ m to have a sufficiently high thermal conductivity through the
  • Insulation layer 185 to ensure. In this way, heat generated during operation of the transistor 100, via the carrier substrate 1 10, the
  • Insulating layer 185 and the filling layer 187 are discharged. Insofar as shown in FIG. 1 deposition of an insulating layer 185 and the serves
  • Isolation layer 185 remaining trench with a thermal and / or electrically conductive (filling) layer 187 of an improvement of the properties of the transistor 100 over conventional transistors.
  • the (optional) gate oxide layer 165 (which is also known as
  • Gatedielektrikum can be formed), the drain terminal 150, the
  • Source 145 and / or the gate 170 may be protected by a protective layer 195.
  • This protective layer 195 may be formed, for example, as a protective lacquer.
  • the protective layer 195 may be applied directly to the gate oxide layer 165 and the gate terminal 170 and cover these mentioned elements. This makes it possible to protect the transistor 100 or a surface of the transistor 100 from damage or environmental influences.
  • the above-described structure of a transistor 100 may be referred to as a standard gate dielectric dielectric HEMT structure.
  • the structure of the HEMT transistor consists of layers of different semiconductor materials with different sized band gaps (so-called heterostructure).
  • compound semiconductors are suitable for this purpose, which consist of elements of the III / V
  • the material system GaN / AIGaN can be used. If these two materials are separated, a two-dimensional electron gas is formed at the interface of these materials on both sides of the GaN, which can serve as a conductive channel, since the electron mobility therein is very high (typically
  • GaN HEMT transistors can be produced by epitaxially depositing GaN / AlGaN heterostructures on Si, SiC or sapphire substrates. These components are always self-conducting due to the presence of the highly conductive channel. Self-locking components are, however, in many Applications, for example in the automotive sector, for safety and circuit aspects desired. Therefore, in order to realize self-blocking GaN devices, it is necessary to locally destroy the 2DEG in the interface 140 by a suitable method in the channel region. Although several such methods already appear successful, such as local
  • a structure is proposed which addresses this problem and makes it possible to realize high-performance self-blocking transistors based on GaN.
  • GaN HEMT transistors are usually epitaxial
  • GaN / AIGaN heterostructures on Si, SiC or sapphire substrates.
  • Heteroepitaxy of GaN on Si is particularly critical to stress evolution in the grown layer due to the large lattice mismatch between Si and GaN.
  • Si is mechanically unstable at the typical growth temperatures for GaN (1000-1200 ° C). Due to the comparatively better mechanical and thermal properties, preference is therefore given to choosing doped Si (1: 1) substrates for growth.
  • Heterostructure interface 140 move, for example, in the GaN / AIGaN material system.
  • the heterostructure 125 can be contacted laterally by source 150 and drain terminals 145, and the channel region 155 between source 155 and drain 145 is controlled by a gate electrode 170.
  • Gate electrode 170 is from channel region 155 through a gate dielectric Separate 165 in which specifically stable charges can be introduced, which set the threshold voltage of the transistor 100.
  • One approach of such a device fabrication process may include the following steps, as explained in greater detail with respect to FIG. 2A.
  • a deposition of a buffer layer 120 (buffer layer) and a GaN / AlGaN heterostructure 125 on a main component 15 of a carrier substrate 110 may take place.
  • This deposition may be in the form of depositing MOCVD-GaN / AlGaN layers 125 on a highly doped Si (11) 1 substrate as major constituent 15.
  • a heterostructure 125 consisting of or containing a first semiconductor layer 130 of a first semiconductor material, such as GaN, and containing a second semiconductor layer 135 of a second semiconductor material, such as AIGaN, may be formed a so-called 2-dimensional
  • Electron gas is present, which is a particularly good electrical
  • Conductivity of the device to be manufactured, d. H. of the transistor 100 allows.
  • a lateral component isolation can be carried out in the area 153, as shown for example in FIG. 2B. This isolation can be done, for example, by ion implantation in the lateral isolation layer 153 of the transistor 100 of FIG.
  • This is followed by an optional deposition of a gate dielectric 165 into which charges can be introduced in a targeted manner. These charges cause, depending on the polarity,
  • a shift in the electrical properties of the HEMT transistor 100 can be prepared as a transistor 100.
  • deposition and patterning of a gate electrode 170 may occur, followed by contacting of the 2DEG (i.e., barrier layer 140) by source 150 and drain 145 terminals.
  • FIG. 2B Cross-sectional view of FIG. 2B, a semifinished product, which allows a standard HEMT production with lateral isolation by implantation and optimal gate dielectric and representation of Substratleckstrompfade.
  • the approach presented here now allows an improvement of the
  • Breakthrough property to realize, for example, by otherwise occurring (substrate) leakage currents 200 can be prevented or at least reduced.
  • a protective layer is now first of all shown on FIG. 2C on a front side (ie the side on which the gate electrode 170 is located) of the transistor prepared in accordance with the aforementioned method steps 195, for example, applied from protective lacquer. Thereafter, a thinning of the carrier substrate 1 10 and a local removal of the
  • a recess 180 in the carrier substrate is made by removing the main component 15 in the section 190, this section 190 at least partially overlapping the channel region 155.
  • the insulating layer is now applied to the edges 182 and the bottom 183 of the recess 180, so that the transistor 100 results, as shown in FIG. 1. To better align the local distance, a better mechanical
  • a etching for the front side is performed to make a trench 300 (or a trench) on or from the front side of the transistor 100.
  • This trench 310 extends from the gate oxide layer 165 to the skin component 1 15 of the carrier substrate 1 10 and forms an opening in the carrier substrate 1 10 or the entire transistor 100.
  • a passivation layer 310 is deposited on the front side of the transistor 100, for example
  • Si02 or Si0 2 at least partially contains.
  • another carrier substrate 320 is now glued to stabilize the transistor 100 for further fabrication steps.
  • the trench 300 can be used for electrical and / or thermal contacting of the drain connection 150 from the rear side (ie the side on which the main component 1 15 of FIG.
  • Support substrate 1 10 is arranged) can be used, as will be described in more detail below.
  • the trench 300 at its edges and bottom (that is to say the boundary to the passivation layer 310) itself, can now be used for this purpose
  • Insulation layer 185 is arranged, and is now filled with the filling layer 187, carried out a thermal coupling of the drain terminal 150 from the back of the transistor 100.
  • this trench 300 can be understood as a further recess (similar to the recess 180). However, such a further recess 300 is made from the front side of the transistor 100, and not like the recess 180 from the backside of the transistor 100, but for the function of the other
  • Recess 300 is irrelevant.
  • Source 145 are thermally and / or electrically contacted by such a filled trench 300.
  • the insulation layer 185 has a corresponding opening or at least electrical permeability, for example, the drain connection 150 also from the rear side of the transistor 100 to contact.
  • the filling layer can thus be used as an optional back gate.
  • Bach drain electrode can be used.
  • an electrical contacting of a connection such as the drain connection can then be achieved, for example by an electrically conductive material of the filling layer 187 (which is arranged in the further recess 300)
  • the transistor s100 can be realized as a vertical component, which enables a contacting possibility by the carrier substrate.
  • the transistor s100 can be realized as a vertical component, which enables a contacting possibility by the carrier substrate.
  • Embodiments presented manufacturing method allows to achieve a significant improvement of the breakdown characteristics and thus an increase in the reliability of GaN power transistors. Furthermore, the manufacturing method presented here in different embodiments allows an improvement of the thermal properties and an additional
  • the transistor 100 can be provided as a component, which is characterized in that the charge carriers are arranged on a 2-dimensional heterostructure interface move, for example in the GaN / AIGaN material system.
  • a heterostructure may be contacted laterally by source 145 and drain terminals 150, and the channel region 155 between source 145 and drain terminal 150 is controlled by a gate electrode 170.
  • the (support) substrate 110 may be thinned by anisotropic ion etching after fabrication of a transistor precursor and removed behind the active transistor structure. The thus formed holes 300 and 180 (the recesses form), for example, by a metal with high thermal
  • Conductor filled for example, coated by copper by electroplating or electroplating and optionally used as an additional electrode.
  • a second etch process is used to remove the drain metallization from the back (i.e., from the back of the
  • Carrier substrate 1 10) to contact.
  • a method for producing a component, in particular a transistor, according to an exemplary embodiment presented here is also described here.
  • the method includes, for example, the following steps:
  • sputtering it can, for. B. AIN are deposited, which has a high thermal conductivity Filling the trenches with a metallic layer, e.g. B. copper deposition by electroplating; in an alternative embodiment, for. B.
  • the approach presented herein further enables a method 600 for fabricating a transistor, the method 600 having a step of providing 610 a carrier substrate. Furthermore, the method 600 has a step of depositing 620 a first semiconductor layer 130 from a first one
  • Method 600 includes a step of forming 630 a drain terminal 145 and a source terminal 150, which are embedded at least in the second semiconductor layer 135, wherein by means of the drain terminal 145 and the source terminal 150 at least one barrier layer 140 between the first and second semiconductor material is electrically contacted and through the
  • Drain terminal 145 and the source terminal 150 Drain terminal 145 and the source terminal 150, a channel region 155 between the drain terminal 145 and the source terminal 150 is defined. Furthermore, the method 600 comprises a step of arranging 640 a gate terminal 170 which at least partially covers the channel area 155. Finally, the method 600 comprises a step of inserting 650 a recess on a side of the carrier substrate 1 10 opposite the drain connection 145 and / or the source connection 150 in one
  • Channel region 155 at least partially overlapping portion of the
  • Carrier substrate 1 10 wherein an edge of the recess by a
  • Insulation layer is covered.
  • an exemplary embodiment comprises a "and / or" link between a first feature and a second feature, then this is to be read so that the embodiment according to one embodiment, both the first feature and the second feature and according to another embodiment either only first feature or only the second feature.

Abstract

L'invention concerne un transistor (100) pourvu d'un substrat support (110) et d'une première couche semi-conductrice (130) constituée d'un premier matériau semi-conducteur, placée sur le substrat support (110). Le transistor (100) comporte également une seconde couche semi-conductrice (135) constituée d'un second matériau semi-conducteur, placée sur la première couche semi-conductrice (130), la largeur de bande interdite du premier matériau semi-conducteur étant différente de celle du second matériau semi-conducteur. Le transistor (100) présente en outre un drain (145) et une source (150) qui sont incorporés au moins dans la seconde couche semi-conductrice (135), au moins une couche interfaciale (140) située entre le premier et le second matériau semi-conducteur pouvant être mise en contact électrique au moyen du drain (145) et de la source (150). Le transistor (100) comprend également une zone de canal (155) entre le drain (145) et la source (150). Le transistor (100) comprend en outre une grille (170) qui recouvre au moins partiellement la zone de canal (155). Enfin, le transistor (100) comprend un évidement (180), qui est ménagé sur un côté du substrat support (100) opposé au drain (145) et à la source (150) et qui chevauche au moins partiellement la zone de canal (155), un bord latéral (182) et/ou un fond (183) de l'évidement (180) étant recouvert d'une couche isolante (185).
PCT/EP2014/061800 2013-06-18 2014-06-06 Transistor et procédé de fabrication d'un transistor WO2014202409A1 (fr)

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EP14730126.1A EP3011598A1 (fr) 2013-06-18 2014-06-06 Transistor et procédé de fabrication d'un transistor
JP2016520370A JP2016524819A (ja) 2013-06-18 2014-06-06 トランジスタ、及び、トランジスタの製造方法
CN201480034526.XA CN105283959A (zh) 2013-06-18 2014-06-06 晶体管和用于制造晶体管的方法

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DE102013211374.9A DE102013211374A1 (de) 2013-06-18 2013-06-18 Transistor und Verfahren zur Herstellung eines Transistors

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CN106992210A (zh) * 2016-01-21 2017-07-28 罗伯特·博世有限公司 用于制造横向hemt的装置和方法
CN110212028A (zh) * 2019-05-22 2019-09-06 张士英 一种集成反向二极管和内嵌漏极场板的横向扩散eGaN HEMT器件
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DE102015212048A1 (de) * 2015-06-29 2016-12-29 Robert Bosch Gmbh Transistor mit hoher Elektronenbeweglichkeit
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JP2020150280A (ja) * 2016-05-11 2020-09-17 アールエフエイチアイシー コーポレイション 高電子移動度トランジスタ（ｈｅｍｔ）
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CN110212028A (zh) * 2019-05-22 2019-09-06 张士英 一种集成反向二极管和内嵌漏极场板的横向扩散eGaN HEMT器件
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CN117133802A (zh) * 2023-03-30 2023-11-28 荣耀终端有限公司 一种半导体器件及其制作方法、封装器件、电子设备

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