JP7066778B2 - 高電子移動度トランジスタ(hemt) - Google Patents
高電子移動度トランジスタ(hemt) Download PDFInfo
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- JP7066778B2 JP7066778B2 JP2020102756A JP2020102756A JP7066778B2 JP 7066778 B2 JP7066778 B2 JP 7066778B2 JP 2020102756 A JP2020102756 A JP 2020102756A JP 2020102756 A JP2020102756 A JP 2020102756A JP 7066778 B2 JP7066778 B2 JP 7066778B2
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/1033—Gallium nitride [GaN]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10344—Aluminium gallium nitride [AlGaN]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
Description
[例1] エピタキシャル層と、
前記エピタキシャル層上に形成されたドレインと、
前記エピタキシャル層上に形成され、前記ドレインの頂面上の第1コンタクト開口領域を除いて前記ドレインを覆う絶縁層と、
導電材料で形成され、前記絶縁層の一部上及び前記第1コンタクト開口領域上に配置され、それにより前記第1コンタクト開口領域において前記ドレインへの直接的な接触を為すドレインフィールドプレートであり、前記ドレインの投影領域の外側まで延在する投影領域を持つドレインフィールドプレートと、
を有する半導体トランジスタ。
[例2] 電気絶縁材料で形成され、前記絶縁層と前記ドレインフィールドプレートとの間に配置され、前記ドレインの前記頂面上の前記第1コンタクト開口領域を除いて前記ドレインを覆うパッシベーション層、
を更に有する例1に記載の半導体トランジスタ。
[例3] 前記パッシベーション層及び前記絶縁層は、前記ドレインの側方に配置された少なくとも1つの第2コンタクト開口領域を有し、前記ドレインフィールドプレートが、前記少なくとも1つの第2コンタクト開口領域上に形成され、それにより前記少なくとも1つの第2コンタクト開口領域において前記エピタキシャル層への直接的な接触を為す、例2に記載の半導体トランジスタ。
[例4] 前記エピタキシャル層はGaNを含み、当該半導体トランジスタは高電子移動度トランジスタ(HEMT)である、例1に記載の半導体トランジスタ。
[例5] 前記エピタキシャル層上に形成されたゲートであり、当該ゲートの頂面が前記パッシベーション層によって覆われているゲートと、
前記パッシベーション層上に形成され且つ前記ゲートの上方に配置されたゲートフィールドプレートと、
を更に有する例1に記載の半導体トランジスタ。
[例6] 前記ドレインフィールドプレート上に直接的に配置された金属素子と、
前記金属素子を覆い、前記金属素子の頂面上にコンタクト開口領域を有する絶縁層と、
を更に有する例1に記載の半導体トランジスタ。
[例7] エピタキシャル層と、
前記エピタキシャル層上に形成されたドレインと、
前記エピタキシャル層と前記ドレインとの上に形成された絶縁層であり、前記ドレインの頂面上の第1コンタクト開口領域と前記エピタキシャル層の頂面上の第2コンタクト開口領域とを有する絶縁層と、
第1の金属プレートと第2の金属プレートとを含むドレインフィールドプレートであり、前記第1の金属プレートは、前記絶縁層の一部上及び前記第1コンタクト開口領域上に配置され、それにより前記第1コンタクト開口領域において前記ドレインへの直接的な接触を為し、前記第2の金属プレートは、前記絶縁層の一部上及び前記第2コンタクト開口領域上に配置され、それにより前記エピタキシャル層への直接的な接触を為し、前記第1及び第2の金属プレートは互いに離隔されている、ドレインフィールドプレートと、
を有する半導体トランジスタ。
[例8] 前記第1及び第2の金属プレートは、インターデジテートに配置された突出部及び凹所部を有する、例7に記載の半導体トランジスタ。
[例9] 電気絶縁材料で形成され、前記絶縁層と前記ドレインフィールドプレートとの間に配置されたパッシベーション層、
を更に有する例7に記載の半導体トランジスタ。
[例10] 前記エピタキシャル層はGaNを含み、当該半導体トランジスタは高電子移動度トランジスタ(HEMT)である、例7に記載の半導体トランジスタ。
[例11] 前記エピタキシャル層上に形成されたゲートであり、当該ゲートの頂面が前記パッシベーション層によって覆われているゲートと、
前記パッシベーション層上に形成され且つ前記ゲートの上方に配置されたゲートフィールドプレートと、
を更に有する例7に記載の半導体トランジスタ。
[例12] 前記ドレインフィールドプレート上に直接的に配置された金属素子と、
前記金属素子を覆い、前記金属素子の頂面上にコンタクト開口領域を有する絶縁層と、
を更に有する例7に記載の半導体トランジスタ。
[例13] 半導体トランジスタの処理方法であって、前記半導体トランジスタは、基板と、エピタキシャル層と、該エピタキシャル層上に形成された複数のトランジスタコンポーネントとを含み、当該方法は、
前記複数のトランジスタコンポーネントの一部の下方に配置された前記基板の一部を除去し、それにより前記エピタキシャル層の底面の一部を露出させることと、
前記エピタキシャル層の前記底面の前記露出された部分上に、電気絶縁材料からなる絶縁層を形成することと、
前記絶縁層の底面から前記複数のトランジスタコンポーネントのうちの少なくとも1つのトランジスタコンポーネントの底面まで延在する少なくとも1つのビアホールを形成することと、
前記絶縁層の前記底面上、前記ビアホールの側壁上、及び前記複数のトランジスタコンポーネントのうちの前記少なくとも1つのトランジスタコンポーネントの前記底面上に、少なくとも1つの金属層を堆積させることと
を有する、方法。
[例14] 前記少なくとも1つの金属層の底面上にはんだペーストを付与すること、
を更に有する例13に記載の方法。
[例15] 前記少なくとも1つの金属層を堆積させるステップは、
前記絶縁層の前記底面上、前記ビアホールの前記側壁上、及び前記複数のトランジスタコンポーネントのうちの前記1つのトランジスタコンポーネントの前記底面上に、第1の金属層を堆積させることと、
前記第1の金属層の底面上に第2の金属層を堆積させることと
を含む、例13に記載の方法。
[例16] 前記少なくとも1つの金属層は、前記基板よりも高い熱伝導率を有する、例13に記載の方法。
[例17] エピタキシャル層と、
前記エピタキシャル層の頂面に形成された複数のトランジスタコンポーネントと、
前記エピタキシャル層の底面上に形成され、前記複数のトランジスタコンポーネントの一部の下の領域の外側にある領域に配置された基板と、
電気絶縁材料で形成され、前記基板の底面と前記エピタキシャル層の底面の一部との上に配置された絶縁層と、
前記絶縁層の底面から、前記複数のトランジスタコンポーネントのうちの少なくとも1つのトランジスタコンポーネントの底面まで、前記エピタキシャル層を貫いて延在する少なくとも1つのビアホールと、
前記絶縁層の底面、前記少なくとも1つのビアホールの側壁、及び前記複数のトランジスタコンポーネントのうちの前記少なくとも1つのトランジスタコンポーネントの前記底面、の上に形成された少なくとも1つの金属層と、
を有する半導体トランジスタ。
[例18] 前記少なくとも1つの金属層の底面に付与されたはんだペースト、
を更に有する例17に記載の半導体トランジスタ。
[例19] 前記少なくとも1つの金属層は、
前記絶縁層の前記底面、前記少なくとも1つのビアホールの前記側壁、及び前記複数のトランジスタコンポーネントのうちの前記1つのトランジスタコンポーネントの前記底面、の上に形成された第1の金属層と、
前記第1の金属層の底面上に形成された第2の金属層と
を含む、例17に記載の半導体トランジスタ。
[例20] 当該半導体トランジスタは高電子移動度トランジスタ(HEMT)である、例17に記載の半導体トランジスタ。
Claims (8)
- エピタキシャル層と、
前記エピタキシャル層の頂面に形成された複数のトランジスタコンポーネントと、
前記エピタキシャル層の底面上に形成され、前記複数のトランジスタコンポーネントの一部の下の領域の外側にある領域に配置された基板と、
電気絶縁材料で形成され、前記基板の底面と前記エピタキシャル層の底面の一部との上に配置された絶縁層と、
前記複数のトランジスタコンポーネントのうちの少なくとも1つのトランジスタコンポーネントの底面まで前記絶縁層及び前記エピタキシャル層を貫いて延在する少なくとも1つのビアホールと、
前記絶縁層の底面、前記少なくとも1つのビアホールの側壁、及び前記複数のトランジスタコンポーネントのうちの前記少なくとも1つのトランジスタコンポーネントの前記底面、の上に形成された少なくとも1つの金属層と、
を有する半導体トランジスタ。 - 前記少なくとも1つの金属層の底面に付与されたはんだペースト、
を更に有する請求項1に記載の半導体トランジスタ。 - 前記少なくとも1つの金属層は、
前記絶縁層の前記底面、前記少なくとも1つのビアホールの前記側壁、及び前記複数のトランジスタコンポーネントのうちの前記1つのトランジスタコンポーネントの前記底面、の上に形成された第1の金属層と、
前記第1の金属層の底面上に形成された第2の金属層と
を含む、請求項1に記載の半導体トランジスタ。 - 当該半導体トランジスタは高電子移動度トランジスタ(HEMT)である、請求項1に記載の半導体トランジスタ。
- 半導体トランジスタの処理方法であって、前記半導体トランジスタは、基板と、エピタキシャル層と、該エピタキシャル層上に形成された複数のトランジスタコンポーネントとを含み、当該方法は、
前記複数のトランジスタコンポーネントの一部の下方に配置された前記基板の一部を除去し、それにより前記エピタキシャル層の底面の一部を露出させることと、
前記エピタキシャル層の前記底面の露出された部分上に、電気絶縁材料からなる絶縁層を形成することと、
前記絶縁層を貫いて前記複数のトランジスタコンポーネントのうちの少なくとも1つのトランジスタコンポーネントの底面まで延在する少なくとも1つのビアホールを形成することと、
前記絶縁層の前記底面上、前記ビアホールの側壁上、及び前記複数のトランジスタコンポーネントのうちの前記少なくとも1つのトランジスタコンポーネントの前記底面上に、少なくとも1つの金属層を堆積させることと
を有する、方法。 - 前記少なくとも1つの金属層の底面上にはんだペーストを付与すること、
を更に有する請求項5に記載の方法。 - 前記少なくとも1つの金属層を堆積させるステップは、
前記絶縁層の前記底面上、前記ビアホールの前記側壁上、及び前記複数のトランジスタコンポーネントのうちの前記1つのトランジスタコンポーネントの前記底面上に、第1の金属層を堆積させることと、
前記第1の金属層の底面上に第2の金属層を堆積させることと
を含む、請求項5に記載の方法。 - 前記少なくとも1つの金属層は、前記基板よりも高い熱伝導率を有する、請求項5に記載の方法。
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US10861947B2 (en) | 2020-12-08 |
EP3455883A4 (en) | 2020-03-18 |
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JP6718982B2 (ja) | 2020-07-08 |
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US20200287004A1 (en) | 2020-09-10 |
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WO2017196740A2 (en) | 2017-11-16 |
CN114122128A (zh) | 2022-03-01 |
JP2020150280A (ja) | 2020-09-17 |
US10217827B2 (en) | 2019-02-26 |
CN109716530A (zh) | 2019-05-03 |
EP3905340A1 (en) | 2021-11-03 |
CN109716530B (zh) | 2022-03-25 |
US20170330940A1 (en) | 2017-11-16 |
KR20200068745A (ko) | 2020-06-15 |
KR102136356B1 (ko) | 2020-07-23 |
EP3455883B1 (en) | 2021-11-03 |
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