CN114122128A - 高电子迁移率晶体管 - Google Patents

高电子迁移率晶体管 Download PDF

Info

Publication number
CN114122128A
CN114122128A CN202111392945.9A CN202111392945A CN114122128A CN 114122128 A CN114122128 A CN 114122128A CN 202111392945 A CN202111392945 A CN 202111392945A CN 114122128 A CN114122128 A CN 114122128A
Authority
CN
China
Prior art keywords
transistor
drain
layer
field plate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111392945.9A
Other languages
English (en)
Inventor
李源祥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rfhic Corp
Original Assignee
Rfhic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rfhic Corp filed Critical Rfhic Corp
Publication of CN114122128A publication Critical patent/CN114122128A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05084—Four-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05583—Three-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29009—Layer connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29022—Disposition the layer connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29025—Disposition the layer connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10344—Aluminium gallium nitride [AlGaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Die Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

提供拥有漏极场板(140)的高电子迁移率晶体管。漏极场板(140)形成在高电子迁移率晶体管的栅极(118)与漏极(104)之间的区域内。漏极场板(140)包含具有投影区域大于漏极垫(104)的金属垫。漏极场板(140)与设置在漏极场板之下的半导体层(102)形成金属‑半导体(M‑S)肖特基结构。M‑S肖特基结构的电容在半导体区域(102)产生电容，提高高电子迁移率晶体管的晶体管构件的击穿电压。可移除在有源区(203)下的衬底(100)部分，从而提高高电子迁移率晶体管的晶体管构件的热传导性及降低结温度。

Description

高电子迁移率晶体管
本申请是申请号为201780042843.X，申请日为2017年05月08日，发明名称为“高电子迁移率晶体管”的专利申请的分案申请。
技术领域
本发明是有关于半导体装置，特别是有关于高电子迁移率晶体管。
背景技术
高电子迁移率晶体管(High Electron Mobility Transistor,HEMT)，也被称为异质结构FET(HFET)或调制掺杂FET(MODFET)，是一种在其中形成信道层与电子亲和力小于信道层的阻挡层之间的异质结的场效应晶体管(FET)。HEMT能够在比常规晶体管高的频率，上至毫米波频率操作，且通常使用在高频及高功率产品，例如移动电话站的功率放大器及军用相控阵激光器。
通常，在射频(RF)范围操作的HEMT需要高于常规晶体管的击穿电压，所述击穿电压是晶体管的栅极可处理的最大电压。现有的HEMT中，已使用连接源极的栅极场板提高击穿电压。然而，随着现代移动通信科技的出现，对具有较高击穿电压的HEMT的需求持续增加。而且，为了得到好的线性度，栅极-漏极电容(Cgd)值需要在动态驱动范围内保持平坦。
此外，设计在高功率范围操作的HEMT可能会产生高热能。因此，它们需要被设计用于低输出电阻，以便其可传递大电流至其负载，及良好的结绝缘以抵撑高电压。因为大部分的热能在异质结产生，结的面积可做得尽可能的大，以便热能可被非常快的耗散从而防止过热。然而，在许多高功率应用中，HEMT的尺寸外型可能会加诸限制在装置面积的尺寸上，造成HEMT可处理的最大功率的限制。
因此，存在对于具有高击穿电压、在动态驱动范围内平坦的Cgd值、及加强的热耗散机制的HEMT的需求，从而提高在各种应用，尤其在射频范围的最大电压、线性度、及额定功率。
发明内容
在实施例中，漏极场板形成在HEMT的漏极上。漏极场板包含具有投影面积比漏极垫大的金属垫。漏极场板降低栅极侧的漏极垫产生的电场强度，使HEMT的击穿电压的增加。
在实施例中，漏极场板通过沉积SiN钝化层、图形化SiN钝化层、及沉积金属层在图形化SiN钝化层上而形成。漏极场板及下方的半导体层形成在半导体内产生耗尽层的金属-半导体(M-S)肖特基结，耗尽层提高HEMT的击穿电压。而且，通过改变漏极场板的形状，可控制栅极-漏极电容(Cgd)及漏极-源极电容(Cds)，增强HEMT的RF特性。
在实施例中，设计HEMT以减少体漏电流及结温度(Tj)。在前侧的加工完成后，(即在衬底的前侧形成晶体管构件)，可加工衬底的背侧以加强热耗散。在实施例中，背侧加工包含数个步骤。首先，移除(蚀刻)有源区下的衬底的部分。之后，可将SiN层沉积在整个背侧表面上，其中SiN层的厚度较佳为接近35nm。下一步，形成穿过源极下AlGaN/GaN外延层的贯通孔。由Ti/Au制成的第一金属层可通过像是溅镀的适合的工序沉积在背侧表面上，且具有像是Cu/Au、Cu/Au/Cu/Au、或Cu/Ag/Au复合结构的第二金属层可形成在第一金属层之上，使得衬底的背侧及在前侧上的源极通过贯通孔电连接。
在实施例中，背侧加工可在金属层沉积在有源区下之前移除有源区下的衬底。由于典型的衬底材料，像是Si或蓝宝石，具有比金属层低的热传导率，背侧加工可提高HEMT的热传导率，降低晶体管构件的Tj。在实施例中，背侧加工可在沉积SiN层之前移除有源区下的衬底。由于典型的衬底材料具有比SiN低的电绝缘性，背侧加工可提高电绝缘性，降低晶体管构件的体漏电流。
在实施例中，每个HEMT可从晶圆切块(即执行切割工序)及附接于封装，而无常规的共晶附接的预成形，其减少至少一个制造步骤并因此降低制造成本。在实施例中，表面安装装置(SMD)回流法可用于将裸晶附接至封装。
通常，常规的裸晶黏合工序会遭遇空气空隙问题，空气空隙降低热传导率且负面地影响晶体管的可靠度。在实施例中，焊膏沉积在背侧以填充贯通孔及衬底的凹部区域，避免在裸晶黏合工序期间形成空气空隙。
附图说明
将参考本发明实施例，它们的示例可在附图中示出。这些附图旨在说明而非限制。尽管本发明主要在这些实施例的背景中描述，但应理解，并不意图将本发明的范围限制于这些具体实施例。
图1至图5显示根据本发明实施例在衬底的前侧上形成半导体构件的例示性工序。
图6显示根据本发明实施例沉积钝化层的例示性工序。
图7显示根据本发明实施例形成接触开口的例示性工序。
图8显示根据本发明实施例形成栅极场板及漏极场板的例示性工序。
图9显示根据本发明实施例的漏极场板的俯视图。
图10显示根据本发明实施例的漏极场板的俯视图。
图11显示根据本发明实施例镀覆金属层在晶体管构件上的例示性工序。
图12及图13显示根据本发明实施例沉积电绝缘层及蚀刻电绝缘层的部分的例示性工序。
图14显示根据本发明实施例的晶圆薄化的例示性工序。
图15显示根据本发明实施例的衬底蚀刻的例示性工序。
图16显示根据本发明实施例沉积SiN层的例示性工序。
图17显示根据本发明实施例产生贯通孔的例示性工序。
图18显示根据本发明实施例沉积金属层在晶圆的背侧表面上的例示性工序。
图19显示根据本发明实施例沉积金属层在晶圆的背侧表面上的例示性工序。
图20显示根据本发明实施例施予焊膏至晶圆的背侧表面的例示性工序。
图21显示根据本发明实施例加工HEMT晶圆的背侧的例示性工序。
图22显示根据本发明实施例沉积金属层在晶圆的背侧表面上的例示性工序。
图23显示根据本发明实施例沉积金属层在晶圆的背侧表面上的例示性工序。
图24显示根据本发明实施例施予焊膏至晶圆的背侧表面的例示性工序。
具体实施方式
在以下描述中，出于解释的目的，阐述了具体细节以便提供对本公开的理解。然而，对于本领域技术人员显而易见的是，本公开可在没有这些细节的情况下实践。此外，本领域技术人员将意识到，以下描述本公开的实施例可以各种方式，诸如有形计算器可读取媒介上的工序、设备、系统、装置或方法实现。
本领域技术人员将意识到：(1)某些步骤可选择性地执行，(2)步骤可不限于本文所载的具体顺序，以及(3)某些步骤可以不同的顺序进行，包括同时进行。
图中所示的组件/构件是本公开的示例性实施例的说明，并且旨在避免模糊本公开。本说明书中提及的“一个实施例”、“较佳的实施例”、“一实施例”或“实施例”意味着结合实施例描述的具体特征、结构、特性或功能包括在本公开的至少一个实施例中，且可包含在多于一个实施例中。在本说明书中各处出现的短语“在一个实施例中”，“在一实施例中”或“在实施例中”不一定都指代相同的一或多个实施例。用语“包括”、“包括”、“包含”和“包含”应被理解为开放用语，且该些用语后的任何列表是示例，并不意味着限于所列项目。本文使用的任何标题仅用于组织目的，且不应用于限制说明书或权利要求书的范围。此外，在本说明书中的各个地方使用某些用语仅用于说明而不应被解释为限制。
本公开的实施例包含漏极场板以提高HEMT的击穿电压。而且，漏极场板可用来提高或降低HEMT的Cgd及/或Cds、维持平坦的Cgd值、增强HEMT的RF特性。
本公开的实施例包含移除有源区下的衬底的部分的工序，从而提高HEMT构件的热传导率及降低结温度。
本公开的实施例包含移除有源区下的衬底的部分及沉积SiN层的工序。由于SiN层具有比衬底材料更佳的电绝缘特性，此工序可降低HEMT构件的体漏电流。
本公开的实施例包含移除有源区下的衬底的部分及沉积金属层的工序。由于金属层具有比衬底材料更佳的热传导率，此工序可提高HEMT构件的热传导率及降低结温度。
本公开的实施例包含移除有源区下的衬底的部分及形成贯通孔，其中金属层沉积在所述贯通孔中的工序。此工序可降低HEMT的源电感。
本公开的实施例包含移除有源区下的衬底的部分、沉积金属层、及施予焊膏至晶圆的背表面的工序，避免空气空隙的形成，从而增强HEMT构件的热传导特性及降低HEMT构件的结温度。
本公开的实施例包含移除有源区下的衬底的部分、沉积金属层、及施予焊膏至晶圆的背表面的工序。此工序可省去附接HEMT裸晶至封装的常规预成形工序(像是共晶附接工序)，其可降低制造成本。
本公开的实施例包含移除有源区下的衬底的部分、沉积金属层、及施予焊膏至晶圆的背表面的工序。因此，可使用共晶附接工序或SMD回流工序来将HEMT裸晶附接至封装。
图1至图5显示根据本发明实施例形成HEMT构件在衬底的前(或上)侧的例示性工序。如图1描述，外延层102形成在衬底100的前(上)侧。衬底100可较佳地由硅或蓝宝石形成，尽管如此，衬底可用其他适合的材料。外延层102可由GaN形成，使得AlGaN/GaN异质结层形成在衬底上。应注意外延层102可由其他适合类型的材料形成。下文中，使用GaN HEMT作为例示性HEMT，尽管如此，其可通过本文件描述的工序制造他类型的HEMT。
漏极(或者，等效地，漏极垫或漏极电极或漏极的奥姆金属化)104及108与源极(或者，等效地，源极垫或源极电极或用于源极的奥姆金属化)106可形成在外延层102之上，其中漏极及源极可由适合的金属形成。在实施例中，漏极及源极可各具有包含Ti/Al/Ni/Au的复合金属层结构。漏极及源极的奥姆接触可通过合金化漏极及源极产生，从而降低在漏极/源极及外延层102之间接口的电阻。
如图2所示，电绝缘层110可形成在衬底100的前表面之上。在实施例中，绝缘层110可由SiN，或可用于电绝缘的任何其他适合的材料制成。绝缘层110可覆盖外延层102、漏极104及108及源极106的这些器件的制造期间形成在外延层102、漏极104及108及源极106的上表面上的损伤。如之后描述，SiN层可被图形化以形成栅极。
图3显示离子布植工序以产生离子布植部分(或者，简短地，布植部分)112，布植部分112可隔绝漏极104及108及源极106作为HEMT的独立工作单元。在实施例中，图形化光致抗蚀剂层(未显示在图3中)可通过适合的光刻工序涂布在HEMT的上表面之上，并用作为光致抗蚀剂(PR)掩模层以选择性地允许离子，像是氮离子或氧离子，在布植工序期间通过绝缘层110且被布植在外延层102之内。接着，随后移除光致抗蚀剂层。
如图4描述，绝缘层110的一或多个部分通过适合的蚀刻工序蚀刻。在实施例中，图形化掩模层(未显示在图4内)可通过光刻工序形成在绝缘层110之上，并用以移除绝缘层的部分，从而形成凹陷116且曝露外延层的上表面。
图5显示形成在凹陷116内，且具有延伸至绝缘层110上的翼的T形栅极118。在实施例中，可执行T形栅极光刻工序(未描述在图5内)且随后使用像是Ni/Au或Ni/Pt/Au的适合的金属执行栅极金属化。
如图6所述，钝化层120可沉积在HEMT的前表面上。在实施例中，钝化层120可由SiN形成，尽管如此，钝化层120可使用其他适合的电绝缘材料。钝化层120可提高T形栅极118及漏极/源极之间的击穿电压层，从而增强HEMT的可靠度。T形栅极118的翼及绝缘层110可产生降低在漏极侧上的栅极边缘区域的电场的电容，从而提高栅极118的击穿电压。
图7显示根据本发明实施例制作接触开口的例示性工序。如所述，移除绝缘层110的部分及钝化层120以形成接触开口(或凹陷)130、132及134，以及SiN接触开口(或凹陷)131及135。如下所述，SiN接触开口131及135可以金属填充以形成漏极场金属(或者，等效的漏极场板)。在实施例中，基于光刻工序的蚀刻工序可用来移除绝缘层110及钝化层120的部分，从而曝露外延层102的上表面的部分。
图8显示根据本发明实施例形成连接源极的栅极场效金属(或者，等效地，连接源极的栅极场板)144及漏极场板140的例示性工序。图9显示根据本发明实施例的漏极场板140的俯视图。连接源极的栅极场板(或者，简短地栅极场板)144，形成在钝化层120上，钝化层在T形栅极118上且向漏极104延伸，与底下的层110及120产生电容，其中此电容降低在漏极侧上的栅极边缘区域的电场，从而提高栅极118及漏极104之间的击穿电压。在实施例中，连接源极的栅极场板144可由适合的金属形成。
在实施例中，漏极场板140可形成在漏极104上并且延伸超过漏极104的边缘。漏极场板140具有与连接源极的栅极场板144相似的效应，其中通过漏极场板140产生的电容可提高击穿电压。更具体的说，漏极场板140；层110、120；及外延层102形成金属-半导体(M-S)结构。M-S肖特基结构产生电容，电容又在外延层102内产生耗尽区域，从而提高击穿电压。
通常，当RF信号被施加至栅极118，即静态电流具有波动的瞬态周期时，栅极118及漏极104之间的边缘电容(Cgd)在漏极-源极静态电流上具有负效应。在实施例中，通过漏极场板140的M-S肖特基结构产生电容可控制边缘电容(Cgd)，从而可维持Cgd的平坦性。
如图9所述，在实施例中，漏极场板140指的是覆盖漏极104的投影区域及进一步在X方向延伸至漏极104的投影区域外的金属区域。(下文中，用语投影区域指的是通过将三维物体的形状投影至x-y平面上而获得的二维区域，其中x-y平面平行外延层102的上表面。)漏极场板140也指覆盖SiN接触开口131的投影区域的金属区域及进一步在x及y两方向延伸至SiN接触开口131的投影区域外的金属区域。相反地，在常规的系统中，漏极接触开口130填充金属材料，且漏极接触开口130的投影区域不延伸至漏极104的投影区域外。
在实施例中，为SiN接触开口131的边缘及漏极场板140的边缘之间在y方向的距离的长度D1为约1μm。为漏极场板140的边缘及漏极104的边缘之间在y方向的距离的长度D2为约1μm。为SiN接触开口131在x方向的尺寸的宽度D3为约1μm。为SiN接触开口131的边缘及漏极104的边缘之间在x方向的距离的宽度D4为约1μm。为SiN接触开口131的边缘及漏极场板140的边缘之间在x方向的距离的宽度D5为约1μm。为SiN接触开口131的边缘及漏极场板140的边缘之间在x方向的距离的宽度D6为约3μm。为接触开口区域130的边缘及漏极104的边缘之间在x方向的距离的宽度D7为约5μm。应注意的是长度D1至D7的值为例示性且可以使用其他适合的值。
在实施例中，即使在漏极104的尺寸改变时，仍可维持长度D1至D7之间的比值。例如，在漏极104的尺寸改变时，D6及D7之间的比值可维持为1。
漏极场板140可由多重金属层结构形成，像是Ti/Au或Ti/Au/Ti/Au。在实施例中，连接源极的栅极场板144及漏极场板140可在相同工序期间形成，例如，图形化掩模层(未显示在图8及图9内)可通过适合的光刻工序沉积，使得在沉积连接源极的栅极场板140极漏极场板140的同时，接触开口区域130、132及134也可在相同工序期间以相同金属材料填充。
图10显示根据本发明的另一个实施例的漏极场板的俯视图。
如所述，漏极场板150包含三个板401、402、及403，其中板401及403与板402电性分离且板402电连接至漏极104。板402包含填充接触开口区域130的金属层，而板401及403包含分别填充二个SiN接触开口131的金属层。
在实施例中，宽度D10、D11、及D12与图9中的D5、D3、及D4相似，其各皆为约1μm。同样地，分别地与D2及D1相似的长度D13及D14，各约为1μm。
如图10所述，漏极场板401、402及403的侧面可为交指形。例如，与交指部分的突起/凹陷部分相关长度D15至D17及D19至D23，可各为约1μm。为漏极104的边缘及接触孔区域130的边缘之间在x方向的距离的长度D18可为约5μm。
在实施例中，漏极场板140、401、402及403可具有其他适合的形状，使得M-S肖特基结构可具有预期的电容以控制Cgd及/或Cgs(栅极与源极之间的边缘电容)。在实施例中，漏极场板的形状及漏极场板与漏极104的边缘之间的距离可被调整以达到预期的电容。在实施例中，指叉式电容对DC信号是断路，但是对RF信号是电短路，其导致指叉式电容响应于RF信号选择性的操作。应注意的是漏极场板142及SiN接触开口135的俯视图具有与图9及图10相同的配置，即漏极场板142可具有与漏极场板140相同的形状或漏极场板142可具有与金属板401、402、及403相似的三个金属板。
图11显示根据本发明实施例镀覆金属层在晶体管构件上的例示性工序。如所述，金属组件160、162、及164可通过镀覆工序沉积在漏极及源极之上，像是Au镀覆工序，使得构件可通过气桥或接合垫工序电连接。
图12及图13显示根据本发明实施例沉积电绝缘层166及蚀刻绝缘层166的部分的例示性工序。如所述，绝缘层166被部分蚀刻使得金属组件(接合垫)160、162及164分别具有接触开口170、172及174以连接引线至其。例如，在实施例中，引线的一端可被接合(引线接合)至接触孔170，使得电信号经由金属组件(接合垫)160及漏极场板140从引线传输至漏极104或从漏极104传输至引线。
图14至图24说明加工衬底100及外延层102的背侧(底侧)。图14显示根据本发明实施例的晶圆薄化的例示性工序。如所述，衬底100可通过适合的工序薄化，像是研磨及抛光，以便于HEMT的组装至封装及背侧工序，像是贯通孔的产生及切割。
图15显示根据本发明实施例的衬底蚀刻的例示性工序。如所述，有源区203下的衬底100的部分可通过适合的工序移除，像是干式蚀刻或湿式蚀刻。此处，有源区203指的是在工作期间产生热的主动半导体构件，像是漏极、栅极及源极的下方区域。然后，如图16所示，电绝缘层204，像是SiN层，可沉积在衬底的背侧(或底侧)表面上。
图17显示根据本发明实施例产生贯通孔206的例示性工序。如所述，在实施例中，贯通孔206可延伸至源极106的底侧。如所述，绝缘层204及外延层102可通过适合的蚀刻工序蚀刻以形成贯通孔206，其中贯通孔206可为槽孔。
图18显示根据本发明实施例沉积金属层206在衬底的背侧表面上的例示性工序。在实施例中，溅镀工序可用来沉积例如由Ti/Au形成的金属层，于衬底的背侧表面上，尽管如此，可使用其他适合的工序来沉积金属层206。
图19显示根据本发明实施例电镀金属层208在衬底的背侧表面上的例示性工序。在实施例中，金属层206可为金属层208的晶种层。在实施例中，金属层208可通过适合的工序沉积，像是电镀工序，且金属层208可具有复合金属结构，像是Cu/Au/Cu/Au及Cu/Ag/Au。
图20显示根据本发明实施例施予焊膏208至衬底的背侧表面的例示性工序。如所述，焊膏208可填充至贯通孔206中以及在有源区203下的衬底100的凹陷部分。
如上所述，有源区203下的衬底的部分可在金属层206及208沉积之前移除。由于衬底材料，像是硅或蓝宝石，可具有比金属层206及208低的热传导率，图15至图20中的工序可提高HEMT的热传导率，降低有源区203中晶体管构件的Tj。同样地，由于典型的衬底材料具有比SiN低的电绝缘性，背侧工序提高电绝缘性，降低晶体管构件的体漏电流。
图21显示根据本发明实施例的HEMT晶圆的背侧加工。图21中HEMT与图17中的HEMT相似，差异在于图21中的HEMT为具有彼此可通过气桥(未表示在图21中)连接的多重源极310、314及318。例如，在实施例中，贯通孔302及304可用于电连接源极310及318至HEMT的底侧，其中贯通孔302及304可位于有源区309外。如所述，绝缘层(像是SiN层)301、衬底300、外延层305及离子布植区307可通过适合的工序蚀刻以形成贯通孔302及304。
应注意在图21只显示三个源极。然而，对所属技术领域具有通常知识者来说显而易见的是，其他适合的数量的源极可通过气桥彼此连接。而且，在图21只显示二个标准贯通孔，尽管如此，可形成其他适合数量的贯通孔。
图22显示根据本发明实施例沉积金属层330在衬底的背侧表面上的例示性工序。在实施例中，溅镀工序可用来沉积例如由Ti/Au形成的金属层在衬底的背侧表面上。
图23显示根据本发明实施例沉积金属层332在衬底的背侧表面上的例示性工序。在实施例中，金属层330可为金属层332的晶种层。在实施例中，金属层332可通过适合的工序沉积，像是电镀工序，且金属层332可具有复合金属结构，像是Cu/Au/Cu/Au及Cu/Ag/Au。
图24显示根据本发明实施例用于施予焊膏334至晶圆的背侧表面的例示性工序。如所述，焊膏334可填充在贯通孔302及304中以及有源区309下的衬底300的凹陷部分。
本公开的实施例包含移除(蚀刻)有源区203或309下的衬底100或300的部分及沉积一或多个金属层的工序。由于金属层具有较典型衬底材料更佳的热传导率，这些工序可提高操作期间HEMT构件产生的热耗散。
本公开的实施例包含移除(蚀刻)有源区下的衬底的部分、沉积金属层、及施予焊膏220或334至背侧表面的工序，避免空气空隙的形成，从而增强HEMT构件的热传导特性及降低HEMT构件的结温度。
本公开的实施例包含移除(蚀刻)有源区下的衬底的部分及沉积SiN层204或301的工序。由于SiN层具有较典型衬底材料更佳的电绝缘特性，此工序可降低HEMT构件的体漏电流。
在实施例中，在图20及图24中的每个HEMT可从晶圆切块(切割)及通过加热(即回流)焊膏220或332附接至封装(未显示在图20及图24中)。相反的，在常规方法中，包含共晶金属的焊膏在裸晶被附接之前被施予在陶瓷封装或引线框上。因此，在实施例中，不需要常规共晶金属的预成形，减少至少一个制造工序及制造成本。在实施例中，表面安装装置(SMD)回流法可用于将HEMT附接至封装。
结合图1至图24描述的一或多个工序可通过计算器软件执行。应注意的是，本公开的实施例可进一步涉及其上具有用于执行各种计算器实施操作的计算器编码的非瞬时、有形的计算器可读取媒介的计算器产品。媒介及计算器编码可为那些为了本公开的目的而特别设计及建构的，或可为所属技术领域具有通常知识者习知或可得的种类。有形计算器可读取媒介的例子包含，但不限于：磁媒介，像是硬盘、软盘、及磁带；光学媒介，像是CD-ROM及全息装置；磁光媒介，及特别配置以存储或存储及执行程序编码的硬件装置，像是专用集成电路(ASICs)、可编程逻辑设备(PLDs)、闪存装置、及ROM与RAM装置。计算器编码的例子包含像是通过编译程序产生的机械编码及包含通过使用编译程序的计算器来执行的更高阶编码的文件。本公开的实施例可整个或部分作为可在通过加工装置执行的程序模块中的机械执行指令实施。程序模块的例子包含库、编码指令、程序、对象、构件、及数据结构。在分布式计算环境中，程序模块可物理性地位于本机、远程或者两者的设定中。
所属技术领域具有通常知识者应理解的是，没有计算系统或程序语言为本公开的实践的关键。所属技术领域具有通常知识者也应理解的是，以上描述的组件数量可物理性地及/或功能性地分离成子模块或结合在一起。
所属技术领域具有通常知识者将理解的是，前述例子和实施例是例示性的，并不限制本公开的范围。意图将经由阅读说明书和研究附图而对所属技术领域具有通常知识者是显而易见的对其所有的排列、增强、等效、组合和改进都包括在本公开的真实精神和范围内。

Claims (9)

1.一种半导体晶体管，其特征在于，包含：
外延层；
多个晶体管构件，形成在所述外延层的上表面上；
衬底，形成在所述外延层的底表面上，且设置在所述多个晶体管构件的部分下的区域外的区域上；
绝缘层，由电绝缘材料形成，且设置在所述衬底的底表面上以及在所述外延层的底表面的部分上；
至少一个贯通孔，从所述绝缘层的底表面经过所述外延层延伸至所述多个晶体管构件的至少一个的底表面，以及
至少一个金属层，形成在所述绝缘层的底表面、所述至少一个贯通孔的侧壁、及在所述多个晶体管构件的所述至少一个的所述底表面上；
焊膏，施予在所述至少一个金属层的底表面。
2.根据权利要求1所述的半导体晶体管，其特征在于，所述至少一个金属层包含：
第一金属层，形成在所述衬底的所述底表面、所述至少一个贯通孔的所述侧壁、及所述多个晶体管构件的所述至少一个的所述底表面上；以及
第二金属层，形成在所述第一金属层的底表面上。
3.根据权利要求1所述的半导体晶体管，其特征在于，所述半导体晶体管是高电子迁移率晶体管。
4.根据权利要求1所述的半导体晶体管，其特征在于，所述多个晶体管构件的所述至少一个包含源极。
5.根据权利要求1所述的半导体晶体管，其特征在于，所述多个晶体管构件的所述至少一个包含二个或更多的源极，其中所述至少一个贯通孔包含二个或更多的贯通孔，且所述二个或更多的贯通孔的每一个延伸到所述二个或更多的源极中的对应一个的所述底表面。
6.一种半导体晶体管，其特征在于，包含：
外延层；
多个晶体管构件，形成在所述外延层的上表面上；
衬底，形成在所述外延层的底表面上，且设置在所述多个晶体管构件的部分下的区域外的区域上；
绝缘层，由电绝缘材料形成，且设置在所述衬底的底表面上以及在所述外延层的底表面的部分上；
至少一个贯通孔，从所述绝缘层的底表面经过所述外延层延伸至所述多个晶体管构件的至少一个的底表面，
第一金属层，形成在所述衬底的所述底表面、所述至少一个贯通孔的所述侧壁、及所述多个晶体管构件的所述至少一个的所述底表面上；以及
第二金属层，形成在所述第一金属层的底表面上。
7.根据权利要求6所述的半导体晶体管，其特征在于，所述半导体晶体管是高电子迁移率晶体管。
8.根据权利要求6所述的半导体晶体管，其特征在于，所述多个晶体管构件的所述至少一个包含源极。
9.根据权利要求6所述的半导体晶体管，其特征在于，所述多个晶体管构件的所述至少一个包含二个或更多的源极，其中所述至少一个贯通孔包含二个或更多的贯通孔，且所述二个或更多的贯通孔的每一个延伸到所述二个或更多的源极中的对应一个的所述底表面。
CN202111392945.9A 2016-05-11 2017-05-08 高电子迁移率晶体管 Pending CN114122128A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662334837P 2016-05-11 2016-05-11
US62/334,837 2016-05-11
US15/588,650 US10217827B2 (en) 2016-05-11 2017-05-07 High electron mobility transistor (HEMT)
US15/588,650 2017-05-07
CN201780042843.XA CN109716530B (zh) 2016-05-11 2017-05-08 高电子迁移率晶体管

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201780042843.XA Division CN109716530B (zh) 2016-05-11 2017-05-08 高电子迁移率晶体管

Publications (1)

Publication Number Publication Date
CN114122128A true CN114122128A (zh) 2022-03-01

Family

ID=60266705

Family Applications (3)

Application Number Title Priority Date Filing Date
CN202111392488.3A Pending CN114093939A (zh) 2016-05-11 2017-05-08 用于加工半导体晶体管的方法
CN202111392945.9A Pending CN114122128A (zh) 2016-05-11 2017-05-08 高电子迁移率晶体管
CN201780042843.XA Active CN109716530B (zh) 2016-05-11 2017-05-08 高电子迁移率晶体管

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202111392488.3A Pending CN114093939A (zh) 2016-05-11 2017-05-08 用于加工半导体晶体管的方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201780042843.XA Active CN109716530B (zh) 2016-05-11 2017-05-08 高电子迁移率晶体管

Country Status (6)

Country Link
US (3) US10217827B2 (zh)
EP (2) EP3905340A1 (zh)
JP (2) JP6718982B2 (zh)
KR (2) KR102199173B1 (zh)
CN (3) CN114093939A (zh)
WO (1) WO2017196740A2 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3058831B1 (fr) * 2016-11-15 2019-06-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Composant electronique a heterojonction a haute mobilite electronique
KR102044244B1 (ko) * 2016-12-13 2019-12-02 (주)웨이비스 질화물계 전자소자 및 그 제조방법
CN107068611A (zh) * 2016-12-23 2017-08-18 苏州能讯高能半导体有限公司 半导体芯片、半导体晶圆及半导体晶圆的制造方法
US10734498B1 (en) * 2017-10-12 2020-08-04 Hrl Laboratories, Llc Method of making a dual-gate HEMT
CN107799590B (zh) * 2017-11-21 2024-05-24 华南理工大学 一种大栅宽的GaN基微波功率器件及其制造方法
US11404541B2 (en) 2018-02-14 2022-08-02 Hrl Laboratories, Llc Binary III-nitride 3DEG heterostructure HEMT with graded channel for high linearity and high power applications
EP3753051A4 (en) 2018-02-14 2021-11-17 Hrl Laboratories, Llc VERY STAGGERED LINEAR HEMT STRUCTURES
US10483356B2 (en) * 2018-02-27 2019-11-19 Siliconix Incorporated Power semiconductor device with optimized field-plate design
KR102313029B1 (ko) * 2019-12-30 2021-10-13 홍익대학교 산학협력단 반도체 소자의 전극 형성 방법 및 그에 따라 형성된 전극 구조
DE102020213621A1 (de) 2020-10-29 2022-05-05 Robert Bosch Gesellschaft mit beschränkter Haftung Vertikales Galliumnitrid-Leistungshalbleiterbauelement und Verfahren zur Herstellung des Galliumnitrid-Leistungshalbleiterbauelements
US12015075B2 (en) * 2021-05-20 2024-06-18 Macom Technology Solutions Holdings, Inc. Methods of manufacturing high electron mobility transistors having a modified interface region
US12009417B2 (en) 2021-05-20 2024-06-11 Macom Technology Solutions Holdings, Inc. High electron mobility transistors having improved performance
DE102021205315A1 (de) 2021-05-26 2022-12-01 Robert Bosch Gesellschaft mit beschränkter Haftung Membran-halbleiterbauelement und verfahren zum herstellen desselben
TWI839620B (zh) * 2021-06-30 2024-04-21 立積電子股份有限公司 半導體裝置及形成半導體裝置之方法
KR20240035105A (ko) 2022-09-08 2024-03-15 주식회사 디비하이텍 전력 반도체 소자 및 제조방법
KR20240048736A (ko) 2022-10-07 2024-04-16 주식회사 디비하이텍 전력 반도체 소자 및 제조방법
KR20240050587A (ko) 2022-10-12 2024-04-19 주식회사 디비하이텍 질화물계 반도체 소자 및 그 제조방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007128994A (ja) * 2005-11-02 2007-05-24 New Japan Radio Co Ltd 半導体装置
CN101335247A (zh) * 2007-06-29 2008-12-31 富士通株式会社 半导体器件及其制造方法
US20120043586A1 (en) * 2010-08-23 2012-02-23 Fujitsu Limited Semiconductor device and method for manufacturing the same
JP2013191763A (ja) * 2012-03-14 2013-09-26 Fujitsu Ltd 半導体装置の製造方法
US20160056273A1 (en) * 2014-08-20 2016-02-25 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing semiconductor device

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06244277A (ja) 1993-02-19 1994-09-02 Toshiba Corp 半導体装置の製造方法
US6611002B2 (en) 2001-02-23 2003-08-26 Nitronex Corporation Gallium nitride material devices and methods including backside vias
US11791385B2 (en) * 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
US7675090B2 (en) * 2005-05-13 2010-03-09 Flextronics International Usa, Inc. Semiconductor device having a contact on a buffer layer thereof and method of forming the same
US7285807B2 (en) * 2005-08-25 2007-10-23 Coldwatt, Inc. Semiconductor device having substrate-driven field-effect transistor and Schottky diode and method of forming the same
JP5105160B2 (ja) * 2006-11-13 2012-12-19 クリー インコーポレイテッド トランジスタ
US7692263B2 (en) * 2006-11-21 2010-04-06 Cree, Inc. High voltage GaN transistors
US8461631B2 (en) 2007-02-23 2013-06-11 Sensor Electronic Technology, Inc. Composite contact for semiconductor device
JP2010272689A (ja) * 2009-05-21 2010-12-02 Renesas Electronics Corp 電界効果トランジスタ
JP2011040597A (ja) * 2009-08-12 2011-02-24 Toshiba Corp 半導体装置およびその製造方法
US8319309B2 (en) * 2009-08-28 2012-11-27 Samsung Electro-Mechanics Co., Ltd. Semiconductor device and method for manufacturing of the same
US8389977B2 (en) * 2009-12-10 2013-03-05 Transphorm Inc. Reverse side engineered III-nitride devices
JP5618571B2 (ja) * 2010-03-02 2014-11-05 パナソニック株式会社 電界効果トランジスタ
JP2013038239A (ja) * 2011-08-09 2013-02-21 Sanken Electric Co Ltd 窒化物半導体装置
JP5995309B2 (ja) * 2012-03-28 2016-09-21 住友電工デバイス・イノベーション株式会社 半導体装置及びその製造方法
WO2013147710A1 (en) * 2012-03-29 2013-10-03 Agency For Science, Technology And Research Iii-nitride high electron mobility transistor structures and methods for fabrication of same
JP6268366B2 (ja) * 2012-09-28 2018-01-31 パナソニックＩｐマネジメント株式会社 半導体装置
JP6326638B2 (ja) * 2013-04-25 2018-05-23 パナソニックＩｐマネジメント株式会社 半導体装置
US20150079738A1 (en) * 2013-06-18 2015-03-19 Stephen P. Barlow Method for producing trench high electron mobility devices
DE102013211374A1 (de) * 2013-06-18 2014-12-18 Robert Bosch Gmbh Transistor und Verfahren zur Herstellung eines Transistors
US9184243B2 (en) * 2013-07-12 2015-11-10 Infineon Technologies Americas Corp. Monolithic composite III-nitride transistor with high voltage group IV enable switch
JP6252122B2 (ja) * 2013-11-13 2017-12-27 富士通株式会社 半導体装置及び半導体装置の製造方法
JP2015220430A (ja) 2014-05-21 2015-12-07 シャープ株式会社 電界効果トランジスタ
DE102014113467B4 (de) 2014-09-18 2022-12-15 Infineon Technologies Austria Ag Metallisierung eines Feldeffekt-Leistungstransistors
US10312358B2 (en) 2014-10-02 2019-06-04 University Of Florida Research Foundation, Incorporated High electron mobility transistors with improved heat dissipation
US20170033187A1 (en) * 2015-07-31 2017-02-02 Ohio State Innovation Foundation Enhancement mode field effect transistor with doped buffer and drain field plate
US9680035B1 (en) * 2016-05-27 2017-06-13 Solar Junction Corporation Surface mount solar cell with integrated coverglass

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007128994A (ja) * 2005-11-02 2007-05-24 New Japan Radio Co Ltd 半導体装置
CN101335247A (zh) * 2007-06-29 2008-12-31 富士通株式会社 半导体器件及其制造方法
US20120043586A1 (en) * 2010-08-23 2012-02-23 Fujitsu Limited Semiconductor device and method for manufacturing the same
JP2013191763A (ja) * 2012-03-14 2013-09-26 Fujitsu Ltd 半導体装置の製造方法
US20160056273A1 (en) * 2014-08-20 2016-02-25 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HSIEN-CHIN CHIU等: ""Normally-off matrix layout p-GaN gate AlGaN/GaN power HEMT with a throughsubstrate via process"", 《THE J. VAC.SCI. TECHNOL. B》 *

Also Published As

Publication number Publication date
US20190115435A1 (en) 2019-04-18
CN109716530B (zh) 2022-03-25
WO2017196740A3 (en) 2018-07-26
US10217827B2 (en) 2019-02-26
EP3905340A1 (en) 2021-11-03
KR20180136553A (ko) 2018-12-24
US20170330940A1 (en) 2017-11-16
EP3455883A4 (en) 2020-03-18
CN114093939A (zh) 2022-02-25
US20200287004A1 (en) 2020-09-10
WO2017196740A2 (en) 2017-11-16
JP2019519099A (ja) 2019-07-04
CN109716530A (zh) 2019-05-03
KR102199173B1 (ko) 2021-01-07
EP3455883A2 (en) 2019-03-20
US10707311B2 (en) 2020-07-07
KR20200068745A (ko) 2020-06-15
JP6718982B2 (ja) 2020-07-08
JP2020150280A (ja) 2020-09-17
KR102136356B1 (ko) 2020-07-23
EP3455883B1 (en) 2021-11-03
JP7066778B2 (ja) 2022-05-13
US10861947B2 (en) 2020-12-08

Similar Documents

Publication Publication Date Title
CN109716530B (zh) 高电子迁移率晶体管
US9577064B2 (en) High electron mobility transistors with field plate electrode
JP2023528051A (ja) ダイの前面でのピラー接続及び裏面での受動デバイス集積のための方法
CN111199883B (zh) 具有经调整的栅极-源极距离的hemt晶体管及其制造方法
CN117546299A (zh) 包括半导体表面修改的晶体管及相关制造方法
US9437626B2 (en) Millimetre wave integrated circuits with thin film transistors
US20220376098A1 (en) Field effect transistor with selective modified access regions
CN110556301A (zh) 半导体器件及其制造方法
US7990223B1 (en) High frequency module and operating method of the same
TWI718300B (zh) 半導體電晶體及其加工方法
US20230029763A1 (en) Interconnect metal openings through dielectric films
US11869964B2 (en) Field effect transistors with modified access regions
JPS5914906B2 (ja) 電界効果トランジスタの製造方法
CN106992210B (zh) 用于制造横向hemt的装置和方法
WO2022246142A1 (en) Field effect transistor with modified access regions
KR20230055221A (ko) GaN RF HEMT 소자 및 그 제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination